/** @file
  File name:    SAI_BOXTYPE.h
  Input File:   GLK_SOC.xlsx

  THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.

  If edits are needed in this file, they must be done via the MMRC tool.

  If there is additional project-specific data required by the MMRC, it
  can be placed in SAI_BOXTYPE.h, which is used for non-tool-generated
  data

  Includes register defines specific to a project.

 @copyright
  INTEL CONFIDENTIAL
  Copyright 2005 - 2016 Intel Corporation.

  The source code contained or described herein and all documents related to the
  source code ("Material") are owned by Intel Corporation or its suppliers or
  licensors. Title to the Material remains with Intel Corporation or its suppliers
  and licensors. The Material may contain trade secrets and proprietary and
  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
  without Intel's prior express written permission.

  No license under any patent, copyright, trade secret or other intellectual
  property right is granted to or conferred upon you by disclosure or delivery
  of the Materials, either expressly, by implication, inducement, estoppel or
  otherwise. Any license under such intellectual property rights must be
  express and approved by Intel in writing.

  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
  the terms of your license agreement with Intel or your vendor. This file may
  be modified by the user, subject to additional terms of the license agreement.

  @par Specification
**/
#ifndef _SAI_BOXTYPE_H_
#define _SAI_BOXTYPE_H_

#include "DataTypes.h"

#if USE_64_BIT_VARIABLES
#define UINTX UINT64
#else
#define UINTX UINT32
#endif

#define SAI_CTRL_REG0_SAI_BOXTYPE_REG                      0x0000F840
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Control Policy for Group 1 (LSB)
    //
    // Bits[31:0], RW, default = 0x61010202
    //
    UINTX sai_ctrl_policy : 32;
  } Bits;
  UINTX Data;
} SAI_CTRL_REG0_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_CTRL_REG0_1_SAI_BOXTYPE_REG                    0x0000F844
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Control Policy for Group 1 (MSB)
    //
    // Bits[31:0], RW, default = 0xC00
    //
    UINTX sai_ctrl_policy_1 : 32;
  } Bits;
  UINTX Data;
} SAI_CTRL_REG0_1_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG0_SAI_BOXTYPE_REG                        0x0000F848
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Read/Write Policy for Group 1: policy0
    //
    // Bits[31:0], RW, default = 0x1000212
    //
    UINTX sai_rw_policy0 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG0_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG0_1_SAI_BOXTYPE_REG                      0x0000F84C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Read/Write Policy for Group 2: policy0
    //
    // Bits[31:0], RW, default = 0xC00
    //
    UINTX sai_rw_policy0_1 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG0_1_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG1_SAI_BOXTYPE_REG                        0x0000F850
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX sai_rw_policy1 : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} SAI_RW_REG1_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG1_1_SAI_BOXTYPE_REG                      0x0000F854
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX sai_rw_policy1_1 : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} SAI_RW_REG1_1_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG2_SAI_BOXTYPE_REG                        0x0000F858
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX sai_rw_policy2 : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} SAI_RW_REG2_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG2_1_SAI_BOXTYPE_REG                      0x0000F85C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX sai_rw_policy2_1 : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} SAI_RW_REG2_1_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define REG_POLICY0_SAI_BOXTYPE_REG                        0x0000F860
#ifndef ASM_INC
typedef union {
  struct {
    //
    // CR Region Policy0: [br] 1'b1 (applicable for all indexes): The corresponding configuration
    // register region is locked and only accessible by trusted agents associated with
    // policy0 [br]1'b0 (applicable for all indexes): The corresponding configuration
    // register region is unlocked - all agents (trusted or untrusted) are allowed to
    // access this region.
    //
    // Bits[31:0], RW, default = 0x3
    //
    UINTX region_policy0 : 32;
  } Bits;
  UINTX Data;
} REG_POLICY0_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define REG_POLICY1_SAI_BOXTYPE_REG                        0x0000F864
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX region_policy1 : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} REG_POLICY1_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define REG_POLICY2_SAI_BOXTYPE_REG                        0x0000F868
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX region_policy2 : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} REG_POLICY2_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC

#define REG_RSVD_SAI_BOXTYPE_REG                           0x0000F86C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reg_rsvd : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} REG_RSVD_SAI_BOXTYPE_STRUCT;
#endif // ASM_INC


#endif // _SAI_BOXTYPE_H_
