//// @file
//  Assembly code of Cpu
//
// @copyright
//  INTEL CONFIDENTIAL
//  Copyright 2006 - 2017 Intel Corporation.
//
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//  source code ("Material") are owned by Intel Corporation or its suppliers or
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//
//  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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//
// @par Specification
////

.equ IA32_CR4_OSFXSR,              0x200
.equ IA32_CR4_OSXMMEXCPT,          0x400
.equ IA32_CR0_MP,                  0x02

.equ IA32_CPUID_SSE2,              0x2000000
.equ IA32_CPUID_SSE2_B,            0x1A      //26


//------------------------------------------------------------------------------
//   Set up flags in CR4 for XMM instruction enabling
//------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(InitXmm)
ASM_PFX(InitXmm):
  push    %ebx

  //
  // Check whether SSE2 is supported
  //
  mov     $0x01, %eax
  cpuid
  bt      $IA32_CPUID_SSE2_B, %edx
  jnc     InitXmmL0

  //
  // Enable XMM
  //
  movl    %cr0, %eax
  or      $IA32_CR0_MP, %eax
  movl    %eax, %cr0
  movl    %cr4, %eax
  or      $0x600, %eax                       //or      eax, IA32_CR4_OSFXSR OR IA32_CR4_OSXMMEXCPT
  movl    %eax, %cr4

InitXmmL0:
  pop     %ebx
  ret

ASM_GLOBAL ASM_PFX(CacheInvd)
ASM_PFX(CacheInvd):
  invd
  ret


