/** @file
  File name:    StringsGenerated.c
  Input File:   GLK_SOC.xlsx

  THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.

  If edits are needed in this file, they must be done via the MMRC tool.

  If there is additional project-specific data required by the MMRC, it
  can be placed in Strings.c, which is used for non-tool-generated
  data

  Includes various strings specific to a project.

 @copyright
  INTEL CONFIDENTIAL
  Copyright 2005 - 2016 Intel Corporation.

  The source code contained or described herein and all documents related to the
  source code ("Material") are owned by Intel Corporation or its suppliers or
  licensors. Title to the Material remains with Intel Corporation or its suppliers
  and licensors. The Material may contain trade secrets and proprietary and
  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
  without Intel's prior express written permission.

  No license under any patent, copyright, trade secret or other intellectual
  property right is granted to or conferred upon you by disclosure or delivery
  of the Materials, either expressly, by implication, inducement, estoppel or
  otherwise. Any license under such intellectual property rights must be
  express and approved by Intel in writing.

  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
  the terms of your license agreement with Intel or your vendor. This file may
  be modified by the user, subject to additional terms of the license agreement.

  @par Specification
**/

#include "MmrcData.h"

#if CAPSULESTRINGS
char *OutputStrings[] = {
  NULL,
};
#endif //CAPSULESTRINGS

#if DUMP_REGISTER_NAMES
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields0[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "dramdevice_pr", "Specifies the number of DRAM devices that are ganged together to form a single rank. \r\n"
"      [list]\r\n"
"      [*]00: 1 DRAM device in each rank.\r\n"
"      [*]01: 2 DRAM devices in each rank.\r\n"
"      [*]10: 4 DRAM devices in each rank.\r\n"
"      [*]11: 8 DRAM devices in each rank. \r\n"
"      [/list]\r\n"
"      [p]Note: The actual number of devices is one more than the value programmed when ECC is enabled.[/p]"},
#else
{30, 31, 0x0000000000000000, "RW", "dramdevice_pr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000001, "RW", "addrdec", "Specifies the address mapping to be used:\r\n"
"  [list]\r\n"
"  [*]00: 1KB (A). \r\n"
"  [*]01: 2KB (B).\r\n"
"  [*]10: 4KB (C).\r\n"
"  [*]11: Reserved.\r\n"
"  [/list]"},
#else
{28, 29, 0x0000000000000001, "RW", "addrdec", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 27, 0x0000000000000000, "RW", "blmode", "\r\n"
"  [list]\r\n"
"  [*]000: Fixed BL8.  \r\n"
"  [*]001: Onthefly BL8.\r\n"
"  [*]010: Fixed BL16.\r\n"
"  [*]011: Onthefly BL16.\r\n"
"  [*]100: Fixed BL32.\r\n"
"  [*]101: Onthefly BL32.\r\n"
"  [*]110-111: Reserved.\r\n"
"  [/list]"},
#else
{25, 27, 0x0000000000000000, "RW", "blmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 24, 0x0000000000000000, "RW", "dramtype", "\r\n"
"  [list]\r\n"
"  [*]000: DDR3L.\r\n"
"  [*]001: LPDDR3.\r\n"
"  [*]010: LPDDR4.\r\n"
"  [*]011: WIO2.\r\n"
"  [*]100: DDR4.\r\n"
"  [*]101-111: Reserved.\r\n"
"      [/list]\r\n"
"  [p]Note: The D-Unit should only use this field if allowed by fuse.[/p]"},
#else
{22, 24, 0x0000000000000000, "RW", "dramtype", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "eccen", "\r\n"
"  [list]\r\n"
"  [*]0: ECC is disabled.\r\n"
"  [*]1: ECC is enabled.\r\n"
"      [/list]\r\n"
"  [p]This bit determines if the D-Unit treats the PMI BE_ECC bits as ECC bits or Byte Enables. The D-Unit should not allow this bit to be set if ECC is disabled by fuse. This should only be used in configurations that support ECC.[/p]"},
#else
{21, 21, 0x0000000000000000, "RW", "eccen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW", "caswizzle", "\r\n"
"      [list]\r\n"
"      [*]00: uniDIMM/SODIMM/UDIMM.\r\n"
"      [*]01: BGA. \r\n"
"      [*]10: BGA mirrored (LPDDR3 Only). \r\n"
"      [*]11: uniDIMM/SODIMM/UDIMM with Rank 1 mirrored (DDR4 Only).\r\n"
"      [/list]"},
#else
{19, 20, 0x0000000000000000, "RW", "caswizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 18, 0x0000000000000000, "RO", "rsvd18_17", "Reserved."},
#else
{17, 18, 0x0000000000000000, "RO", "rsvd18_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "fbginten", "When enabled, D-unit will use a lower order address bit in the bank hashing function (DDR4 Only). \r\n"
"  [list]\r\n"
"  [*]0: Bank Group Interleave disabled.\r\n"
"  [*]1: Bank Group Interleave enabled.\r\n"
"  [/list]\r\n"
"      [p]Note: BAHEN must be set for this bit to take effect.[/p]"},
#else
{16, 16, 0x0000000000000000, "RW", "fbginten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "bahen", "See Address Mapping section for full description.  \r\n"
"  [list]\r\n"
"  [*]0: Bank Address Hashing disabled.\r\n"
"  [*]1: Bank Address Hashing enabled.\r\n"
"  [/list]"},
#else
{15, 15, 0x0000000000000000, "RW", "bahen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "rsien", "See Address Mapping section for full description.\r\n"
"      [list]\r\n"
"  [*]0: Rank Select Interleaving disabled.\r\n"
"  [*]1: Rank Select Interleaving enabled.\r\n"
"  [/list]"},
#else
{14, 14, 0x0000000000000000, "RW", "rsien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 13, 0x0000000000000000, "RO", "rsvd13_9", "Reserved."},
#else
{9, 13, 0x0000000000000000, "RO", "rsvd13_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000000, "RW", "dden", "Density of the DRAM devices populated on Ranks 0 and 1.\r\n"
"      [list]\r\n"
"  [*]000: 4 Gb.\r\n"
"  [*]001: 6 Gb.\r\n"
"  [*]010: 8 Gb.\r\n"
"  [*]011: 12 Gb.\r\n"
"  [*]100: 16 Gb.\r\n"
"  [*]101-111: Reserved.\r\n"
"      [/list]\r\n"
"  [p]Note: For LPDDR4 this value is the die density.[/p]"},
#else
{6, 8, 0x0000000000000000, "RW", "dden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "dwid", "Data width of the DRAM device populated on Ranks 0 and 1.\r\n"
"      [list]\r\n"
"  [*]00: x8.\r\n"
"  [*]01: x16.\r\n"
"  [*]10: x32.\r\n"
"  [*]11: x64.\r\n"
"  [/list]"},
#else
{4, 5, 0x0000000000000000, "RW", "dwid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "rsvd3", "Reserved."},
#else
{3, 3, 0x0000000000000000, "RO", "rsvd3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ddmen", "\r\n"
"      [list]\r\n"
"      [*]0: PMI Dual Data Mode is disabled in D-Unit.\r\n"
"      [*]1: PMI Dual Data Mode is enabled.\r\n"
"      [/list]\r\n"
"      [p]Note: Dual Data Mode must be enable for DDR3L/DDR4 configurations."},
#else
{2, 2, 0x0000000000000000, "RW", "ddmen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rken1", "Enable Rank 1: Must be set to 1 to enable use of this rank."},
#else
{1, 1, 0x0000000000000000, "RW", "rken1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rken0", "Enable Rank 0: Must be set to 1 to enable use of this rank.  \r\n"
"  [p]Note: Setting this bit to 0 is not a functional mode.[/p]"},
#else
{0, 0, 0x0000000000000000, "RW", "rken0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo0[] = {{"D_CR_DRP0", "", 0x00000000, 17, 0x00000000FFFFFFFF, 0x0000000010000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "rsvd31_23", "Reserved."},
#else
{23, 31, 0x0000000000000000, "RO", "rsvd31_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000005, "RW", "twwsr_l", "Specifies the delay from a DRAM Write to another Write command within the same bank group of the same rank (in DRAM clocks).\r\n"
"  [p]DDR4 Equation: tWWSR_L = tCCD_L.[/p]"},
#else
{18, 22, 0x0000000000000005, "RW", "twwsr_l", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 17, 0x0000000000000005, "RW", "trrsr_l", "Specifies the delay from a DRAM Read to another Read command  within the same bank group of the same rank (in DRAM clocks).\r\n"
"  [p]DDR4 Equation: tRRSR_L = tCCD_L.[/p]"},
#else
{13, 17, 0x0000000000000005, "RW", "trrsr_l", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 12, 0x0000000000000015, "RW", "twrsr_l", "Specifies the delay from a DRAM Read to Write command within the same bank group of the same rank (in DRAM clocks).\r\n"
"      [list]\r\n"
"      [*]DDR4 Equation: tWRSR_L  = CWL + tDQSSmax + BL/2 + tWPST + tWTR_L.\r\n"
"      [/list]"},
#else
{6, 12, 0x0000000000000015, "RW", "twrsr_l", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000006, "RW", "trrd_l", "Specifies the minimum delay (in DRAM clocks) between two DRAM Activate commands to different banks within the same bank group of a rank. (DDR4 Only)"},
#else
{0, 5, 0x0000000000000006, "RW", "trrd_l", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1[] = {{"D_CR_DTR9A", "", 0x00000004, 5, 0x00000000FFFFFFFF, 0x000000000014A546}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields2[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000010, "RW", "tckckeh", "Number of valid clocks before CKE high (in DRAM clocks).\r\n"
"  [list]\r\n"
"  [*]LPDDR4: The value in this register covers both tCKCKEH and tCSCKEH.\r\n"
"  [*]DDR3L/DDR4/LPDDR3/WIO2: The value covers tCKSRX which is defined as the number of valid DRAM clocks that have to toggle before the issuing of the Self Refresh Exit SRX. This value is also used if the clock frequency is changed or the clock is stopped or tristated during Power Down i.e. the number valid DRAM clocks that have to toggle before the issuing of the Power Down Exit PDX command.\r\n"
"  [/list]\r\n"
"  [p]TCKCKEH can be used to compensate for clock stabilization delays in the motherboard.[/p]\r\n"
"      [p]Note: D-unit hardware enforces minimum of two SPID clock before CKEH, any value in this register is the additional time.[/p]"},
#else
{27, 31, 0x0000000000000010, "RW", "tckckeh", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 26, 0x0000000000000008, "RW", "txsdll", "D-Unit waits max(tXSR+tZQCL/tZQCS, tXSDLL) before allowing traffic to DRAM (in 32 x DRAM Clocks). \r\n"
"      [p]LPDDR3/LPDDR4/WIO2: tXSDLL = 0.[/p] \r\n"
"      [p]DDR3L/DDR4: tXSDLL = tDLLK.[/p]\r\n"
"      [p]Note: In the equation above, tZQCL/tZQCS = 0 if no ZQ is performed on SR exit.[/p]"},
#else
{22, 26, 0x0000000000000008, "RW", "txsdll", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 21, 0x0000000000000070, "RW", "txsr", "DDR3L/DDR4: tXS - Delay between Self Refresh Exit SRX to any DRAM Command not requiring DLL Lock.\r\n"
"  [p]LPDDR/WIO2: tXSR - Delay between Self Refresh Exit SRX to any DRAM Command. (in DRAM clocks).[/p]"},
#else
{12, 21, 0x0000000000000070, "RW", "txsr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x000000000000000B, "RW", "trcd", "Specifies the delay between a DRAM Activate command and a DRAM Read or Write command to the same bank (in DRAM clocks).\r\n"
"  [p]Note: Derating adds 1.875ns to this timing.[/p]"},
#else
{6, 11, 0x000000000000000B, "RW", "trcd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000000B, "RW", "trppb", "Specifies the delay between a DRAM Precharge command and a DRAM Activate command to the same bank (in DRAM Clocks). \r\n"
"      [p]Note : this CR should be constrained to a minimum of 4 in LPDDR3/DDR3L/WIO2 and minimum of 8 in LPDDR4/DDR4.[/p]\r\n"
"  [p]Note: Derating adds 1.875ns to this timing.[/p]"},
#else
{0, 5, 0x000000000000000B, "RW", "trppb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo2[] = {{"D_CR_DTR0A", "", 0x00000008, 5, 0x00000000FFFFFFFF, 0x00000000820702CB}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields3[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000006, "RW", "txp", "Specifies the delay from the DRAM Power Down Exit (PDX) command to any valid command (in DRAM clocks).\r\n"
"      [p]Note: The value in this field must be programmed to tXPDLL when Slow Exit Mode Power-down is enabled for DDR3L.[/p]"},
#else
{27, 31, 0x0000000000000006, "RW", "txp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO", "rsvd26", "Reserved."},
#else
{26, 26, 0x0000000000000000, "RO", "rsvd26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 25, 0x0000000000000120, "RW", "tzqcl", "\r\n"
"  [list]\r\n"
"  [*]LPDDR3/DDR3L/DDR4: tZQCL/tZQoper - Specifies the delay between the DRAM ZQ Calibration Long (ZQCL) command and any DRAM command during normal operation. \r\n"
"  [*]LPDDR4: tZQCAL - ZQ Calibration time (in DRAM clocks).\r\n"
"  [/list]\r\n"
"  [p]Note: This field defines the ZQ Calibration Long delay during normal operation. It is not the same as tZQinit which uses the same ZQCL command but the delay is longer. tZQinit applies only during poweron initialization of the DRAM devices and tZQoper applies during normal operation. BIOS executes the DRAM initialization sequence so it has to ensure tZQinit is met and not the D-Unit.[/p]"},
#else
{14, 25, 0x0000000000000120, "RW", "tzqcl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 13, 0x0000000000000048, "RW", "tzqcs", "ZQCS to any DRAM Command Delay:  Specifies the delay between the DRAM ZQ Calibration Short (ZQCS) command and any DRAM command (in DRAM clocks).\r\n"
"  [p]DDR3L/DDR4/LPDDR3 only. LPDDR4 does not support ZQCS command[/p]"},
#else
{6, 13, 0x0000000000000048, "RW", "tzqcs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000018, "RW", "tzqlat", "Specifies the delay between the DRAM ZQ Calibration Latch command and any DRAM command (in DRAM clocks).\r\n"
"  [p]LPDDR4 only. Not used in DDR3L/DDR4/LPDDR3/WIO2.[/p]"},
#else
{0, 5, 0x0000000000000018, "RW", "tzqlat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo3[] = {{"D_CR_DTR1A", "", 0x0000000C, 5, 0x00000000FFFFFFFF, 0x0000000030481218}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields4[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000118, "RW", "nrfcab", "Specifies the delay between the REFab command to the next valid command. (in DRAM clocks)"},
#else
{22, 31, 0x0000000000000118, "RW", "nrfcab", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RO", "rsvd21", "Reserved."},
#else
{21, 21, 0x0000000000000000, "RO", "rsvd21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 20, 0x0000000000000004, "RW", "tcke", "Specifies the minimum time from CKEL to CKEH (in DRAM clocks)."},
#else
{17, 20, 0x0000000000000004, "RW", "tcke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "rsvd16", "Reserved."},
#else
{16, 16, 0x0000000000000000, "RO", "rsvd16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000C30, "RW", "nrefi", "Specifies the average time between refresh commands. JEDEC Base Refresh Interval time (in DRAM clocks).\r\n"
"      [p]Note: D-Unit will ignore the 2 LSBs of this field.[/p]"},
#else
{0, 15, 0x0000000000000C30, "RW", "nrefi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo4[] = {{"D_CR_DTR2A", "", 0x00000010, 5, 0x00000000FFFFFFFF, 0x0000000046080C30}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields5[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000006, "RW", "trtp", "Specifies the minimum delay between the DRAM Read and Precharge commands to the same bank (in DRAM clocks).\r\n"
"  [list]\r\n"
"  [*]LPDDR3 Equation: = BL/2 + tRTP - 4.\r\n"
"  [*]LPDDR4 Equation: = BL/2 + Max (8, tRTP) - 8.\r\n"
"  [*]WIO2 Equation: = BL/2 + tRTP - 2.\r\n"
"      [*]DDR3L/DDR4 Equation: = tRTP.\r\n"
"  [/list]"},
#else
{27, 31, 0x0000000000000006, "RW", "trtp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 26, 0x0000000000000000, "RW", "tccd_inc", "Specifies the number of clocks to be added to turnaround times (for Stretch Mode). It increases delay between Read to Read or Read to Write commands by the amount programmed in this field (in 4 x DRAM clocks)."},
#else
{20, 26, 0x0000000000000000, "RW", "tccd_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 19, 0x0000000000000017, "RW", "twtp", "Specifies the minimum delay between the DRAM Write command and the Precharge command to the same bank (in DRAM clocks).\r\n"
"  [list]\r\n"
"      [*]LPDDR3/LPDDR4/WIO2 Equation: tWTP = BL/2 + WL + tWR + 1.\r\n"
"      [*]DDR3L/DDR4 Equation: tWTP = BL/2 + CWL + tWR.\r\n"
"      [/list]"},
#else
{13, 19, 0x0000000000000017, "RW", "twtp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000001, "RW", "tcmd", "Specifies the number of DRAM clocks a command is held valid on the DRAM Address and Control buses. 1N is the DDR3 basic requirement.  2N is the extended mode for board signal integrity. \r\n"
"  [list]\r\n"
"  [*]0h: Reserved.\r\n"
"  [*]1h: 1 DRAM Clock (1N).\r\n"
"  [*]2h: 2 DRAM Clocks (2N).\r\n"
"  [*]3h: Reserved.\r\n"
"  [/list]\r\n"
"  [p]Note: DDR3L/DDR4 only. tCMD must be set to 1N for LPDDR3/LPDDR4/WIO2.[/p]"},
#else
{11, 12, 0x0000000000000001, "RW", "tcmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 10, 0x0000000000000008, "RW", "tcwl", "The delay between the internal write command and the availability of the first word of DRAM input data (in DRAM clocks)."},
#else
{6, 10, 0x0000000000000008, "RW", "tcwl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000028, "RW", "twmwsb", "Specifies the minimum delay between DRAM Write command to Masked Write command to same bank (in DRAM clocks).\r\n"
"      [list]\r\n"
"  [*]LPDDR4 Equation: tWMWSB = tCCDMW (BL16) or tCCDMW + 8 (BL32).\r\n"
"  [*]WIO2 Equation: tWMWSB = tCCDMW (BL4) or tCCDMW + 2 (BL8).\r\n"
"  [/list]\r\n"
"  [p]Note: Masked Write operation in LPDDR4 is always BL16 and in WIO2 is always BL4.[/p]\r\n"
"  [p]D-Unit applies this timing for same rank as well as same bank, refer to D-Unit HAS for more details.[/p]"},
#else
{0, 5, 0x0000000000000028, "RW", "twmwsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo5[] = {{"D_CR_DTR3A", "", 0x00000014, 6, 0x00000000FFFFFFFF, 0x000000003002EA28}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields6[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000030, "RW", "tfaw", "A rolling timeframe in which a maximum of four Activate commands can be issued to the same rank. This is to limit the peak current draw from the DRAM devices (in DRAM clocks)."},
#else
{24, 31, 0x0000000000000030, "RW", "tfaw", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 23, 0x0000000000000008, "RW", "twrdr", "Specifies the delay from the start of a Write data burst of one rank to the start of a Read data burst of a different rank (in DRAM clocks).\r\n"
"  [list]\r\n"
"  [*]LPDDR3 Equation: tWRDR = WL + tDQSSmax + BL/2 - (RL + tDQSCKmin - tRPRE).\r\n"
"  [*]LPDDR4 Equation: tWRDR = WL - RL + BL/2 + 4 - tDQSCKmin.\r\n"
"      [*]DDR3L/DDR4 Equation: tWRDR = CWL + tDQSSmax + BL/2 - (CL + tDQSCKmin - tRPRE).\r\n"
"      [/list]   \r\n"
"  [p]Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.[/p]"},
#else
{18, 23, 0x0000000000000008, "RW", "twrdr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 17, 0x0000000000000009, "RW", "trwdr", "Specifies the delay from the start of a Read data burst of one rank to the Start of a Write data burst of a different rank (in DRAM clocks).\r\n"
"  [list]\r\n"
"  [*]LPDDR3/LPDDR4 Equation: tRWDR = RL + tDQSCKmax + BL/2 - (WL - tWPRE).\r\n"
"      [*]DDR3L/DDR4 Equation: tRWDR = CL + tDQSCKmax + BL/2 - (CWL - tWPRE).\r\n"
"  [/list]\r\n"
"  [p]Note: For LPDDR3/4 using ODT, this latency may need to be adjusted by tODTon.[/p]\r\n"
"      [p]Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.[/p]"},
#else
{12, 17, 0x0000000000000009, "RW", "trwdr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000005, "RW", "twwdr", "Specifies the delay from the start of a Write data burst of one rank to the start of a Write data burst of a different rank (in DRAM clocks).\r\n"
"  [list]\r\n"
"  [*]LPDDR3/DDR3L/DDR4 Equation: tWWDR = BL/2 + tDQSSmax - tDQSSmin + tWPRE.\r\n"
"  [*]LPDDR4 Equation: tWWDR = BL/2 + 4 - tDQSSmin.\r\n"
"  [/list]\r\n"
"  [p]Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.[/p]"},
#else
{6, 11, 0x0000000000000005, "RW", "twwdr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000009, "RW", "trrdr", "Specifies the delay from the start of a Read data burst of one rank to the Start of a Read data burst of a different rank (in DRAM clocks).\r\n"
"      [list]\r\n"
"  [*]Equation: tRRDR = BL/2 + tDQSCKmax - tDQSCKmin + tRPRE.\r\n"
"      [/list]"},
#else
{0, 5, 0x0000000000000009, "RW", "trrdr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo6[] = {{"D_CR_DTR4A", "", 0x00000018, 5, 0x00000000FFFFFFFF, 0x0000000030209149}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields7[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000006, "RW", "trrd", "Specifies the minimum delay in DRAM clocks between two DRAM Activate commands to the same rank but different banks (tRC is the minimum delay between activations of the same bank).\r\n"
"  [p]Note: Derating adds 1.875ns to this timing.[/p]"},
#else
{27, 31, 0x0000000000000006, "RW", "trrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO", "rsvd26", "Reserved."},
#else
{26, 26, 0x0000000000000000, "RO", "rsvd26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 25, 0x0000000000000000, "RW", "tderate_inc", "Specifies the additional delay that is added to DRAM timing when indicated by MR4 status. (in DRAM clocks)\r\n"
"  [p]LPDDR3/LPDDR4/WIO2: Value is 1.875ns.[/p]\r\n"
"  [p]Note: The value in this register is only added to these timing parameters: tRCD, tRAS, tRP and tRRD.[/p]"},
#else
{23, 25, 0x0000000000000000, "RW", "tderate_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000010, "RW", "twwsr", "Specifies the delay from a DRAM Write to another Write command of the same rank (in DRAM clocks).\r\n"
"  [p]Equation: tWWSR = tCCD.[/p]"},
#else
{18, 22, 0x0000000000000010, "RW", "twwsr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 17, 0x0000000000000010, "RW", "trrsr", "Specifies the delay from a DRAM Read to another Read command of the same rank (in DRAM clocks).\r\n"
"  [p]Equation: tRRSR = tCCD.[/p]"},
#else
{13, 17, 0x0000000000000010, "RW", "trrsr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 12, 0x0000000000000003, "RW", "twrsr", "Specifies the delay from a DRAM Read to Write command of the same rank (in DRAM clocks).\r\n"
"      [list]\r\n"
"  [*]LPDDR3/LPDDR4/WIO2 Equation: tWRSR  = WL + tDQSSmax + BL/2 + tWTR.\r\n"
"      [*]DDR3L Equation: tWRSR  = CWL + tDQSSmax + BL/2 + tWTR.\r\n"
"      [*]DDR4 Equation: tWRSR  = CWL + tDQSSmax + BL/2 + tWTR_S.\r\n"
"      [/list]"},
#else
{6, 12, 0x0000000000000003, "RW", "twrsr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000002, "RW", "trwsr", "Specifies the delay from a DRAM Read to a Write command of the same rank (in DRAM clocks).\r\n"
"      [list]\r\n"
"  [*]LPDDR3/LPDDR4/WIO2 Equation: tRWSR = RL + tDQSCKmax + BL/2 - WL + tWPRE.\r\n"
"      [*]DDR3L/DDR4 Equation: tRWSR = CL + tDQSCKmax + BL/2 - CWL + tWPRE.\r\n"
"      [/list]\r\n"
"  [p]Note: For LPDDR3/4 using ODT, this latency may need to be increased by tODToffadj.[/p]\r\n"
"      [p]Note: For DDR3L/DDR4 using ODT, this latency may need to be increased by one clock.[/p]"},
#else
{0, 5, 0x0000000000000002, "RW", "trwsr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo7[] = {{"D_CR_DTR5A", "", 0x0000001C, 7, 0x00000000FFFFFFFF, 0x00000000304200C2}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields8[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000020, "RW", "orefdly", "Rank idle period that defines an opportunity for refresh (in DRAM clocks)."},
#else
{24, 31, 0x0000000000000020, "RW", "orefdly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 23, 0x0000000000000002, "RW", "tckckel", "Specifies the amount of time that DRAM clocks need to toggle after CKE goes low (in DRAM Clocks).\r\n"
"  [list]\r\n"
"  [*]For WIO2/LPDDR3, this covers tCPDED.\r\n"
"  [*]For LPDDR4, this covers both tCKELCK and tCKELCS.\r\n"
"  [*]For DDR3L/DDR4, this is tCKSRE.\r\n"
"      [/list]\r\n"
"  [p]Note: D-Unit hardware enforces minimum of one SPID clocks after CKEL, any value in this register is the additional time.[/p]"},
#else
{19, 23, 0x0000000000000002, "RW", "tckckel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 18, 0x0000000000000000, "RW", "rsvd18_15", "Reserved."},
#else
{15, 18, 0x0000000000000000, "RW", "rsvd18_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000000, "RW", "tpstmrrblk", "Specifies the quiet time after issuing MRR command (in DRAM Clocks). This is the channel block time for the MR19 command issued as part of LPDDR4 DQS Retraining flow. For all other MR commands this is the rank block time.   \r\n"
"      [p]Note: D-Unit treats MRR as a read and always applies relevant turnaround times, any value programmed in this CR must be greater than those turnaround times for D-Unit to enforce any additional time from MRR to the next read/write.[/p]"},
#else
{8, 14, 0x0000000000000000, "RW", "tpstmrrblk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "rsvd7", "Reserved."},
#else
{7, 7, 0x0000000000000000, "RO", "rsvd7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "tpremrblk", "Specifies the channel quiet time before issuing MRR/MRW command. (in DRAM clocks).\r\n"
"      [list]\r\n"
"      [*]LPDDR3 Equation: = tXP + tMRRI - 4.\r\n"
"      [*]LPDDR4 Equation: = tXP + tMRRI - 8.\r\n"
"      [*]DDR3L Equation: = CWL + BL/2 + 1 - 8\r\n"
"      [*]DDR4 Equation: = CWL + BL/2 + 1 - 16.\r\n"
"      [/list]\r\n"
"      [p]Note: D-Unit treats MRR as a read and MRW/MRS as a write and always applies relevant turnaround times, any value programmed in this CR must be greater than those turnaround times for D-Unit to enforce any additional time from previous read/writes.[/p]"},
#else
{0, 6, 0x0000000000000000, "RW", "tpremrblk", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo8[] = {{"D_CR_DTR6A", "", 0x00000020, 6, 0x00000000FFFFFFFF, 0x0000000020100000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields9[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000003, "RW", "trpab", "Specifies the delay between a DRAM Precharge All Bank command and a DRAM Activate command (in DRAM Clocks). \r\n"
"      [p]Note: This CR should be constrained to a minimum of 4 in LP3 and minimum of 8 in LP4.[/p]\r\n"
"  [p]Note: Derating adds 1.875ns to this timing.[/p]\r\n"
"  [list]\r\n"
"  [*]For LPDDR, tRPpb = tRP, tRPab = tRP + 3ns.\r\n"
"  [*]For DDR3L, DDR4 and WIO2 8ch tRPpb = tRPab = tRP.\r\n"
"  [/list]"},
#else
{26, 31, 0x0000000000000003, "RW", "trpab", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 25, 0x0000000000000002, "RW", "tpstmrwblk", "Specifies the quiet time after issuing MRW command (in 8 x DRAM clocks).\r\n"
"      [p]Note: This time covers for both tMRD and tMRW.[/p]"},
#else
{23, 25, 0x0000000000000002, "RW", "tpstmrwblk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000006, "RW", "twrpden", "Specifies the minimum time between a write command to PowerDown command (in DRAM clocks).\r\n"
"  [p]Must be at least equal to tWR + tCCD + tWL + 2.[/p]"},
#else
{16, 22, 0x0000000000000006, "RW", "twrpden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 15, 0x0000000000000006, "RW", "trdpden", "Specifies the minimum time between a read command to PowerDown command (in DRAM clocks).\r\n"
"  [p]Must be at least equal to CL/RL + tDQSCKmax + tCCD + 1.[/p]"},
#else
{9, 15, 0x0000000000000006, "RW", "trdpden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RO", "rsvd8_7", "Reserved."},
#else
{7, 8, 0x0000000000000000, "RO", "rsvd8_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000006, "RW", "tras", "Specifies the minimum delay between the DRAM Activate and Precharge commands to the same bank (in DRAM clocks).\r\n"
"      [p]Note: Derating adds 1.875ns to this timing.[/p]"},
#else
{0, 6, 0x0000000000000006, "RW", "tras", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo9[] = {{"D_CR_DTR7A", "", 0x00000024, 6, 0x00000000FFFFFFFF, 0x000000000D060C06}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields10[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000003, "RW", "tckesr", "Specifies the minimum time that DRAM should remain in SR (in DRAM clocks)."},
#else
{26, 31, 0x0000000000000003, "RW", "tckesr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 25, 0x0000000000000006, "RW", "lpmdres", "Specifies the minimum time that PHY should remain in LPMode (in DRAM clocks)."},
#else
{21, 25, 0x0000000000000006, "RW", "lpmdres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x000000000000000A, "RW", "lpmdtockedly", "Specifies the minimum time between the LP Mode exit to the CK stop/tristate deassertion and powerdown exit (in DRAM clocks).\r\n"
"  [p]Note: Must be equal to t_idle_latency published in the DDRIO PHY HAS and less than 0x3C.[/p]"},
#else
{15, 20, 0x000000000000000A, "RW", "lpmdtockedly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x000000000000000A, "RW", "cketolpmddly", "Specifies the time between CK stop/tristate to the Low Power Mode entry. This timing parameter is used to delay Low Power Mode entry (in DRAM clocks).\r\n"
"  [p]Note: Must be at least equal to t_idle_length parameter published in the DDRIO PHY HAS and less than 0x7C.[/p]"},
#else
{8, 14, 0x000000000000000A, "RW", "cketolpmddly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000018, "RW", "pwddly", "This is a non-JEDEC timing parameter used to delay powerdown entry (in DRAM clocks)."},
#else
{0, 7, 0x0000000000000018, "RW", "pwddly", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo10[] = {{"D_CR_DTR8A", "", 0x00000028, 5, 0x00000000FFFFFFFF, 0x000000000CC50A18}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields11[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "r1rdodtctl", "Specifies the behavior of ODT signals when a Read command is issued to Rank 1.\r\n"
"      [p]0 - Read ODT is disabled for Rank 1[/p] \r\n"
"      [p]1 - Assert ODT to for Rank 0 (non-targeted Rank) [/p]\r\n"
"      [p]Note: This register should be set to 0 for LPDDR3 devices[/p]"},
#else
{29, 29, 0x0000000000000000, "RW", "r1rdodtctl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "r0rdodtctl", "Specifies the behavior of ODT signals when a Read command is issued to Rank 0.\r\n"
"      [p]0 - Read ODT is disabled for Rank 0 [/p]\r\n"
"      [p]1 - Assert ODT to for Rank 1 (non-targeted Rank) [/p]\r\n"
"      [p]Note: This register is reserved for LPDDR3 devices[/p]"},
#else
{28, 28, 0x0000000000000000, "RW", "r0rdodtctl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "r1wrodtctl", "Specifies the behavior of ODT signals when a Write command is issued to Rank 1.\r\n"
"      [p]00 - Write ODT is disabled [/p]\r\n"
"      [p]01 - Assert ODT to Rank 0 (non-targeted Rank) [/p]\r\n"
"      [p]10 - Assert ODT to Rank 1 (targeted Rank) [/p]\r\n"
"      [p]11 - Assert ODT to Rank 0 and Rank 1 [/p]\r\n"
"      [p]Note: 10 and 11 are reserved values for LPDDR3[/p]"},
#else
{26, 27, 0x0000000000000000, "RW", "r1wrodtctl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "r0wrodtctl", "Specifies the behavior of ODT signals when a Write command is issued to Rank 0.\r\n"
"      [p]00 - Write ODT is disabled [/p]\r\n"
"      [p]01 - Assert ODT to Rank 0 (targeted Rank) [/p]\r\n"
"      [p]10 - Assert ODT to Rank 1 (non-targeted Rank) [/p]\r\n"
"      [p]11 - Assert ODT to Rank 0 and Rank 1 [/p]\r\n"
"      [p]Note: 10 and 11 are reserved values for LPDDR3[/p]"},
#else
{24, 25, 0x0000000000000000, "RW", "r0wrodtctl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 23, 0x0000000000000000, "RO", "rsvd23_18", "Reserved."},
#else
{18, 23, 0x0000000000000000, "RO", "rsvd23_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x0000000000000000, "RW", "rdodtstop", "Specifies Read ODT assertion to ODT de-assert delay (in DRAM clocks).\r\n"
"      [p]DDR3L Equation: RDODTSTOP = 6.[/p]\r\n"
"      [p]DDR4 Equation: RDODTSTOP = 5 + tRPRE.[/p]\r\n"
"      [p]Note: Add 1 if DOCRx.RDODTSTART = CL - CWL in 2N mode.[/p]"},
#else
{14, 17, 0x0000000000000000, "RW", "rdodtstop", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RO", "rsvd13", "Reserved."},
#else
{13, 13, 0x0000000000000000, "RO", "rsvd13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 12, 0x0000000000000000, "RW", "rdodtstart", "Specifies Read ODT assertion delay after Read Command (in DRAM clocks).\r\n"
"      [p]DDR3L/DDR4 Equation: RDODTSTART = CL - CWL + tWPRE - tRPRE.[/p]\r\n"
"      [p]Note: In DDR3L/DDR4 2N mode add 1 to enable termination at the start of read data burst.[/p]"},
#else
{9, 12, 0x0000000000000000, "RW", "rdodtstart", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 8, 0x0000000000000000, "RW", "wrodtstop", "Specifies number of clocks after ODT assertion that D-Unit deasserts ODT signal (in DRAM clocks).\r\n"
"      [p]LPDDR3 Equation: WRODTSTOP = RU(tODTon(max)/tCK) + RU((tDQSSmax+tWPST)/tCK) + BL/2 - RD(tODToffmin/tCK)[/p]\r\n"
"      [p]DDR3L Equation: WRODTSTOP = 6.[/p]\r\n"
"      [p]DDR4 Equation: WRODTSTOP = 5 + tWPRE.[/p]\r\n"
"      [p]Note: Add 1 if DOCRx.WRODTSTART = 0 in 2N mode.[/p]"},
#else
{5, 8, 0x0000000000000000, "RW", "wrodtstop", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO", "rsvd4", "Reserved."},
#else
{4, 4, 0x0000000000000000, "RO", "rsvd4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "wrodtstart", "Specifies number of clocks after Write command that D-Unit asserts ODT signal (in DRAM clocks).\r\n"
"      [p]LPDDR3 Equation: WRODTSTART = WL - RU(tODTon(max)/tCK) [/p]\r\n"
"      [p]DDR3L/DDR4 Equation: WRODTSTART = 0[/p]\r\n"
"      [p]Note: In DDR3L/DDR4 2N mode the value can be set to 0 to assert ODT one DRAM clock earlier than the Write Command (WR) or set to 1 to assert at the same clock as command (CS assertion).[/p]"},
#else
{0, 3, 0x0000000000000000, "RW", "wrodtstart", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo11[] = {{"D_CR_DOCRA", "", 0x0000002C, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields12[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "rsvd31_29", "Reserved."},
#else
{29, 31, 0x0000000000000000, "RO", "rsvd31_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "suspmop", "DDRIO PHY Power Mode Opcode: After the D-Unit has placed the DRAM devices in Self Refresh/PASR mode as the result of a SUSPEND/SUSPENDP message, it sends this 5-bit value to the DDRIO PHY to tell it which power saving mode it should enter.\r\n"
"  [p]Changing this register value while in SUSPEND will have no effect.[/p]\r\n"
"  [p]Note: This opcode cannot be a PM state where it disables PHY PLLs i.e PM7 in LPDDR PHY.[/p]"},
#else
{24, 28, 0x0000000000000000, "RW", "suspmop", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "rsvd23", "Reserved."},
#else
{23, 23, 0x0000000000000000, "RO", "rsvd23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "srpmclkw", "Specifies when it is safe to send PM message to the PHY. When enabled, D-Unit waits for SPID Clock to deassert before sending a PM message on SR entry.\r\n"
"  [list]\r\n"
"  [*]0: D-Unit will not wait for SPID_clk to deassert before sending the PM message to PHY.\r\n"
"  [*]1: D-Unit will wait for SPID_clk to deassert before sending PM message to the PHY.\r\n"
"      [/list]\r\n"
"  [p]Note: The value must be 1 when DYNPMOP = 7h.[/p]"},
#else
{22, 22, 0x0000000000000000, "RW", "srpmclkw", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 21, 0x0000000000000000, "RW", "dynpmop", "DDRIO PHY Power Mode Opcode:  After the D-Unit has placed the DRAM devices in Self Refresh mode as the result of a Dynamic Self-Refresh, it sends this 5bit value to the DDRIO PHY to tell it which power saving mode it should enter. \r\n"
"  [p]Changing this register value while in self-refresh will only change the PM state for the next entry in DynSR.[/p]"},
#else
{17, 21, 0x0000000000000000, "RW", "dynpmop", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynsren", "When set to 1, the D-Unit will automatically control DRAM Self Refresh entry and exit based on interface state and requests in pending queues. When there is no pending request in the queues and PMI is idle, then the D-Unit will place the DRAM devices in Self Refresh mode. The DRAM devices will be brought out of Self-Refresh when idle conditions don't hold."},
#else
{16, 16, 0x0000000000000000, "RW", "dynsren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "sredly", "Specifies the minimum time the D-Unit will wait before it enters Dynamic Self-Refresh mode when idle (in 16x DRAM Clocks). \r\n"
"      [p]Note: The value in this field needs to be minimum of 4 in functional mode and minimum of 50 in PSMI mode.[/p]"},
#else
{0, 15, 0x0000000000000000, "RW", "sredly", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo12[] = {{"D_CR_DPMC0", "", 0x00000030, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields13[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "rptclkgtdis", "Setting this bit to 0 allows majority of the repeaters between D-Unit and PHY to clock gate when there is no activity in order to save power.\r\n"
"      [list]\r\n"
"      [*]0 -  Enable Repeaters clock gating.  \r\n"
"      [*]1 -  Disable Repeaters clock gating.\r\n"
"      [/list]\r\n"
"      [p]Note: This is a de-feature bit and should be set to 0 for normal operation.[/p]\r\n"
"      [p]Note: The value should only change after DRAM Timing Registers (DTR) are programmed.[/p]"},
#else
{29, 29, 0x0000000000000000, "RW", "rptclkgtdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000001, "RW", "sbepclkgtdis", "Setting this bit to 0 enables the clock gating of IOSF-SB End Points in D-Unit and CPGC when there is no IOSF-SB activity in order to save power.\r\n"
"      [list]\r\n"
"      [*]0 -  Enable IOSF-SB EP clock gating.\r\n"
"      [*]1 -  Disable IOSF-SB clock gating.\r\n"
"      [/list] \r\n"
"      [p]Note: This is a de-feature bit and should be set to 0 for normal operation.[/p]\r\n"
"      [p]Note: The value should only change after DRAM Timing Registers (DTR) are programmed.[/p]"},
#else
{28, 28, 0x0000000000000001, "RW", "sbepclkgtdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "clkgtdis", "Setting this bit to 0 allows the majority of the D-Unit clocks to be gated off when there is no activity in order to save power. \r\n"
"  [p]When set to 1, D-Unit clockgating is disabled.[/p]\r\n"
"  [list]\r\n"
"  [*]0: Enable.  \r\n"
"  [*]1: Disable. \r\n"
"      [/list]\r\n"
"  [p]Note: This is a de-feature bit and should be set to 0 for normal operation.[/p]\r\n"
"      [p]Note: The value should only change after DRAM Timing Registers (DTR) are programmed.[/p]"},
#else
{27, 27, 0x0000000000000000, "RW", "clkgtdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "cstrist", "\r\n"
"  [list]\r\n"
"  [*]0: The DRAM CS pins associated with the enabled ranks are never tristated.  \r\n"
"  [*]1: The DRAM CS pins are tristated when DRAM clock is stopped or tristated.\r\n"
"  [/list]\r\n"
"  [p]Note: CS is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).[/p]"},
#else
{26, 26, 0x0000000000000000, "RW", "cstrist", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "cmdtrist", "\r\n"
"      [list]\r\n"
"      [*]00: The DRAM CA pins are never tristated. \r\n"
"      [*]01: The DRAM CA pins are only tristated when all enabled CKE pins are low.\r\n"
"      [*]10: The DRAM CA pins are tristated when not driving a valid command.\r\n"
"      [*]11: Reserved\r\n"
"      [/list]"},
#else
{24, 25, 0x0000000000000000, "RW", "cmdtrist", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "pasr", "This is the Segment Mask used for the MRW to enable PASR during SUSPENDP (Partial Array Self Refresh entry)."},
#else
{16, 23, 0x0000000000000000, "RW", "pasr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "pclsto", "Specifies the time from the last access of a DRAM page until that page is scheduled to close by sending a Precharge command to DRAM (in 16 x DRAM clocks)."},
#else
{8, 15, 0x0000000000000000, "RW", "pclsto", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "pclstodis", "When disabled, D-Unit will not close the DRAM page when idle. \r\n"
"  [list]\r\n"
"  [*]0: Enable page close timer.  \r\n"
"  [*]1: Disable page close timer (Used during DRAM init and DDRIO training).\r\n"
"  [/list]"},
#else
{7, 7, 0x0000000000000000, "RW", "pclstodis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "rsvd6", "Reserved."},
#else
{6, 6, 0x0000000000000000, "RO", "rsvd6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "odttrist", "\r\n"
"      [list]\r\n"
"      [*]0: The DRAM ODT pins associated with the enabled ranks are never tristated.  \r\n"
"      [*]1: DRAMs ODT pins are tristated when DRAM clock is stopped or tristated.\r\n"
"      [/list]\r\n"
"      [p]Note: ODT is not tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1)[/p]"},
#else
{5, 5, 0x0000000000000001, "RW", "odttrist", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000001, "RW", "enckstp", "Enable/Disable CK Stop/Tristate During Power down.\r\n"
"  [list]\r\n"
"  [*]00: Disable CK Stop/Tristate During Power down. \r\n"
"  [*]01: Enable CK Stop During Power down. \r\n"
"  [*]10: Enable CK Tristate During Power down. \r\n"
"  [*]11: Reserved\r\n"
"      [/list]\r\n"
"      [p]Note: CK is not stopped or tristated when global tristate flow is disabled (DCBR.TRISTDIS = 1).[/p]"},
#else
{3, 4, 0x0000000000000001, "RW", "enckstp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000000, "RW", "lpmodeop", "D-Unit will send the value in this register after it has entered Powerdown Mode and has stopped/tristated the clock. \r\n"
"  [p]00: Disable LPMode.[/p]\r\n"
"      [p]Note: LPMODE entry is not possible when global tristate flow is disabled (DCBR.TRISTDIS = 1).[/p]"},
#else
{1, 2, 0x0000000000000000, "RW", "lpmodeop", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dispwrdn", "Setting this bit to 1 disables dynamic control of DRAM Power-Down entry and exit by keeping the CKE pins driven high. BIOS may set it to 1 during DRAM initialization and DDRIO training. This bit should be set to 0 for normal operation. \r\n"
"  [list]\r\n"
"  [*]0: The D-Unit dynamically controls the CKE pins to place the DRAM devices in Power Down mode and bring them out of Power Down mode. \r\n"
"  [*]1: The D-Unit constantly drives the CKE pins high to keep the DRAM devices from entering Power Down mode when ranks are idle. \r\n"
"  [/list]\r\n"
"  [p]Note: This bit is overridden if CKEMODE = 1.[/p]\r\n"
"  [p]This bit does not control CKE behavior on SR entry/exit.[/p]"},
#else
{0, 0, 0x0000000000000000, "RW", "dispwrdn", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo13[] = {{"D_CR_DPMC1", "", 0x00000034, 14, 0x00000000FFFFFFFF, 0x0000000010000028}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields14[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000001, "RW", "mntchnblktime", "Specifies the amount of time that D-unit will block the channel before any DRAM maintenance operation is issued. (in SPIDclk)"},
#else
{29, 31, 0x0000000000000001, "RW", "mntchnblktime", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 28, 0x0000000000000000, "RW", "mntdlycascount", "When a critical read request is pending in RPQ and a maintenance operation (MRR, ZQCal, Ref, etc.) needs to be performed, D-unit delays the maintenance operation and allows this many read or write requests to be scheduled before allowing the maintenance operation.\r\n"
"      [p]Note: This mode does not apply to Panic refreshes.[/p]"},
#else
{25, 28, 0x0000000000000000, "RW", "mntdlycascount", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 24, 0x0000000000000000, "RO", "rsvd24_22", "Reserved."},
#else
{22, 24, 0x0000000000000000, "RO", "rsvd24_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "disrefdbtclr", "When set, D-Unit will not clear refresh debt before Self Refresh SR Entry:\r\n"
"  [list]\r\n"
"  [*]0: D-Unit sends all postponed REF commands to DRAM before it enters Self Refresh. \r\n"
"  [*]1: D-Unit enters SR without clearing the Refresh Debt (for Debug only).\r\n"
"  [/list]"},
#else
{21, 21, 0x0000000000000000, "RW", "disrefdbtclr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "refskwdis", "Disables Skewing of Refresh Counting between Ranks.  \r\n"
"  [p]Each rank has its own refresh counter. By default incrementing these refresh counters are skewed by 1/2 the tREFI period. Setting this bit to a 1 disables this feature and all refresh counters will increment at the same time per tREFI period. Skewing the tREFI counters can improve performance since traffic to all ranks does not have to be blocked to perform refresh.[/p] \r\n"
"  [list]\r\n"
"  [*]0: Incrementing the refresh counters are skewed by 1/2 tREFI period. \r\n"
"  [*]1: All refresh counters will increment at the same time per tREFI period. \r\n"
"  [/list]\r\n"
"  [p]Reserved in BXT0/1.[/p]"},
#else
{20, 20, 0x0000000000000000, "RW", "refskwdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RO", "rsvd19_18", "Reserved."},
#else
{18, 19, 0x0000000000000000, "RO", "rsvd19_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RO", "rsvd17_16", "Reserved."},
#else
{16, 17, 0x0000000000000000, "RO", "rsvd17_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "extrarefdbt", "When set to 1, D-Unit adds one extra refresh debit (for a total of two) on Self-refresh exit."},
#else
{15, 15, 0x0000000000000000, "RW", "extrarefdbt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000001, "RW", "minrefrate", "Ensures that refresh rate never drops below a certain limit regardless of TQ polling. \r\n"
"  [list]\r\n"
"  [*]000: Stop issuing refresh commands and accumulating refresh debits. (does not stop tREFI counter). \r\n"
"  [*]001: 0.25x refresh rate (i.e. 4x tREFI same as no limit).\r\n"
"  [*]010: 0.5x refresh rate (i.e. 2x tREFI). \r\n"
"  [*]011: 1x refresh rate (i.e. 1x tREFI). \r\n"
"  [*]100: 2x refresh rate (i.e. 0.5x tREFI). \r\n"
"  [*]101: 4x refresh rate (i.e. 0.25x tREFI). \r\n"
"  [*]110: 4x refresh rate with derating forced on i.e. 0.25x tREFI. \r\n"
"  [*]111: Reserved.\r\n"
"  [/list]"},
#else
{12, 14, 0x0000000000000001, "RW", "minrefrate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "refwmpnc", "When the Refresh counter per rank is greater than this value, the D-Unit will send a REF command to the rank regardless of pending requests.\r\n"
"  [p]Note: REFWMPNC must be greater than or equal to REFWMHI and greater than 2, Max Value must be less than 8 to not violate 9xtREFI JEDEC requirement.[/p]"},
#else
{8, 11, 0x0000000000000007, "RW", "refwmpnc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000005, "RW", "refwmhi", "When the Refresh counter per rank is greater than this value, the D-Unit will send a REF command to the rank if there is no critical priority requests in the pending queues.\r\n"
"  [p]Note: Value must be greater or equal to 1 and less than or equal to REFWMPNC.[/p]"},
#else
{4, 7, 0x0000000000000005, "RW", "refwmhi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x0000000000000000, "RO", "rsvd3_1", "Reserved."},
#else
{1, 3, 0x0000000000000000, "RO", "rsvd3_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "orefdis", "Disable opportunistic scheduling of refresh.\r\n"
"      [list]   \r\n"
"  [*]0: D-Unit will send a REF command only if there is no pending request to that rank.\r\n"
"  [*]1: D-Unit will not send any opportunistic refreshes. Refresh commands are only sent when the refresh counter is greater than REFWMHI.\r\n"
"  [/list]\r\n"
"  [p]Note: When set, DISREFDBTCLR must also be set to be able to enter SR.[/p]"},
#else
{0, 0, 0x0000000000000000, "RW", "orefdis", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo14[] = {{"D_CR_DRFC", "", 0x00000038, 13, 0x00000000FFFFFFFF, 0x0000000020001750}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields15[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "early_dq_en", "Enables D-unit to send the write data to the PHY one clock earlier than WL value (WL - 1). \r\n"
"      [p]Note: Applicable to DDR3L and DDR4 only.[/p]"},
#else
{31, 31, 0x0000000000000000, "RW", "early_dq_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "bgf_early_rddata_valid", "Specifies the number of clocks the D-Unit sends the read data valid through the BGF earlier as compared to the data.\r\n"
"      [list]\r\n"
"      [*]00: Always write read valid in same SPID clock as data (STATIC_0). \r\n"
"      [*]01: Always write read valid one SPID clock before data (STATIC_1). \r\n"
"      [*]10: Write read valid up to 2 SPID clocks before data (DYNAMIC). \r\n"
"      [*]11: Reserved\r\n"
"      [/list]"},
#else
{29, 30, 0x0000000000000000, "RW", "bgf_early_rddata_valid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 28, 0x0000000000000000, "RW", "spid_early_rddata_valid", "Specifies the delay in SPID clocks from RDDATA_VALID assertion to actual data on SPID. The value should match what is programmed in DDRIO (PHY)."},
#else
{27, 28, 0x0000000000000000, "RW", "spid_early_rddata_valid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 26, 0x000000000000001C, "RW", "wpqcount", "Used to limit the number of available slots in Write Pending Queue/ Write Data Buffer. WPQCOUNT will only recognize changes when PMI ISM is not active."},
#else
{21, 26, 0x000000000000001C, "RW", "wpqcount", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000010, "RW", "rpqcount", "Used to limit the number of entries in Read Pending Queue. RPQCOUNT will only recognize changes when PMI ISM is not active."},
#else
{16, 20, 0x0000000000000010, "RW", "rpqcount", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "rsvd15", "Reserved."},
#else
{15, 15, 0x0000000000000000, "RO", "rsvd15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x0000000000000007, "RW", "blkrdbf_add_rddata_cr", "Number of additional  full cacheline (64B) read data return credits exposed to D-Unit when BLKRDBF is set.\r\n"
"      [p]Note: The value in this field has no effect on Read return credits when BLKRDBF is not set.[/p]"},
#else
{10, 14, 0x0000000000000007, "RW", "blkrdbf_add_rddata_cr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "inordermode", "\r\n"
"  [list]\r\n"
"  [*]0h: In order mode disabled: Commands are sent out of order. \r\n"
"  [*]1h: Partial in order mode: Read and Write CAS commands are sent in the order they were recieved. ACT and PRE can go out of order. \r\n"
"  [*]2h: Full in order mode serialized test: All DRAM commands CAS ACT PRE associated with a PMI request are issued to DDR before any DRAM commands for a subsequent PMI request.  \r\n"
"  [*]3h: Reserved.   \r\n"
"  [/list]\r\n"
"  In order modes should be enabled during init/training/CPGC testing. Should never be changed while the D-Unit queues are nonempty. For WIO2, when in-order mode is enabled (01 or 10), D_CR_DSCH_BYPASSEN must be set to 0"},
#else
{8, 9, 0x0000000000000000, "RW", "inordermode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "bypassen", "When set new page hit/empty read requests will bypass D-Unit pipeline stages to save latency 0 - Disable Idle Bypass 1 - Enable Idle Bypass Note: Only applies to WIO2, this bit is reserved for other technologies"},
#else
{7, 7, 0x0000000000000000, "RW", "bypassen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "blkrdbf", "When set D-Unit stops scheduling new read commands to DRAM when the read data buffer (RDB) is full."},
#else
{6, 6, 0x0000000000000000, "RW", "blkrdbf", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "stretchmode", "When stretch mode is enabled, commands are initiated only on Phase 0 of SPIDClk. \r\n"
"  [list]\r\n"
"  [*]00: Stretch mode is disabled. \r\n"
"  [*]01: Commands are initiated on Phase 0 of every SPID clocks. \r\n"
"  [*]10: Commands are initiated on Phase 0 of even SPID clocks. \r\n"
"  [*]11: Commands are initiated on Phase 0 of odd SPID clocks.\r\n"
"  [/list]"},
#else
{4, 5, 0x0000000000000000, "RW", "stretchmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000008, "RW", "tmwr_ta_delta", "The value in this register is subtracted from Masked Write to Read, Masked Write to Write and Masked Write to Masked Write turnaround times to account for half BL MWr commands in LPDDR4 and WIO2. \r\n"
"  [list]\r\n"
"  [*]LPDDR4: = MWr tCCD = MWr BL/2 = 8.\r\n"
"  [*]WIO2: = MWr tCCD = MWr BL/2 = 2.\r\n"
"  [/list]"},
#else
{0, 3, 0x0000000000000008, "RW", "tmwr_ta_delta", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo15[] = {{"D_CR_DSCH", "", 0x0000003C, 12, 0x00000000FFFFFFFF, 0x0000000003901C08}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields16[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "zqcaltype", "Determines whether the ZQ Calibration is a long or short calibration command (due to ZQCALSTRT). \r\n"
"      [p]0: Short calibration (ZQCS).[/p]\r\n"
"      [p]1: Long calibration (ZQCL).[/p]"},
#else
{31, 31, 0x0000000000000000, "RW", "zqcaltype", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/V", "zqcalstrtr1", "Set this bit to 1 to start the ZQ calibration sequence on Rank 1. This bit will remain a 1 until the ZQ calibration is complete for rank 1, then it will return to 0. \r\n"
"      [p]0: ZQ calibration is done.[/p] \r\n"
"      [p]1: ZQ calibration has started and is in progress.[/p]"},
#else
{30, 30, 0x0000000000000000, "RW/V", "zqcalstrtr1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW/V", "zqcalstrtr0", "Set this bit to 1 to start the ZQ calibration sequence on Rank 0. This bit will remain a 1 until the ZQ calibration is complete for rank 0, then it will return to 0. \r\n"
"      [p]0: ZQ calibration is done.[/p] \r\n"
"      [p]1: ZQ calibration has started and is in progress.[/p]"},
#else
{29, 29, 0x0000000000000000, "RW/V", "zqcalstrtr0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 28, 0x0000000000000000, "RO", "rsvd28_23", "Reserved."},
#else
{23, 28, 0x0000000000000000, "RO", "rsvd28_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "srxzqc", "\r\n"
"  [list]\r\n"
"  [*]00: On DynSR exit ZQ timer determines the ZQ type. When the state is lost (i.e due to AutoPG/S0ix) ZQCL is always performed. \r\n"
"  [*]01: Always perform ZQCL after self refresh exit. In LPDDR4, ZQ with traffic blocked.\r\n"
"  [*]10: Always perform ZQCS on SR exit. For LPDDR4, ZQ while traffic is allowed. \r\n"
"  [*]11: No ZQCL commands are sent (it disables ZQCAL commands on SR exit).\r\n"
"  [/list]"},
#else
{21, 22, 0x0000000000000000, "RW", "srxzqc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 20, 0x0000000000000000, "RO", "rsvd20_18", "Reserved."},
#else
{18, 20, 0x0000000000000000, "RO", "rsvd20_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "zqclmode", "Specifies how ZQCal commands are sent to different ranks.\r\n"
"  [list]\r\n"
"  [*]0: ZQCal commands are sent in parallel to all ranks. \r\n"
"  [*]1: ZQCal commands are sent serially to each rank.\r\n"
"  [/list]"},
#else
{17, 17, 0x0000000000000000, "RW", "zqclmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "zqcdis", "\r\n"
"  [list]\r\n"
"  [*]0: Periodic ZQ Calibration is Enabled. \r\n"
"  [*]1: Disable periodic ZQ Calibration.\r\n"
"  [/list]"},
#else
{16, 16, 0x0000000000000000, "RW", "zqcdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 13, 0x0000000000001057, "RW", "zqint", "Specifies the time interval between two ZQCS (LPDDR3/DDR3L/DDR4) or ZQ Start (LPDDR4) commands to a DRAM device. (in RTC 32.8KHz clocks)"},
#else
{0, 13, 0x0000000000001057, "RW", "zqint", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo16[] = {{"D_CR_DCAL", "", 0x00000040, 10, 0x00000000FFFFFFFF, 0x0000000000001057}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields17[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "rsvd31_20", "Reserved."},
#else
{20, 31, 0x0000000000000000, "RO", "rsvd31_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "mansrdis", "When set before a SUSPEND/WAKE command, D-Unit will not send SR entry/exit commands to DRAM."},
#else
{19, 19, 0x0000000000000000, "RW", "mansrdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "cpgclock", "Write a 1 to this bit to lock and clock gate the CPGC."},
#else
{18, 18, 0x0000000000000000, "RW", "cpgclock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000001, "RW", "cpgcwarmrst", "Write a 1 to this bit to send warm reset to CPGC and then set to 0 to deassert the reset. Value of this field must be 0 before CPGC funtional usage is enabled."},
#else
{17, 17, 0x0000000000000001, "RW", "cpgcwarmrst", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "coldwake", "This bit must be set and then cleared by BIOS during cold/warm reset."},
#else
{16, 16, 0x0000000000000000, "RW", "coldwake", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "rsvd15_13", "Reserved."},
#else
{13, 15, 0x0000000000000000, "RO", "rsvd15_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "odtmode", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit auto controls the ODT pins based on DRAM transactions. \r\n"
"  [*]1: The value of ODTVAL directly controls the ODT pins.\r\n"
"  [/list]"},
#else
{12, 12, 0x0000000000000000, "RW", "odtmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO", "rsvd11_10", "Reserved."},
#else
{10, 11, 0x0000000000000000, "RO", "rsvd11_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "odtval", "Each bit of ODTVAL directly controls an ODT pin when ODTMODE is set to 1.  Used only during init flow. Note: Reserved for BXT0/1"},
#else
{8, 9, 0x0000000000000000, "RW", "odtval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "rsvd7_5", "Reserved."},
#else
{5, 7, 0x0000000000000000, "RO", "rsvd7_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ckemode", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit auto controls the CKE pins based on PowerDown and Self Refresh entry and exit.  \r\n"
"  [*]1: The value of CKEVAL field directly controls the CKE pins.\r\n"
"  [/list]"},
#else
{4, 4, 0x0000000000000000, "RW", "ckemode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "rsvd3_2", "Reserved."},
#else
{2, 3, 0x0000000000000000, "RO", "rsvd3_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "ckeval", "Each bit of CKEVAL directly controls a CKE pin when CKEMODE is set to 1.  \r\n"
"  [p]Used only during init flow.[/p]"},
#else
{0, 1, 0x0000000000000000, "RW", "ckeval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo17[] = {{"D_CR_DRMC", "", 0x00000044, 13, 0x00000000FFFFFFFF, 0x0000000000020000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields18[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 29, 0x0000000000000000, "RW", "mr_value2", "MR3 Shadow Register (DDR4):\r\n"
"      [p]BIOS writes the correct value of MR3 register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the MR3 into DDR4 to enter and exit MPR mode.[/p]"},
#else
{16, 29, 0x0000000000000000, "RW", "mr_value2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 13, 0x0000000000000000, "RW", "mr_value", "MR3 Shadow Register (WIO2): \r\n"
"      [p]BIOS sets the value of this field at boot time based on the DRAM device configuration. D-Unit merges the value in MR3_THERM_OFFSET with this field and writes the result into DRAM MR3 [/p]\r\n"
"      [p]MR2 Shadow Register (DDR3L):[/p]\r\n"
"      [p]BIOS writes the correct value of MR2 register in DDR3L into this field at boot time. D-Unit modifies one bit and rewrites the MR2 into DDR3L DRAM before SR entry.[/p]\r\n"
"      [p]MR4 Shadow Register (DDR4):[/p]\r\n"
"      [p]BIOS writes the correct value of MR4 register in DDR4 into this field at boot time. D-Unit modifies one bit and rewrites the MR4 into DDR4 DRAM after temperature read out.[/p]"},
#else
{0, 13, 0x0000000000000000, "RW", "mr_value", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo18[] = {{"D_CR_MR_SHADOW", "", 0x00000048, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields19[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "vnn_timer_en", "\r\n"
"  [list]\r\n"
"  [*]0: The D-Unit VNN Scaling Timer is disabled. \r\n"
"  [*]1: The D-Unit VNN Scaling Timer is enabled.\r\n"
"  [/list]"},
#else
{31, 31, 0x0000000000000000, "RW", "vnn_timer_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 30, 0x0000000000000000, "RO", "rsvd30_12", "Reserved."},
#else
{12, 30, 0x0000000000000000, "RO", "rsvd30_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 11, 0x0000000000000000, "RW", "vnn_timer_time", "The final timer value (in 16 x DRAM clocks)."},
#else
{0, 11, 0x0000000000000000, "RW", "vnn_timer_time", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo19[] = {{"D_CR_VNNTIMER", "", 0x0000004C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields20[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000003, "RW/V", "tqdatar1", "If Rank 1 is disabled, this value will remain zero. \r\n"
"  [p]This field contains the data of the last temperature sensor read from Rank 1 DRAM Mode Register. It is overwritten with each command.[/p]"},
#else
{29, 31, 0x0000000000000003, "RW/V", "tqdatar1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 28, 0x0000000000000003, "RW/V", "tqdatar0", "This field contains the data of the last temperature sensor read from Rank 0 DRAM Mode Register. It is overwritten with each command."},
#else
{26, 28, 0x0000000000000003, "RW/V", "tqdatar0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 25, 0x0000000000000000, "RO", "rsvd25_22", "Reserved."},
#else
{22, 25, 0x0000000000000000, "RO", "rsvd25_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 21, 0x0000000000000000, "RW", "tqpollper", "This sets the frequency by which the D-Unit initiates temperature sensor read from DRAM mode register to determine required refresh rate (in 4x tREFI units)."},
#else
{8, 21, 0x0000000000000000, "RW", "tqpollper", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "tcrren", "When set, after a DRAM temperature read out (MPR sequence), D-unit writes a 1 to bit 2 of MR_SHADOW.MR_VALUE when temperature sensor read out for that rank indicates a value higher than 0x1, and writes a 0 to that bit otherwise. The new MR_VALUE is then written into MR4 of DDR4 for each enabled rank."},
#else
{7, 7, 0x0000000000000000, "RW", "tcrren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW/V", "tqpoll_start_r1", "When set Dunit will initiate temperature sensor read for Rank 1.\r\n"
"      [p]Hardware will clear the bit once the MR read command is issued for this rank.[/p]\r\n"
"      [p]Note:  TQPOLLEN mus be 0 before this bit is set.[/p]"},
#else
{6, 6, 0x0000000000000000, "RW/V", "tqpoll_start_r1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW/V", "tqpoll_start_r0", "When set Dunit will initiate temperature sensor read for Rank 0.\r\n"
"      [p]Hardware will clear the bit once the MR read command is issued for this rank.[/p]\r\n"
"      [p]Note:  TQPOLLEN mus be 0 before this bit is set.[/p]"},
#else
{5, 5, 0x0000000000000000, "RW/V", "tqpoll_start_r0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "srten", "When set, before every Self refresh entry, D-Unit writes a 1 to bit 7 of MR_SHADOW.MR_VALUE when TQDATA for that rank indicates a value higher then 0x3, and writes a 0 to that bit otherwise. The new MR_VALUE is then written into MR2 of DDR3 for each enabled rank."},
#else
{4, 4, 0x0000000000000000, "RW", "srten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "enderate", "When set to 1, the Dynamic Timing Derating is enabled. When the D-Unit determines (via TQ polling) that the DRAM requires timing derating in addition to refresh interval adjustment, the D-Unit will automatically adjust the relevant timing parameters."},
#else
{3, 3, 0x0000000000000001, "RW", "enderate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "tqdatapushen", "When set to 1, D-Unit pushes the data form the last temperature sensor read to a punit register."},
#else
{2, 2, 0x0000000000000000, "RW", "tqdatapushen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "tqpollsren", "This bit enables temperature sensor read on Self Refresh Exit. If disabled, D-Unit will not initiate MR Read sequence to read temperature value on Self-Refresh exit."},
#else
{1, 1, 0x0000000000000000, "RW", "tqpollsren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "tqpollen", "This bit enables periodic TQ Poll. If disabled, D-Unit will not read the DRAM's temperature sensor value periodically."},
#else
{0, 0, 0x0000000000000000, "RW", "tqpollen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo20[] = {{"D_CR_TQCTL", "", 0x00000050, 12, 0x00000000FFFFFFFF, 0x000000006C000008}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields21[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "rsvd31_16", "Reserved."},
#else
{16, 31, 0x0000000000000000, "RO", "rsvd31_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x0000000000000000, "RO", "rsvd15_11", "Reserved."},
#else
{11, 15, 0x0000000000000000, "RO", "rsvd15_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "mr4_adder", "D-Unit adds the value of this field to TQDATA read from MR4 the resulting value is used to control refresh rate and AC timing derating."},
#else
{8, 10, 0x0000000000000000, "RW", "mr4_adder", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x0000000000000000, "RO", "rsvd7_3", "Reserved."},
#else
{3, 7, 0x0000000000000000, "RO", "rsvd7_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW/V", "mr3_offset_update", "When set, D-Unit writes the merged value of MR3_VALUE and MR3_THERM_OFFSET into MR3 of DRAM. D-Unit clears this bit once the value is written."},
#else
{2, 2, 0x0000000000000000, "RW/V", "mr3_offset_update", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "mr3_therm_offset", "(WIO2 only) Everytime MR3_OFFSET_UPDATE is set, D-Unit merges the value in this field with MR3_VALUE and writes the result to MR3 in DRAM"},
#else
{0, 1, 0x0000000000000000, "RW", "mr3_therm_offset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo21[] = {{"D_CR_TQOFFSET", "", 0x00000054, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields22[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/V", "ic", "Indicates that initialization of the D-Unit has been completed. Memory accesses are permitted and maintenance operation begins. Until this bit is set to a 1, the memory controller will not accept DRAM requests from the Bunit/GSA/2LM (PMI ISMs will not leave idle).  \r\n"
"  [p]Note: Set this bit to 1 only when all other D-Unit registers have been configured. Usually set at the last configuration step by BIOS on cold/warm reset. D-Unit hardware sets this bit on SR exit.[/p]"},
#else
{31, 31, 0x0000000000000000, "RW/V", "ic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO/V", "dioic", "Status indication that the DDRIO PHY initialization is complete reflects the status spid_init_complete signal."},
#else
{30, 30, 0x0000000000000000, "RO/V", "dioic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "rsvd29", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "rsvd29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "pmictl", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit PMI is connected to Bunit/GSA/2LM. \r\n"
"  [*]1: D-Unit PMI is connected to CPGC. \r\n"
"      [/list]\r\n"
"      [p]Note: D_CR_DSCH_BYPASSEN must be set to 0 in CPGC mode.[/p]\r\n"
"  [p]Note: PMI must be idle and D-Unit BGF_RUN = 0 before changing the value in this register.[/p]"},
#else
{28, 28, 0x0000000000000000, "RW", "pmictl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 27, 0x0000000000000000, "RO", "rsvd27_8", "Reserved."},
#else
{8, 27, 0x0000000000000000, "RO", "rsvd27_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "rsvd7_4", "Reserved."},
#else
{4, 7, 0x0000000000000000, "RO", "rsvd7_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "psmien", "When enabled, D-Unit will synchronize clock crossing signals.\r\n"
"  [list]\r\n"
"  [*]0: PSMI Mode is disabled. \r\n"
"  [*]1: PSMI Mode is enabled.\r\n"
"      [/list]\r\n"
"  [p]Note: Change only allowed when D-Unit is idle.[/p]"},
#else
{3, 3, 0x0000000000000000, "RW", "psmien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "mntrst", "Writing a 1 to this field resets all maintenance timers. Clears all states and also clears refresh debt queues. This bit must be cleared by software after at least 3 SPID clocks."},
#else
{2, 2, 0x0000000000000000, "RW", "mntrst", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "mnten", "Setting this field to 1 enables all maintenance operations. When DCO.IC is set, the maintenance operations are enabled irrespective of the value of this field."},
#else
{1, 1, 0x0000000000000000, "RW", "mnten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "rsvd0", "Reserved."},
#else
{0, 0, 0x0000000000000000, "RO", "rsvd0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo22[] = {{"D_CR_DCO", "", 0x00000058, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields23[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{11, 31, 0x0000000000000000, "RO", "rsvd31_11", "Reserved."},
#else
{11, 31, 0x0000000000000000, "RO", "rsvd31_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "pgtbl_bypass_en", "When set, D-unit scheduler will bypass page table lookups when scheduling read/write and assumes a Page Hit. So D-unit will only send RD/WR CAS command (without the ACT). After issuing the CAS command, D-unit will also not update the Page Table status to avoid issuing PRE due to access to same page."},
#else
{10, 10, 0x0000000000000000, "RW", "pgtbl_bypass_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "cpgc_ecc_bypass_en", "When set, CPGC will have full control of the Write ECC data and bypasses D-Unit's runtime ECC and data scrambling function. Also when enabled, read ECC error detection/correction/reporting logic is disabled."},
#else
{9, 9, 0x0000000000000000, "RW", "cpgc_ecc_bypass_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "catrainen", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit is not in JEDEC CA Training Mode. \r\n"
"  [*]1: D-Unit is in JEDEC CA Training Mode.\r\n"
"  [/list]"},
#else
{8, 8, 0x0000000000000000, "RW", "catrainen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "dqcalen", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit is not in DQ Calibration Mode. \r\n"
"  [*]1: D-Unit is in DQ Calibration Mode.\r\n"
"  [/list]"},
#else
{7, 7, 0x0000000000000000, "RW", "dqcalen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "blkphaseb", "The D-Unit runs at half (LPDDR3/WIO2/DDR3L) or quarter (LPDDR4/DDR4) the frequency of the DRAM clock to save power. In order to issue back-to-back commands on every DRAM clock cycle, the D-Unit has to schedule two/four commands per D-Unit clock. Therefore, it processes requests through separate arbitration paths labeled as Phase_0, Phase_1, Phase_2 and Phase_3.  \r\n"
"      [p]In LPDDR3/WIO2/DDR3 case setting this bit to a 1 will disable Phase_1 and all memory requests will be processed through Phase_0 arbitration path. With only Phase_0 enabled, the DRAM device will never see back-to-back commands. The best it will see is a command every other DRAM clock cycle.[/p]\r\n"
"      [p]In LPDDR4 case, each command is two DRAM clocks and they are sent in two consecutive phases. Also, most of the LPDDR4 operations are broken into two commands that have to be sent back-to-back. Therefore, setting this bit to 1 will disable initiating *new* commands on Phase_1, Phase_2 and Phase_3.[/p]\r\n"
"      [p]in DDR4, D-unit schedules command through Phase_0 and Phase_2. Setting this bit disables new commands from being scheduled on Phase_2, so the DRAM will only see one command every 4 DRAM clocks.[/p] \r\n"
"      [p]0: No block[/p]\r\n"
"      [p]1: Block [/p]\r\n"
"      [p]Note: This bit does/must not impact the CPGCs ability to send requests to the SPID in Phase 1/2/3.  D-Unit arbiter comprehends this bit to issue 1 Command per SPIDCLK when set versus 2 Commands per SPIDCLK when not set.[/p]\r\n"
"      [p]Note 2: Setting this bit will not affect commands issued via the DRAM CMD register interface as those bypass the arbiter entirely. So it is possible to see commands issued on phase 1/2/3 when the DRAM_Command.M2N bit is set.[/p]\r\n"
"      [p]Note 3: When DRAM_Timing_Register_3A.TCMD is set to 2N mode commands can only win through the phase 0 arbitration path but it is possible to see DDR3 and DDR4 commands issued on phase 1 due to the nature of 2N delaying sending the command until the second DRAM clock.[/p]"},
#else
{6, 6, 0x0000000000000000, "RW", "blkphaseb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "blkwpqf", "Block Processing Write Requests until WPQ is Full. \r\n"
"  [p]When this bit is set to 1, the D-Unit is blocked from processing any of the requests in the WPQ until it is full. The full level is based on the WPQCOUNT value.[/p] \r\n"
"  [list]\r\n"
"  [*]0: No block. \r\n"
"  [*]1: Block.\r\n"
"  [/list]\r\n"
"  [p]Note: Once WPQ is full, it is unblocked until an entry is deallocated. So there could be more than one write scheduled during that window.[/p]"},
#else
{5, 5, 0x0000000000000000, "RW", "blkwpqf", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "blkrpqf", "Block Processing Read Requests until RPQ is Full. \r\n"
"  [p]When this bit is set to 1, the D-Unit is blocked from processing any of the requests in the RPQ until it is full. The full level is based on the RPQCOUNT value.[/p] \r\n"
"  [list]\r\n"
"  [*]0: No block.\r\n"
"  [*]1: Block.\r\n"
"  [/list]"},
#else
{4, 4, 0x0000000000000000, "RW", "blkrpqf", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "blkpre", "Block Precharge Commands to DRAM.\r\n"
"      [p]Note: setting this bit only blocks functional precharge commands issued via the RPQ and WPQ.  Precharge commands issued by the page table as part of the idle page timer feature and Precharge All commands issued as part of maintenance or CKE power down commands are not blocked by this bit. There are separate bits to enable/disable those functionalities.[/p]\r\n"
"  [list]\r\n"
"  [*]0: No Block. \r\n"
"  [*]1: Block.\r\n"
"  [/list]"},
#else
{3, 3, 0x0000000000000000, "RW", "blkpre", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "blkact", "Block Activate Commands to DRAM.\r\n"
"  [list]\r\n"
"  [*]0: No Block. \r\n"
"  [*]1: Block.\r\n"
"  [/list]"},
#else
{2, 2, 0x0000000000000000, "RW", "blkact", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "blkwr", "Block Write Commands to DRAM.\r\n"
"      [list]\r\n"
"  [*]0: No Block.\r\n"
"  [*]1: Block.\r\n"
"  [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "blkwr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "blkrd", "Block Read Commands to DRAM.\r\n"
"      [list]\r\n"
"  [*]0: No Block.\r\n"
"  [*]1: Block.\r\n"
"  [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "blkrd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo23[] = {{"D_CR_DTRC", "", 0x0000005C, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields24[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "rsvd31_12", "Reserved."},
#else
{12, 31, 0x0000000000000000, "RO", "rsvd31_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "pasrdis", "When set, D-Unit will not do a Mode Register Write to set the mask on SR entry due to SUSPENDP message and will not do Mode Register Write to clear the mask on SR due to WAKE message."},
#else
{11, 11, 0x0000000000000000, "RW", "pasrdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "tristdis", "When set, D-Unit will not be able to enter the state to stop/tristate the CK or tristate ODT/CS pins. \r\n"
"      [p]Note: Setting this bit also disables entry to LPMODEs.[/p]"},
#else
{10, 10, 0x0000000000000000, "RW", "tristdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "fullcmdcrdis", "When set to 1, D-Unit will always use credit metering to only advertise few initial credits to PMI requestor rather than advertising the full Pending Queue size."},
#else
{9, 9, 0x0000000000000000, "RW", "fullcmdcrdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "srxnrqdis", "Disable Accepting Requests During Self Refresh Exit (prevent D-Unit PMI ISM to leave idle).\r\n"
"  [list]\r\n"
"  [*]0: D-Unit accepts and loads PMI requests into the queues during Self Refresh exit period while maintenance operation are in progress.\r\n"
"  [*]1: D-Unit does not accept PMI requests until Self Refresh exit and all maintenance operations have completed.\r\n"
"  [/list]"},
#else
{8, 8, 0x0000000000000000, "RW", "srxnrqdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "mrrcp", "When set to 1, D-Unit closes all pages by issuing a PREALL before sending the MRR command to DRAM."},
#else
{7, 7, 0x0000000000000000, "RW", "mrrcp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RO", "rsvd6_5", "Reserved."},
#else
{5, 6, 0x0000000000000000, "RO", "rsvd6_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "pgtblstaten", "When set, D-Unit will update the status bits in PGTBLSTAT.PGTBLVLD. If not set, the status CR, will not reflect the latest status of the page table."},
#else
{4, 4, 0x0000000000000000, "RW", "pgtblstaten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "phyqtdis", "When set to 1, the D-Unit ignores PHY periodic quite time update requests. \r\n"
"  [p]Note: Setting this bit does not prevent PHY from requesting selfrefresh exit or bus quiet time.[/p]"},
#else
{3, 3, 0x0000000000000000, "RW", "phyqtdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "pmidis", "When set to 1, the PMI interface remains in idle state. \r\n"
"  [p]Note: Setting this bit does not force the PMI ISM to move to idle state.[/p]"},
#else
{2, 2, 0x0000000000000000, "RW", "pmidis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "cr_stat_en", "When set, D-Unit will update the status bits in D_CR_DSTAT. If not set, D_CR_DSTAT will not reflect the latest status of the D-Unit. \r\n"
"      [p]Note: This enable bit does not control Page Table Status Field in DSTAT CR.[/p]"},
#else
{1, 1, 0x0000000000000000, "RW", "cr_stat_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ecdis", "When set to 1, D-Unit error correction logic will be disabled. So all ECC errors would be considered uncorrectable."},
#else
{0, 0, 0x0000000000000000, "RW", "ecdis", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo24[] = {{"D_CR_DCBR", "", 0x000000A0, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields25[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "scrm_en", "When set to 1, data scrambling is enabled. When set to 0, data scrambling is disabled. Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1."},
#else
{31, 31, 0x0000000000000000, "RW", "scrm_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO", "rsvd30", "Reserved."},
#else
{30, 30, 0x0000000000000000, "RO", "rsvd30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "clockgate", "This field controls how the scrambler output code is clock gated to reduce power.\r\n"
"  [list]\r\n"
"  [*]00: Clock gate disabled.  \r\n"
"  [*]01: Clock Gate every 2 cycles.  \r\n"
"  [*]10: Clock Gate every 3 cycles.  \r\n"
"  [*]11: Clock Gate every 4 cycles.\r\n"
"  [/list]"},
#else
{28, 29, 0x0000000000000000, "RW", "clockgate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 27, 0x0000000000000000, "RO", "rsvd27_16", "Reserved."},
#else
{16, 27, 0x0000000000000000, "RO", "rsvd27_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "key", "Sets the key for the scrambler. The key should be a random value that is set following each cold boot."},
#else
{0, 15, 0x0000000000000000, "RW", "key", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo25[] = {{"D_CR_SCRAMCTRL", "", 0x000000A4, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields26[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "rsvd31_16", "Reserved."},
#else
{16, 31, 0x0000000000000000, "RO", "rsvd31_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x0000000000000000, "RO", "rsvd15_11", "Reserved."},
#else
{11, 15, 0x0000000000000000, "RO", "rsvd15_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO/V", "disr", "The D-Unit sets this bit to a 1 after it has placed the DRAM devices in Self Refresh mode.  \r\n"
"  [p]The D-Unit clears this bit when it brings the DRAM devices out of Self Refresh mode and completes maintenance operations.[/p]\r\n"
"  [list]\r\n"
"  [*]0: DRAM not in SelfRefresh.  \r\n"
"  [*]1: DRAM in SelfRefresh.\r\n"
"  [/list]\r\n"
"  [p]Note: If DRAM is in SR because of Dynamic SR reading any D-Unit register will bring DRAM out of SR.[/p]"},
#else
{10, 10, 0x0000000000000000, "RO/V", "disr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V", "refdbt1", "Rank 1 has a Refresh Debt."},
#else
{9, 9, 0x0000000000000000, "RO/V", "refdbt1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO/V", "refdbt0", "Rank 0 has a Refresh Debt."},
#else
{8, 8, 0x0000000000000000, "RO/V", "refdbt0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "invtech", "\r\n"
"  [list]\r\n"
"  [*]0: Selected DRAM technology is valid.\r\n"
"  [*]1: Selected DRAM technology is not supported.\r\n"
"  [/list]"},
#else
{7, 7, 0x0000000000000000, "RO/V", "invtech", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RO/V", "wpqempty", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit WPQ is not empty (pending write requests in WPQ).\r\n"
"  [*]1: D-Unit WPQ is empty.\r\n"
"  [/list]"},
#else
{6, 6, 0x0000000000000001, "RO/V", "wpqempty", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RO/V", "rpqempty", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit RPQ is not empty (pending read requests in RPQ).\r\n"
"  [*]1: D-Unit RPQ is empty.\r\n"
"  [/list]"},
#else
{5, 5, 0x0000000000000001, "RO/V", "rpqempty", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "rsvd4_0", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "rsvd4_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo26[] = {{"D_CR_DSTAT", "", 0x000000A8, 9, 0x00000000FFFFFFFF, 0x0000000000000060}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields27[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "rsvd31", "Reserved."},
#else
{31, 31, 0x0000000000000000, "RO", "rsvd31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 30, 0x0000000000000000, "RW", "address", "Specifies the PMI address of the write transaction to be injected with the error. Only applicable to Write transactions. Read/under-fill read of the partial write operation is not affected."},
#else
{1, 30, 0x0000000000000000, "RW", "address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "rsvd0", "Reserved."},
#else
{0, 0, 0x0000000000000000, "RO", "rsvd0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo27[] = {{"D_CR_ERR_INJ", "", 0x000000AC, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields28[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "rsvd31_4", "Reserved"},
#else
{4, 31, 0x0000000000000000, "RO", "rsvd31_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "sel_hi", "0 - Uncorrectable Error (UE) is armed for write address matching to inject UE by using the same poisoning scheme, i.e. inverting corresponding write ECC[6:0] on every QW of the 32B data. [br]1 - Correctable Error (CE) is armed for write address matching to inject CE by inverting corresponding write ECC[0] on every QW of the 32B data."},
#else
{3, 3, 0x0000000000000000, "RW", "sel_hi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "en_hi", "When set the error injection is continuously armed for higher 32B of D_CR_ERR_INJ_ADDR write address matching until it is cleared. "},
#else
{2, 2, 0x0000000000000000, "RW", "en_hi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "sel_lo", "0 - Uncorrectable Error (UE) is armed for write address matching to inject UE by using the same poisoning scheme, i.e. inverting corresponding write ECC[6:0] on every QW of the 32B data. [br]1 - Correctable Error (CE) is armed for write address matching to inject CE by inverting corresponding write ECC[0] on every QW of the 32B data."},
#else
{1, 1, 0x0000000000000000, "RW", "sel_lo", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "en_lo", "When set, the error injection is continuously armed for lower 32B of D_CR_ERR_INJ_ADDR write address matching until it is cleared. "},
#else
{0, 0, 0x0000000000000000, "RW", "en_lo", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo28[] = {{"D_CR_ERR_INJ_CTL", "", 0x000000B0, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields29[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/V", "clear", "Setting this bit to one clears all fields in this register, including itself."},
#else
{31, 31, 0x0000000000000000, "RW/V", "clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "ecc_visa", "Select ECC or PMI byte on VISA : \r\n"
"      [list]\r\n"
"      [*]00: ECC byte, \r\n"
"      [*]01: PMI Data Byte [7:0],\r\n"
"      [*]10: PMI Data Byte [63:56],\r\n"
"      [*]11: PMI Data Byte [255:248]\r\n"
"      [/list]"},
#else
{29, 30, 0x0000000000000000, "RW", "ecc_visa", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW/V", "cerr", "This bit is set when a correctable single-bit error occurs on a memory read data transfer.  When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. A multiple bit error that occurs after this bit is set will override the address/error syndrome information."},
#else
{28, 28, 0x0000000000000000, "RW/V", "cerr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW/V", "merr", "This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer.  When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared."},
#else
{27, 27, 0x0000000000000000, "RW/V", "merr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 26, 0x0000000000000000, "RW/V", "err_burst", "Burst number (in BL8) of the error within a chunk."},
#else
{25, 26, 0x0000000000000000, "RW/V", "err_burst", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW/V", "err_chunk", "Chunk number of the error. [br]0 - lower 32B chunk has error if MERR/CERR is set [br]1 - higher 32B chunk has the error if MERR/CERR is set"},
#else
{24, 24, 0x0000000000000000, "RW/V", "err_chunk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW/V", "syndrome_qw", "ECC Syndrome for a QW (64 bit) within 32B Address"},
#else
{16, 23, 0x0000000000000000, "RW/V", "syndrome_qw", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW/V", "tag", "Read Return Tag matches with the PMI Request Tag which triggered the error log."},
#else
{0, 15, 0x0000000000000000, "RW/V", "tag", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo29[] = {{"D_CR_ERR_ECC_LOG", "", 0x000000B4, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields30[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "pgtblvld", "This register indicates whether a page is open within a bank. Each bit reflects the page open status of a bank.\r\n"
"      [p]DDR3L/LPDDR3/LPDDR4/WIO2:[/p]\r\n"
"  [list]\r\n"
"  [*]PGTBLVLD[7:0] = Page open status for Rank 0 Bank[7:0]. \r\n"
"  [*]PGTBLVLD[23:16] = Page open status for Rank 1 Bank[7:0].\r\n"
"      [/list]\r\n"
"      [p]DDR4:[/p]\r\n"
"      [list]\r\n"
"      [*]PGTBLVLD[3:0] = Page open status for Rank 0, Bank Group 0, Bank[3:0]. \r\n"
"      [*]PGTBLVLD[7:4] = Page open status for Rank 0, Bank Group 1, Bank[3:0].\r\n"
"      [*]PGTBLVLD[11:8] = Page open status for Rank 0, Bank Group 2, Bank[3:0].\r\n"
"      [*]PGTBLVLD[15:12] = Page open status for Rank 0, Bank Group 3, Bank[3:0].\r\n"
"      [*]PGTBLVLD[19:16] = Page open status for Rank 1, Bank Group 0, Bank[3:0].\r\n"
"      [*]PGTBLVLD[23:20] = Page open status for Rank 1, Bank Group 1, Bank[3:0].\r\n"
"      [*]PGTBLVLD[27:24] = Page open status for Rank 1, Bank Group 2, Bank[3:0].\r\n"
"      [*]PGTBLVLD[31:28] = Page open status for Rank 1, Bank Group 3, Bank[3:0].\r\n"
"      [/list]\r\n"
"      [list]\r\n"
"      [*]0: The associated bank is closed.\r\n"
"  [*]1: The associated bank has been opened. \r\n"
"  [/list]"},
#else
{0, 31, 0x0000000000000000, "RO/V", "pgtblvld", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo30[] = {{"D_CR_PGTBLSTAT", "", 0x000000B8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields31[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "rsvd31_16", "Reserved."},
#else
{16, 31, 0x0000000000000000, "RO", "rsvd31_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO/V", "fusestat", "D-Unit fuse bits are captured into this register and are available to be read.\r\n"
"      [list]\r\n"
"  [*][0]: fus_dun_ecc_dis.  \r\n"
"  [*][3:1]: fus_dun_max_supported_device_size[2:0].\r\n"
"  [*][4:4]: fus_dun_lpddr3_dis.\r\n"
"  [*][5:5]: fus_dun_lpddr4_dis.\r\n"
"  [*][6:6]: fus_dun_wio2_dis.\r\n"
"  [*][7:7]: fus_dun_ddr3l_dis.\r\n"
"      [*][8:8]: fus_dun_ddr4_dis.\r\n"
"  [*][15:9]: reserved.\r\n"
"  [/list]"},
#else
{0, 15, 0x0000000000000000, "RO/V", "fusestat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo31[] = {{"D_CR_DFUSESTAT", "", 0x000000BC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields32[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "val", "General purpose scratchpad.  May be used for BIOS for data storage."},
#else
{0, 31, 0x0000000000000000, "RW", "val", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo32[] = {{"D_CR_SSKPD0", "", 0x000000C0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields33[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "val", "General purpose scratchpad.  May be used for BIOS for data storage."},
#else
{0, 31, 0x0000000000000000, "RW", "val", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo33[] = {{"D_CR_SSKPD1", "", 0x000000C4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields34[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "bonus0", "This register is reserved for ECO."},
#else
{0, 31, 0x0000000000000000, "RW", "bonus0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo34[] = {{"D_CR_BONUS0", "", 0x000000C8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields35[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "bonus1", "This register is reserved for ECO."},
#else
{0, 31, 0x0000000000000000, "RW", "bonus1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo35[] = {{"D_CR_BONUS1", "", 0x000000CC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields36[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "dqcalrdatlo", "Holds least significant 32 bits returned as a result of CA Training."},
#else
{0, 31, 0x0000000000000000, "RO/V", "dqcalrdatlo", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo36[] = {{"D_CR_DQCALRDATLO", "", 0x000000D0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields37[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "dqcalrdathi", "Holds most significant 32 bits returned as a result of DQ calibration/CA training (Reserved in BXT/GLK)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "dqcalrdathi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo37[] = {{"D_CR_DQCALRDATHI", "", 0x000000D4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields38[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "cmdspid_to_saby2_tsvs", "Provides custom TSVs for BGFs which write in the CMD SPID clock and read in SABY2 clock."},
#else
{16, 31, 0x0000000000000000, "RW", "cmdspid_to_saby2_tsvs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "saby2_to_cmdspid_tsvs", "Provides custom TSVs for BGFs which write in the SABY2 clock and read in CMD SPID clock."},
#else
{0, 15, 0x0000000000000000, "RW", "saby2_to_cmdspid_tsvs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo38[] = {{"D_CR_BGF_CUSTOM_TSV_CMD_PATTERN", "", 0x000000D8, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields39[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "cmdspid_to_saby2_tsvs", "Provides custom TSVs for BGFs which write in the CMD SPID clock and read in SABY2 clock."},
#else
{16, 31, 0x0000000000000000, "RW", "cmdspid_to_saby2_tsvs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "saby2_to_cmdspid_tsvs", "Provides custom TSVs for BGFs which write in SABY2 clock and read in CMD SPID clock."},
#else
{0, 15, 0x0000000000000000, "RW", "saby2_to_cmdspid_tsvs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo39[] = {{"D_CR_BGF_CUSTOM_TSV_CMD_INIT", "", 0x000000DC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields40[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "dataspid_to_saby2_tsvs", "Provides custom TSVs for BGFs which write in the DATA SPID clock and read in SABY2 clock."},
#else
{16, 31, 0x0000000000000000, "RW", "dataspid_to_saby2_tsvs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "saby2_to_dataspid_tsvs", "Provides custom TSVs for BGFs which write in SABY2 clock and read in DATA SPID clock"},
#else
{0, 15, 0x0000000000000000, "RW", "saby2_to_dataspid_tsvs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo40[] = {{"D_CR_BGF_CUSTOM_TSV_DATA_PATTERN", "", 0x000000E0, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields41[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "dataspid_to_saby2_tsvs", "Provides custom TSVs for BGFs which write in the DATA SPID clock and read in SABY2 clock."},
#else
{16, 31, 0x0000000000000000, "RW", "dataspid_to_saby2_tsvs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "saby2_to_dataspid_tsvs", "Provides custom TSVs for BGFs which write in SABY2 clock and read in DATA SPID clock."},
#else
{0, 15, 0x0000000000000000, "RW", "saby2_to_dataspid_tsvs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo41[] = {{"D_CR_BGF_CUSTOM_TSV_DATA_INIT", "", 0x000000E4, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields42[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000003, "RW", "spiddataclk_ratio", "The ratio of clock C (SPIDData):1."},
#else
{24, 31, 0x0000000000000003, "RW", "spiddataclk_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000003, "RW", "spidcmdclk_ratio", "The ratio of clock B (SPIDCmd):1."},
#else
{16, 23, 0x0000000000000003, "RW", "spidcmdclk_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000001, "RW", "saclkby2_ratio", "The ratio of clock A (SAby2):1.   \r\n"
"  [p]Note: this field must be set to the same value as SPIDCMDCLK_RATIO when CPGC is active.[/p]"},
#else
{8, 15, 0x0000000000000001, "RW", "saclkby2_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "fus_separation_spidsaby2", "Variable separation of the serial fifos to be passed into the se module."},
#else
{6, 7, 0x0000000000000000, "RW", "fus_separation_spidsaby2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "cg_dis", "BGF Reset."},
#else
{5, 5, 0x0000000000000000, "RW", "cg_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RW", "fus_separation_saby2spid", "Variable separation of the serial fifos to be passed into the se module. BEZAN TO FIX"},
#else
{3, 4, 0x0000000000000000, "RW", "fus_separation_saby2spid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "use_localsync", "Enable the use of locally generated sync signals."},
#else
{2, 2, 0x0000000000000000, "RW", "use_localsync", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "rsvd1", "Reserved."},
#else
{1, 1, 0x0000000000000000, "RO", "rsvd1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "bgf_run", "Start BGFs."},
#else
{0, 0, 0x0000000000000000, "RW", "bgf_run", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo42[] = {{"D_CR_BGF_CTL", "", 0x00000120, 9, 0x00000000FFFFFFFF, 0x0000000003030100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields43[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 29, 0x0000000000000005, "RW", "raw_wmm", "If a conflict read reaches this priority (or greater depending on access class occupancy), WMM will be triggered to unblock the corresponding write. D-Unit will stay in WMM until corresponding write is issued. \r\n"
"  [p]Note: The value in this bit must not be higher than lowest terminal priority level of each access class.[/p]"},
#else
{27, 29, 0x0000000000000005, "RW", "raw_wmm", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO", "rsvd26", "Reserved."},
#else
{26, 26, 0x0000000000000000, "RO", "rsvd26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 25, 0x0000000000000006, "RW", "rimprio", "If any read in the RPQ is at this programmable priority, RIM is triggered."},
#else
{23, 25, 0x0000000000000006, "RW", "rimprio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000000, "RO", "rsvd22_18", "Reserved."},
#else
{18, 22, 0x0000000000000000, "RO", "rsvd22_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 17, 0x000000000000001A, "RW", "wimthrs", "When the number of entries in WPQ is greater than or equal to this value (higher than WMM entry watermark, less than WPQ size), it triggers write isoch mode (WIM)."},
#else
{12, 17, 0x000000000000001A, "RW", "wimthrs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000014, "RW", "wmmexit", "When the number of entries in WPQ is less than this value, the D-Unit will switch back to read major mode."},
#else
{6, 11, 0x0000000000000014, "RW", "wmmexit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000018, "RW", "wmmentry", "When the number of entries in WPQ is greater than or equal to this value, the D-Unit will switch to write major mode (WMM).\r\n"
"  [p]Note: the value must not be set to 0.[/p]"},
#else
{0, 5, 0x0000000000000018, "RW", "wmmentry", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo43[] = {{"D_CR_MMC", "", 0x00000124, 8, 0x00000000FFFFFFFF, 0x000000002B01A518}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields44[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RO", "rsvd31_26", "Reserved."},
#else
{26, 31, 0x0000000000000000, "RO", "rsvd31_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 25, 0x0000000000000010, "RW", "maxwrb", "Maximum number of writes D-Unit can send in WMM mode before returning to RMM (set B)."},
#else
{20, 25, 0x0000000000000010, "RW", "maxwrb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 19, 0x0000000000000008, "RW", "minrdb", "Minimum number of reads that has to be serviced before a switch to WMM is allowed (set B)."},
#else
{14, 19, 0x0000000000000008, "RW", "minrdb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RO", "rsvd13_12", "Reserved."},
#else
{12, 13, 0x0000000000000000, "RO", "rsvd13_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000010, "RW", "maxwra", "Maximum number of writes D-Unit can send in WMM mode before returning to RMM (set A)."},
#else
{6, 11, 0x0000000000000010, "RW", "maxwra", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000008, "RW", "minrda", "Minimum number of reads that has to be serviced before a switch to WMM is allowed (set A)."},
#else
{0, 5, 0x0000000000000008, "RW", "minrda", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo44[] = {{"D_CR_MMRDWR_AB", "", 0x00000128, 6, 0x00000000FFFFFFFF, 0x0000000001020408}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields45[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RO", "rsvd31_26", "Reserved."},
#else
{26, 31, 0x0000000000000000, "RO", "rsvd31_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 25, 0x0000000000000010, "RW", "maxwrd", "Maximum number of writes D-Unit can send in WMM mode before returning to RMM (set D)."},
#else
{20, 25, 0x0000000000000010, "RW", "maxwrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 19, 0x0000000000000008, "RW", "minrdd", "Minimum number of reads that has to be serviced before a switch to WMM is allowed (set D)."},
#else
{14, 19, 0x0000000000000008, "RW", "minrdd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RO", "rsvd13_12", "Reserved."},
#else
{12, 13, 0x0000000000000000, "RO", "rsvd13_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000010, "RW", "maxwrc", "Maximum number of writes D-Unit can send in WMM mode before returning to RMM (set C)."},
#else
{6, 11, 0x0000000000000010, "RW", "maxwrc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000008, "RW", "minrdc", "Minimum number of reads that has to be serviced before a switch to WMM is allowed (set C)."},
#else
{0, 5, 0x0000000000000008, "RW", "minrdc", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo45[] = {{"D_CR_MMRDWR_CD", "", 0x0000012C, 6, 0x00000000FFFFFFFF, 0x0000000001020408}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields46[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{15, 31, 0x0000000000000000, "RO", "rsvd31_15", "Reserved."},
#else
{15, 31, 0x0000000000000000, "RO", "rsvd31_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000001, "RW", "ac4ip", "Initial priority level of read requests coming with access class 4."},
#else
{12, 14, 0x0000000000000001, "RW", "ac4ip", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000003, "RW", "ac3ip", "Initial priority level of read requests coming with access class 3."},
#else
{9, 11, 0x0000000000000003, "RW", "ac3ip", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000007, "RW", "ac2ip", "Initial priority level of read requests coming with access class 2."},
#else
{6, 8, 0x0000000000000007, "RW", "ac2ip", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "ac1ip", "Initial priority level of read requests coming with access class 1."},
#else
{3, 5, 0x0000000000000000, "RW", "ac1ip", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000002, "RW", "ac0ip", "Initial priority level of read requests coming with access class 0."},
#else
{0, 2, 0x0000000000000002, "RW", "ac0ip", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo46[] = {{"D_CR_ACCIP", "", 0x00000130, 6, 0x00000000FFFFFFFF, 0x00000000000017C2}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields47[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x0000000000000000, "RW", "p6res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{25, 29, 0x0000000000000000, "RW", "p6res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x000000000000001F, "RW", "p5res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{20, 24, 0x000000000000001F, "RW", "p5res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x000000000000000A, "RW", "p4res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{15, 19, 0x000000000000000A, "RW", "p4res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x000000000000000A, "RW", "p3res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{10, 14, 0x000000000000000A, "RW", "p3res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x000000000000000A, "RW", "p2res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{5, 9, 0x000000000000000A, "RW", "p2res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "p1res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{0, 4, 0x0000000000000000, "RW", "p1res", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo47[] = {{"D_CR_RD_PROM0", "", 0x00000134, 7, 0x00000000FFFFFFFF, 0x0000000001F52940}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields48[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x000000000000000A, "RW", "p6res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{25, 29, 0x000000000000000A, "RW", "p6res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x0000000000000000, "RW", "p5res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{20, 24, 0x0000000000000000, "RW", "p5res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x0000000000000000, "RW", "p4res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{15, 19, 0x0000000000000000, "RW", "p4res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x0000000000000000, "RW", "p3res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{10, 14, 0x0000000000000000, "RW", "p3res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000000, "RW", "p2res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{5, 9, 0x0000000000000000, "RW", "p2res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "p1res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{0, 4, 0x0000000000000000, "RW", "p1res", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo48[] = {{"D_CR_RD_PROM1", "", 0x00000138, 7, 0x00000000FFFFFFFF, 0x0000000014000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields49[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x0000000000000000, "RW", "p6res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{25, 29, 0x0000000000000000, "RW", "p6res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x0000000000000000, "RW", "p5res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{20, 24, 0x0000000000000000, "RW", "p5res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x0000000000000000, "RW", "p4res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{15, 19, 0x0000000000000000, "RW", "p4res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x0000000000000000, "RW", "p3res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{10, 14, 0x0000000000000000, "RW", "p3res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000000, "RW", "p2res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{5, 9, 0x0000000000000000, "RW", "p2res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "p1res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{0, 4, 0x0000000000000000, "RW", "p1res", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo49[] = {{"D_CR_RD_PROM2", "", 0x0000013C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields50[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x0000000000000000, "RW", "p6res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{25, 29, 0x0000000000000000, "RW", "p6res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x000000000000001F, "RW", "p5res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{20, 24, 0x000000000000001F, "RW", "p5res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x0000000000000005, "RW", "p4res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{15, 19, 0x0000000000000005, "RW", "p4res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x0000000000000005, "RW", "p3res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{10, 14, 0x0000000000000005, "RW", "p3res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000000, "RW", "p2res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{5, 9, 0x0000000000000000, "RW", "p2res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "p1res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{0, 4, 0x0000000000000000, "RW", "p1res", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo50[] = {{"D_CR_RD_PROM3", "", 0x00000140, 7, 0x00000000FFFFFFFF, 0x0000000001F29400}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields51[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "rsvd31_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x0000000000000000, "RW", "p6res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{25, 29, 0x0000000000000000, "RW", "p6res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x000000000000001F, "RW", "p5res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{20, 24, 0x000000000000001F, "RW", "p5res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x000000000000000A, "RW", "p4res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{15, 19, 0x000000000000000A, "RW", "p4res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x000000000000000A, "RW", "p3res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{10, 14, 0x000000000000000A, "RW", "p3res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x000000000000000A, "RW", "p2res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{5, 9, 0x000000000000000A, "RW", "p2res", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000000A, "RW", "p1res", "Number of CASes that pass before a request in this priority promotes to the next priority level."},
#else
{0, 4, 0x000000000000000A, "RW", "p1res", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo51[] = {{"D_CR_RD_PROM4", "", 0x00000144, 7, 0x00000000FFFFFFFF, 0x0000000001F5294A}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields52[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{11, 31, 0x0000000000000000, "RO", "rsvd31_11", "Reserved."},
#else
{11, 31, 0x0000000000000000, "RO", "rsvd31_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 10, 0x0000000000000006, "RW", "deadline_thrs", "A requests with initial priority of 0 will exit priority 0 when its deadline is equal or less than this value plus current time.  This field does not affect the priority of any requests in access classes with initial priority bigger than 0."},
#else
{0, 10, 0x0000000000000006, "RW", "deadline_thrs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo52[] = {{"D_CR_DL_THRS", "", 0x00000148, 2, 0x00000000FFFFFFFF, 0x0000000000000006}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields53[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "rsvd31_25", "Reserved."},
#else
{25, 31, 0x0000000000000000, "RO", "rsvd31_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "wmm_reg_r1", "Disable WMM unsafe write page hits block safe write page misses same bank."},
#else
{24, 24, 0x0000000000000000, "RW", "wmm_reg_r1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RO", "rsvd23_20", "Reserved."},
#else
{20, 23, 0x0000000000000000, "RO", "rsvd23_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "wmm_prio_r4", "Disable WMM unsafe priority 1 read miss block write hit to same bank. \r\n"
"  [p]Note: This rule does not block the bank that is being blocked by WMM_PRIO_R3.[/p]\r\n"
"  [p]Priority rules 1, 3 and 4 should be enabled/disabled together.[/p]"},
#else
{19, 19, 0x0000000000000000, "RW", "wmm_prio_r4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "wmm_prio_r3", "Disable WMM unsafe priority 1 write hit block write miss to same bank.\r\n"
"  [p]Note: This rule does not block the bank that is being blocked by WMM_PRIO_R1.[/p]\r\n"
"  [p]Priority rules 1,3 and 4 should be enabled/disabled together.[/p]"},
#else
{18, 18, 0x0000000000000000, "RW", "wmm_prio_r3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "wmm_prio_r2", "Disable WMM CAS block rule."},
#else
{17, 17, 0x0000000000000000, "RW", "wmm_prio_r2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "wmm_prio_r1", "Disable WMM unsafe top priority 1 write miss block write hit same bank.\r\n"
"  [p]Priority rules 1, 3 and 4 should be enabled/disabled together.[/p]"},
#else
{16, 16, 0x0000000000000000, "RW", "wmm_prio_r1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "rmm_reg_r6", "Disable RMM unsafe write page hits block safe write page misses same bank."},
#else
{13, 13, 0x0000000000000000, "RW", "rmm_reg_r6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000001, "RW", "rmm_reg_r5", "Disable RMM unsafe read page miss block all safe and unsafe write page hit to the same bank. \r\n"
"  [p]Note: This field must not be set to 0 (enabled) if RMM_REG_R4 is also 0.[/p]"},
#else
{12, 12, 0x0000000000000001, "RW", "rmm_reg_r5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000001, "RW", "rmm_reg_r4", "Disable RMM unsafe write page hit block safe read page miss same bank. \r\n"
"  [p]Note: This field must not be set to 0 (enabled) if RMM_REG_R5 is also 0.[/p]"},
#else
{11, 11, 0x0000000000000001, "RW", "rmm_reg_r4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "rmm_reg_r3", "Disable RMM unsafe read page hit block safe read and write page miss same bank. \r\n"
"  [p]Note: This rule does not block the bank that is being blocked by RMM_PRIO_R3 and RMM_PRIO_R1.[/p]"},
#else
{10, 10, 0x0000000000000000, "RW", "rmm_reg_r3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "rmm_reg_r2", "Disable RMM unsafe read page empty block safe write page empty same rank."},
#else
{9, 9, 0x0000000000000000, "RW", "rmm_reg_r2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "rmm_reg_r1", "Disable RMM unsafe read page hit block safe write page hit same rank."},
#else
{8, 8, 0x0000000000000000, "RW", "rmm_reg_r1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "rsvd7_4", "Reserved."},
#else
{4, 7, 0x0000000000000000, "RO", "rsvd7_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "rmm_prio_r4", "Disable RMM unsafe critical read miss block read and write hit to same bank. \r\n"
"  [p]Note: This rule does not block the bank that is being blocked by RMM_PRIO_R3.[/p]\r\n"
"  [p]Priority rules 1, 3 and 4 should be enabled/disabled together.[/p]"},
#else
{3, 3, 0x0000000000000000, "RW", "rmm_prio_r4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "rmm_prio_r3", "Disable RMM unsafe critical read hit block read and write miss to same bank. \r\n"
"  [p]Note: This rule does not block the bank that is being blocked by RMM_PRIO_R1.[/p]\r\n"
"  [p]Priority rules 1, 3 and 4 should be enabled/disabled together.[/p]"},
#else
{2, 2, 0x0000000000000000, "RW", "rmm_prio_r3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rmm_prio_r2", "Disable RMM CAS block rule."},
#else
{1, 1, 0x0000000000000000, "RW", "rmm_prio_r2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rmm_prio_r1", "Disable RMM unsafe top critical read miss block read and write hit same bank. \r\n"
"  [p]Note: Priority rules 1, 3 and 4 should be enabled/disabled together.[/p]"},
#else
{0, 0, 0x0000000000000000, "RW", "rmm_prio_r1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo53[] = {{"D_CR_MM_BLK", "", 0x0000014C, 19, 0x00000000FFFFFFFF, 0x0000000000001800}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields54[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "rsvd31_4", "Reserved."},
#else
{4, 31, 0x0000000000000000, "RO", "rsvd31_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW/V", "suspendp", "A SUSPENDP message will put the DRAM into self-refresh mode. The D-Unit will complete servicing outstanding memory requests and flush all queued Refresh commands to DRAM before putting the DRAM in self refresh mode. Finally, a PM message will be sent to the PHY. The bit is cleared by hardware after the PHY indicates the transition requested in the PM message has been completed.  D-Unit will perform an MRW to MR17 with an opcode as defined by DPMC0.PASR before it places the DRAM into Self-Refresh. \r\n"
"  [p]Note: Reserved for BXT0/1.[/p]"},
#else
{3, 3, 0x0000000000000000, "RW/V", "suspendp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW/V", "suspend", "A SUSPEND message will put the DRAM into self-refresh mode. The D-Unit will complete servicing outstanding memory requests and flush all queued Refresh commands to DRAM before putting the DRAM in Self Refresh mode. Finally, a PM message will be sent to the PHY. The bit is cleared by hardware only after the PHY indicates the transition requested in the PM message has been completed. \r\n"
"  [p]Note: When COLDWAKE is set prior of setting this bit the DRAM will not be placed in SR.[/p]"},
#else
{2, 2, 0x0000000000000000, "RW/V", "suspend", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "rsvd1", "Reserved."},
#else
{1, 1, 0x0000000000000000, "RO", "rsvd1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "wake", "Take PHY out of PM states and wakes the DRAM out of self refresh mode. The bit is cleared by hardware only when the DRAM has exited out of self refresh mode and is accessible. \r\n"
"  [p]Note: When COLDWAKE is set prior of setting this bit the D-Unit will not send SR exit command and will not set the DCO.IC bit.[/p]"},
#else
{0, 0, 0x0000000000000000, "RW/V", "wake", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo54[] = {{"D_CR_DRAM_SR_CMD", "", 0x00000154, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields55[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "m2n", "2N Mode Command (LPDDR3/DDR3L/DDR4)"},
#else
{31, 31, 0x0000000000000000, "RW", "m2n", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "rank", "Rank select. \r\n"
"  [list]\r\n"
"  [*]0: Rank0.\r\n"
"  [*]1: Rank1.\r\n"
"  [/list]"},
#else
{30, 30, 0x0000000000000000, "RW", "rank", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "mrrcmd", "This bit needs to be set if the command is a MRR/Read."},
#else
{29, 29, 0x0000000000000000, "RW", "mrrcmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "bl", "This field sets the BL that D-Unit drives on SPID interface. \r\n"
"  For LPDDR3, DDR3L and WIO2: \r\n"
"  [list]\r\n"
"  [*]0: Burst Length is 4.  \r\n"
"  [*]1: Burst Length is 8. \r\n"
"  [/list]\r\n"
"  For LPDDR4:\r\n"
"      [list]\r\n"
"  [*]0: Burst Length is 16.\r\n"
"  [*]1: Burst Length is 32.\r\n"
"      [/list]\r\n"
"  "},
#else
{28, 28, 0x0000000000000000, "RW", "bl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "rdcmd_type", "Dunit will drive the value on SPID RDCMD_TYPE bus. Indicates to PHY whether it needs to consume DRAM returned data\r\n"
"      [list]\r\n"
"  [*]00: All commands other than MR18 and MR19.\r\n"
"  [*]01: LPDDR4 MR18 Command.\r\n"
"      [*]10: LPDDR4 MR19 Command.\r\n"
"      {*]11: Reserved.\r\n"
"      [/list]\r\n"
"      "},
#else
{26, 27, 0x0000000000000000, "RW", "rdcmd_type", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RO", "rsvd25_24", "Reserved."},
#else
{24, 25, 0x0000000000000000, "RO", "rsvd25_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 23, 0x0000000000000000, "RW", "data", "Command to be sent to DRAM. Not all DRAM commands are supported. \r\n"
"      [p]For DDR3L: DATA[15:0] = A[15:0], DATA[18:16] = BA[2:0], DATA[19] = WE_N, DATA[20] = CAS_N, DATA[21] = RAS_N, DATA[23:22] not used.[/p]\r\n"
"  [p]For LPDDR3: DATA[9:0]=CA[9:0] Rising Edge, DATA [19:10]=CA[9:0] Falling Edge, DATA[23:20] not used.[/p] \r\n"
"  [p]For WIO2: DATA[10:0]=CA[10:0] Rising Edge, DATA[21:11]=CA[10:0] Falling Edge, Data[23:22] not used.[/p] \r\n"
"  [p]For LPDDR4: DATA[5:0]=CA[5:0] CMD1 Edge1, DATA[11:6]=CA[5:0] CMD1 Edge2, DATA[17:12]=CA[5:0] CMD2 Edge1, DATA[23:18]=CA[5:0] CMD2 Edge2.[/p]\r\n"
"      [p]For DDR4: DATA[13:0] = A[13:0], DATA[14:14] = A[14]/WE_N, DATA[15:15] = A[15]/CAS_N, DATA[16:16] = A[16]/RAS_N, DATA[18:17] = BA[1:0], DATA[20:19] = BG[1:0], DATA[21] = ACT_N, DATA[23:22] not used.[/p]"},
#else
{0, 23, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo55[] = {{"D_CR_DRAM_CMD", "", 0x00000158, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields56[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "rsvd31_24", "Reserved."},
#else
{24, 31, 0x0000000000000000, "RO", "rsvd31_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "mrrdata2", "MRR Data (2nd Device): This field contains the 2nd device data of the last DRAM mode register read (MRR) issued through DRAM_CMD register. It is overwritten with each MRR command.\r\n"
"      [p]Note: Correct byte is selected in MR4_BYTE_SEL2.[/p]"},
#else
{16, 23, 0x0000000000000000, "RO/V", "mrrdata2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "rsvd15_8", "Reserved."},
#else
{8, 15, 0x0000000000000000, "RO", "rsvd15_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "mrrdata", "MRR Data (1st Device): This field contains 8bit data of the last DRAM mode register read (MRR) issued through DRAM_CMD register. It is overwritten with each MRR command. \r\n"
"      [p]Note: Correct byte is selected in MR4_BYTE_SEL.[/p]"},
#else
{0, 7, 0x0000000000000000, "RO/V", "mrrdata", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo56[] = {{"D_CR_DCMDDATA", "", 0x0000015C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields57[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enable_prdr", "Enables pseudo-random data return feature in D-Unit. Should be\r\n"
"      set before D_CR_BGF_CTL_BGF_RUN is set to 1. Note one should always enable PRDR before enabling CheckSum for any usage model that requires both features"},
#else
{31, 31, 0x0000000000000000, "RW", "enable_prdr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "enable_checksum", "Enables checksum calculation in D-Unit. Should be set before D_CR_BGF_CTL_BGF_RUN is set to 1"},
#else
{30, 30, 0x0000000000000000, "RW", "enable_checksum", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "WO", "reset", "Resets the checksum registers when written to 1. \r\n"
"  [p]Bit automatically resets to 0.[/p]"},
#else
{29, 29, 0x0000000000000000, "WO", "reset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "rddata_credit_en", "When set, read data credit counter register is used for credit handling instead of initial credit handshaking."},
#else
{28, 28, 0x0000000000000000, "RW", "rddata_credit_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rddata_credit", "Read data credit counter value. This values is used as read return credit."},
#else
{24, 27, 0x0000000000000000, "RW", "rddata_credit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW/1C", "addr_checksum", "Contains the address checksum value for all addresses read and written from this D-Unit. Write 1 to clear this field."},
#else
{16, 23, 0x0000000000000000, "RW/1C", "addr_checksum", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW/1C", "data_checksum", "Contains the final checksum value for all data written to this D-Unit. Write 1 to clear this field."},
#else
{0, 15, 0x0000000000000000, "RW/1C", "data_checksum", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo57[] = {{"D_CR_SBFT_CTL", "", 0x00000160, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields58[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000FFFFFFFF, "RW", "clear_mask", "Mask ANDed with pseudo-random data. Resets to all 1s. Setting bit n to 0 in this register will force every nth bit in the data to be set to 0"},
#else
{0, 31, 0x00000000FFFFFFFF, "RW", "clear_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo58[] = {{"D_CR_SBFT_CMASK", "", 0x00000164, 1, 0x00000000FFFFFFFF, 0x00000000FFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields59[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "set_mask", "Mask ORed with pseudo-random data.  Resets to all 0s.  Setting bit n to 1 in this register will force every nth bit in the data to be set to 1."},
#else
{0, 31, 0x0000000000000000, "RW", "set_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo59[] = {{"D_CR_SBFT_SMASK", "", 0x00000168, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields60[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "seed", "Seed XORed with address bits to produce pseudo-random data.  Use this to statically produce different pseudo-random data streams for the same set of request addresses."},
#else
{0, 31, 0x0000000000000000, "RW", "seed", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo60[] = {{"D_CR_SBFT_SEED", "", 0x0000016C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields61[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "rsvd31_6", "Reserved."},
#else
{6, 31, 0x0000000000000000, "RO", "rsvd31_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "hae", "If enabled (1), D-Unit may request a power-gate whenever it is idle. \r\n"
"  [p]Note: If this bit is set, then PMCRE must be 0.[/p]"},
#else
{5, 5, 0x0000000000000000, "RW", "hae", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO", "rsvd4", "Reserved."},
#else
{4, 4, 0x0000000000000000, "RO", "rsvd4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "se", "\r\n"
"  [list]\r\n"
"  [*]0: D-Unit will never asset Sleep to the retention flops. \r\n"
"  [*]1: D-Unit may assert Sleep during Power Gating. \r\n"
"  [/list]\r\n"
"  [p]Note: Some platforms may default this bit to 0 others to 1.[/p]"},
#else
{3, 3, 0x0000000000000001, "RW", "se", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000000, "RO", "rsvd2_1", "Reserved."},
#else
{1, 2, 0x0000000000000000, "RO", "rsvd2_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "pmcre", "When enabled (1), D-Unit will power gate when idle and the PMC requests power gating."},
#else
{0, 0, 0x0000000000000001, "RW", "pmcre", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo61[] = {{"D_CR_PGCB_PWRGATE_PCE", "", 0x00000170, 6, 0x00000000FFFFFFFF, 0x0000000000000009}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields62[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "rsvd31_4", "Reserved."},
#else
{4, 31, 0x0000000000000000, "RO", "rsvd31_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "pg_timer", "This is the time from which all internal Idle conditions have been observed to when PGCB actually starts the power gating sequence. Used only when power gating is enabled (HAE is set to 1). \r\n"
"  [p]Note: The actual count value is 2^value.[/p]"},
#else
{0, 3, 0x0000000000000000, "RW", "pg_timer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo62[] = {{"D_CR_PGCB_PG_IDLE_TIMER", "", 0x00000174, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields63[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "rsvd31_12", "Reserved."},
#else
{12, 31, 0x0000000000000000, "RO", "rsvd31_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "pgcb_clkreq_dis", "When set to 1, it prevents the PGCB from deasserting PGCB clkreq. Prevents PGCB clock trunk from ever gating.  \r\n"
"  [list]\r\n"
"  [*]0: Enable PGCB clock request.\r\n"
"  [*]1: Disable PGCB clock request.\r\n"
"  [/list]"},
#else
{11, 11, 0x0000000000000000, "RW", "pgcb_clkreq_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "saby2_clkreq_dis", "When set to 1, it prevents the SA/2 CDC from deasserting clkreq due to idle conditions. Has no effect on clkreq deassertion during a forced power gate entry flow. This prevents trunk clock gating. However, local clock gating can still be enabled. \r\n"
"  [list]\r\n"
"  [*]0: Enable SA/2 clock request. \r\n"
"  [*]1: Disable SA/2 clock request.\r\n"
"  [/list]"},
#else
{10, 10, 0x0000000000000000, "RW", "saby2_clkreq_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "spid_clkreq_dis", "When set to 1, it prevents the SPID CDC from deasserting clkreq due to idle conditions. Has no effect on clkreq deassertion during a forced power gate entry flow. This prevents trunk clock gating. However, local clock gating can still be enabled. \r\n"
"  [list]\r\n"
"  [*]0: Enable SPID clock request.\r\n"
"  [*]1: Disable SPID clock request.\r\n"
"  [/list]"},
#else
{9, 9, 0x0000000000000000, "RW", "spid_clkreq_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "sb_clkreq_dis", "When set to 1, it prevents the SB CDC from deasserting clkreq due to idle conditions. Has no effect on clkreq deassertion during a forced power gate entry flow. This prevents trunk clock gating. However, local clock gating can still be enabled. \r\n"
"  [list]\r\n"
"  [*]0: Enable SB clock request.\r\n"
"  [*]1: Disable SB clock request.\r\n"
"  [/list]"},
#else
{8, 8, 0x0000000000000000, "RW", "sb_clkreq_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "ug_cg_dis", "Setting this field to 1 disables any clock gating in the ungated domain due to idle conditions. Also, if set, it prevents D-Unit ungated domain trunk clock gating.\r\n"
"      [list]\r\n"
"      [*]0 - Enable ungated domain Clock Gating.\r\n"
"      [*]1 - Disable ungated domain Clock Gating.\r\n"
"      [/list]"},
#else
{7, 7, 0x0000000000000001, "RW", "ug_cg_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 6, 0x0000000000000000, "RO", "rsvd6_3", "Reserved"},
#else
{3, 6, 0x0000000000000000, "RO", "rsvd6_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "saby2_cg_dis", "Setting this field to 1 disables SA/2 clock gating due to idle conditions. Also, if set, it prevents SA/2 trunk clock gating. \r\n"
"  [list]\r\n"
"  [*]0: Enable SA/2 clock gating.\r\n"
"  [*]1: Disable SA/2 clock gating.\r\n"
"  [/list]"},
#else
{2, 2, 0x0000000000000000, "RW", "saby2_cg_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "spid_cg_dis", "Setting this field to 1 disables any SPID clock gating due to idle conditions. Also if set, it prevents SPID trunk clock gating.  \r\n"
"  [list]\r\n"
"  [*]0: Enable SPID clock gating.\r\n"
"  [*]1: Disable SPID clock gating.\r\n"
"  [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "spid_cg_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "sb_cg_dis", "Setting this field to 1 disables any Side Band clock gating due to idle conditions. Also if set, it prevents SB trunk clock gating. \r\n"
"  [list]\r\n"
"  [*]0: Enable SB Clock Gating.\r\n"
"  [*]1: Disable SB Clock Gating.\r\n"
"  [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "sb_cg_dis", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo63[] = {{"D_CR_PGCB_CLKGATE_DIS", "", 0x00000178, 10, 0x00000000FFFFFFFF, 0x0000000000000080}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields64[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "rsvd31_20", "Reserved."},
#else
{20, 31, 0x0000000000000000, "RO", "rsvd31_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000002, "RW", "saby2_clk_timer", "This is the minimum time from the SA/2 CDC detects clock reqs deasserting until gclock is gated.  The actual count is 2^value. For example, setting this register to 4'd5 would result in a holdoff time of 32 clock cycles."},
#else
{16, 19, 0x0000000000000002, "RW", "saby2_clk_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO", "rsvd15_12", "Reserved."},
#else
{12, 15, 0x0000000000000000, "RO", "rsvd15_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000002, "RW", "spid_clk_timer", "This is the minimum time from the SPID CDC detects all clock reqs deasserting until gclock is gated. The actual count is 2^value. For example, setting this register to 4'd5 would result in a holdoff time of 32 clock cycles."},
#else
{8, 11, 0x0000000000000002, "RW", "spid_clk_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "rsvd7_4", "Reserved."},
#else
{4, 7, 0x0000000000000000, "RO", "rsvd7_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000002, "RW", "sb_clk_timer", "This is the minimum time from the SB CDC detects all clock reqs deasserting until gclock is gated. The actual count is 2^value. For example, setting this register to 4'd5 would result in a holdoff time of 32 clock cycles."},
#else
{0, 3, 0x0000000000000002, "RW", "sb_clk_timer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo64[] = {{"D_CR_PGCB_CG_IDLE_TIMER", "", 0x0000017C, 6, 0x00000000FFFFFFFF, 0x0000000000020202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields65[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "dqs_retrain_int", "This sets the frequency by which the D-Unit initiates periodic retraining (in 1x NREFI)."},
#else
{16, 31, 0x0000000000000000, "RW", "dqs_retrain_int", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "rsvd15_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 13, 0x0000000000000000, "RW", "dqs_osc_rt", "After D-Unit starts DQS oscillator, it must wait this amount of time before being able to read the value in MR18 and MR19 (in 16x DRAM clocks).\r\n"
"  [p]Value in this register must be at least equal to DRAM's MR23 value. + tOSCO.[/p]"},
#else
{4, 13, 0x0000000000000000, "RW", "dqs_osc_rt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW/V", "dqs_retrain_start_r1", "When set, Dunit will initiate LPDDR4 DQS training sequence on Rank1. \r\n"
"      [p]Hardware will clear bit when sequence completes (after issuing MR19).[/p]\r\n"
"      [p]Note: DQS_RETRAIN_EN must be 0 before setting this bit.[/p]"},
#else
{3, 3, 0x0000000000000000, "RW/V", "dqs_retrain_start_r1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW/V", "dqs_retrain_start_r0", "When set, Dunit will initiate LPDDR4 DQS training sequence on Rank0. \r\n"
"      [p]Hardware will clear bit when sequence completes (after issuing MR19).[/p]\r\n"
"      [p]Note: DQS_RETRAIN_EN must be 0 before setting this bit.[/p]"},
#else
{2, 2, 0x0000000000000000, "RW/V", "dqs_retrain_start_r0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "dqs_retrain_srx_en", "Enable retraining on SR exit.\r\n"
"  [p]This bit enables LPDDR4 DQS retraining on Self Refresh Exit. If disabled, D-Unit will not perform retraining on SR exit.[/p]"},
#else
{1, 1, 0x0000000000000000, "RW", "dqs_retrain_srx_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dqs_retrain_en", "Periodic retraining enable:\r\n"
"  [p]This bit enables periodic DQS retraining. If disabled, D-Unit will not perform retraining periodically.[/p] \r\n"
"  [p]Note: Will be enabled only if DCO.IC is set and refreshes are enabled in DRF.MINREFRATE.[/p]"},
#else
{0, 0, 0x0000000000000000, "RW", "dqs_retrain_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo65[] = {{"D_CR_DQS_RETRAINING_CTL", "", 0x00000180, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields66[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "rsvd31", "Reserved."},
#else
{31, 31, 0x0000000000000000, "RO", "rsvd31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "mr4_bit2_sel2", "Selects bit 2 of MR4 data."},
#else
{28, 30, 0x0000000000000000, "RW", "mr4_bit2_sel2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "rsvd27", "Reserved"},
#else
{27, 27, 0x0000000000000000, "RO", "rsvd27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "mr4_bit1_sel2", "Selects bit 1 of MR4 data"},
#else
{24, 26, 0x0000000000000000, "RW", "mr4_bit1_sel2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "rsvd23", "Reserved"},
#else
{23, 23, 0x0000000000000000, "RO", "rsvd23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000000, "RW", "mr4_bit0_sel2", "Selects bit 0 of MR4 data."},
#else
{20, 22, 0x0000000000000000, "RW", "mr4_bit0_sel2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RO", "rsvd19_18", "Reserved"},
#else
{18, 19, 0x0000000000000000, "RO", "rsvd19_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "mr4_byte_sel2", "Selects byte position of the MR4 data for second device."},
#else
{16, 17, 0x0000000000000000, "RW", "mr4_byte_sel2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "rsvd15", "Reserved"},
#else
{15, 15, 0x0000000000000000, "RO", "rsvd15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "mr4_bit2_sel", "Selects bit 2 of MR4 data."},
#else
{12, 14, 0x0000000000000000, "RW", "mr4_bit2_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "rsvd11", "Reserved."},
#else
{11, 11, 0x0000000000000000, "RO", "rsvd11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "mr4_bit1_sel", "Selects bit 1 of MR4 data."},
#else
{8, 10, 0x0000000000000000, "RW", "mr4_bit1_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "rsvd7", "Reserved."},
#else
{7, 7, 0x0000000000000000, "RO", "rsvd7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "mr4_bit0_sel", "Selects bit 0 of MR4 data."},
#else
{4, 6, 0x0000000000000000, "RW", "mr4_bit0_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "rsvd3_2", "Reserved."},
#else
{2, 3, 0x0000000000000000, "RO", "rsvd3_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "mr4_byte_sel", "Selects byte position of the MR4 data first device."},
#else
{0, 1, 0x0000000000000000, "RW", "mr4_byte_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo66[] = {{"D_CR_MR4_DESWIZZLE", "", 0x00000184, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields67[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00610D0212, "RW", "rac_policy", "Each bit specifies read access policy of one SAI agent."},
#else
{0, 63, 0x00000C00610D0212, "RW", "rac_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo67[] = {{"D_CR_DUNIT_GRPA_RAC", "", 0x00000190, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00610D0212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields68[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00610D0212, "RW", "wac_policy", "Each bit specifies write access policy of one SAI agent."},
#else
{0, 63, 0x00000C00610D0212, "RW", "wac_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo68[] = {{"D_CR_DUNIT_GRPA_WAC", "", 0x00000198, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00610D0212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields69[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "c_policy", "Each bit specifies control access policy of one SAI agent. Agents who have access can modify the control policies in the SAI registers."},
#else
{0, 63, 0x00000C0061010202, "RW", "c_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo69[] = {{"D_CR_DUNIT_GRPA_CP", "", 0x000001A0, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields70[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00010C0212, "RW", "rac_policy", "Each bit specifies read access policy of one SAI agent."},
#else
{0, 63, 0x00000C00010C0212, "RW", "rac_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo70[] = {{"D_CR_DUNIT_GRPB_RAC", "", 0x000001A8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00010C0212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields71[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00010C0212, "RW", "wac_policy", "Each bit specifies write access policy of one SAI agent."},
#else
{0, 63, 0x00000C00010C0212, "RW", "wac_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo71[] = {{"D_CR_DUNIT_GRPB_WAC", "", 0x000001B0, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00010C0212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields72[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0001000202, "RW", "c_policy", "Each bit specifies control access policy of one SAI agent. Agents who have access can modify the control policies in the SAI registers."},
#else
{0, 63, 0x00000C0001000202, "RW", "c_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo72[] = {{"D_CR_DUNIT_GRPB_CP", "", 0x000001B8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0001000202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields73[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "tmpdata", "xxx"},
#else
{0, 31, 0x0000000000000000, "RW", "tmpdata", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo73[] = {{"CR_BGF_CTL", "", 0x00000120, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields74[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "tmpdata", "xxx"},
#else
{0, 31, 0x0000000000000000, "RW", "tmpdata", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo74[] = {{"FAKE_WAKE", "", 0x000001F0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields75[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000061010202, "RW", "control_policy_l", "Lower half of the SAI Control Policy Value [31:0]."},
#else
{0, 31, 0x0000000061010202, "RW", "control_policy_l", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo75[] = {{"CPGC2_ACCESS_CONTROL_POLICY_L", "", 0x00000000, 1, 0x00000000FFFFFFFF, 0x0000000061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields76[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000C00, "RW", "control_policy_h", "Upper half of the SAI Control Policy Value [63:32]."},
#else
{0, 31, 0x0000000000000C00, "RW", "control_policy_h", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo76[] = {{"CPGC2_ACCESS_CONTROL_POLICY_H", "", 0x00000004, 1, 0x00000000FFFFFFFF, 0x0000000000000C00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields77[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000FFFFFF3F, "RW", "read_policy_l", "Lower half of the SAI Read Policy Value [31:0]."},
#else
{0, 31, 0x00000000FFFFFF3F, "RW", "read_policy_l", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo77[] = {{"CPGC2_ACCESS_READ_POLICY_L", "", 0x00000008, 1, 0x00000000FFFFFFFF, 0x00000000FFFFFF3F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields78[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000001371FFF, "RW", "read_policy_h", "Upper half of the SAI Read Policy Value [63:32]."},
#else
{0, 31, 0x0000000001371FFF, "RW", "read_policy_h", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo78[] = {{"CPGC2_ACCESS_READ_POLICY_H", "", 0x0000000C, 1, 0x00000000FFFFFFFF, 0x0000000001371FFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields79[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000001000212, "RW", "write_policy_l", "Lower half of the SAI Write Policy Value [31:0]."},
#else
{0, 31, 0x0000000001000212, "RW", "write_policy_l", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo79[] = {{"CPGC2_ACCESS_WRITE_POLICY_L", "", 0x00000010, 1, 0x00000000FFFFFFFF, 0x0000000001000212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields80[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000C00, "RW", "write_policy_h", "Upper half of the SAI Write Policy Value [63:32]."},
#else
{0, 31, 0x0000000000000C00, "RW", "write_policy_h", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo80[] = {{"CPGC2_ACCESS_WRITE_POLICY_H", "", 0x00000014, 1, 0x00000000FFFFFFFF, 0x0000000000000C00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields81[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "address_decode_rotate_repeats", "Number of times the current Address_Instruction will repeat if Address_Decode_Enable is set (as N-1) (0=1 time).[br]\r\n"
"If  for the current Address_Instruction, Address_Decode_Enable is set, then at the start of that Address_Instruction, initialize the XOR_Address_Pattern to a single 1 in the LSB of Column Address. Otherwise, it is initialized to all zero's.[br]\r\n"
"For (Address_Decode_Rotate_Repeat_Current = 0; Current_ Address_Decode_Rotate_Repeat_Current <= Address_Decode_Rotate_Repeat;  Address_Decode_Rotate_Repeat_Current ++)[br]\r\n"
"Execute the entire Algorithm (Block Traversal, Algorithm_Instruction, Commands) with the following behavior:[br]\r\n"
"At the end of each complete Block Traversal, rotate the XOR Address Pattern 1 bit position from LSB to MSB (Column through Region_Bits_Column, Region_Bits_Row, Region_Num_Banks, and through Region_Num_Ranks).[br]\r\n"
"Region_Size.Num_Bank and Region_Size.Num_Rank numbers are converted to the equivalent number of adddress bits to cover their range (ceil(log2(Num+1))) and should be programmed to a power of 2 value (minus 1): 1,3,7, or 15.[br]\r\n"
"If only one Rank is being tested, then you should limit the amount in this register to the sum of the number of address bits without Rank bits."},
#else
{0, 5, 0x0000000000000000, "RW", "address_decode_rotate_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo81[] = {{"CPGC2_ADDRESS_CONTROL", "", 0x00000018, 1, 0x000000000000003F, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields82[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set, then this is the last Address Instruction and the test will terminate following full execution of this instruction. If there are no Last bits set in the Address Instruction list, then the test will not stop due to a completion of the test, but will be an Infinite Test."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", "Enables rotating XOR of address bits. Used in concert with the Address_Decode_Enable field in the Command_Instruction list.[br]\r\n"
"This bit enables repeating of the current Address_Instruction for Address_Decode_Rotate_Repeats times."},
#else
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(10) Inv(FastX) - North West[/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(11) Diagonal2 - East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  West [/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"Note that the Bank and Rank Address direction follows the same as the Column (Increment or Decrement).[br]\r\n"
"Note for diagonal directions, a Carry results in twice the normal increment/decrement of the Row field.[br]\r\n"
"Incrementing fields start at 0, and Decrementing fields start at 2^(field_block_size)-2^(field_increment)= top of block."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "address_order", "Controls the fastest changing address field, and how that carries into higher order fields.[br]\r\n"
"000 Rank, Bank, Row/Col.[br]\r\n"
"001 Rank, Row/Col, Bank.[br]\r\n"
"010 Bank, Rank, Row/Col.[br]\r\n"
"011 Bank, Row/Col, Rank.[br]\r\n"
"100 Row/Col, Rank, Bank.[br]\r\n"
"101 Row/Col, Bank, Rank.[br]\r\n"
"110 Row/Col  (Used for Offset) Rank and Bank are unchanged.[br]\r\n"
"111 Row-Col (Used for Stripe Offset) No Carry from any field to another.[br]\r\n"
"Carry order between Row and Column is dependent on the Address_Direction field."},
#else
{0, 2, 0x0000000000000000, "RW", "address_order", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo82[] = {{"CPGC2_ADDRESS_INSTRUCTION_0_", "", 0x0000001C, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields83[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set, then this is the last Address Instruction and the test will terminate following full execution of this instruction. If there are no Last bits set in the Address Instruction list, then the test will not stop due to a completion of the test, but will be an Infinite Test."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", "Enables rotating XOR of address bits. Used in concert with the Address_Decode_Enable field in the Command_Instruction list.[br]\r\n"
"This bit enables repeating of the current Address_Instruction for Address_Decode_Rotate_Repeats times."},
#else
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(10) Inv(FastX) - North West[/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(11) Diagonal2 - East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  West [/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"Note that the Bank and Rank Address direction follows the same as the Column (Increment or Decrement).[br]\r\n"
"Note for diagonal directions, a Carry results in twice the normal increment/decrement of the Row field.[br]\r\n"
"Incrementing fields start at 0, and Decrementing fields start at 2^(field_block_size)-2^(field_increment)= top of block."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "address_order", "Controls the fastest changing address field, and how that carries into higher order fields.[br]\r\n"
"000 Rank, Bank, Row/Col.[br]\r\n"
"001 Rank, Row/Col, Bank.[br]\r\n"
"010 Bank, Rank, Row/Col.[br]\r\n"
"011 Bank, Row/Col, Rank.[br]\r\n"
"100 Row/Col, Rank, Bank.[br]\r\n"
"101 Row/Col, Bank, Rank.[br]\r\n"
"110 Row/Col  (Used for Offset) Rank and Bank are unchanged.[br]\r\n"
"111 Row-Col (Used for Stripe Offset) No Carry from any field to another.[br]\r\n"
"Carry order between Row and Column is dependent on the Address_Direction field."},
#else
{0, 2, 0x0000000000000000, "RW", "address_order", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo83[] = {{"CPGC2_ADDRESS_INSTRUCTION_1_", "", 0x0000001D, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields84[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set, then this is the last Address Instruction and the test will terminate following full execution of this instruction. If there are no Last bits set in the Address Instruction list, then the test will not stop due to a completion of the test, but will be an Infinite Test."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", "Enables rotating XOR of address bits. Used in concert with the Address_Decode_Enable field in the Command_Instruction list.[br]\r\n"
"This bit enables repeating of the current Address_Instruction for Address_Decode_Rotate_Repeats times."},
#else
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(10) Inv(FastX) - North West[/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(11) Diagonal2 - East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  West [/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"Note that the Bank and Rank Address direction follows the same as the Column (Increment or Decrement).[br]\r\n"
"Note for diagonal directions, a Carry results in twice the normal increment/decrement of the Row field.[br]\r\n"
"Incrementing fields start at 0, and Decrementing fields start at 2^(field_block_size)-2^(field_increment)= top of block."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "address_order", "Controls the fastest changing address field, and how that carries into higher order fields.[br]\r\n"
"000 Rank, Bank, Row/Col.[br]\r\n"
"001 Rank, Row/Col, Bank.[br]\r\n"
"010 Bank, Rank, Row/Col.[br]\r\n"
"011 Bank, Row/Col, Rank.[br]\r\n"
"100 Row/Col, Rank, Bank.[br]\r\n"
"101 Row/Col, Bank, Rank.[br]\r\n"
"110 Row/Col  (Used for Offset) Rank and Bank are unchanged.[br]\r\n"
"111 Row-Col (Used for Stripe Offset) No Carry from any field to another.[br]\r\n"
"Carry order between Row and Column is dependent on the Address_Direction field."},
#else
{0, 2, 0x0000000000000000, "RW", "address_order", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo84[] = {{"CPGC2_ADDRESS_INSTRUCTION_2_", "", 0x0000001E, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields85[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set, then this is the last Address Instruction and the test will terminate following full execution of this instruction. If there are no Last bits set in the Address Instruction list, then the test will not stop due to a completion of the test, but will be an Infinite Test."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", "Enables rotating XOR of address bits. Used in concert with the Address_Decode_Enable field in the Command_Instruction list.[br]\r\n"
"This bit enables repeating of the current Address_Instruction for Address_Decode_Rotate_Repeats times."},
#else
{6, 6, 0x0000000000000000, "RW", "address_decode_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(10) Inv(FastX) - North West[/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(11) Diagonal2 - East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  West [/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"Note that the Bank and Rank Address direction follows the same as the Column (Increment or Decrement).[br]\r\n"
"Note for diagonal directions, a Carry results in twice the normal increment/decrement of the Row field.[br]\r\n"
"Incrementing fields start at 0, and Decrementing fields start at 2^(field_block_size)-2^(field_increment)= top of block."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "address_order", "Controls the fastest changing address field, and how that carries into higher order fields.[br]\r\n"
"000 Rank, Bank, Row/Col.[br]\r\n"
"001 Rank, Row/Col, Bank.[br]\r\n"
"010 Bank, Rank, Row/Col.[br]\r\n"
"011 Bank, Row/Col, Rank.[br]\r\n"
"100 Row/Col, Rank, Bank.[br]\r\n"
"101 Row/Col, Bank, Rank.[br]\r\n"
"110 Row/Col  (Used for Offset) Rank and Bank are unchanged.[br]\r\n"
"111 Row-Col (Used for Stripe Offset) No Carry from any field to another.[br]\r\n"
"Carry order between Row and Column is dependent on the Address_Direction field."},
#else
{0, 2, 0x0000000000000000, "RW", "address_order", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo85[] = {{"CPGC2_ADDRESS_INSTRUCTION_3_", "", 0x0000001F, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields86[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Data_Instruction indication, execution is continued at Data_Instruction[0] if the test does not otherwise terminate. This bit is implied to be set for Data_Instruction[3]."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Globally Invert all data.  Combined with the Algorithm_Instruction Invert_Data field, and the Command_Instruction or Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "data_background", "00 - Solid[br]\r\n"
"01 - Column Stripes[br]\r\n"
"10 - Row Stripes[br]\r\n"
"11 - Checkerboard"},
#else
{4, 5, 0x0000000000000000, "RW", "data_background", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", "Enables rotating lane pattern data. Used in concert with the Data_Select_Rotation_Enable field in the Data_Instruction list.[br]\r\n"
"This bit enables repeating of the current Data_Instruction for Data_Select_Rotation_Repeat times.[br]\r\n"
"Data generated using the advanced pattern generation will rotate by one data bit (LSB toward MSB) for each Data_Select_Rotation_Repeat.[br]\r\n"
"For the purpose of this shift, the order follows the Address_Instruction Address_Order and the Algorithm_Instruction[0] Address_Direction."},
#else
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo86[] = {{"CPGC2_DATA_INSTRUCTION_0_", "", 0x00000020, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields87[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Data_Instruction indication, execution is continued at Data_Instruction[0] if the test does not otherwise terminate. This bit is implied to be set for Data_Instruction[3]."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Globally Invert all data.  Combined with the Algorithm_Instruction Invert_Data field, and the Command_Instruction or Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "data_background", "00 - Solid[br]\r\n"
"01 - Column Stripes[br]\r\n"
"10 - Row Stripes[br]\r\n"
"11 - Checkerboard"},
#else
{4, 5, 0x0000000000000000, "RW", "data_background", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", "Enables rotating lane pattern data. Used in concert with the Data_Select_Rotation_Enable field in the Data_Instruction list.[br]\r\n"
"This bit enables repeating of the current Data_Instruction for Data_Select_Rotation_Repeat times.[br]\r\n"
"Data generated using the advanced pattern generation will rotate by one data bit (LSB toward MSB) for each Data_Select_Rotation_Repeat.[br]\r\n"
"For the purpose of this shift, the order follows the Address_Instruction Address_Order and the Algorithm_Instruction[0] Address_Direction."},
#else
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo87[] = {{"CPGC2_DATA_INSTRUCTION_1_", "", 0x00000021, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields88[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Data_Instruction indication, execution is continued at Data_Instruction[0] if the test does not otherwise terminate. This bit is implied to be set for Data_Instruction[3]."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Globally Invert all data.  Combined with the Algorithm_Instruction Invert_Data field, and the Command_Instruction or Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "data_background", "00 - Solid[br]\r\n"
"01 - Column Stripes[br]\r\n"
"10 - Row Stripes[br]\r\n"
"11 - Checkerboard"},
#else
{4, 5, 0x0000000000000000, "RW", "data_background", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", "Enables rotating lane pattern data. Used in concert with the Data_Select_Rotation_Enable field in the Data_Instruction list.[br]\r\n"
"This bit enables repeating of the current Data_Instruction for Data_Select_Rotation_Repeat times.[br]\r\n"
"Data generated using the advanced pattern generation will rotate by one data bit (LSB toward MSB) for each Data_Select_Rotation_Repeat.[br]\r\n"
"For the purpose of this shift, the order follows the Address_Instruction Address_Order and the Algorithm_Instruction[0] Address_Direction."},
#else
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo88[] = {{"CPGC2_DATA_INSTRUCTION_2_", "", 0x00000022, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields89[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Data_Instruction indication, execution is continued at Data_Instruction[0] if the test does not otherwise terminate. This bit is implied to be set for Data_Instruction[3]."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Globally Invert all data.  Combined with the Algorithm_Instruction Invert_Data field, and the Command_Instruction or Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "data_background", "00 - Solid[br]\r\n"
"01 - Column Stripes[br]\r\n"
"10 - Row Stripes[br]\r\n"
"11 - Checkerboard"},
#else
{4, 5, 0x0000000000000000, "RW", "data_background", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", "Enables rotating lane pattern data. Used in concert with the Data_Select_Rotation_Enable field in the Data_Instruction list.[br]\r\n"
"This bit enables repeating of the current Data_Instruction for Data_Select_Rotation_Repeat times.[br]\r\n"
"Data generated using the advanced pattern generation will rotate by one data bit (LSB toward MSB) for each Data_Select_Rotation_Repeat.[br]\r\n"
"For the purpose of this shift, the order follows the Address_Instruction Address_Order and the Algorithm_Instruction[0] Address_Direction."},
#else
{3, 3, 0x0000000000000000, "RW", "data_select_rotation_enable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo89[] = {{"CPGC2_DATA_INSTRUCTION_3_", "", 0x00000023, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields90[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "data_select_rotation_repeats", "Any Data_Instruction with Data_Select_Rotation_Enable will repeat this many times.  As N-1. (0=1 time)"},
#else
{0, 7, 0x0000000000000000, "RW", "data_select_rotation_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo90[] = {{"CPGC2_DATA_CONTROL", "", 0x00000024, 1, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields91[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "data_select_rotation_repeats_current", "Current state of Data_Select_Rotation_Repeats loop (down count)."},
#else
{16, 23, 0x0000000000000000, "RO/V", "data_select_rotation_repeats_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RO/V", "address_decode_rotate_repeats_current", "Current state of Address_Decode_Rotate_Repeats loop (down count)."},
#else
{0, 5, 0x0000000000000000, "RO/V", "address_decode_rotate_repeats_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo91[] = {{"CPGC2_ADDRESS_DATA_STATUS", "", 0x00000028, 2, 0x0000000000FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields92[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo92[] = {{"CPGC2_ALGORITHM_INSTRUCTION_0_", "", 0x0000002C, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields93[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo93[] = {{"CPGC2_ALGORITHM_INSTRUCTION_1_", "", 0x0000002D, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields94[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo94[] = {{"CPGC2_ALGORITHM_INSTRUCTION_2_", "", 0x0000002E, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields95[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo95[] = {{"CPGC2_ALGORITHM_INSTRUCTION_3_", "", 0x0000002F, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields96[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo96[] = {{"CPGC2_ALGORITHM_INSTRUCTION_4_", "", 0x00000030, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields97[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo97[] = {{"CPGC2_ALGORITHM_INSTRUCTION_5_", "", 0x00000031, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields98[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo98[] = {{"CPGC2_ALGORITHM_INSTRUCTION_6_", "", 0x00000032, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields99[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Algorithm instruction, and the memory block is moved at its completion. Execution continues at the first Algorithm_Instruction until the test is complete.  Algorithm_Instruction[7] has this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Algorithm_Instruction.  Combined with the Data_Instruction Invert_Data field, and the Command_Instruction and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "inverse_direction", "Invert the direction as set in the current Address_Instruction for the duration of this Algorithm_Instruction."},
#else
{5, 5, 0x0000000000000000, "RW", "inverse_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", "Starting Command_Instruction for exection of this Algorithm_Instruction.  The Command_Inxtruction_Current cycles from Command_Start_Pointer, incrementing until a Command_Instruction contains the Last bit set, and then repeats for each Base_Address, Base_Repeats.[br]\r\n"
"Pointer to which one of the 24 command list to start with."},
#else
{0, 4, 0x0000000000000000, "RW", "command_start_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo99[] = {{"CPGC2_ALGORITHM_INSTRUCTION_7_", "", 0x00000033, 4, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields100[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo100[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_", "", 0x00000034, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields101[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo101[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_1_", "", 0x00000035, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields102[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo102[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_2_", "", 0x00000036, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields103[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo103[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_3_", "", 0x00000037, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields104[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo104[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_4_", "", 0x00000038, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields105[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo105[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_5_", "", 0x00000039, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields106[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo106[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_6_", "", 0x0000003A, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields107[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", "Enable the BE Training Error Detection feature for individual Algorithm Instructions. This bit is inactive unless the BE_TRAIN_ERR_ENABLE bit is set in CPGC_ERR_CTL."},
#else
{7, 7, 0x0000000000000000, "RW", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "select_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during chip select cycles."},
#else
{6, 6, 0x0000000000000000, "RW", "select_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "deselect_on", "If set, the CADB will be able to issue harassment patterns into the command and address bus during non Chip Select cycles."},
#else
{5, 5, 0x0000000000000000, "RW", "deselect_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "wait_event_start", "Wait_Event_Start causes the delay in beginning the current Algorithm_Instruction until the Event indicated by Select_Event has been acknowledged to have occurred.[br]\r\n"
"The Select_Event is acknowledged to be in progress.[br]\r\n"
"The latency between the event and the acknowledgement must be a known fixed value (preventing a hang situation).[br]\r\n"
"The Current_Repeat_Value is reset tzero."},
#else
{4, 4, 0x0000000000000000, "RW", "wait_event_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "wait_count_start", "Wait_Count_Start and Wait_Time are used to synchronize a specific time an Algorithm should start. [br]\r\n"
"Wait_Time is commonly used for Pause Refresh test where the read to a particular address needs to be a specific time away from when the write to an address occurs.[br]\r\n"
"If Wait_Count_Start = 0 then the start of the Algorithm_Instruction is not stalled.[br]\r\n"
"If Wait_Count_Start = 1 then the start of the Algorithm_Instruction is stalled until the Wait_Time_Current is equal to the Wait_Time.[br]\r\n"
"Wait_Time_Current represent the current count value from when it was last reset either by a Test starting or Wait_Count_Clear.[br]\r\n"
"Wait_Time_Current is a free running counter that accurately reflects the time from when it was last reset by using the following formula.[br]\r\n"
"Time elapsed = Wait_Timer_Current * (1/(frequency selected by Count_Value_Frequency).[br]\r\n"
"If Wait_Count_Clear = 1 then prior to starting the current Algorithm_Instruction, Wait_Time_Current is reset tzero.[br]\r\n"
"Wait_Time_Current is frozen if a Test encounters any stop condition.[br]\r\n"
"Wait_Time_Current is reset to zer0 when a test starts (Start_Test is asserted).[br]\r\n"
"Wait_Time_Current rolls over at the maximum value back tzero.[br]\r\n"
"Wait_Clock_Frequency(1:0) set the frequency that increment Current_Repeat_Value. The possible frequencies that can be selected are the following.[br]\r\n"
"Wait_Clock_Frequency = 00 = 1GHz (time = 1ns).[br]\r\n"
"Wait_Clock_Frequency = 01 = 1MHZ (time = 1us).[br]\r\n"
"Wait_Clock_Frequency = 10 = 1KHZ (time = 1ms).[br]\r\n"
"Wait_Clock_Frequence = 11 = DUNIT clock."},
#else
{3, 3, 0x0000000000000000, "RW", "wait_count_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", "Reset the Wait Timer at the start of this Algorithm Instruction."},
#else
{2, 2, 0x0000000000000000, "RW", "wait_count_clear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "base_range_row", "Instead of using the Base_Repeats setting, use Base_Col_Repeats setting for the size of the block for this instruction as the size of the block. This may be used for a rapid short test hitting all banks to open pages etc, or to initialize a row worth of data."},
#else
{1, 1, 0x0000000000000000, "RW", "base_range_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "fasty_init", "FastY_Init is used to allow a background write initialization type algorithm to use FastY with Columns as the LSB address field to ensure the fastest initialization possible.[br]\r\n"
"^(wD1) is a the most typical background Init function.[br]\r\n"
"MEMTEL uses the keyword INIT() to reference this feature.[br]\r\n"
"FastY_Init enables the current Algortihm_Instruction to override the current Address_Instruction[].Address_Direction and Address_Order.[br]\r\n"
"If set, then use the Address_Direction=000 (FastY) and Address_Order=000 (Rank, Bank, Row/Col), else use the settings defined in the current Address_Instruction."},
#else
{0, 0, 0x0000000000000000, "RW", "fasty_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo107[] = {{"CPGC2_ALGORITHM_INSTRUCTION_CTRL_7_", "", 0x0000003B, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields108[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW/1C/V", "wait_timer_current", "Current wait timer value. See Wait_Time description. (down count)"},
#else
{0, 15, 0x0000000000000000, "RW/1C/V", "wait_timer_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo108[] = {{"CPGC2_ALGORITHM_WAIT_COUNT_CURRENT", "", 0x0000003C, 1, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields109[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "select_event", "Select_Event is decoded in the following ways.[br]\r\n"
"Select_Event = 00 = Read/Write Pending CAS cue is empty[br]\r\n"
"Select_Event = 01 = CKE Power Down[br]\r\n"
"Select_Event = 10 = Refresh[br]\r\n"
"Select_Event = 11 = Self Refresh"},
#else
{30, 31, 0x0000000000000000, "RW", "select_event", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "wait_clock_frequency", "00 - 1GHz[br]\r\n"
"01 - 1MHz[br]\r\n"
"10 - 1KHz[br]\r\n"
"11 - Native DUNIT clock"},
#else
{24, 25, 0x0000000000000000, "RW", "wait_clock_frequency", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "timer", "Exponential timer (timer value calculated as 2^Timer).  If WaitEventStart is set in the currently executing Algorithm Instruction, this timer dynamically replaces the current Wait_Time counter following the Select_Event occurring (such as SelfRefresh or PowerDown) , to add a fixed delay for the Select_Event condition to remain before CPGC activity resumes."},
#else
{20, 23, 0x0000000000000000, "RW", "timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "wait_time", "Number of clocks at Wait_Clock_Frequency to wait before starting current Algorithm_Instruction if Wait_Start = 1."},
#else
{0, 15, 0x0000000000000000, "RW", "wait_time", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo109[] = {{"CPGC2_ALGORITHM_WAIT_EVENT_CONTROL", "", 0x00000040, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields110[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "base_repeats", "Base Address Loopcount - Typically the number of Base Addresses within the Block (Row*Col*Bank*Rank) As N-1 value.[br]\r\n"
"This is the number of times the current Algorithm Instruction will be executed."},
#else
{0, 31, 0x0000000000000000, "RW", "base_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo110[] = {{"CPGC2_BASE_REPEATS", "", 0x00000044, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields111[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "base_repeats_current", "Current remaining Base Address loops (down count)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "base_repeats_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo111[] = {{"CPGC2_BASE_REPEATS_CURRENT", "", 0x00000048, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields112[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "base_col_repeats", "Alternate Base_Address_Loopcount. Often used to initialze a Row or Column worth of data. [br]\r\n"
"This is used when Base_Range_Row field of ALGORITHM_INSTRUCTION_CTL is activated.[br]\r\n"
"This is the number of times the current Algorithm Instruction will be executed."},
#else
{0, 31, 0x0000000000000000, "RW", "base_col_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo112[] = {{"CPGC2_BASE_COL_REPEATS", "", 0x0000004C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields113[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "block_repeats", "Block Loopcount. Typically the number of Blocks to be tested to traverse the entire Tested Region. (2^region_size/2^block_size -1) As N-1 value.[br]\r\n"
"This is the number of times the entire list of Algorithm Instructions will be executed."},
#else
{0, 31, 0x0000000000000000, "RW", "block_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo113[] = {{"CPGC2_BLOCK_REPEATS", "", 0x00000050, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields114[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "block_repeats_current", "Current Block Loopcount (down count)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "block_repeats_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo114[] = {{"CPGC2_BLOCK_REPEATS_CURRENT", "", 0x00000054, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields115[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo115[] = {{"CPGC2_COMMAND_INSTRUCTION_0_", "", 0x00000058, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields116[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo116[] = {{"CPGC2_COMMAND_INSTRUCTION_1_", "", 0x00000059, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields117[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo117[] = {{"CPGC2_COMMAND_INSTRUCTION_2_", "", 0x0000005A, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields118[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo118[] = {{"CPGC2_COMMAND_INSTRUCTION_3_", "", 0x0000005B, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields119[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo119[] = {{"CPGC2_COMMAND_INSTRUCTION_4_", "", 0x0000005C, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields120[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo120[] = {{"CPGC2_COMMAND_INSTRUCTION_5_", "", 0x0000005D, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields121[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo121[] = {{"CPGC2_COMMAND_INSTRUCTION_6_", "", 0x0000005E, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields122[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo122[] = {{"CPGC2_COMMAND_INSTRUCTION_7_", "", 0x0000005F, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields123[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo123[] = {{"CPGC2_COMMAND_INSTRUCTION_8_", "", 0x00000060, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields124[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo124[] = {{"CPGC2_COMMAND_INSTRUCTION_9_", "", 0x00000061, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields125[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo125[] = {{"CPGC2_COMMAND_INSTRUCTION_10_", "", 0x00000062, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields126[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo126[] = {{"CPGC2_COMMAND_INSTRUCTION_11_", "", 0x00000063, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields127[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo127[] = {{"CPGC2_COMMAND_INSTRUCTION_12_", "", 0x00000064, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields128[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo128[] = {{"CPGC2_COMMAND_INSTRUCTION_13_", "", 0x00000065, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields129[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo129[] = {{"CPGC2_COMMAND_INSTRUCTION_14_", "", 0x00000066, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields130[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo130[] = {{"CPGC2_COMMAND_INSTRUCTION_15_", "", 0x00000067, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields131[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo131[] = {{"CPGC2_COMMAND_INSTRUCTION_16_", "", 0x00000068, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields132[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo132[] = {{"CPGC2_COMMAND_INSTRUCTION_17_", "", 0x00000069, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields133[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo133[] = {{"CPGC2_COMMAND_INSTRUCTION_18_", "", 0x0000006A, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields134[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo134[] = {{"CPGC2_COMMAND_INSTRUCTION_19_", "", 0x0000006B, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields135[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo135[] = {{"CPGC2_COMMAND_INSTRUCTION_20_", "", 0x0000006C, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields136[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo136[] = {{"CPGC2_COMMAND_INSTRUCTION_21_", "", 0x0000006D, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields137[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo137[] = {{"CPGC2_COMMAND_INSTRUCTION_22_", "", 0x0000006E, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields138[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "If set this is the last Command Instruction for this Algorithm Command Sequence.Command_Instruction[23] has this bit set implicitly.[br]\r\n"
"Execution continues at the Command_Instruction pointed to by the Algorithm_Instruction's Command_Start_Pointer until the end of the Algorithm_Instruction."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert the data used for this command. This is combined with the Algorithm_Instruction and Data_Instruction Invert_Data bits for Base accesses. For Offset accesses, it is further combined with the Offset_Command Invert_Data bit."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", "Enable rotating XOR of address bits or PRBS address generation. If the Address_Decode_Enable field in the Address_Instruction list is active, and [name] is also active, then for the access of this Command_Instruction, the address will be XOR with the XOR_Address_Pattern.[br]\r\n"
"If the Address_Decode_Enable field in the Address_Instruction list is inactive (0), and the Address_PRBS_Enable bit in the Address_PRBS_Control register is set, then the desired address bits will be replaced with the PRBS generated value."},
#else
{5, 5, 0x0000000000000000, "RW", "address_decode_or_prbs_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Base command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "If set, this is an Offset operation, and the selected Offset_Group will be executed in its place. In this case the Write, Hammer, and Alternate_Data fields are ignored."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "offset_group", "Selects which Offset_Group will be used if Offset field is set."},
#else
{1, 1, 0x0000000000000000, "RW", "offset_group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Base Write operation will be performed."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo138[] = {{"CPGC2_COMMAND_INSTRUCTION_23_", "", 0x0000006F, 8, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields139[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "hammer_repeats", "Hammer_Repeats is the number of times any command is repeated at the same address when the Hammer control bit is set in the Command_Instruction (if not an offset command)."},
#else
{0, 31, 0x0000000000000000, "RW", "hammer_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo139[] = {{"CPGC2_HAMMER_REPEATS", "", 0x00000070, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields140[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "hammer_repeats_current", "Current Hammer Loopcount (down count)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "hammer_repeats_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo140[] = {{"CPGC2_HAMMER_REPEATS_CURRENT", "", 0x00000074, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields141[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo141[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_", "", 0x00000078, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields142[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo142[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_1_", "", 0x00000079, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields143[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo143[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_2_", "", 0x0000007A, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields144[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo144[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_3_", "", 0x0000007B, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields145[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo145[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_4_", "", 0x0000007C, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields146[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo146[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_5_", "", 0x0000007D, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields147[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo147[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_6_", "", 0x0000007E, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields148[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo148[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_7_", "", 0x0000007F, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields149[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo149[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_8_", "", 0x00000080, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields150[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo150[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_9_", "", 0x00000081, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields151[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo151[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_10_", "", 0x00000082, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields152[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo152[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_11_", "", 0x00000083, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields153[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo153[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_12_", "", 0x00000084, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields154[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo154[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_13_", "", 0x00000085, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields155[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo155[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_14_", "", 0x00000086, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields156[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Address_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[7] and Offset_Address_Instruction[15] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "stripe", "Normal Offsets use Address_Order=110.[br]\r\n"
"This allows full traversal of the entire Block by and offset.[br]\r\n"
"If Stripe is active, then there is no carry between Row and Column. This will keep the offset address within the same Row, or the same Column or on the same diagonal."},
#else
{6, 6, 0x0000000000000000, "RW", "stripe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "address_direction", "[b]Address_Direction[/b][br]\r\n"
"There are 4 basic address directions and their inverse for a total of 8.[br]\r\n"
"We will denote this as a combination of a 1-bit field and a 2-bit field.[br]\r\n"
"[b](0)(00)  FastY -North[/b][br]\r\n"
" Increment Column and Carry Increment into Row.[br]\r\n"
"[b](1)(00) Inv(FastY) - South[/b][br]\r\n"
" Decrement Column and Carry Decrement into Row.[br]\r\n"
"[b](0)(01) Diagonal  North East[/b][br]\r\n"
" Increment Row and Column together and Carry Increment Column into Row.[br]\r\n"
"[b](1)(01) Inv(Diagonal)  South West[/b][br]\r\n"
" Decrement Row and Column together and Carry Decrement Column into Row.[br]\r\n"
"[b](0)(10) FastX  East[/b][br]\r\n"
" Increment Row and Carry Increment into Column.[br]\r\n"
"[b](1)(10) Inv(FastX) - West[/b][br]\r\n"
" Decrement Row and Carry Decrement into Column.[br]\r\n"
"[b](0)(11) Diagonal2 - South East[/b][br]\r\n"
" Decrement Column and Increment Row and Carry Increment Column into Row.[br]\r\n"
"[b](1)(11) Inv(Diagonal2)  North West [/b][br]\r\n"
" Increment Column and Decrement Row and Carry Decrement Column into Row.[br]\r\n"
"\r\n"
"Offset accesses begin one 'step' in the given direction from the current Base_Address."},
#else
{3, 5, 0x0000000000000000, "RW", "address_direction", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", "Enabled periodic data inversion - based on Address_Direction (OrderX field) -normally invert every 2^Block_Size_Bits_Row/Col, modified based on Periodic_Data_Inversion_Adjustment."},
#else
{2, 2, 0x0000000000000000, "RW", "periodic_data_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", "Reduce or increase the inversion interval by -1,0,1 based on the value in this field.[br]00 - no adjust[br]01 - interval is increased by 1[br]11 - interval is decreased by 1[br]10 - reserved"},
#else
{0, 1, 0x0000000000000000, "RW", "periodic_data_inv_adj", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo156[] = {{"CPGC2_OFFSET_ADDRESS_INSTRUCTION_15_", "", 0x00000087, 5, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields157[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo157[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_0_", "", 0x00000088, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields158[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo158[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_1_", "", 0x00000089, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields159[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo159[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_2_", "", 0x0000008A, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields160[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo160[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_3_", "", 0x0000008B, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields161[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo161[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_4_", "", 0x0000008C, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields162[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo162[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_5_", "", 0x0000008D, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields163[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo163[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_6_", "", 0x0000008E, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields164[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo164[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_7_", "", 0x0000008F, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields165[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo165[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_8_", "", 0x00000090, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields166[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo166[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_9_", "", 0x00000091, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields167[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo167[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_10_", "", 0x00000092, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields168[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "last", "Last Offset_Command_Instruction. The offset instruction is complete after all Offset_Address, Offset_Repeats, and Offset_Commands have finished.[br]\r\n"
"Offset_Address_Instruction[5] and Offset_Address_Instruction[11] have this bit set implicitly."},
#else
{7, 7, 0x0000000000000000, "RW", "last", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "invert_data", "Invert all data for this Offset_Command_Instruction.  Combine the Data_Instruction Invert_Data field, the Algorithm_Instruction  Invert_Data field, Command_Instruction Invert_Data field and Offset_Command_Instruction Invert_Data field to determine the final data polarity."},
#else
{6, 6, 0x0000000000000000, "RW", "invert_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "alternate_data", "Use the alternate zero data source instead of the UniSequencers and Pattern_Select."},
#else
{4, 4, 0x0000000000000000, "RW", "alternate_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hammer", "This Offset command will be repeated Hammer_Repeats times."},
#else
{3, 3, 0x0000000000000000, "RW", "hammer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "offset", "1=Normal Offset Command/Address, 0=Use Base Address and Offset_Command_Instruction Write bit."},
#else
{2, 2, 0x0000000000000000, "RW", "offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "write", "A Write operation will be performed at the Offset (or Base if the Offset field = 0) Address."},
#else
{0, 0, 0x0000000000000000, "RW", "write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo168[] = {{"CPGC2_OFFSET_COMMAND_INSTRUCTION_11_", "", 0x00000093, 6, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields169[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "offset_repeats", "Set the loopcount for Offset (Distance from Base). The entire list of Offset Commands are executed for each loop."},
#else
{0, 31, 0x0000000000000000, "RW", "offset_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo169[] = {{"CPGC2_OFFSET_REPEATS_0_", "", 0x00000094, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields170[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "offset_repeats", "Set the loopcount for Offset (Distance from Base). The entire list of Offset Commands are executed for each loop."},
#else
{0, 31, 0x0000000000000000, "RW", "offset_repeats", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo170[] = {{"CPGC2_OFFSET_REPEATS_1_", "", 0x00000098, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields171[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "offset_repeats_current", "Current Offset Loopcount (down count)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "offset_repeats_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo171[] = {{"CPGC2_OFFSET_REPEATS_CURRENT", "", 0x0000009C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields172[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RW", "low_row", "Set the bottom Row for the physical memory being tested. This value is added to all Region Row Addresses computed."},
#else
{0, 17, 0x0000000000000000, "RW", "low_row", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo172[] = {{"CPGC2_REGION_LOW_ROW", "", 0x000000A0, 1, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields173[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 10, 0x0000000000000000, "RW", "low_col", "Set the lowest Column for the physical memory being tested. This value is added to all Region Column Addresses computed."},
#else
{2, 10, 0x0000000000000000, "RW", "low_col", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo173[] = {{"CPGC2_REGION_LOW_COL", "", 0x000000A4, 1, 0x00000000000007FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields174[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RO/V", "block_origin_row_current", "Current row within the testing region of memory Updated as the block traverses through the region."},
#else
{0, 17, 0x0000000000000000, "RO/V", "block_origin_row_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo174[] = {{"CPGC2_BLOCK_ORIGIN_ROW_CURRENT", "", 0x000000A8, 1, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields175[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RO/V", "base_rank_current", "Current Base Address Rank within the block."},
#else
{16, 18, 0x0000000000000000, "RO/V", "base_rank_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 10, 0x0000000000000000, "RO/V", "base_col_current", "Current Base Address Column within the block."},
#else
{2, 10, 0x0000000000000000, "RO/V", "base_col_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo175[] = {{"CPGC2_BASE_ADDRESS_COL_RANK_CURRENT", "", 0x000000AC, 2, 0x000000000007FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields176[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RO/V", "base_bank_current", "Current Base Address Bank within the block."},
#else
{24, 27, 0x0000000000000000, "RO/V", "base_bank_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RO/V", "base_row_current", "Current Base Address Row within the block."},
#else
{0, 17, 0x0000000000000000, "RO/V", "base_row_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo176[] = {{"CPGC2_BASE_ADDRESS_ROW_BANK_CURRENT", "", 0x000000B0, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields177[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 10, 0x0000000000000000, "RO/V", "offset_col_current", "Current Offset Address Column within the block.[br]\r\n"
"Only valid if the current Command_Instruction pointed to by Command_Instruction_Current is an Offset command."},
#else
{2, 10, 0x0000000000000000, "RO/V", "offset_col_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo177[] = {{"CPGC2_OFFSET_ADDRESS_COL_CURRENT", "", 0x000000B4, 1, 0x00000000000007FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields178[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RO/V", "offset_row_current", "Current Offset Address Row within the block.[br]\r\n"
"Only valid if the current Command_Instruction pointed to by Command_Instruction_Current is an Offset command."},
#else
{0, 17, 0x0000000000000000, "RO/V", "offset_row_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo178[] = {{"CPGC2_OFFSET_ADDRESS_ROW_CURRENT", "", 0x000000B8, 1, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields179[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "region_size_bits_row", "2^Region_Size_Bits_Row is the number of rows in the testing region. Must be >= to Block_Size_Bits_Row."},
#else
{24, 28, 0x0000000000000000, "RW", "region_size_bits_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "region_size_bits_col", "2^Region_Size_Bits_Col is the number of columns in the testing region. It is also used as the Block_Size_Bits_Col value to set the size of the block. Minimum value is 1 if Address_Decode_Enable =1. , so this normally needs to be set to the number of Column bits of the memory."},
#else
{20, 23, 0x0000000000000000, "RW", "region_size_bits_col", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "block_size_num_ranks", "Number of Ranks to test for a Block (as N-1 = top rank number).[br]\r\n"
"All Rank Addresses go through the Rank Address Lookup table."},
#else
{16, 19, 0x0000000000000000, "RW", "block_size_num_ranks", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "block_size_num_banks", "Number of Banks to test for a Block (as N-1 = top bank number).[br]\r\n"
"All Bank Address values go through the Bank Address Lookup table."},
#else
{12, 15, 0x0000000000000000, "RW", "block_size_num_banks", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 8, 0x0000000000000000, "RW", "block_size_bits_row", "2^Block_Size_Bits_Row is the number of rows for a Block. If block traversal is used, then this must be at least 4 rows (=2). Minimum value is 1 if Address_Decode_Enable =1."},
#else
{4, 8, 0x0000000000000000, "RW", "block_size_bits_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "block_size_bits_col", "Reserved for use as Block_Size_Bits_Col - Fixed as same as Region_Size_Bits_Col for BXT. There is no column traversal of a block in BXT."},
#else
{0, 3, 0x0000000000000000, "RW", "block_size_bits_col", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo179[] = {{"CPGC2_ADDRESS_SIZE", "", 0x000000BC, 6, 0x000000001FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields180[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "address_inversion_rate", "Address_Inversion_Rate determines if the enabled Address Fields toggle inversion on the Command Sequence Boundary (following a Command_Instruction with the Last bit set) or every Command_Instruction. [br]\r\n"
"   0  Invert enabled Address fields after executing the Command_Instruction with the Last bit set. [br][br]\r\n"
"1  Invert enabled Address fields following each Command_Instruction"},
#else
{26, 26, 0x0000000000000000, "RW", "address_inversion_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 25, 0x0000000000000000, "RW", "address_inversion_enable", "Address_Inversion_Enable enables particular Address Fields to be inverted.[br]\r\n"
"[25] Rank_Inversion_Enable.[br]\r\n"
"[24] Bank_Inversion_Enable.[br]\r\n"
"[23] Row_Inversion_Enable.[br]\r\n"
"[22] Col_Inversion_Enable."},
#else
{22, 25, 0x0000000000000000, "RW", "address_inversion_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "address_order0_inc_rate", "Address_Order0_Inc_Rate determines if the Address Order 0 Field is incremented on the Command Sequence Boundary (following a Command_Instruction with the Last bit set) or every Command_Instruction. [br][br]\r\n"
"0  Increment Address after executing the Command_Instruction with the Last bit set.[br][br]\r\n"
"1  Increment Address following each Command_Instruction."},
#else
{21, 21, 0x0000000000000000, "RW", "address_order0_inc_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 20, 0x0000000000000000, "RO/V", "reserved_rank_inc", "All Base Rank addresses are incremented (or decremented) by 2^Rank_Inc (unsigned value) - Fixed at 0 for BXT."},
#else
{18, 20, 0x0000000000000000, "RO/V", "reserved_rank_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 17, 0x0000000000000000, "RO/V", "reserved_bank_inc", "All Base Bank addresses are incremented (or decremented) by 2^Bank_Inc (unsigned value)  - Fixed at 0 for BXT."},
#else
{15, 17, 0x0000000000000000, "RO/V", "reserved_bank_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 14, 0x0000000000000000, "RW", "col_inc", "All Base and Offset Column addresses are incremented (or decremented) by 2^Col_Inc (unsigned value)."},
#else
{11, 14, 0x0000000000000000, "RW", "col_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 9, 0x0000000000000000, "RW", "row_inc", "All Base and Offset Row addresses are incremented (or decremented) by 2^Row_Inc (unsigned value)."},
#else
{6, 9, 0x0000000000000000, "RW", "row_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "block_move_half_block", "if Block_Move_One_Row =1 then[br]\r\n"
"the Block is moved by 1 row[br]\r\n"
"Else if Block_Move_Half_Bock = 1 then[br]\r\n"
"the Block is moved by 2^(Block_Size_Bits_Row)/2 Rows[br]\r\n"
"Else[br]\r\n"
"the Block is moved by = 2^(Row_Block_Size)."},
#else
{5, 5, 0x0000000000000000, "RW", "block_move_half_block", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "block_move_one_row", "See Block_Move_Half_Block for description."},
#else
{4, 4, 0x0000000000000000, "RW", "block_move_one_row", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo180[] = {{"CPGC2_BASE_ADDRESS_CONTROL", "", 0x000000C0, 9, 0x0000000007FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields181[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "address_prbs_high_row", "The higher order bits of the PRBS Address Generator (bits 3 through Address_PRBS_Size-1) will be on the same Row bits when the PRBS Address is selected."},
#else
{25, 25, 0x0000000000000000, "RW", "address_prbs_high_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "address_prbs_high_col", "The higher order bits of the PRBS Address Generator (bits 3 through Address_PRBS_Size-1) will be on the same Column bits when the PRBS Address is selected."},
#else
{24, 24, 0x0000000000000000, "RW", "address_prbs_high_col", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "address_prbs_mid_row", "Bits [2:1] of the Row address will be bits [2:1] of the PRBS Address Generator  when the PRBS Address is selected."},
#else
{17, 17, 0x0000000000000000, "RW", "address_prbs_mid_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "address_prbs_mid_col", "Bits [2:1] of the Column address will be bits [2:1] of the PRBS Address Generator when the PRBS Address is selected."},
#else
{16, 16, 0x0000000000000000, "RW", "address_prbs_mid_col", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "address_prbs_low_row", "LSB of Row address will be the LSB of the PRBS Address Generator when the PRBS Address is selected."},
#else
{9, 9, 0x0000000000000000, "RW", "address_prbs_low_row", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "address_prbs_low_col", "LSB of Column address will be the LSB of the PRBS Address Generator when the PRBS Address is selected."},
#else
{8, 8, 0x0000000000000000, "RW", "address_prbs_low_col", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "address_prbs_enable", "If Address_PRBS_Enable is active, and Address_Decode_Enable is not active in the current Address_Instruction, thenn each command is enabled to use the PRBS address if the Address_Decode_or_PRBS_En bit is set."},
#else
{7, 7, 0x0000000000000000, "RW", "address_prbs_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "address_prbs_size", "Size of PRBS for address generation if Address_PRBS_Enable is active.  See text for PRBS Polynomials being used for each setting."},
#else
{0, 3, 0x0000000000000000, "RW", "address_prbs_size", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo181[] = {{"CPGC2_ADDRESS_PRBS_CONTROL", "", 0x000000C4, 8, 0x0000000003FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields182[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RW", "address_prbs_seed", "Seed for Address PRBS generator."},
#else
{0, 17, 0x0000000000000000, "RW", "address_prbs_seed", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo182[] = {{"CPGC2_ADDRESS_PRBS_SEED", "", 0x000000C8, 1, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields183[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RO/V", "address_prbs_current", "Current value of Address PRBS generator.  Address advances as Address_Order0_Inc_Rate.  The Seed is re-loaded (from Save) at each Algorithm_Instruction boundary."},
#else
{0, 17, 0x0000000000000000, "RO/V", "address_prbs_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo183[] = {{"CPGC2_ADDRESS_PRBS_CURRENT", "", 0x000000CC, 1, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields184[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 17, 0x0000000000000000, "RO/V", "address_prbs_save", "Saved value of Address PRBS generator.  Value is saved automatically during block advance, and restored (from Seed) when Block Traversal (Repeats) is complete. "},
#else
{0, 17, 0x0000000000000000, "RO/V", "address_prbs_save", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo184[] = {{"CPGC2_ADDRESS_PRBS_SAVE", "", 0x000000D0, 1, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields185[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RO/V", "address_instruction_current", "Current Address_Instruction pointer."},
#else
{28, 29, 0x0000000000000000, "RO/V", "address_instruction_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RO/V", "data_instruction_current", "Current Data_Instruction pointer."},
#else
{24, 25, 0x0000000000000000, "RO/V", "data_instruction_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 17, 0x0000000000000000, "RO/V", "algorithm_instruction_current", "Current Algorithm_Instruction pointer."},
#else
{15, 17, 0x0000000000000000, "RO/V", "algorithm_instruction_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RO/V", "command_instruction_current", "Current Command_Instruction pointer."},
#else
{8, 12, 0x0000000000000000, "RO/V", "command_instruction_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "offset_group_instruction_current", "Current Offset_Group as pointed to by the Current Command_Instruction (if an Offset instruction)."},
#else
{6, 6, 0x0000000000000000, "RO/V", "offset_group_instruction_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RO/V", "offset_address_instruction_current", "Current Offset_Address_Instruction pointer."},
#else
{3, 5, 0x0000000000000000, "RO/V", "offset_address_instruction_current", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO/V", "offset_command_instruction_current", "Current Offset_Command_Instruction pointer."},
#else
{0, 2, 0x0000000000000000, "RO/V", "offset_command_instruction_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo185[] = {{"CPGC2_CMD_FSM_CURRENT", "", 0x000000D4, 7, 0x000000003FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields186[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "increment_value", "See Prescaler field for information on this field."},
#else
{28, 31, 0x0000000000000000, "RW", "increment_value", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 25, 0x0000000000000000, "RW", "clock_freq", "When a setting of 1MHz or 1KHz is used in Wait_Clock_Frequency, this field provides a way to tell the hardware the native Memory Controller clock frequency, which is fed into the Prescaler automatically (with a 1 Increment_Value also automatically fed into the counter)."},
#else
{16, 25, 0x0000000000000000, "RW", "clock_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 9, 0x0000000000000000, "RW", "prescaler_for_clock_freq", "In order to make the 'standard' 1 GHz clock for the CPGC specified Wait_Clock_Frequency setting, we need to provide a pre-scaler, and Increment Value to modify the existing Wait_Timer_Current advancement. This field will divide the native Memory Controller clock by the provided value, with '1' being 'No Divide'. After that divide, the Wait_Timer_Current will advance by the 'Increment_Value' field. In this way, we are creating a clock ratio able to 'multiply' the native Memory Controller clock by 'Increment_Value/Prescaler'.  For small values of Wait_Time, the error will be substantial, and it may be better to modify the programming to the '11' Native Clock setting and manually compute the required Wait_Time for the desired delay."},
#else
{0, 9, 0x0000000000000000, "RW", "prescaler_for_clock_freq", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo186[] = {{"CPGC2_WAIT_2_START_CONFIG", "", 0x000000D8, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields187[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "err1_grp_sel", "Err Group 1 Select."},
#else
{13, 14, 0x0000000000000000, "RW", "err1_grp_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000000, "RW", "err0_grp_sel", "Err Group 0 Select."},
#else
{11, 12, 0x0000000000000000, "RW", "err0_grp_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "dpat1_grp_sel", "Dpat Group 1 Select."},
#else
{9, 10, 0x0000000000000000, "RW", "dpat1_grp_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "dpat0_grp_sel", "Dpat Group 0 Select."},
#else
{7, 8, 0x0000000000000000, "RW", "dpat0_grp_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RW", "cmd1_grp_sel", "Cmd Group 1 Select."},
#else
{5, 6, 0x0000000000000000, "RW", "cmd1_grp_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RW", "cmd0_grp_sel", "Cmd Group 0 Select."},
#else
{3, 4, 0x0000000000000000, "RW", "cmd0_grp_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "err1_or_cmd1", "Err group 1 or Cmd group 1 select."},
#else
{2, 2, 0x0000000000000000, "RW", "err1_or_cmd1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "cmd0_or_dpat1", "Cmd group 0  or Dpat group 1 select."},
#else
{1, 1, 0x0000000000000000, "RW", "cmd0_or_dpat1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dpat0_or_err0", "Dpat group 0 or Err group 0 select."},
#else
{0, 0, 0x0000000000000000, "RW", "dpat0_or_err0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo187[] = {{"CPGC2_VISA_MUX_SEL", "", 0x000000DC, 9, 0x0000000000007FFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields188[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "start_test_delay", "Start_Test_Delay is the delay period (in byte clocks) to execute a test(i.e transition to Loopback.Pattern) after the link is in Loopback.Idle and Local_Start_Test is asserted.[br][br]\r\n"
"If Local_Start_Test is set upon the initial enttry to Loopback.Idle then a test (entry to Loopback.Pattern) will immediately start after Start_Test_Delay number of byte clocks is enforced.[br][br]\r\n"
"During Start_Test_test the Valid must not be asserted (i.e Loopback.PM) and no comparison of data will be taking place.[br][br]\r\n"
"Start_Test_Delay=0 is reserved and not allowed.[br][br]\r\n"
"Start_Test_Delay=1 will result in a 1byte clock delay.[br][br]\r\n"
"Start_Test_Delay=2 will result in a 2byte clock delay."},
#else
{24, 31, 0x0000000000000000, "RW", "start_test_delay", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "loopcount", "2^(Loopcount) determines the length of a test.[br][br]\r\n"
"                One Loopcount consists of Pattern_Length followed by PM_Length.[br][br]\r\n"
"                Pattern_Length corresponds to the Loopback Master generating patterns and the Loopback.Slave and/or Loopback Master performing error checking occueeing (valid is assered).[br][br]\r\n"
"                PM_Length corresponds to the functional power savings mode (valid is not asserted).[br][br]\r\n"
"Loopcount=0 means the test is infinite.[br][br]\r\n"
"Loopcount=1 means the test will end after two loops.[br][br]\r\n"
"Loopcount=2 means the test will end after four loops.[br][br]\r\n"
"Loopcount=3 means the test will end after eight loops."},
#else
{16, 20, 0x0000000000000000, "RW", "loopcount", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "pm_length", "PM_Length(i.e Loopback.PM) forms the second half of the loopcount sequence with Pattern_Length (i.e Loopback.Pattern)forming the first half.[br][br]\r\n"
"            PM_Length is used in conjection with Pattern_Length and Loopcount to go in and out of Power Savings Modes in an identical way to how the functional power saving mode behave. This includes post amble, pre-amble, etc.[br][br]\r\n"
"            PM_Length duration is defined in total # of byte clocks.[br][br]\r\n"
"            If PM_Length is set to 0 then no power saving modes will be entered.[br][br]\r\n"
"            If the end of the test has not been reached, (Curren_Loopcount !=Loopcount) the loopcount is incremented and the sequence repeats (Pattern_Length followed by PM_Length).[br][br]\r\n"
"            If the end of the test has not been reached (Current_Loopcount=Loopcount) the link transitions back to Loopback.Idle following the PM state."},
#else
{8, 15, 0x0000000000000000, "RW", "pm_length", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "pattern_length", "Pattern_Length (i.e Loopback.Pattern) forms the first half of the Loopcount sequence with PM_Length (i.e Loopback.PM) forming the second half.[br][br]\r\n"
"            Pattern_Length is the portion of Loopcount when patterns are generated(Loopback Master) and compared (Loopback Master and optionally the Loopback Slave).[br][br]\r\n"
"            Pattern_Length suration is defined in total # of byte clocks. A zero value is illegal.[br][br]\r\n"
"            The Sum of Pattern_Length and PM_Length (Duration of a Loopcount)must always be set to a value of two or more."},
#else
{0, 7, 0x0000000000000000, "RW", "pattern_length", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo188[] = {{"CPGC_LB_SEQ_CFG", "", 0x000000E0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields189[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "initialization_mode", "A change to Initialization_Mode occurs immediately.[br]\r\n"
"00 - OFF - REUT is clock gated.[br]\r\n"
"01 - LSM Mode  - Enter Loopback.Idle state through the appropriate Link Layer bits as a Loopback Master or Loopback Slave.[br]\r\n"
"10 - Force Master - Force entry to Loopback.Idle as a Loopback Master (Supported if Force_Loopback capability is set).[br]\r\n"
"11 - Force Slave - Force entry to Loopback.Idle as Loopback Slave (Supported if Force_Loopback capability is set).[br]\r\n"
"Note: A user must be careful to transition both sides of the Link to Loopback.Idle if switching Initialization_Mode from Force Master or Force Slave to LSM Mode or undefined behavior can be expected.[br]\r\n"
"Note: Initialization Mode should not be changed while Local_Start_Test is set, or while Test_In_Progress is set."},
#else
{12, 13, 0x0000000000000000, "RW", "initialization_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "bind_stop_on_error", "Test will stop based on Global_Error (external input) and Local_Error will drive Global_Error."},
#else
{6, 6, 0x0000000000000000, "RW", "bind_stop_on_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "bind_clear_errors", "Local_Clear_Errors will clear all other REUT instances that have this bit set."},
#else
{5, 5, 0x0000000000000000, "RW", "bind_clear_errors", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "bind_stop_test", "Local_Stop_Test will stop all other REUT instances that have this bit set."},
#else
{4, 4, 0x0000000000000000, "RW", "bind_stop_test", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "bind_start_test", "Local_Start_Test will start all other REUT instances that have this bit  set."},
#else
{3, 3, 0x0000000000000000, "RW", "bind_start_test", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW/V", "local_clear_errors", "Setting Local_Clear_Errors  to 1 will immediately clear all local Error registers (i.e. CPGC_ERR_* registers).[br]\r\n"
"Local_Clear_Errors will immediately clear to 0 after clearing affected registers.[br]\r\n"
"If this bit fails to auto-clear, then there is no clock and the clear will occur at the start of the next test."},
#else
{2, 2, 0x0000000000000000, "RW/V", "local_clear_errors", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/V", "local_stop_test", "If  Local_Stop_Test is set to 1 and a Loopback test is in progress (i.e. Test_In_Progress=1) then a transition to Loopback. Idle will occur as soon as possible (i.e. Link enters Loopback.PM).[br]\r\n"
"Local_Stop_Test will immediately clear to 0 after stopping a Loopback test (i.e. Local_Stop_Test=0 while in Loopback.Idle)."},
#else
{1, 1, 0x0000000000000000, "RW/V", "local_stop_test", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "local_start_test", "If  Local_Start_Test is set a Sequence will immediately start, or wait until entry to Loopback state.  A complete Sequence is defined by the following behavior:[br]\r\n"
"1) An initial delay of Start_Test_Delay byte clocks must first occur in Loopback.PM (with Valid de-asserted).[br]\r\n"
"2) Transition to Loopback.Pattern (Valid asserted) for a duration of Pattern_Length Byte clocks during which data is generated and compared by the Loopback Master and optionally compared by the Loopback Slave.[br]\r\n"
"3) Increment Loopcounter.[br]\r\n"
"4) Optionally Transition to Loopback.PM (with Valid deasserted), if so programmed, for a duration of PM_Length Byte clocks during which power modes are functionally enforced as what would happen normally based on the length of the PM_Length duration.[br]\r\n"
"5) If Current Loopcount !=2^Loopcount then go to step 2.[br]\r\n"
"6) If Current Loopcount !=2^Loopcount then the Link returns to Loopback.Idle, Local_Start_Test is cleared for the Master. Local_Start_Test is not cleared on the Loopback.Slave."},
#else
{0, 0, 0x0000000000000000, "RW/V", "local_start_test", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo189[] = {{"CPGC_LB_SEQ_CTL", "", 0x000000E4, 8, 0x0000000000003FFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields190[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "current_loopcount", "Current_Loopcount indicates how many times the full Sequence has been executed in the TX path. [br][br]\r\n"
"Current_Loopcount is cleared by Local_Clear_Errors."},
#else
{0, 31, 0x0000000000000000, "RO/V", "current_loopcount", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo190[] = {{"CPGC_LB_SEQ_LOOPCOUNT_TX_STATUS", "", 0x000000E8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields191[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "current_loopcount", "Current_Loopcount indicates how many times the full Sequence has been executed in the RX path.[br][br]\r\n"
"Current_Loopcount is cleared by Local_Clear_Errors."},
#else
{0, 31, 0x0000000000000000, "RO/V", "current_loopcount", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo191[] = {{"CPGC_LB_SEQ_LOOPCOUNT_RX_STATUS", "", 0x000000EC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields192[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "current_pattern_length", " Current_Pattern_Length is used in conjuntion with Stop_On_Error_Control conditons to determine where the last failure occurred within Loopback.Pattern.[br][br]\r\n"
"Current_Pattern_Length indicates how many Bytes were left in Loopback.Pattern when the error occurred.[br][br]\r\n"
"Current_Pattern_Length is cleared by Local_Clear_Errors."},
#else
{0, 7, 0x0000000000000000, "RO/V", "current_pattern_length", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo192[] = {{"CPGC_LB_SEQ_PL_RX_STATUS", "", 0x000000F0, 1, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields193[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "panic_refresh_only", "(Not Implemented in BXT) If Panick_Refresh_Only=1, then opportunistic and high priority auto refreshes will be disabled for all ranks and refreshes will only occur when the panic refresh watermark has been exceeded. If Panic_Refresh_Only=0, then refreshes will occur using the existing MC functional refresh logic.[br]\r\n"
"[br]\r\n"
"tREFI defines the average period between refreshes, and the rate that tREFI counter is incremented (in DCLK cycles, default is 4100). This field is a often a shadow register to an exisitng MC tREFI field. tREFI is located in another CR.  In Haswell this is located in the CR TC_RFTP.tREFI (15:0) in MCMNTS."},
#else
{31, 31, 0x0000000000000000, "RW", "panic_refresh_only", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "refzq_en_start_test_sync", "(Not Implemented in BXT) If RefZQ_En_Start_Test_Sync=1, this field will ensure all refresh/ZQ powerdown logic (counters, FSMs, etc.) is kept in the default reset state (no refresh/ZQ happening) while in Loopback.Marker during REUT Mode. Once the test starts and the transition to Loopback.Pattern occurs, the refresh/ZQ logic will behave identical to normal functional MC mode based on the values programmed in the refresh/ZQ CRs. This allows deterministic and reproducible behavior across REUT tests with respect to refresh/ZQ since the logic is synchronized to the start of a REUT test.[br]\r\n"
"If RefZQ_En_Start_Test_Sync=0, the refresh/ZQ logic will not be synchronized to the start of a REUT test and will always behave identical to normal functional MC mode based on the values programmed in the refresh/ZQ CRs, whether in Loopback.Marker or Loopback.Pattern.[br]\r\n"
"[br]\r\n"
"NOTE: This bit should not be used in conjuction with Self Refresh.[br]\r\n"
""},
#else
{8, 8, 0x0000000000000000, "RW", "refzq_en_start_test_sync", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "refresh_rank_mask", "(Not Implemented in BXT) Refresh_Rank_Mask is a per rank field.[br]\r\n"
"[br]\r\n"
"The LSB relates to Rank0 and the MSB relates to the highest Rank.  If the per Rank bit of the Refresh_Rank_Mask is set to 1, then the REUT engine will disable executing any refresh to that rank while in REUT mode.[br]\r\n"
"[br]\r\n"
"If the per rank bit of the Refresh_Rank_Mask is set to 0 and then the REUT engine will enable executing a refresh (assuming the MC has refreshes enabled) to that Rank while in REUT mode based on the Panic_Refresh_Only value."},
#else
{0, 3, 0x0000000000000000, "RW", "refresh_rank_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo193[] = {{"CPGC_MISC_REFRESH_CTL", "", 0x000000F4, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields194[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "always_do_zq", "(Not Implemented in BXT) If Always_Do_ZQ is set to 1, a ZQ operation will always take place after a refresh occurs as long as the ZQ_Rank_Mask for that rank is set to 0.[br]\r\n"
"[br]\r\n"
"If Always_Do_ZQ is set to 0, a ZQ operation will take place at the normal programmed 128*ZQCS_period after a refresh occurs as long as the ZQ_Rank_Mask for that rank is set to 0."},
#else
{31, 31, 0x0000000000000000, "RW", "always_do_zq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "zq_rank_mask", "(Not Implemented in BXT) ZQ Mask is a per rank (Chip Select) field.  The LSB relates to Rank0 and the MSB relates to the highest Rank.[br]\r\n"
"[br]\r\n"
"If the per rank bit of the ZQ Mask is set to 1, then the REUT engine will disable executing ZQ operations to that Rank.   Note that if the Refresh_Rank_Mask for the same rank is set to 1 then the ZQ Mask will have no effect and ZQ will disabled to that rank.[br]\r\n"
"[br]\r\n"
"If the per rank bit of the ZQ mask is set to 0 and refreshes are being issued to the corresponding Rank, ZQ will be issued at a rate equal to 128*ZQCS_period programmed inside the channel TC_ZQCAL CR, always occurring after refreshes occur.[br]\r\n"
"ZQCS_period is the time between ZQCS operations in tREFI*128 (2 to 255, default is 128.[br]\r\n"
"ZQCS_period is located in another CR.  In Haswell this is located in the CR TC_ZQCAL.[br]\r\n"
"ZQCS_period (7:0) in MCMNTS."},
#else
{0, 1, 0x0000000000000000, "RW", "zq_rank_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo194[] = {{"CPGC_MISC_ZQ_CTL", "", 0x000000F8, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields195[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "mpr_train_ddr_on", "(Not Implemented in BXT) This bit is to be set during DDR training.  The MPR pattern (Hardcoded 0101 pattern) from the DRAM will be used to initially train the read timing.  This MPR pattern is accessed via the MR3 DRAM register and, per the JEDEC spec, the mode comes with two key limitations:[br]\r\n"
"[br]\r\n"
"   1. Before entering this mode, all pages must be precharged.[br]\r\n"
"[br]\r\n"
"   2. Once in this mode, the MC can only issue RD or RDA commands.[br]\r\n"
"[br]\r\n"
"   When this CR bit is set, the RAS# and WE# will always drive high.  This will morph any command from the scheduler into either READ or DESELECT.[br]\r\n"
"[br]\r\n"
"   The flow is as follows:[br]\r\n"
"[br]\r\n"
"   1. MRS Mode to write MR3.[br]\r\n"
"[br]\r\n"
"   2. Set MPR_Train_DDR_On.[br]\r\n"
"[br]\r\n"
"   3. Set REUT Mode.[br]\r\n"
"[br]\r\n"
"   4. Wait for all pages to close (page table idle counter to expire).[br]\r\n"
"[br]\r\n"
"   5. Run REUT Test.[br]\r\n"
"[br]\r\n"
"   6. Stop Test, clear MPR_Train_DDR_On bit, clear MR3 register.[br]\r\n"
"[br]\r\n"
"   7. Continue with other REUT tests.[br]\r\n"
"[br]\r\n"
"   Note that ZQ, CKE and Refresh should be disabled using the appropriate CR settings during MPR_Train_DDR_On."},
#else
{31, 31, 0x0000000000000000, "RW", "mpr_train_ddr_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "odt_on", "(Not Implemented in BXT) ODT_on is a 4-bit field, one bit per rank (Chip Select).  The LSB relates to Rank0 and the MSB relates to the highest Rank.  When ODT_Override is set to 1 for a rank the value in ODT_On will be used as the ODT value for that rank.[br]\r\n"
""},
#else
{16, 17, 0x0000000000000000, "RW", "odt_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "odt_override", "(Not Implemented in BXT) ODT_Override is a per rank field.  The LSB relates to Rank0 and the MSB relates to the highest Rank. When ODT_Override is set to 1 for a rank, the ODT functional logic will be bypassed and the ODT_On value for that rank will be used. When ODT_Override is set to 0 for a rank, the ODT functional logic will drive the ODT value for that rank.[br]\r\n"
""},
#else
{0, 1, 0x0000000000000000, "RW", "odt_override", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo195[] = {{"CPGC_MISC_ODT_CTL", "", 0x000000FC, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields196[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "cke_on", "(Not Implemented in BXT) CKE_On is a 4-bit field, one bit per rank.  The LSB relates to Rank0 and the MSB relates to the highest Rank.  In REUT mode when the per rank bit is set CKE will be always on for that rank."},
#else
{16, 17, 0x0000000000000000, "RW", "cke_on", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "cke_en_start_test_sync", "(Not Implemented in BXT) When CKE_En_Start_Test_Sync is set to 1 this field will ensure all CKE powerdown logic (counters, FSMs, etc.) is kept in the default reset state (no CKE powerdowns happening) while in Loopback.Marker during REUT Mode. Once the test starts and the transition to Loopback.Pattern occurs the CKE powerdown logic will behave identical to normal functional MC mode based on the values programmed in the powerdown CR, PM_PDWN_config_0_0_0_MCHBAR. This allows deterministic and reproducible behavior across REUT tests with respect to CKE powerdown since the logic is synchronized to the start of a REUT test.[br]\r\n"
"[br]\r\n"
"When CKE_En_Start_Test_Sync is set to 0 the CKE powerdown logic will not be synchronized to the start of a REUT test and will always behave identical to normal functional MC mode based on the values programmed in the powerdown CR, PM_PDWN_config_0_0_0_MCHBAR, whether in Loopback.Marker or Loopback.Pattern.[br]\r\n"
"[br]\r\n"
"NOTE: This bit should not be used in conjuction with Self Refresh.[br]\r\n"
""},
#else
{8, 8, 0x0000000000000000, "RW", "cke_en_start_test_sync", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "cke_override", "(Not Implemented in BXT) CKE_Override is a a per rank field.  The LSB relates to Rank0 and the MSB relates to the highest Rank. When CKE_Override is set to 1 for a rank, the CKE functional logic will be bypassed and the CKE_On value for that rank will be used. When CKE_Override is set to 0 for a rank, the CKE functional logic will drive the CKE value for that rank.[br]\r\n"
""},
#else
{0, 1, 0x0000000000000000, "RW", "cke_override", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo196[] = {{"CPGC_MISC_CKE_CTL", "", 0x00000100, 3, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields197[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "init_mrw_2n_cs", "(Not Implemented in BXT) When sending a MRW command via MRH and setting the Init_MRW bit, send the CS for two DCLK cycles (on the third and fourth cycles, rather than on just the third one)."},
#else
{31, 31, 0x0000000000000000, "RW", "init_mrw_2n_cs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000001, "RW", "ck_to_cke_delay", "(Not Implemented in BXT) TBD."},
#else
{12, 13, 0x0000000000000001, "RW", "ck_to_cke_delay", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "reset_delay", "(Not Implemented in BXT) Inserts an N Dclk delay ranging from 0 to 7 after the N to 1 Reset on Cmd is triggered."},
#else
{8, 11, 0x0000000000000000, "RW", "reset_delay", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "reset_on_command", "(Not Implemented in BXT) N:1 mode is set and utilized as designed in the functional MC logic where N is the number of cycles of allowed continuous CMD cycles before the MC logic will stall a sequence and insert a tri-state bubble.[br]\r\n"
"[br]\r\n"
"When Deselect traffic is driven by the CADB (combination of Subsequence_Deselect_Enable being set, CMD_Deselect_Enable enabling deselects, and a non zero value for Lane_Deselect_Enable) all Deselect cycles within the MC scheduler logic will be considered as consecutive Select cycles in the N:1 logic and thus a tri-state bubble will be inserted regularly as enforced by the N:1 logic.  Tristate effects both select and deselect cycles.[br]\r\n"
"[br]\r\n"
"The N:1 logic can also be triggered to insert a tri-state bubble and reset the N:1 logic after a programmable delay (Reset_N_to_1_Delay=0-7 Dclks) after a PRE/ACT/RD/WR CMD.  This allows one to synchronize the N:1 logic periodically to ensure the correct worst case pattern between victim and aggressor occurs.[br]\r\n"
"[br]\r\n"
"Reset N to 1 Logic on a WR (bit 4).[br]\r\n"
"Reset N to 1 Logic on a RD (bit 5).[br]\r\n"
"Reset N to 1 Logic on a ACT (bit 6).[br]\r\n"
"Reset N to 1 Logic on a PRE (bit 7)."},
#else
{4, 7, 0x0000000000000000, "RW", "reset_on_command", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x0000000000000005, "RW", "cmd_rate_limit", "(Not Implemented in BXT) Cmd_Rate_Limit - The legal range is 2-7."},
#else
{1, 3, 0x0000000000000005, "RW", "cmd_rate_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_cmd_rate_limit", "(Not Implemented in BXT) Enable the Cmd_Rate_Limit."},
#else
{0, 0, 0x0000000000000000, "RW", "enable_cmd_rate_limit", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo197[] = {{"CPGC_MISC_CMD_RATE", "", 0x00000104, 6, 0x00000000FFFFFFFF, 0x000000000000100A}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields198[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "trigger_out_on_test_done", "(Not Implemented in BXT) Setting Trigger_Out_On_Test_Done enables external equipment to be synced deterministically to the exact moment when Trigger_Out_On_Channel_Test_Done_Status_1 is set.[br]\r\n"
"[br]\r\n"
"This capability enables external test equipment to be deterministically synched to when Channel 1 REUT test is completed.  This is required to allow synchronous REUT operation with external test hardware (HVM Tester, BERT, etc.).[br]\r\n"
"[br]\r\n"
"When Trigger_Out_On_Channel_Test_Done_Status_1 is set a deterministic externally viewable uBP trigger is generated each time REUT_GLOBAL_ERR.Channel_Test_Done_Status_1 is set to 1."},
#else
{3, 3, 0x0000000000000000, "RW", "trigger_out_on_test_done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "trigger_out_on_error", "(Not Implemented in BXT) Setting Trigger_Out_On_Error_0 enables external equipment to be synced deterministically to when any bit in Data_Error_Status or ECC_Error_Status on channel 0 is set.  Once any bit in Data_Error_Status or ECC_Error_Status on channel 0 is set no additional triggers will be generated.[br]\r\n"
"[br]\r\n"
"This capability enables external test equipment to be synched to an error event within REUT on channel 0.  This is required to allow synchronous REUT operation with external test hardware (HVM Tester, BERT, etc.).[br]\r\n"
"[br]\r\n"
"When Trigger_Out_On_Error_0 is set a deterministic uBP trigger is generated in relation to when REUT_CH_ERR_DATA_STATUS.Data_Error_Status or REUT_CH_ERR_ECC_CHUNK_RANK_BYTE_NTH_STATUS.ECC_Error_Status becomes non zero on channel 0.[br]\r\n"
""},
#else
{2, 2, 0x0000000000000000, "RW", "trigger_out_on_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "trigger_out_global_start", "(Not Implemented in BXT) Setting Trigger_Out_Global_Start will generate a deterministic external uBP trigger that is based on Global_Start_Test being set.[br]\r\n"
"[br]\r\n"
"This capability enables a test to start in a synchronous fashion with respect to an external event.  This is required to allow synchronous REUT operation with external test hardware (HVM Tester, BERT, etc.).[br]\r\n"
"[br]\r\n"
"When Trigger_OUT_Global_Start is set a deterministic uBP trigger is generated each time REUT_GLOBAL_CTL.Global_Start_Test is set."},
#else
{1, 1, 0x0000000000000000, "RW", "trigger_out_global_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "trigger_in_global_start", "(Not Implemented in BXT) Setting Trigger_In_Global_Start enables a test to start based on a uBP trigger.  This capability enables a test to start in a synchronous fashion with respect to an external event.[br]\r\n"
"[br]\r\n"
"This is required to allow synchronous REUT operation with external test hardware (HVM Tester, BERT, etc.).[br]\r\n"
"When Trigger_In_Global_Start is set the uBP used to start a REUT test will set REUT_GLOBAL_CTL.Global_Start_Test on a deterministic boundary."},
#else
{0, 0, 0x0000000000000000, "RW", "trigger_in_global_start", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo198[] = {{"CPGC_MISC_EXT_TRIGGER", "", 0x00000108, 4, 0x000000000000000F, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields199[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW/V", "continue_single_mode", "When in Single_Command_Mode setting this bit will enable a new command to be issued. This bit immediately clears after being set."},
#else
{9, 9, 0x0000000000000000, "RW/V", "continue_single_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "single_cmd_mode", "Enter Single Command mode were we will issue one command from CPGC and then pause command issuing. This may be resumed by setting Continue_Single_Mode, or normal continuous operation resumed by clearing this bit."},
#else
{8, 8, 0x0000000000000000, "RW", "single_cmd_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW/V", "clear_errors", "Setting this bit will immediately clear all error registers and error status. This bit will automatically self clear."},
#else
{2, 2, 0x0000000000000000, "RW/V", "clear_errors", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/V", "stop_test", "Forces an exit from the tests running on this engine/channel.  Note that this will also cause a test stop for all engines with GLB_STOP_BIND set. This bit will self clear."},
#else
{1, 1, 0x0000000000000000, "RW/V", "stop_test", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "start_test", "Used to initiate a transition to active mode on this engine/channel (note that INIT_MODE has to be programmed first).  Note that this will also cause a test start for all engines with GLB_START_BIND set.[br]\r\n"
"This bit will self clear."},
#else
{0, 0, 0x0000000000000000, "RW/V", "start_test", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo199[] = {{"CPGC_SEQ_CTL", "", 0x0000010C, 5, 0x00000000000003FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields200[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "request_data_size", "Size of requests CPGC is issuing, 64B and 32B transactions and is encoded as follows:[br][br]\r\n"
"                        0 - 32 Byte Transactions[br][br]\r\n"
"                        1 - 64 Byte Transactions"},
#else
{22, 22, 0x0000000000000000, "RW", "request_data_size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000001, "RW", "cpgc_control", "Used to indicate the OPIO(MCDRAM) or CPGC(DDR) mode.[br][br]\r\n"
"1 - CPGC Mode.[br][br]\r\n"
"0 - OPIO Mode."},
#else
{21, 21, 0x0000000000000001, "RW", "cpgc_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "initialization_mode", "000 - IDLE MODE[br]\r\n"
"001 - ACTIVE MODE[br]\r\n"
"010 - DIRECT MODE[br]\r\n"
"011 - ACTIVE MODE[br]\r\n"
"100 - MRS MODE[br]\r\n"
"101 - ERROR DUMP MODE (Reserved)[br]\r\n"
"110 - WDB FILL MODE (Reserved)[br]\r\n"
"111 - REWIND MODE (Reserved)"},
#else
{12, 14, 0x0000000000000000, "RW", "initialization_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "global_stop_bind", "Setting this bit will bind this channel engine to all other channel engines.  A test stop (both forced and due to a stop condition) for any channel engine with GLOBAL_STOP_BIND set will cause the same action to occur on all engines with GLOBAL_STOP_BIND set.  This feature is usually used when synchronization between multiple engines/channels necessitates a global control of all supported engines.[br] Note: this field is only available if multiple channels/engines are supported for the current implementation, otherwise it is reserved."},
#else
{11, 11, 0x0000000000000000, "RW", "global_stop_bind", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "global_start_bind", "Setting this bit will bind this channel engine to all other channel engines. A test start for any channel with GLOBAL_START_BIND set will cause the same action to occur on all engines with GLOBAL_START_BIND set. This feature is usually used when synchronization between multiple engines/channels necessitates a global control of all supported engines.[br] Note: this field is only available if multiple channels/engines are supported for the current implementation, otherwise it is reserved."},
#else
{10, 10, 0x0000000000000000, "RW", "global_start_bind", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "global_stop_on_err_bind", "Setting this bit will bind this channel engine to all other channel engines. A test stop (due to an error condition) for any channel with GLOBAL_STOP_ON_ERR_BIND set will cause the same action to occur on all engines with GLOBAL_STOP_ON_ERR_BIND set. This feature is usually used when synchronization between multiple engines/channels necessitates a global control of all supported engines.[br] Note: this field is only available if multiple channels/engines are supported for the current implementation, otherwise it is reserved."},
#else
{9, 9, 0x0000000000000000, "RW", "global_stop_on_err_bind", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "global_clear_err_bind", "Setting this bit will bind this channel engine to all other channel engines. Clearing all error registers and error status for any channel with GLOBAL_CLEAR_ERR_BIND set will cause the same action to occur on all engines with GLOBAL_CLEAR_ERR_BIND set. This feature is usually used when synchronization between multiple engines/channels necessitates a global control of all supported engines.[br] Note: this field is only available if multiple channels/engines are supported for the current implementation, otherwise it is reserved."},
#else
{8, 8, 0x0000000000000000, "RW", "global_clear_err_bind", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "enable_constant_write_strobe", "(Not Implemented in BXT) Setting this bit will cause the Tx write strobe to be driven out constantly while a test is in progress.[br] Note: This is most often used to help train the correct setting for per rank write levelling."},
#else
{6, 6, 0x0000000000000000, "RW", "enable_constant_write_strobe", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo200[] = {{"CPGC_SEQ_CFG_A", "", 0x00000110, 8, 0x00000000007FFFFF, 0x0000000000200000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields201[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 9, 0x0000000000000000, "RW", "start_delay", "Number of clock cycles (in CPGC-S clock domain) the start of the test is delayed by after START_TEST has been asserted by the user. This is usually used to synchronize multiple SoC CPGC engines on multiple channels according to a defined phase relationship."},
#else
{0, 9, 0x0000000000000000, "RW", "start_delay", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo201[] = {{"CPGC_SEQ_CFG_B", "", 0x00000114, 1, 0x00000000000003FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields202[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO/V", "test_done", "This bit will be set when the test is complete (or has been forced to exit due to a stop condition). Bit is cleared on a reset or when user starts another test."},
#else
{31, 31, 0x0000000000000000, "RO/V", "test_done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO/V", "test_busy", "This bit will be set when once a test has started.  Bit is cleared on a reset or once test is done (or has been forced to exit due a stop condition)."},
#else
{30, 30, 0x0000000000000000, "RO/V", "test_busy", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO/V", "algo_done", "This bit will be set when all the algorithms are complete. It is cleared on a reset."},
#else
{29, 29, 0x0000000000000000, "RO/V", "algo_done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RO/V", "single_mode_paused", "This bit will be set when a command has been issued and we are paused due to Single_Command_Mode.  The test may be continued by either clearing Single_Command_Mode or by setting Continue_Single_Mode."},
#else
{28, 28, 0x0000000000000000, "RO/V", "single_mode_paused", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo202[] = {{"CPGC_SEQ_STATUS", "", 0x00000118, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields203[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 10, 0x0000000000000020, "RW/P", "wr_credit_init", "This gives the default value for write credit counter at reset."},
#else
{5, 10, 0x0000000000000020, "RW/P", "wr_credit_init", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000010, "RW/P", "rd_credit_init", "This gives the default value for read credit counter at reset."},
#else
{0, 4, 0x0000000000000010, "RW/P", "rd_credit_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo203[] = {{"CPGC2_CHICKEN_REG", "", 0x0000011C, 2, 0x00000000000007FF, 0x0000000000000410}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields204[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo204[] = {{"CPGC2_RASTER_REPO_CONTENT_0_", "", 0x00000120, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields205[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo205[] = {{"CPGC2_RASTER_REPO_CONTENT_1_", "", 0x00000124, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields206[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo206[] = {{"CPGC2_RASTER_REPO_CONTENT_2_", "", 0x00000128, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields207[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo207[] = {{"CPGC2_RASTER_REPO_CONTENT_3_", "", 0x0000012C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields208[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo208[] = {{"CPGC2_RASTER_REPO_CONTENT_4_", "", 0x00000130, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields209[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo209[] = {{"CPGC2_RASTER_REPO_CONTENT_5_", "", 0x00000134, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields210[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo210[] = {{"CPGC2_RASTER_REPO_CONTENT_6_", "", 0x00000138, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields211[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo211[] = {{"CPGC2_RASTER_REPO_CONTENT_7_", "", 0x0000013C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields212[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo212[] = {{"CPGC2_RASTER_REPO_CONTENT_8_", "", 0x00000140, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields213[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo213[] = {{"CPGC2_RASTER_REPO_CONTENT_9_", "", 0x00000144, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields214[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo214[] = {{"CPGC2_RASTER_REPO_CONTENT_10_", "", 0x00000148, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields215[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo215[] = {{"CPGC2_RASTER_REPO_CONTENT_11_", "", 0x0000014C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields216[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo216[] = {{"CPGC2_RASTER_REPO_CONTENT_12_", "", 0x00000150, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields217[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo217[] = {{"CPGC2_RASTER_REPO_CONTENT_13_", "", 0x00000154, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields218[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo218[] = {{"CPGC2_RASTER_REPO_CONTENT_14_", "", 0x00000158, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields219[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "content", "Flat register read access to Raster Repository.[br]\r\n"
"The format of this is 2 consecutive addresses contain a complete 64-bit data chunk error bit-map, or one Error_Summary entry.[br]\r\n"
"In Mode3, there are up to 4 Row addresses for read failures for the associated Bank, based on the indicators in RASTER_REPO_CONTENT_ECC*."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "content", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo219[] = {{"CPGC2_RASTER_REPO_CONTENT_15_", "", 0x0000015C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields220[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO/V/P", "ecc_chunk3", "ECC chunk 3 raster when in Mode 1."},
#else
{28, 31, 0x0000000000000000, "RO/V/P", "ecc_chunk3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RO/V/P", "fail_count3", "Bank 3 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{26, 27, 0x0000000000000000, "RO/V/P", "fail_count3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RO/V/P", "fail_any3", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{25, 25, 0x0000000000000000, "RO/V/P", "fail_any3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO/V/P", "fail_excess3", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{24, 24, 0x0000000000000000, "RO/V/P", "fail_excess3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RO/V/P", "ecc_chunk2", "ECC chunk 2 raster when in Mode 1."},
#else
{20, 23, 0x0000000000000000, "RO/V/P", "ecc_chunk2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RO/V/P", "fail_count2", "Bank 2 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{18, 19, 0x0000000000000000, "RO/V/P", "fail_count2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO/V/P", "fail_any2", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{17, 17, 0x0000000000000000, "RO/V/P", "fail_any2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO/V/P", "fail_excess2", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{16, 16, 0x0000000000000000, "RO/V/P", "fail_excess2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO/V/P", "ecc_chunk1", "ECC chunk 1 raster when in Mode 1."},
#else
{12, 15, 0x0000000000000000, "RO/V/P", "ecc_chunk1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO/V/P", "fail_count1", "Bank 1 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{10, 11, 0x0000000000000000, "RO/V/P", "fail_count1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V/P", "fail_any1", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{9, 9, 0x0000000000000000, "RO/V/P", "fail_any1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO/V/P", "fail_excess1", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{8, 8, 0x0000000000000000, "RO/V/P", "fail_excess1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO/V/P", "ecc_chunk0", "ECC chunk 0 raster when in Mode 1."},
#else
{4, 7, 0x0000000000000000, "RO/V/P", "ecc_chunk0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO/V/P", "fail_count0", "Bank 0 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{2, 3, 0x0000000000000000, "RO/V/P", "fail_count0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V/P", "fail_any0", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{1, 1, 0x0000000000000000, "RO/V/P", "fail_any0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V/P", "fail_excess0", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{0, 0, 0x0000000000000000, "RO/V/P", "fail_excess0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo220[] = {{"CPGC2_RASTER_REPO_CONTENT_ECC1", "", 0x00000160, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields221[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO/V/P", "ecc_chunk7", "ECC chunk 7 raster when in Mode 1."},
#else
{28, 31, 0x0000000000000000, "RO/V/P", "ecc_chunk7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RO/V/P", "fail_count7", "Bank 7 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{26, 27, 0x0000000000000000, "RO/V/P", "fail_count7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RO/V/P", "fail_any7", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{25, 25, 0x0000000000000000, "RO/V/P", "fail_any7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO/V/P", "fail_excess7", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{24, 24, 0x0000000000000000, "RO/V/P", "fail_excess7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RO/V/P", "ecc_chunk6", "ECC chunk 6 raster when in Mode 1."},
#else
{20, 23, 0x0000000000000000, "RO/V/P", "ecc_chunk6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RO/V/P", "fail_count6", "Bank 6 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{18, 19, 0x0000000000000000, "RO/V/P", "fail_count6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO/V/P", "fail_any6", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{17, 17, 0x0000000000000000, "RO/V/P", "fail_any6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO/V/P", "fail_excess6", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{16, 16, 0x0000000000000000, "RO/V/P", "fail_excess6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO/V/P", "ecc_chunk5", "ECC chunk 5 raster when in Mode 1."},
#else
{12, 15, 0x0000000000000000, "RO/V/P", "ecc_chunk5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO/V/P", "fail_count5", "Bank 5 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{10, 11, 0x0000000000000000, "RO/V/P", "fail_count5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V/P", "fail_any5", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{9, 9, 0x0000000000000000, "RO/V/P", "fail_any5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO/V/P", "fail_excess5", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{8, 8, 0x0000000000000000, "RO/V/P", "fail_excess5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO/V/P", "ecc_chunk4", "ECC chunk 4 raster when in Mode 1."},
#else
{4, 7, 0x0000000000000000, "RO/V/P", "ecc_chunk4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO/V/P", "fail_count4", "Bank 4 Number of failing address. 0=none or 1, 1=2, 2=3, and 3=4 entries."},
#else
{2, 3, 0x0000000000000000, "RO/V/P", "fail_count4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V/P", "fail_any4", "0 - indicates no failing address, 1 - indicates 1 or more failing address in the corresponding Content entry."},
#else
{1, 1, 0x0000000000000000, "RO/V/P", "fail_any4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V/P", "fail_excess4", "0  indicates no more than fail_max failing addresses, 1 - indicates more than fail_max failing addresses."},
#else
{0, 0, 0x0000000000000000, "RO/V/P", "fail_excess4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo221[] = {{"CPGC2_RASTER_REPO_CONTENT_ECC2", "", 0x00000164, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields222[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "read_command_count_current", "Current count of reads - freezes on stop_on_error conditions at the number of reads including the error that caused the stop."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "read_command_count_current", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo222[] = {{"CPGC2_READ_COMMAND_COUNT_CURRENT", "", 0x00000168, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields223[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/P", "mask_first_n_reads", "0=no masking, N= number of reads that will not result in any error indication for the raster repository."},
#else
{0, 31, 0x0000000000000000, "RW/P", "mask_first_n_reads", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo223[] = {{"CPGC2_MASK_ERRS_FIRST_N_READS", "", 0x0000016C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields224[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/V", "rasterrepoclear", "Reset the raster repo entries. This bit auto-clears."},
#else
{31, 31, 0x0000000000000000, "RW/V", "rasterrepoclear", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/P", "stoponraster", "If Raster Mode 1, test will stop after loading the bitmap into the raster. If Raster Mode 2, test will stop after loading 8 errors in the raster."},
#else
{30, 30, 0x0000000000000000, "RW/P", "stoponraster", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW/P", "rasterrepomode", "00 Mode 1 BitMap Mode.[br]\r\n"
"01 Mode 2 Summary Mode.[br]\r\n"
"10 mode 3 Filtered Failed Row Mode."},
#else
{16, 17, 0x0000000000000000, "RW/P", "rasterrepomode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW/P", "failmax", "Maximum number of failing address before an additional failing address will set fail_excess for any bank.[br]\r\n"
"00  one failure, 01 - two failures, 10 - three failures, 11- four failures.[br]\r\n"
""},
#else
{10, 11, 0x0000000000000000, "RW/P", "failmax", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V/P", "failanyall", "0 - indicates no failing addresses.[br]\r\n"
"1 - indicates 1 or more failing addresses."},
#else
{9, 9, 0x0000000000000000, "RO/V/P", "failanyall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO/V/P", "failexcessall", "0 - indicates less than or exactly max_fail failing addresses on all banks.[br]\r\n"
"1 - indicates at least one bank's errors exceed the max_fail limit."},
#else
{8, 8, 0x0000000000000000, "RO/V/P", "failexcessall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RO/V/P", "numerrlogged", "Indicates the current number of errors loaded in the raster repo in Mode 2. Max value is 8."},
#else
{4, 6, 0x0000000000000000, "RO/V/P", "numerrlogged", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO/V/P", "rasterrepofull", "Indicates when the no. of errors logged exceed max value of 8."},
#else
{2, 2, 0x0000000000000000, "RO/V/P", "rasterrepofull", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V/P", "summaryvalid", "Indicates when the summary information of the erroneous bitmap is loaded in the current summary buffer. This information consist of Algorithmic data, Physical Addr (Rank, Bank,Row,Col) and 8 2-bit error summary for every chunk."},
#else
{1, 1, 0x0000000000000000, "RO/V/P", "summaryvalid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V/P", "bitmapvalid", "Indicates when Mode 1 erroneous bitmap data is loaded in the raster repo."},
#else
{0, 0, 0x0000000000000000, "RO/V/P", "bitmapvalid", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo224[] = {{"CPGC2_RASTER_REPO_STATUS", "", 0x00000170, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields225[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO/V/P", "algorithm_summary", "Algorithm_Summary - currently formated as:[br]\r\n"
"[2:0] Offset_Command_Instruction_Current.[br]\r\n"
"[5:3] Offset_Address_Instruction_Current.[br]\r\n"
"[10:6] Command_Instruction_Current.[br]\r\n"
"[13:11] Algorithm_Instruction_Current.[br]\r\n"
"[15:14] Data_Instruction_Current."},
#else
{16, 31, 0x0000000000000000, "RO/V/P", "algorithm_summary", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO/V/P", "error_summary", "Error_Summary - formatted as a pair of adjacent bits for each chunk, 00=no error in that chunk, 01=one error in that chunk, 10=two errors in that chunk, 11=three or more errors in that chunk."},
#else
{0, 15, 0x0000000000000000, "RO/V/P", "error_summary", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo225[] = {{"CPGC2_ERR_SUMMARY_A", "", 0x00000174, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields226[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO/V/P", "physical_address_summary", "Error_Summary - Physical Address encoded as:[br]\r\n"
"[7:0] Column, [25:8] Row, [28:26] Bank, [29] Rank."},
#else
{2, 31, 0x0000000000000000, "RO/V/P", "physical_address_summary", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RO/V/P", "algorithm_summary", "Algorithm_Summary - currently formated as:[br]\r\n"
"[1:0] Address_Instruction_Current."},
#else
{0, 1, 0x0000000000000000, "RO/V/P", "algorithm_summary", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo226[] = {{"CPGC2_ERR_SUMMARY_B", "", 0x00000178, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields227[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "dg_reserved", "Reserved for expansion of Error_Summary (bits 7:0)."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "dg_reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo227[] = {{"CPGC2_ERR_SUMMARY_C", "", 0x0000017C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields228[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RO/V", "rd_buf_ptr", "Pointer to current entry in the data pattern buffers used for generating the read data."},
#else
{24, 27, 0x0000000000000000, "RO/V", "rd_buf_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RO/V", "wr_buf_ptr", "Pointer to current entry in the data pattern buffers used for generating the write data."},
#else
{20, 23, 0x0000000000000000, "RO/V", "wr_buf_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RW", "buf_end_pntr", "Pointer to last data pattern buffer entry before wrapping back to BUF_STRT_PTR if incrementing is enabled through being different from BUF_STRT_PTR.[br] Note: The actual size of this field depends on the # of lines supported for data generation. i.e If 1 or 2 lines are supported then it is a 1 bit field, if 8 lines are supported then 3 bits are available. Currently the RTL uses internal CPGC buffers so it has 4 lines and requires 2 bits."},
#else
{16, 18, 0x0000000000000000, "RW", "buf_end_pntr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "buf_strt_pntr", "Pointer to first buffer entry.  Also used as the only entry if BUF_INC_EN is not enabled.[br] Note: The actual size of this field depends on the # of lines supported for data generation (DATA_PAT_DEPTH_CAP), i.e If 1 or 2 lines are supported then it is a 1 bit field, if 16 lines are supported then the whole 4 bits are available. Currently the RTL uses internal CPGC buffers so it has 8 lines and requires 3 bits."},
#else
{8, 10, 0x0000000000000000, "RW", "buf_strt_pntr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "buf_pntr_inc_scale", "If set, the buffer pointer will be incremented at a linear rate given by BUF_PTR_INC_RATE, otherwise the buffer pointer will be incremented at an exponential rate given by BUF_PTR_INC_RATE.[br][br]\r\n"
"1=Buffer Pointer Increment Rate field is treated as a linear number.[br][br]\r\n"
"0=Buffer Pointer Increment Rate field is treated is an exponential number."},
#else
{6, 6, 0x0000000000000000, "RW", "buf_pntr_inc_scale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "buf_pntr_inc_rate", "0: Each buffer entry will be used for 2^BUF_PTR_INC_RATE number of bursts (64Bytes).[br]\r\n"
"1: Each buffer entry will be used for BUF_PTR_INC_RATE + 1 number of 8-UI[br]\r\n"
"-- before incrementing the buffer pointer by 1.[br]\r\n"
" Note:  To disable Buffer Pointer increments, set BUF_END_PTR==BUF_STRT_PTR."},
#else
{0, 5, 0x0000000000000000, "RW", "buf_pntr_inc_rate", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo228[] = {{"CPGC_DPAT_BUF_CTL", "", 0x00000180, 6, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields229[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "reload_lfsr_seed_rate", "Reload_LFSR_Seed_Rate only exists if the LFSR_Save_Restore capability is set to 1.[br][br]\r\n"
"Reload_LFSR_Seed_Rate and Save_LFSR_Seed_Rate is most often used in conjunction with Lane_Rotate_Rate where the user desires to replay the same deterministic LFSR stress as the victim aggressor patterns shifts Lanes left.  When the victim aggressor pattern returns to the starting position the current LFSR stress is saved using Save_LFSR_Seed_Rate to allow the LFSR stress to advance for the new period.[br][br]\r\n"
"2^(Reload_LFSR_Seed_Rate-1) defines the periodic Loopcount interval that the current LFSR Seed UNISEQ#_RDSTAT.Uniseq_RdStat is reloaded from CPGC_UNISEQ#_RDSAVE.Pattern_Buffer.[br][br]\r\n"
"When the Save_LFSR_Seed_Rate and Reload_LFSR_Seed_Rate is reached in the same Bit only the saving of the LFSR seed takes place.[br][br]\r\n"
"Examples:[br][br]\r\n"
"0=Disable - The current LFSR seed is never reloaded.[br][br]\r\n"
"1=The current LFSR seed  is reloaded every Loopcount.[br][br]\r\n"
"2=The current LFSR seed  is reloaded every other Loopcount.[br][br]\r\n"
"3=The current LFSR seed  is reloaded every fourth Loopcount."},
#else
{24, 28, 0x0000000000000000, "RW", "reload_lfsr_seed_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "save_lfsr_seed_rate", "Save_LFSR_Seed_Rate only exists if the LFSR_Save_Restore capability is set to 1.[br][br]\r\n"
"See Reload_LFSR_Seed_Rate for use model.[br][br]\r\n"
"UNISEQ#_RDSAVE.Pattern_Buffer is initially loaded at the start of a test with UNISEQ#_RDSTAT.Uniseq_RdStat (the Seed). [br][br]\r\n"
"2^(Reload_LFSR_Seed_Rate-1) * (Save_LFSR_Seed_Rate) defines the periodic Loopcount interval that the current LFSR Seed is saved into UNISEQ#_RDSAVE.Pattern_Buffer.[br][br]\r\n"
"When the Save_LFSR_Seed_Rate and Reload_LFSR_Seed_Rate is reached in the same Loopcount only the saving of the LFSR seed takes place.[br][br]\r\n"
"Examples:[br][br]\r\n"
"0=Disable - The current LFSR seed (UNISEQ#_RDSTAT.Uniseq_RdStat) is saved only at the start of test into UNISEQ#_RDSAVE.Pattern_Buffer.[br][br]\r\n"
"1=Illegal (Would save every Reload and effectively disable both Save and Reload).[br][br]\r\n"
"2=The current LFSR seed is saved every other 2^(Reload_LFSR_Seed_Rate-1) Loopcounts.[br][br]\r\n"
"3=The current LFSR seed is saved every third Reload (and Reload does not happen)."},
#else
{16, 23, 0x0000000000000000, "RW", "save_lfsr_seed_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "ecc_data_source_sel", "Indicates whether byte 0 (Dq0-Dq7) or byte 7 (dq56-dq63) is transmitted and compared for the ECC byte.[br]\r\n"
"0=byte group 0 will be transmitted and compared for the ECC byte.[br]\r\n"
"1=byte group 7 will be transmitted and compared for the ECC byte.[br]\r\n"
"Hardware directs if ECC is included within Generation and Checking.[br]\r\n"
"This bit may be reserved if ECC is not supported, or if this functionality is controlled from a different register."},
#else
{15, 15, 0x0000000000000000, "RW", "ecc_data_source_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "ecc_replace_byte_control", "ECC_Replace_Byte_Control is used by the Read data path to mux the received ECC byte into the same byte group indicated by ECC_Data_Source_Sel.[br]\r\n"
"This is needed to capture ECC cacheline errors into the WDB when Enable_WDB_Error_Capture is set to 1.[br]\r\n"
"This bit may be reserved if ECC is not supported, or if this functionality is controlled from a different register."},
#else
{14, 14, 0x0000000000000000, "RW", "ecc_replace_byte_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "ecc_disable", "Setting this bit will internally disable all related ECC features in CPGC having the effect of generating all '1 in the ECC CPGC interface outputs, and of Binding to '0 all the ECC interface CPGC inputs. ECC masks and error comparisons will be disabled as well.[br]\r\n"
"If ECC is supported, but not directly passed to CPGC, then this bit when set will enable the ECC_REPLACE_BYTE_CONTROL and ECC_DATA_SOURCE_SEL functionality, to allow driving of ECC from another ByteLane, and replacing the incoming data with ECC for that ByteLane.[br]\r\n"
"When ECC is disabled with this bit, then the output of CPGC will be determined based on BE_TRAIN_ERR_EN and may output all 1's or the content of the DRAMDM and XDRAMDM registers as Byte-Enables."},
#else
{13, 13, 0x0000000000000000, "RW", "ecc_disable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "read_address_as_data", "When Read_Address_as_Data is set to '1' any address fields that the CADB is overriding during a Select cycle should be used for comparing the incoming data.  Otherwise, the functional path decoded address field should be used for comparing the incoming data.[br]\r\n"
"This override of the data will not respect any inversion, rotation or other data modification. It will only be active (override the normal output/reference) when Alternate_Data is active in either the Command_Instruction or the Offset_Command_Instruction as appropriate .[br]\r\n"
"The functional path decoded address field used for read comparison is repeated in chunk and should follow the Data Construction rules described below on what bytegroup relates to what decoded address:[br][br]\r\n"
"Chunk0 - Byte0 =Column(7:0).[br]\r\n"
"Chunk0 - Byte1 =Column(9:8) <- as many Column bits as supported.[br]\r\n"
"Chunk0 - Byte2 =Row(0:7).[br]\r\n"
"Chunk0 - Byte3 =Row(15:8).[br]\r\n"
"Chunk0 - Byte4 =Row(17:16)<- as many Row bits as supported.[br]\r\n"
"Chunk0 - Byte5 =Bank(3:0)  [Note: Bank Group may be part of this field] <- as many Bank bits as supported.[br]\r\n"
"Chunk0 - Byte6 =Rank(1:0) <- as many Rank bits as supported (would be CS# if CADB output supported).[br]\r\n"
"Chunk0 - Byte7 =Reserved (set to 0).[br]\r\n"
"\r\n"
"Note: Broxton will not support CADB Select cycle information being used for Address-as-data."},
#else
{9, 9, 0x0000000000000000, "RW", "read_address_as_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "write_address_as_data", "When Write_Address_as_Data is set to '1', any address fields that the CADB is overriding during a Select cycle should be used for generating the write data.  Otherwise, the functional path decoded address field should be used for generating the write data.[br]\r\n"
"Data Construction rules follow the same as for READ_ADDRESS_AS_DATA.[br]\r\n"
"\r\n"
"This format is subject to change based on memory technology supported and other reasons and the main HAS documentation should be referenced if required. What is to be guaranteed is that every Cacheline of data will be unique to each address."},
#else
{8, 8, 0x0000000000000000, "RW", "write_address_as_data", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "uniseq2_mode", "Defines the operational mode for unified sequence 2 as follows:[br][br]\r\n"
"00 - LMN Mode.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{6, 7, 0x0000000000000000, "RW", "uniseq2_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RW", "uniseq1_mode", "Defines the operational mode for unified sequence 1 as follows:[br][br]\r\n"
"00 - LMN Mode.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{3, 4, 0x0000000000000000, "RW", "uniseq1_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "uniseq0_mode", "Defines the operational mode for unified sequence 0 as follows:[br][br]\r\n"
"00 - LMN Mode.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{0, 1, 0x0000000000000000, "RW", "uniseq0_mode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo229[] = {{"CPGC_DPAT_CFG", "", 0x00000184, 10, 0x000000001FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields230[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "lane_rotate_rate", "Lane_Rotate_Rate only exists if the Lane_Rotation_Support capability exists.[br][br]\r\n"
"2^(Lane_Rotate_Rate-1) indicates the periodic Loopcount rate when the EXTBUF_# registers are rotated up by one bit.[br][br]\r\n"
"Lane_Rotate_Rate=0 disables all rotation.[br][br]\r\n"
"Lane_Rotate_Rate=1 causes the EXTBUF_# registers to be rotated every one Loopcount.[br][br]\r\n"
"Lane_Rotate_Rate=2  causes the EXTBUF_# registers to be rotated every other Loopcount.[br][br]\r\n"
"Etc..[br][br]\r\n"
"When the EXTBUF_# registers are rotated Bit 0 shifts to Bit 1 all the way up to the Max-1 Bit and the Max bit shifts to Bit0."},
#else
{24, 29, 0x0000000000000000, "RW", "lane_rotate_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "uniseq2_lfsr_stagger", "0=No Stagger, 1=Stagger.[br][br]\r\n"
"This bit must not be set unless Uniseq2_Mode is programmed to Select LFSR or the behavior is undefined."},
#else
{23, 23, 0x0000000000000000, "RW", "uniseq2_lfsr_stagger", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 20, 0x0000000000000000, "RW", "uniseq2_lfsr_polynomial_size", "Possible Polynomial Sizes:[br][br]\r\n"
"0x0=Use 8 bit LFSR (x8 + x6 + x5 + x4)[br][br]\r\n"
"0x1=Use 15 bit LFSR (x15 + x14)[br][br]\r\n"
"0x2=Use 31 bit LFSR (x31 + x28)[br][br]\r\n"
"0x3=Use 23 bit LFSR (x23 + x18)[br][br]\r\n"
"0x4=Use 7 bit LFSR (x7 + x6)[br][br]\r\n"
"0x5=Use 16 bit LFSR (x16+x5+x4+x3)[br][br]\r\n"
"0x6=Use 23 bit LFSR (x23+x21+x18+x15+x7+x2)[br][br]\r\n"
"0x7=Use 32 bit LFSR (x32+x31+x30+x10)"},
#else
{18, 20, 0x0000000000000000, "RW", "uniseq2_lfsr_polynomial_size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "uniseq1_lfsr_stagger", "0=No Stagger, 1=Stagger.[br][br]\r\n"
"This bit must not be set unless Uniseq1_Mode is programmed to Select LFSR or the behavior is undefined."},
#else
{15, 15, 0x0000000000000000, "RW", "uniseq1_lfsr_stagger", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 12, 0x0000000000000000, "RW", "uniseq1_lfsr_polynomial_size", "Possible Polynomial Sizes:[br][br]\r\n"
"0x0=Use 8 bit LFSR (x8 + x6 + x5 + x4)[br][br]\r\n"
"0x1=Use 15 bit LFSR (x15 + x14)[br][br]\r\n"
"0x2=Use 31 bit LFSR (x31 + x28)[br][br]\r\n"
"0x3=Use 23 bit LFSR (x23 + x18)[br][br]\r\n"
"0x4=Use 7 bit LFSR (x7 + x6)[br][br]\r\n"
"0x5=Use 16 bit LFSR (x16+x5+x4+x3)[br][br]\r\n"
"0x6=Use 23 bit LFSR (x23+x21+x18+x15+x7+x2)[br][br]\r\n"
"0x7=Use 32 bit LFSR (x32+x31+x30+x10)"},
#else
{10, 12, 0x0000000000000000, "RW", "uniseq1_lfsr_polynomial_size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "uniseq0_lfsr_stagger", "0=No Stagger, 1=Stagger.[br][br]\r\n"
"This bit must not be set unless Uniseq0_Mode is programmed to Select LFSR or the behavior is undefined."},
#else
{7, 7, 0x0000000000000000, "RW", "uniseq0_lfsr_stagger", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "uniseq0_lfsr_polynomial_size", "Possible Polynomial Sizes:[br][br]\r\n"
"0x0=Use 8 bit LFSR (x8 + x6 + x5 + x4)[br][br]\r\n"
"0x1=Use 15 bit LFSR (x15 + x14)[br][br]\r\n"
"0x2=Use 31 bit LFSR (x31 + x28)[br][br]\r\n"
"0x3=Use 23 bit LFSR (x23 + x18)[br][br]\r\n"
"0x4=Use 7 bit LFSR (x7 + x6)[br][br]\r\n"
"0x5=Use 16 bit LFSR (x16+x5+x4+x3)[br][br]\r\n"
"0x6=Use 23 bit LFSR (x23+x21+x18+x15+x7+x2)[br][br]\r\n"
"0x7=Use 32 bit LFSR (x32+x31+x30+x10)"},
#else
{2, 4, 0x0000000000000000, "RW", "uniseq0_lfsr_polynomial_size", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo230[] = {{"CPGC_DPAT_XTRA_LFSR_CFG", "", 0x00000188, 7, 0x000000003FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields231[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000AA55AA55, "RW", "pattern_buffer", "If UniSeq#_Mode is set to Pattern Buffer mode, then this field represents the initial content of the rotating pattern buffer for the unified sequencer. If UniSeq#_Mode is set to LFSR mode, then this field represents the 32-bit LFSR seed for the unified sequencer. Note: This is a shared register, it has a meaning according to the UniSeq# mode.[br]\r\n"
"[b]For PRBS lengths less than or equal to 8, the seed must contain 16 bits of the initial PRBS sequence.[b]"},
#else
{0, 31, 0x00000000AA55AA55, "RW", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo231[] = {{"CPGC_DPAT_UNISEQ_0_", "", 0x0000018C, 1, 0x00000000FFFFFFFF, 0x00000000AA55AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields232[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000AA55AA55, "RW", "pattern_buffer", "If UniSeq#_Mode is set to Pattern Buffer mode, then this field represents the initial content of the rotating pattern buffer for the unified sequencer. If UniSeq#_Mode is set to LFSR mode, then this field represents the 32-bit LFSR seed for the unified sequencer. Note: This is a shared register, it has a meaning according to the UniSeq# mode.[br]\r\n"
"[b]For PRBS lengths less than or equal to 8, the seed must contain 16 bits of the initial PRBS sequence.[b]"},
#else
{0, 31, 0x00000000AA55AA55, "RW", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo232[] = {{"CPGC_DPAT_UNISEQ_1_", "", 0x00000190, 1, 0x00000000FFFFFFFF, 0x00000000AA55AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields233[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000AA55AA55, "RW", "pattern_buffer", "If UniSeq#_Mode is set to Pattern Buffer mode, then this field represents the initial content of the rotating pattern buffer for the unified sequencer. If UniSeq#_Mode is set to LFSR mode, then this field represents the 32-bit LFSR seed for the unified sequencer. Note: This is a shared register, it has a meaning according to the UniSeq# mode.[br]\r\n"
"[b]For PRBS lengths less than or equal to 8, the seed must contain 16 bits of the initial PRBS sequence.[b]"},
#else
{0, 31, 0x00000000AA55AA55, "RW", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo233[] = {{"CPGC_DPAT_UNISEQ_2_", "", 0x00000194, 1, 0x00000000FFFFFFFF, 0x00000000AA55AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields234[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000001, "RW", "n_cnt", "N_Count only exists if  LMN_Support capability is set to 1.[br] After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency.[br] If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br] If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{24, 31, 0x0000000000000001, "RW", "n_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000001, "RW", "m_cnt", "M_Count only exists if  LMN_Support capability is set to 1.[br] After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency.[br] If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br]If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{16, 23, 0x0000000000000001, "RW", "m_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000001, "RW", "l_cnt", "If LMN_Support capability is set to 0 then:[br]A periodic square wave is generated that has the following behavior.[br][br]\r\n"
"1) Drive L_Polarity for L_Count Bits.[br][br]\r\n"
"2) Drive inverse of L_Polarity for L_Count Bits.[br][br]\r\n"
"3) Go to step 1.[br][br]\r\n"
"Else if LMN_Support is set to 1 then:[br][br]\r\n"
"After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency is set to 1.[br][br]\r\n"
"If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br][br]\r\n"
"If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{8, 15, 0x0000000000000001, "RW", "l_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "l_counter_hi", "Additional 4 bits to increase the size of L Count up to 12."},
#else
{4, 7, 0x0000000000000000, "RW", "l_counter_hi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "l_count_en", "Used in concatenation with FREQ_SWEEP_EN to enable 3 possible modes of LMN behavior."},
#else
{2, 2, 0x0000000000000000, "RW", "l_count_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "freq_sweep_en", "Used in concatenation with L_COUNT_EN to enable 3 possible modes of LMN behavior:[br][br]\r\n"
"{L_COUNT_EN,FREQ_SWEEP_EN}[br][br]\r\n"
"{0,0} - Normal LMN.[br][br]\r\n"
"{0,1} - Sweep clock pattern from 2*M period down to 2*N_Count period and repeat.[br][br]\r\n"
"{1,0} - L-Counter - drive clock pattern of 2*L period.[br][br]\r\n"
"{1,1} - Currently same as L-Counter mode - reserved for future use.[br][br]\r\n"
"If Normal LMN mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Count bits with the  polarity set by L_Polarity.[br][br]\r\n"
"  2) Drive M_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  3) Drive N_Count bits with the  value of L_Polarity.[br][br]\r\n"
"  4) Go to step 2.[br][br]\r\n"
"If any L_Count, M_Count, or N_Count=0 then the  state will freeze at the polarity driven for that stage.[br][br][br]\r\n"
"If Sweep mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Count bits with the  polarity set by L_Polarity.[br][br]\r\n"
"  2) X_count=M_Count [br][br]\r\n"
"  3) Drive X_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  4) Drive X_Count bits with the  value of L_Polarity.[br][br]\r\n"
"  5) Drive X_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  6) If X_Count==N_Count then go to step 9.[br][br]\r\n"
"  7) X_Count=X_Count-1[br][br]\r\n"
"  8) Go to step 10.[br][br]\r\n"
"  9) X_Count=M_Count[br][br]\r\n"
"10) Drive X_Count bits with the  value of L_Polarity.[br][br]\r\n"
"11) Go to step 3.[br][br]\r\n"
"[br]\r\n"
"If LCount mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Polarity for L_Count Bits.[br][br]\r\n"
"  2) Drive inverse of L_Polarity for L_Count Bits.[br][br]\r\n"
"  3) Go to step 1.[br][br]\r\n"
"  [br][br]\r\n"
"If {0,1}, L_Count, M_Count, and N_Count must never be programmed to 0 and is considered undefined.[br][br]\r\n"
"If {1,0}, L_Count must never be programmed to 0 and is considered undefined.[br][br]\r\n"
"If {0,1}, M_Count and N_Count must be greater than or equal to 8 or behavior may be implementation specific.[br][br]\r\n"
"If {0,1}, N_Count must be programmed less than M_Count."},
#else
{1, 1, 0x0000000000000000, "RW", "freq_sweep_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "l_sel", "The initial logic output of the sequencer is defined as follows:[br][br]\r\n"
"                        0 - Output Logic '0' for L_CNT UIs.[br][br]\r\n"
"                        1 - Output Logic '1' for L_CNT UIs."},
#else
{0, 0, 0x0000000000000000, "RW", "l_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo234[] = {{"CPGC_DPAT_UNISEQ_LMN_0_", "", 0x00000198, 7, 0x00000000FFFFFFFF, 0x0000000001010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields235[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000001, "RW", "n_cnt", "N_Count only exists if  LMN_Support capability is set to 1.[br] After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency.[br] If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br] If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{24, 31, 0x0000000000000001, "RW", "n_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000001, "RW", "m_cnt", "M_Count only exists if  LMN_Support capability is set to 1.[br] After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency.[br] If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br]If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{16, 23, 0x0000000000000001, "RW", "m_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000001, "RW", "l_cnt", "If LMN_Support capability is set to 0 then:[br]A periodic square wave is generated that has the following behavior.[br][br]\r\n"
"1) Drive L_Polarity for L_Count Bits.[br][br]\r\n"
"2) Drive inverse of L_Polarity for L_Count Bits.[br][br]\r\n"
"3) Go to step 1.[br][br]\r\n"
"Else if LMN_Support is set to 1 then:[br][br]\r\n"
"After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency is set to 1.[br][br]\r\n"
"If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br][br]\r\n"
"If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{8, 15, 0x0000000000000001, "RW", "l_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "l_counter_hi", "Additional 4 bits to increase the size of L Count up to 12."},
#else
{4, 7, 0x0000000000000000, "RW", "l_counter_hi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "l_count_en", "Used in concatenation with FREQ_SWEEP_EN to enable 3 possible modes of LMN behavior."},
#else
{2, 2, 0x0000000000000000, "RW", "l_count_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "freq_sweep_en", "Used in concatenation with L_COUNT_EN to enable 3 possible modes of LMN behavior:[br][br]\r\n"
"{L_COUNT_EN,FREQ_SWEEP_EN}[br][br]\r\n"
"{0,0} - Normal LMN.[br][br]\r\n"
"{0,1} - Sweep clock pattern from 2*M period down to 2*N_Count period and repeat.[br][br]\r\n"
"{1,0} - L-Counter - drive clock pattern of 2*L period.[br][br]\r\n"
"{1,1} - Currently same as L-Counter mode - reserved for future use.[br][br]\r\n"
"If Normal LMN mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Count bits with the  polarity set by L_Polarity.[br][br]\r\n"
"  2) Drive M_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  3) Drive N_Count bits with the  value of L_Polarity.[br][br]\r\n"
"  4) Go to step 2.[br][br]\r\n"
"If any L_Count, M_Count, or N_Count=0 then the  state will freeze at the polarity driven for that stage.[br][br][br]\r\n"
"If Sweep mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Count bits with the  polarity set by L_Polarity.[br][br]\r\n"
"  2) X_count=M_Count [br][br]\r\n"
"  3) Drive X_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  4) Drive X_Count bits with the  value of L_Polarity.[br][br]\r\n"
"  5) Drive X_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  6) If X_Count==N_Count then go to step 9.[br][br]\r\n"
"  7) X_Count=X_Count-1[br][br]\r\n"
"  8) Go to step 10.[br][br]\r\n"
"  9) X_Count=M_Count[br][br]\r\n"
"10) Drive X_Count bits with the  value of L_Polarity.[br][br]\r\n"
"11) Go to step 3.[br][br]\r\n"
"[br]\r\n"
"If LCount mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Polarity for L_Count Bits.[br][br]\r\n"
"  2) Drive inverse of L_Polarity for L_Count Bits.[br][br]\r\n"
"  3) Go to step 1.[br][br]\r\n"
"  [br][br]\r\n"
"If {0,1}, L_Count, M_Count, and N_Count must never be programmed to 0 and is considered undefined.[br][br]\r\n"
"If {1,0}, L_Count must never be programmed to 0 and is considered undefined.[br][br]\r\n"
"If {0,1}, M_Count and N_Count must be greater than or equal to 8 or behavior may be implementation specific.[br][br]\r\n"
"If {0,1}, N_Count must be programmed less than M_Count."},
#else
{1, 1, 0x0000000000000000, "RW", "freq_sweep_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "l_sel", "The initial logic output of the sequencer is defined as follows:[br][br]\r\n"
"                        0 - Output Logic '0' for L_CNT UIs.[br][br]\r\n"
"                        1 - Output Logic '1' for L_CNT UIs."},
#else
{0, 0, 0x0000000000000000, "RW", "l_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo235[] = {{"CPGC_DPAT_UNISEQ_LMN_1_", "", 0x0000019C, 7, 0x00000000FFFFFFFF, 0x0000000001010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields236[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000001, "RW", "n_cnt", "N_Count only exists if  LMN_Support capability is set to 1.[br] After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency.[br] If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br] If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{24, 31, 0x0000000000000001, "RW", "n_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000001, "RW", "m_cnt", "M_Count only exists if  LMN_Support capability is set to 1.[br] After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency.[br] If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br]If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{16, 23, 0x0000000000000001, "RW", "m_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000001, "RW", "l_cnt", "If LMN_Support capability is set to 0 then:[br]A periodic square wave is generated that has the following behavior.[br][br]\r\n"
"1) Drive L_Polarity for L_Count Bits.[br][br]\r\n"
"2) Drive inverse of L_Polarity for L_Count Bits.[br][br]\r\n"
"3) Go to step 1.[br][br]\r\n"
"Else if LMN_Support is set to 1 then:[br][br]\r\n"
"After L_Count bits are driven at the beginning of a test then periodic pattern is continuously repeated depending on the value of Enable_Sweep_Frequency is set to 1.[br][br]\r\n"
"If Enable_Sweep_Frequency=0 then a steady state frequency is driven (see Enable_Sweep_Frequency for exact behavior).[br][br]\r\n"
"If Enable_Sweep_Frequency=1 then a frequency sweep is continuously generated ranging from 2*(M) to 2*(N) driven (see Enable_Sweep_Frequency for exact behavior)."},
#else
{8, 15, 0x0000000000000001, "RW", "l_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "l_counter_hi", "Additional 4 bits to increase the size of L Count up to 12."},
#else
{4, 7, 0x0000000000000000, "RW", "l_counter_hi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "l_count_en", "Used in concatenation with FREQ_SWEEP_EN to enable 3 possible modes of LMN behavior."},
#else
{2, 2, 0x0000000000000000, "RW", "l_count_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "freq_sweep_en", "Used in concatenation with L_COUNT_EN to enable 3 possible modes of LMN behavior:[br][br]\r\n"
"{L_COUNT_EN,FREQ_SWEEP_EN}[br][br]\r\n"
"{0,0} - Normal LMN.[br][br]\r\n"
"{0,1} - Sweep clock pattern from 2*M period down to 2*N_Count period and repeat.[br][br]\r\n"
"{1,0} - L-Counter - drive clock pattern of 2*L period.[br][br]\r\n"
"{1,1} - Currently same as L-Counter mode - reserved for future use.[br][br]\r\n"
"If Normal LMN mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Count bits with the  polarity set by L_Polarity.[br][br]\r\n"
"  2) Drive M_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  3) Drive N_Count bits with the  value of L_Polarity.[br][br]\r\n"
"  4) Go to step 2.[br][br]\r\n"
"If any L_Count, M_Count, or N_Count=0 then the  state will freeze at the polarity driven for that stage.[br][br][br]\r\n"
"If Sweep mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Count bits with the  polarity set by L_Polarity.[br][br]\r\n"
"  2) X_count=M_Count [br][br]\r\n"
"  3) Drive X_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  4) Drive X_Count bits with the  value of L_Polarity.[br][br]\r\n"
"  5) Drive X_Count bits with the  inverse of L_Polarity.[br][br]\r\n"
"  6) If X_Count==N_Count then go to step 9.[br][br]\r\n"
"  7) X_Count=X_Count-1[br][br]\r\n"
"  8) Go to step 10.[br][br]\r\n"
"  9) X_Count=M_Count[br][br]\r\n"
"10) Drive X_Count bits with the  value of L_Polarity.[br][br]\r\n"
"11) Go to step 3.[br][br]\r\n"
"[br]\r\n"
"If LCount mode, then the following pattern is continuously repeated:[br][br]\r\n"
"  1) Drive L_Polarity for L_Count Bits.[br][br]\r\n"
"  2) Drive inverse of L_Polarity for L_Count Bits.[br][br]\r\n"
"  3) Go to step 1.[br][br]\r\n"
"  [br][br]\r\n"
"If {0,1}, L_Count, M_Count, and N_Count must never be programmed to 0 and is considered undefined.[br][br]\r\n"
"If {1,0}, L_Count must never be programmed to 0 and is considered undefined.[br][br]\r\n"
"If {0,1}, M_Count and N_Count must be greater than or equal to 8 or behavior may be implementation specific.[br][br]\r\n"
"If {0,1}, N_Count must be programmed less than M_Count."},
#else
{1, 1, 0x0000000000000000, "RW", "freq_sweep_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "l_sel", "The initial logic output of the sequencer is defined as follows:[br][br]\r\n"
"                        0 - Output Logic '0' for L_CNT UIs.[br][br]\r\n"
"                        1 - Output Logic '1' for L_CNT UIs."},
#else
{0, 0, 0x0000000000000000, "RW", "l_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo236[] = {{"CPGC_DPAT_UNISEQ_LMN_2_", "", 0x000001A0, 7, 0x00000000FFFFFFFF, 0x0000000001010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields237[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "mask_rotate_en", "If set, the inversion/DC mask will rotate to the left at a rate defined by the MASK_ROTATE_RATE field."},
#else
{31, 31, 0x0000000000000000, "RW", "mask_rotate_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "dc_or_inv", "Selects between using the inversion/DC mask for inversion or DC as follows:[br][br]\r\n"
"0 - Mask used for inversion.[br][br]\r\n"
"1 - Mask used for driving a DC signal of polarity DC_POL."},
#else
{30, 30, 0x0000000000000000, "RW", "dc_or_inv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "dc_pol", "Selects the polarity of the signal to be driven through the inversion/DC mask if DC_OR_INV is set to 1:[br][br]\r\n"
"0 - Drive a logic low (zero).[br][br]\r\n"
"1 - Drive a logic high (one)."},
#else
{29, 29, 0x0000000000000000, "RW", "dc_pol", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 24, 0x00000000000000AA, "RW", "bytegroup_mapping", "Select between the two bytes of unique lanes being generated by the DPAT pattern generator, to be applied in each DQ byte group, as many byte groups as required by the number of DQ pins.  MSB is always for the ECC byte group, used only if ECC is present."},
#else
{16, 24, 0x00000000000000AA, "RW", "bytegroup_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "mask_rotate_rate", "If inversion mask rotation is enabled through MASK_ROTATE_EN, the mask will rotate to the left every time 2^MASK_ROTATE_RATE bursts (64Bytes) have been have been issued."},
#else
{8, 11, 0x0000000000000000, "RW", "mask_rotate_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ecc_inv_dc_mask", "A value of  for any of the bits means the corresponding ECC lane(s) will be inverted or a DC value driven on it.  Note that this field is used to load bits [71:64] of the continuous shift register composed of this field along with DATA_INV_DC_MASK_HI and DATA_INV_DC_MASK_LO.   Note: this field is only available if ECC is supported for the current implementation, otherwise it is reserved."},
#else
{0, 7, 0x0000000000000000, "RW", "ecc_inv_dc_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo237[] = {{"CPGC_DPAT_INVDCCTL", "", 0x000001A4, 6, 0x00000000FFFFFFFF, 0x0000000000AA0000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields238[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_inv_dc_mask_lo", "A value of '1' for any of the bits means the corresponding data lane(s) will be inverted or a DC value driven on it. Note that this field is used to load bits [31:0] of the continuous shift register composed of this field along with ECC_INV_DC_MASK and DATA_INV_DC_MASK_HI.[br]\r\n"
"DPAT generator only uses the appropriate bits based on the widest bus that this CPGC block is designed to support.[br]\r\n"
"This register is also used to provide the Initial value for the Alternate Data pattern generator."},
#else
{0, 31, 0x0000000000000000, "RW", "data_inv_dc_mask_lo", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo238[] = {{"CPGC_DPAT_INV_DC_MASK_LO", "", 0x000001A8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields239[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_inv_dc_mask_hi", "A value of '1' for any of the bits means the corresponding data lane(s) will be inverted or a DC value driven on it. Note that this field is used to load bits [63:32] of the continuous shift register composed of this field along with ECC_INV_DC_MASK and DATA_INV_DC_MASK_LO."},
#else
{0, 31, 0x0000000000000000, "RW", "data_inv_dc_mask_hi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo239[] = {{"CPGC_DPAT_INV_DC_MASK_HI", "", 0x000001AC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields240[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000FFFFFFFF, "RW", "data_mask_lo", "A byte enable field with each bit corresponding to a data byte sent during a burst such that:[br]\r\n"
"0 - Mask the Corresponding Byte.[br]\r\n"
"1 - No Mask to the Corresponding Byte.[br]\r\n"
"The byte-to-bit mapping is given by Byte[n] -> bit[n].[br]\r\n"
"This register is for the first half cacheline of data.[br]\r\n"
"It is only used when ECC is not present or is disabled."},
#else
{0, 31, 0x00000000FFFFFFFF, "RW", "data_mask_lo", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo240[] = {{"CPGC_DPAT_DRAMDM", "", 0x000001B0, 1, 0x00000000FFFFFFFF, 0x00000000FFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields241[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000FFFFFFFF, "RW", "data_mask_hi", "A byte enable field with each bit corresponding to a data byte sent during a burst such that:[br]\r\n"
"0 - Mask the Corresponding Byte.[br]\r\n"
"1 - No Mask to the Corresponding Byte.[br]\r\n"
"The byte-to-bit mapping is given by Byte[n+32] -> bit[n].[br]\r\n"
"This register is for the Second half cacheline of data.[br]\r\n"
"It is only used when ECC is not present or is disabled."},
#else
{0, 31, 0x00000000FFFFFFFF, "RW", "data_mask_hi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo241[] = {{"CPGC_DPAT_XDRAMDM", "", 0x000001B4, 1, 0x00000000FFFFFFFF, 0x00000000FFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields242[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "uniseq_wrstat", "The current contents of the Pattern/LFSR buffer in write generation domain."},
#else
{0, 31, 0x0000000000000000, "RO/V", "uniseq_wrstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo242[] = {{"CPGC_DPAT_UNISEQ_WRSTAT_0_", "", 0x000001B8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields243[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "uniseq_wrstat", "The current contents of the Pattern/LFSR buffer in write generation domain."},
#else
{0, 31, 0x0000000000000000, "RO/V", "uniseq_wrstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo243[] = {{"CPGC_DPAT_UNISEQ_WRSTAT_1_", "", 0x000001BC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields244[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "uniseq_wrstat", "The current contents of the Pattern/LFSR buffer in write generation domain."},
#else
{0, 31, 0x0000000000000000, "RO/V", "uniseq_wrstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo244[] = {{"CPGC_DPAT_UNISEQ_WRSTAT_2_", "", 0x000001C0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields245[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "uniseq_rdstat", "Reflects the current and final status of the pattern buffer in the read domain.[br]\r\n"
"If PATBUF mode, then Pattern_Buffer is used as a fixed buffer that is output in serial fashion.   After all the bits in the Pattern_Buffer have been transmitted the  pattern will simply repeat itself continuously while a Loopback Test is in progress.[br][br]\r\n"
"If LFSR mode, then Pattern_Buffer is used as a seed to a fixed LFSR that is output in serial fashion.  Over time the LFSR pattern will repeat itself continuously while a Loopback Test is in progress. In LFSR Mode the contents of Pattern_Buffer will interact with the LFSR in the following ways:[br][br]\r\n"
"If LFSR_Save_Restore is set then CPGC_REG_DPAT_UNISEQ_WRSAVE.Pattern_Buffer will interact with CPGC_UNISEQ#_RDSTAT in the following ways:[br][br]\r\n"
"1) CPGC_UNISEQ#_RDSTAT will be periodically saved into CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Save_LFSR_Seed_Rate (see Save_LFSR_Seed_Rate for more details).[br][br]\r\n"
"2) CPGC_UNISEQ#_RDSTAT will be periodically reloaded with CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Reload_LFSR_Seed_Rate (see Reload_LFSR_Seed_Rate for more details)."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "uniseq_rdstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo245[] = {{"CPGC_DPAT_UNISEQ_RDSTAT_0_", "", 0x000001C4, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields246[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "uniseq_rdstat", "Reflects the current and final status of the pattern buffer in the read domain.[br]\r\n"
"If PATBUF mode, then Pattern_Buffer is used as a fixed buffer that is output in serial fashion.   After all the bits in the Pattern_Buffer have been transmitted the  pattern will simply repeat itself continuously while a Loopback Test is in progress.[br][br]\r\n"
"If LFSR mode, then Pattern_Buffer is used as a seed to a fixed LFSR that is output in serial fashion.  Over time the LFSR pattern will repeat itself continuously while a Loopback Test is in progress. In LFSR Mode the contents of Pattern_Buffer will interact with the LFSR in the following ways:[br][br]\r\n"
"If LFSR_Save_Restore is set then CPGC_REG_DPAT_UNISEQ_WRSAVE.Pattern_Buffer will interact with CPGC_UNISEQ#_RDSTAT in the following ways:[br][br]\r\n"
"1) CPGC_UNISEQ#_RDSTAT will be periodically saved into CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Save_LFSR_Seed_Rate (see Save_LFSR_Seed_Rate for more details).[br][br]\r\n"
"2) CPGC_UNISEQ#_RDSTAT will be periodically reloaded with CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Reload_LFSR_Seed_Rate (see Reload_LFSR_Seed_Rate for more details)."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "uniseq_rdstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo246[] = {{"CPGC_DPAT_UNISEQ_RDSTAT_1_", "", 0x000001C8, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields247[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "uniseq_rdstat", "Reflects the current and final status of the pattern buffer in the read domain.[br]\r\n"
"If PATBUF mode, then Pattern_Buffer is used as a fixed buffer that is output in serial fashion.   After all the bits in the Pattern_Buffer have been transmitted the  pattern will simply repeat itself continuously while a Loopback Test is in progress.[br][br]\r\n"
"If LFSR mode, then Pattern_Buffer is used as a seed to a fixed LFSR that is output in serial fashion.  Over time the LFSR pattern will repeat itself continuously while a Loopback Test is in progress. In LFSR Mode the contents of Pattern_Buffer will interact with the LFSR in the following ways:[br][br]\r\n"
"If LFSR_Save_Restore is set then CPGC_REG_DPAT_UNISEQ_WRSAVE.Pattern_Buffer will interact with CPGC_UNISEQ#_RDSTAT in the following ways:[br][br]\r\n"
"1) CPGC_UNISEQ#_RDSTAT will be periodically saved into CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Save_LFSR_Seed_Rate (see Save_LFSR_Seed_Rate for more details).[br][br]\r\n"
"2) CPGC_UNISEQ#_RDSTAT will be periodically reloaded with CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Reload_LFSR_Seed_Rate (see Reload_LFSR_Seed_Rate for more details)."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "uniseq_rdstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo247[] = {{"CPGC_DPAT_UNISEQ_RDSTAT_2_", "", 0x000001CC, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields248[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "lmn_wrstat", "The current contents of the LMN buffer in write comparison domain."},
#else
{0, 31, 0x0000000000000000, "RO/V", "lmn_wrstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo248[] = {{"CPGC_DPAT_LMN_WRSTAT_0_", "", 0x000001D0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields249[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "lmn_wrstat", "The current contents of the LMN buffer in write comparison domain."},
#else
{0, 31, 0x0000000000000000, "RO/V", "lmn_wrstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo249[] = {{"CPGC_DPAT_LMN_WRSTAT_1_", "", 0x000001D4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields250[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "lmn_wrstat", "The current contents of the LMN buffer in write comparison domain."},
#else
{0, 31, 0x0000000000000000, "RO/V", "lmn_wrstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo250[] = {{"CPGC_DPAT_LMN_WRSTAT_2_", "", 0x000001D8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields251[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "lmn_rdstat", "The current contents of the LMN buffer in read comparison domain."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "lmn_rdstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo251[] = {{"CPGC_DPAT_LMN_RDSTAT_0_", "", 0x000001DC, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields252[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "lmn_rdstat", "The current contents of the LMN buffer in read comparison domain."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "lmn_rdstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo252[] = {{"CPGC_DPAT_LMN_RDSTAT_1_", "", 0x000001E0, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields253[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "lmn_rdstat", "The current contents of the LMN buffer in read comparison domain."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "lmn_rdstat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo253[] = {{"CPGC_DPAT_LMN_RDSTAT_2_", "", 0x000001E4, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields254[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "pattern_buffer", "The current contents of the Save register before the test stops in the write domain."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo254[] = {{"CPGC_DPAT_UNISEQ_WRSAVE_0_", "", 0x000001E8, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields255[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "pattern_buffer", "The current contents of the Save register before the test stops in the write domain."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo255[] = {{"CPGC_DPAT_UNISEQ_WRSAVE_1_", "", 0x000001EC, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields256[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000DEADBEEF, "RO/V", "pattern_buffer", "The current contents of the Save register before the test stops in the write domain."},
#else
{0, 31, 0x00000000DEADBEEF, "RO/V", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo256[] = {{"CPGC_DPAT_UNISEQ_WRSAVE_2_", "", 0x000001F0, 1, 0x00000000FFFFFFFF, 0x00000000DEADBEEF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields257[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "pattern_buffer", "CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer will reflect either the initial or last saved value of CPGC_UNISEQ#_RDSTAT.[br][br]\r\n"
"If PATBUF mode, then Pattern_Buffer is used as a fixed buffer that is output in serial fashion.  After all the bits in the Pattern_Buffer have been transmitted the  pattern will simply repeat itself continuously while a Loopback Test is in progress.[br][br]\r\n"
"If LFSR mode, then Pattern_Buffer is used as a seed to a fixed LFSR that is output in serial fashion.  Over time the LFSR pattern will repeat itself continuously while a Loopback Test is in progress. In LFSR Mode the contents of Pattern_Buffer will interact with the LFSR in the following ways:[br][br]\r\n"
"If LFSR_Save_Restore is set then CPGC_REG_DPAT_UNISEQ_WRSAVE.Pattern_Buffer will interact with CPGC_UNISEQ#_RDSTAT in the following ways:[br][br]\r\n"
"1) CPGC_UNISEQ#_RDSTAT will be periodically saved into CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Save_LFSR_Seed_Rate (see Save_LFSR_Seed_Rate for more details).[br][br]\r\n"
"2) CPGC_UNISEQ#_RDSTAT will be periodically reloaded with CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Reload_LFSR_Seed_Rate (see Reload_LFSR_Seed_Rate for more details)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo257[] = {{"CPGC_DPAT_UNISEQ_RDSAVE_0_", "", 0x000001F4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields258[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "pattern_buffer", "CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer will reflect either the initial or last saved value of CPGC_UNISEQ#_RDSTAT.[br][br]\r\n"
"If PATBUF mode, then Pattern_Buffer is used as a fixed buffer that is output in serial fashion.  After all the bits in the Pattern_Buffer have been transmitted the  pattern will simply repeat itself continuously while a Loopback Test is in progress.[br][br]\r\n"
"If LFSR mode, then Pattern_Buffer is used as a seed to a fixed LFSR that is output in serial fashion.  Over time the LFSR pattern will repeat itself continuously while a Loopback Test is in progress. In LFSR Mode the contents of Pattern_Buffer will interact with the LFSR in the following ways:[br][br]\r\n"
"If LFSR_Save_Restore is set then CPGC_REG_DPAT_UNISEQ_WRSAVE.Pattern_Buffer will interact with CPGC_UNISEQ#_RDSTAT in the following ways:[br][br]\r\n"
"1) CPGC_UNISEQ#_RDSTAT will be periodically saved into CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Save_LFSR_Seed_Rate (see Save_LFSR_Seed_Rate for more details).[br][br]\r\n"
"2) CPGC_UNISEQ#_RDSTAT will be periodically reloaded with CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Reload_LFSR_Seed_Rate (see Reload_LFSR_Seed_Rate for more details)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo258[] = {{"CPGC_DPAT_UNISEQ_RDSAVE_1_", "", 0x000001F8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields259[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "pattern_buffer", "CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer will reflect either the initial or last saved value of CPGC_UNISEQ#_RDSTAT.[br][br]\r\n"
"If PATBUF mode, then Pattern_Buffer is used as a fixed buffer that is output in serial fashion.  After all the bits in the Pattern_Buffer have been transmitted the  pattern will simply repeat itself continuously while a Loopback Test is in progress.[br][br]\r\n"
"If LFSR mode, then Pattern_Buffer is used as a seed to a fixed LFSR that is output in serial fashion.  Over time the LFSR pattern will repeat itself continuously while a Loopback Test is in progress. In LFSR Mode the contents of Pattern_Buffer will interact with the LFSR in the following ways:[br][br]\r\n"
"If LFSR_Save_Restore is set then CPGC_REG_DPAT_UNISEQ_WRSAVE.Pattern_Buffer will interact with CPGC_UNISEQ#_RDSTAT in the following ways:[br][br]\r\n"
"1) CPGC_UNISEQ#_RDSTAT will be periodically saved into CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Save_LFSR_Seed_Rate (see Save_LFSR_Seed_Rate for more details).[br][br]\r\n"
"2) CPGC_UNISEQ#_RDSTAT will be periodically reloaded with CPGC_REG_DPAT_UNISEQ#_RDSAVE.Pattern_Buffer based on Reload_LFSR_Seed_Rate (see Reload_LFSR_Seed_Rate for more details)."},
#else
{0, 31, 0x0000000000000000, "RO/V", "pattern_buffer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo259[] = {{"CPGC_DPAT_UNISEQ_RDSAVE_2_", "", 0x000001FC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields260[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo260[] = {{"CPGC_DPAT_EXTBUF_0_", "", 0x00000200, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields261[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo261[] = {{"CPGC_DPAT_EXTBUF_1_", "", 0x00000204, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields262[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo262[] = {{"CPGC_DPAT_EXTBUF_2_", "", 0x00000208, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields263[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo263[] = {{"CPGC_DPAT_EXTBUF_3_", "", 0x0000020C, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields264[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo264[] = {{"CPGC_DPAT_EXTBUF_4_", "", 0x00000210, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields265[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo265[] = {{"CPGC_DPAT_EXTBUF_5_", "", 0x00000214, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields266[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo266[] = {{"CPGC_DPAT_EXTBUF_6_", "", 0x00000218, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields267[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo267[] = {{"CPGC_DPAT_EXTBUF_7_", "", 0x0000021C, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields268[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo268[] = {{"CPGC_DPAT_EXTBUF_8_", "", 0x00000220, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields269[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo269[] = {{"CPGC_DPAT_EXTBUF_9_", "", 0x00000224, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields270[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo270[] = {{"CPGC_DPAT_EXTBUF_10_", "", 0x00000228, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields271[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo271[] = {{"CPGC_DPAT_EXTBUF_11_", "", 0x0000022C, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields272[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo272[] = {{"CPGC_DPAT_EXTBUF_12_", "", 0x00000230, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields273[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo273[] = {{"CPGC_DPAT_EXTBUF_13_", "", 0x00000234, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields274[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo274[] = {{"CPGC_DPAT_EXTBUF_14_", "", 0x00000238, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields275[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000AA, "RW", "data_line3", "Contents of Pattern Buffer for Cache Line 3.[br]\r\n"
"EXTBUF[0] corresponds to Lane 0 (32 UI of data maximum).[br]\r\n"
"EXTBUF[1] corresponds to Lane 1 (32 UI of data maximum).[br]\r\n"
".....[br]\r\n"
"EXTBUF[15] corresponds to Lane 15.[br]\r\n"
"These 16 lanes are replicated across the number of active DQ lanes on the memory interface."},
#else
{24, 31, 0x00000000000000AA, "RW", "data_line3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000AA, "RW", "data_line2", "Contents of Pattern Buffer for Cache Line 2.[br]\r\n"
"Line 2 (and same for Lines 3..0) refers to the 8-UI partial cache line as pointed to current status at CPGC_DPAT_BUF_CTL.[br]\r\n"
"This advancement is controlled by CPGC_DPAT_BUF_CTL."},
#else
{16, 23, 0x00000000000000AA, "RW", "data_line2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000AA, "RW", "data_line1", "Contents of Pattern Buffer  for Cache Line 1."},
#else
{8, 15, 0x00000000000000AA, "RW", "data_line1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000AA, "RW", "data_line0", "Contents of Pattern Buffer  for Cache Line 0."},
#else
{0, 7, 0x00000000000000AA, "RW", "data_line0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo275[] = {{"CPGC_DPAT_EXTBUF_15_", "", 0x0000023C, 4, 0x00000000FFFFFFFF, 0x00000000AAAAAAAA}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields276[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW/P", "errchk_mask_cacheline", "Defines a periodic burst mask that repeats every 64Bytes of data as follows:[br]\r\n"
"Bit 0 - Burst 0[br]\r\n"
"Bit 1 - Burst 1[br]\r\n"
"...[br]\r\n"
"Bit 7 - Burst 7[br]\r\n"
"Only bursts with a corresponding bit value of '1' will be checked for errors. A burst is defined as a burst length of 64 bytes of data.[br]\r\n"
"In Loopback each bit of this register controls the check of each ByteTime (8-bits) on the bus."},
#else
{24, 31, 0x0000000000000000, "RW/P", "errchk_mask_cacheline", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW/P", "errchk_mask_chunk", "Defines which chunk within the burst of data (i.e. bit within a burst of 8-bits for each lane) to check for errors.[br]\r\n"
"Only chunks with a corresponding bit value of '0' will be checked for errors.[br]\r\n"
"This field is only used for full width (64bit) DQ busses. Otherwise the upper 32 bits of the Lane Mask is used as the Chunk Enable.[br]\r\n"
"This field is also used for Loopback mode for all DQ sizes."},
#else
{16, 23, 0x0000000000000000, "RW/P", "errchk_mask_chunk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW/P", "stop_on_error_ctl", "Defines test stop conditions based on error checking as follows:[br]\r\n"
"00 - Never stop: Prevents any error from stopping the test.[br]\r\n"
"01 - Stop On Nth Error: Stop once STOP_ERR_CNTR has accumulated at least (STOP_ON_N + 1) errors.[br]\r\n"
"10 - Stop On All Byte Groups Error:  Stop if every byte group indicates that at least one of its lanes accumulated at least one error.[br]\r\n"
"That is, if all bits BYTEGRP_ERR_STAT, (and ECC_GRP_ERR_STAT if supported), are all set.[br]\r\n"
"11 - Stop On All Lanes Error:  Stop if every lane within every byte group has accumulated at least one error.[br]\r\n"
"That is, if all bits in LANE_ERR_STAT_LO, LANE_ERR_STAT_HI, (and LANE_ERR_STATECC if supported) are all set."},
#else
{12, 13, 0x0000000000000000, "RW/P", "stop_on_error_ctl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW/P", "be_train_err_en", "Enable BE Training Error Detection Feature.  Note this bit overrides the BE_TRAIN_ERR_EN bit in CPGC2_ALGORITHM_INSTRUCTION_CTRL."},
#else
{8, 8, 0x0000000000000000, "RW/P", "be_train_err_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW/P", "stop_on_n", "If STOP_ON_ERROR is set to Stop on Nth Error Mode, the test will stop after (STOP_ON_N + 1) or more errors have been accumulated in the ERR_CNTR."},
#else
{0, 5, 0x0000000000000000, "RW/P", "stop_on_n", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo276[] = {{"CPGC_ERR_CTL", "", 0x00000240, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields277[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/P", "data_errchk_mask_lo", "A mask used to disable error checking on data lanes [31:0].  Lanes selected through this mask will not be checked for errors. The lane-to-bit mapping for this mask is given by the following formula: Lane[n] -> bit[n].[br]\r\n"
"Functionality will change with special mapping when buswidth is < 64 (or 72) such that ChunkMask will move to this field starting at bit [...:32] extending the necessary number of bits for a full cache line of data. The mask in ERR_CTL will be unused for these busses/modes."},
#else
{0, 31, 0x0000000000000000, "RW/P", "data_errchk_mask_lo", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo277[] = {{"CPGC_ERR_LNEN_LO", "", 0x00000244, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields278[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/P", "data_errchk_mask_hi", "A mask used to disable error checking on data lanes [63:32].  Lanes selected through this mask will not be checked for errors. The lane-to-bit mapping for this mask is given by the following formula: Lane[n+32] -> bit[n].[br]\r\n"
"Functionality will change with special mapping when buswidth is < 64 (or 72) such that ChunkMask will move to this field starting at bit [...:32] extending the necessary number of bits for a full cache line of data. The mask in ERR_CTL will be unused for these busses/modes."},
#else
{0, 31, 0x0000000000000000, "RW/P", "data_errchk_mask_hi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo278[] = {{"CPGC_ERR_LNEN_HI", "", 0x00000248, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields279[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000FF, "RW/P", "ecc_errchk_mask", "A mask used to disable error checking on ECC lanes.  Lanes selected through the mask will not be checked for errors. The lane-to-bit mapping is 1-to-1 and hence bit 1 corresponds to ECC lane 0, bit 1 corresponds to ECC lane 1, and so on.[br]\r\n"
"Note: This field is available only if ECC is supported. The default state is to disable ECC checking."},
#else
{0, 7, 0x00000000000000FF, "RW/P", "ecc_errchk_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo279[] = {{"CPGC_ERR_XLNEN", "", 0x0000024C, 1, 0x00000000000000FF, 0x00000000000000FF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields280[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "lane_err_stat_lo", "Indicates if a mismatch was detected between the WR and the RD data on one of the lanes belonging to byte groups 0 - 3.  Hence lanes [32:0] map to bits [32:0] respectively.  The error status information is encoded as follows:[br]\r\n"
"0: No mismatches detected on corresponding lane.[br]\r\n"
"1: At least one mismatch detected on corresponding lane.[br]\r\n"
"Cleared on Local Clear Errors."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "lane_err_stat_lo", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo280[] = {{"CPGC_ERR_STAT03", "", 0x00000250, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields281[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "lane_err_stat_hi", "Indicates if a mismatch was detected between the WR and the RD data on one of the lanes belonging to byte groups 4 - 7.  Hence lanes [63:32] map to bits [32:0] respectively.[br]\r\n"
"If there are less than 32 data lanes, then this register is used to indicate the Extended Chunk Error Status, and the Chunk Error Status in ECC_CHNK_RANK_STAT is not used. Chunks 0 through 15 (32-bit bus) or 0 through 31 (16-bit bus).[br]\r\n"
"The error status information is encoded as follows:[br]\r\n"
"0: No mismatches detected on corresponding lane (chunk).[br]\r\n"
"1: At least one mismatch detected on corresponding lane (chunk).[br]\r\n"
"Cleared on Local Clear Errors."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "lane_err_stat_hi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo281[] = {{"CPGC_ERR_STAT47", "", 0x00000254, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields282[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RO/V/P", "rank_err_stat", "A status field where each bit corresponds to a specific rank. If set, the corresponding rank has accumulated at least one error.[br]\r\n"
"Cleared on Local Clear Errors."},
#else
{16, 19, 0x0000000000000000, "RO/V/P", "rank_err_stat", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V/P", "chunk_err_stat", "A flag field where each bit corresponds to a specific chunk (i.e. bit within a burst of 8-bits). If set, the corresponding chunk (UI) has accumulated at least one error.[br]\r\n"
"Cleared on Local Clear Errors."},
#else
{8, 15, 0x0000000000000000, "RO/V/P", "chunk_err_stat", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V/P", "ecc_lane_err_stat", "A fag field which indicates if a mismatch was detected between the WR and the RD data on one of the lanes belonging to the ECC byte group.  The error status information is encoded as follows:[br]\r\n"
"0: No mismatches detected on corresponding lane.[br]\r\n"
"1: At least one mismatch detected on corresponding lane.[br]\r\n"
"Note: this field is only available if ECC is supported for the current implementation, otherwise it is reserved.[br]\r\n"
"If BE Training Enable is set then this field indicates that the particular BE lane had a fault during the write pass.[br]\r\n"
"Cleared on Local Clear Errors."},
#else
{0, 7, 0x0000000000000000, "RO/V/P", "ecc_lane_err_stat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo282[] = {{"CPGC_ERR_ECC_CHNK_RANK_STAT", "", 0x00000258, 3, 0x00000000000FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields283[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RO/V/P", "nth_error", "Nth_Error indicates the current Nth Error that has occurred.[br][br]\r\n"
"Nth_Error will roll over upon saturating to its maximum values.[br][br]\r\n"
"An Nth error is defined as 1 or more lane miscompares within a single comparison cycle (i.e. Chunk)."},
#else
{24, 29, 0x0000000000000000, "RO/V/P", "nth_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000000, "RO/V/P", "rd_chunk_num_stat", "RD_Chunk_Num_Status corresponds to the chunk number being read out of the WDB (EXTBUF )for a RdCAS operation while logging an error during Loopback.Pattern.[br][br]\r\n"
"RD_Chunk_Num_Status is needed in conjunction with the lower 3 column address bits of the cacheline experiencing the error in order to deterministically rewind the LFSR/PB/LMN counter after the test is stopped due to an error condition. This is due to the pipelined nature of the data path since a cacheline can be read out of the WDB (EXTBUF) at the same time an error is being detected against an earlier read.[br]\r\n"
"Using RD_Chunk_Num_Status and the lower 3 column address bits of the cacheline experiencing the error allows the user to determine the skid between the LFSR/PB/LMN counter and the error detection.[br]\r\n"
"RD_Chunk_Num_Status can be cleared by one of two ways.[br][br]\r\n"
"1. Local_Clear_Errors or (Global_Control and Global_Clear_Errors) to 1.[br][br]\r\n"
"2. Writing RD_Chunk_Num_Status=0x0. One may also choose to clear individual bits in RD_Chunk_Num_Status.[br]\r\n"
"Setting bits in RD_Chunk_Num_Status is undefined and should be avoided.[br][br]\r\n"
"Writing a 0 to bits in RD_Chunk_Num_Status can be cleared independently of Data_Error_Status, ECC_Error_Status, Rank_Error_Status, Chunk_Error_Status, and Byte_Group_Error_Status."},
#else
{20, 22, 0x0000000000000000, "RO/V/P", "rd_chunk_num_stat", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW/1C/V/P", "eccgrp_err_stat", "A set bit implies that the ECC bytegroup has at least one lane that accumulated at least one error.[br]\r\n"
"Can also be cleared on Local Clear Errors (or Global_Control and a Global_Clear_Errors) ."},
#else
{8, 8, 0x0000000000000000, "RW/1C/V/P", "eccgrp_err_stat", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW/1C/V/P", "bytegrp_err_stat", "A flag field with each bit corresponding to a specific byte group.  Bit 0 corresponds to byte group 0, bit 1 corresponds to byte group 1, bit 2 corresponds to byte group 2, and so on.  A set bit implies that the corresponding byte group has at least one lane that accumulated at least one error.[br]\r\n"
"When BE Training Enable is set, then this field will indicate that a data error has occured that was not due to the corresponding BE signal.[br]\r\n"
"Can also be cleared on Local Clear Errors  (or Global_Control and a Global_Clear_Errors) ."},
#else
{0, 7, 0x0000000000000000, "RW/1C/V/P", "bytegrp_err_stat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo283[] = {{"CPGC_ERR_BYTE_NTH_PAR_STAT", "", 0x0000025C, 4, 0x000000003FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields284[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo284[] = {{"CPGC_ERR_CNTRCTL_0_", "", 0x00000260, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields285[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo285[] = {{"CPGC_ERR_CNTRCTL_1_", "", 0x00000264, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields286[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo286[] = {{"CPGC_ERR_CNTRCTL_2_", "", 0x00000268, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields287[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo287[] = {{"CPGC_ERR_CNTRCTL_3_", "", 0x0000026C, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields288[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo288[] = {{"CPGC_ERR_CNTRCTL_4_", "", 0x00000270, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields289[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo289[] = {{"CPGC_ERR_CNTRCTL_5_", "", 0x00000274, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields290[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo290[] = {{"CPGC_ERR_CNTRCTL_6_", "", 0x00000278, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields291[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo291[] = {{"CPGC_ERR_CNTRCTL_7_", "", 0x0000027C, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields292[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW/P", "counter_control", "Counter_Control determines what gets counted by CPGC_ERR_CNTR_#.Error_Counter.[br]\r\n"
"00=Count Errors on all Lanes - The Error Counter will capture the OR of all errors across all unmasked Lanes in a Chunk.  For example, if 1 lane or 72 lanes experience an error in a Chunk then the CPGC_ERR_CNTR_#.Error_Counter will be incremented by only 1.[br]\r\n"
"01=Count Errors on a particular Lane - The Error Counter will count the exact number of errors on the Lane indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER.[br]\r\n"
"10=Count Errors on a particular Byte Group - The Error Counter will count the number of errors on the Byte group indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER. ECC is byte group 8. An error within one Chunk within the selected ByteGroup is counted as 1 error.[br]\r\n"
"11=Count Errors on a particular Chunk - The Error Counter will count the number of errors on the a particular chunk in the cacheline indicated by CPGC_ERR_CNTRCTL.COUNTER_POINTER, across all lanes."},
#else
{7, 8, 0x0000000000000000, "RW/P", "counter_control", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", "Used in conjunction with Counter_Control to indicate which Lane, which ByteLane or which Chunk the CPGC_ERR_CNTR_#.Error_Counter will count errors on."},
#else
{0, 6, 0x0000000000000000, "RW/P", "counter_pointer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo292[] = {{"CPGC_ERR_CNTRCTL_8_", "", 0x00000280, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields293[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo293[] = {{"CPGC_ERR_CNTR_0_", "", 0x00000284, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields294[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo294[] = {{"CPGC_ERR_CNTR_1_", "", 0x00000288, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields295[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo295[] = {{"CPGC_ERR_CNTR_2_", "", 0x0000028C, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields296[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo296[] = {{"CPGC_ERR_CNTR_3_", "", 0x00000290, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields297[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo297[] = {{"CPGC_ERR_CNTR_4_", "", 0x00000294, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields298[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo298[] = {{"CPGC_ERR_CNTR_5_", "", 0x00000298, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields299[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo299[] = {{"CPGC_ERR_CNTR_6_", "", 0x0000029C, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields300[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo300[] = {{"CPGC_ERR_CNTR_7_", "", 0x000002A0, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields301[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", "CPGC_ERR_ERRCNTR indicates the current error counter value which is configured by CPGC_ERR_CNTRCTL.Counter_Control.  The  Counter_Status will not  saturate and will wrap around, but any overflow of this counter will set the corresponding overflow status bit in CPGC_ERR_ERRCNTR_OVERFLOW_STATUS.ERROR_COUNTER_OVERFLOW.[br][br]\r\n"
"Counter_Status can only be cleared by setting Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) . "},
#else
{0, 22, 0x0000000000000000, "RO/V/P", "error_counter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo301[] = {{"CPGC_ERR_CNTR_8_", "", 0x000002A4, 1, 0x00000000007FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields302[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 8, 0x0000000000000000, "RW/1C/V/P", "error_counter_overflow", "Contains the overflow flags for all Error Counters.[br]\r\n"
"Bit 0 corresponds to ERROR_COUNTER_0.[br]\r\n"
"Bit 1 corresponds to ERROR_COUNTER_1.[br]\r\n"
"..[br]\r\n"
"Bit 8 corresponds to ERROR_COUNTER_8.[br]\r\n"
"Error Counter Overflow Status can be cleared by one of two ways:[br]\r\n"
"1. Local_Clear_Errors (or Global_Control and a Global_Clear_Errors) to 1.[br]\r\n"
"2. Writing the correspoing Error Counter Overflow Status bit to 1.[br]\r\n"
"Writing a 0 to bits in Counter_Overflow_Status can be cleared independently of Data_Error_Status, Byte_Group_Error_Status, Chunk_Error_Status, and ECC_Error_Status."},
#else
{0, 8, 0x0000000000000000, "RW/1C/V/P", "error_counter_overflow", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo302[] = {{"CPGC_ERR_CNTR_OV", "", 0x000002A8, 1, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields303[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW/1S", "clr_dun_rdbuf_ptr", "Initializes the Error Log Current Read Pointer. Do this prior to the start of a test."},
#else
{16, 16, 0x0000000000000000, "RW/1S", "clr_dun_rdbuf_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW/1S", "inc_chunk_count", "Advance to next portion of data which is then available in the Error Log Data Register."},
#else
{15, 15, 0x0000000000000000, "RW/1S", "inc_chunk_count", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW/1S", "errlog_auto", "Asserting this bit will have the effect of CPGC automatically generating the needed Read transactions such as the current Read Pointer targets the last failing cachline. Instead of manually browsing, user can set this bit and logic will make sure that CURR_RD_PTR==ERROR_RD_PTR. This bit will always return '0' if read by software."},
#else
{14, 14, 0x0000000000000000, "RW/1S", "errlog_auto", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW/1S", "errlog_move", "Asserting this bit will have the effect of incrementing by one the Current Read Pointer at the actual Read Data Buffer. User can manually browse through the Read Data Buffer and dump its contents. This bit will always return '0' if read by software."},
#else
{13, 13, 0x0000000000000000, "RW/1S", "errlog_move", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW/P", "errlog_auto_chnk_inc", "Signal that will allow auto-increment feature for each 32bit data chunk read from the Error Log Data register.[br]\r\n"
"Note: If this bit is set, when doing the last 32bit data access via reading the Error Log Data register, the Error Log Current Read Pointer will auto increment as well."},
#else
{12, 12, 0x0000000000000000, "RW/P", "errlog_auto_chnk_inc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 8, 0x0000000000000000, "RO/V/P", "error_rd_ptr", "Provides the Read Pointer location that caused the error that triggered STOP_ON_ERROR. This will be used for knowing exactly which entry in the Read Data Buffer contains the faulty cacheline data."},
#else
{5, 8, 0x0000000000000000, "RO/V/P", "error_rd_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RO/V/P", "curr_rd_ptr", "Provides the current Read Pointer location indexed at the Read Data Buffer. This will be used for knowing how many Reads the user needs to issue to return the pointer to the actual failing entry."},
#else
{0, 3, 0x0000000000000000, "RO/V/P", "curr_rd_ptr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo303[] = {{"CPGC_ERRLOG_CTL_STAT", "", 0x000002AC, 7, 0x000000000001FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields304[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V/P", "errlog_data", "32 bits of data corresponding to one of eight (or four for ANN) 32 bit PMI chunks available per Read Pointer location. If ERRLOG_AUTO_CHNK_INC is set, then each read to this register will read out a successive 32 bit PMI chunk of data."},
#else
{0, 31, 0x0000000000000000, "RO/V/P", "errlog_data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo304[] = {{"CPGC_ERRLOG_DATA", "", 0x000002B0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields305[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "test_in_progress", "Used to indicate a loopback test is in progress."},
#else
{1, 1, 0x0000000000000000, "RO/V", "test_in_progress", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V/P", "error_status", "Bit set during the loopback test. Cleared when Local_Clear_Error in Loopback Sequencer Control is set."},
#else
{0, 0, 0x0000000000000000, "RO/V/P", "error_status", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo305[] = {{"CPGC_ERR_TEST_ERR_STAT", "", 0x000002B4, 2, 0x0000000000000003, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields306[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000007, "RW", "l2p_rank7_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{28, 30, 0x0000000000000007, "RW", "l2p_rank7_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000006, "RW", "l2p_rank6_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{24, 26, 0x0000000000000006, "RW", "l2p_rank6_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000005, "RW", "l2p_rank5_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{20, 22, 0x0000000000000005, "RW", "l2p_rank5_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000004, "RW", "l2p_rank4_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{16, 18, 0x0000000000000004, "RW", "l2p_rank4_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000003, "RW", "l2p_rank3_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{12, 14, 0x0000000000000003, "RW", "l2p_rank3_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000002, "RW", "l2p_rank2_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{8, 10, 0x0000000000000002, "RW", "l2p_rank2_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000001, "RW", "l2p_rank1_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{4, 6, 0x0000000000000001, "RW", "l2p_rank1_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "l2p_rank0_mapping", "Defines what physical Rank address (Memory Controller Rank Mapping) is mapped to this logical Rank address (Sequence Address Logic Domain)."},
#else
{0, 2, 0x0000000000000000, "RW", "l2p_rank0_mapping", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo306[] = {{"CPGC_SEQ_RANK_L2P_MAPPING", "", 0x000002B8, 8, 0x000000007FFFFFFF, 0x0000000076543210}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields307[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000007, "RW", "l2p_bank7_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{28, 31, 0x0000000000000007, "RW", "l2p_bank7_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000006, "RW", "l2p_bank6_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{24, 27, 0x0000000000000006, "RW", "l2p_bank6_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000005, "RW", "l2p_bank5_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{20, 23, 0x0000000000000005, "RW", "l2p_bank5_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000004, "RW", "l2p_bank4_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{16, 19, 0x0000000000000004, "RW", "l2p_bank4_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000003, "RW", "l2p_bank3_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{12, 15, 0x0000000000000003, "RW", "l2p_bank3_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000002, "RW", "l2p_bank2_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{8, 11, 0x0000000000000002, "RW", "l2p_bank2_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000001, "RW", "l2p_bank1_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{4, 7, 0x0000000000000001, "RW", "l2p_bank1_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "l2p_bank0_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{0, 3, 0x0000000000000000, "RW", "l2p_bank0_mapping", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo307[] = {{"CPGC_SEQ_BANK_L2P_MAPPING_A", "", 0x000002BC, 8, 0x00000000FFFFFFFF, 0x0000000076543210}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields308[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x000000000000000F, "RW", "l2p_bank15_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{28, 31, 0x000000000000000F, "RW", "l2p_bank15_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x000000000000000E, "RW", "l2p_bank14_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{24, 27, 0x000000000000000E, "RW", "l2p_bank14_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x000000000000000D, "RW", "l2p_bank13_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{20, 23, 0x000000000000000D, "RW", "l2p_bank13_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x000000000000000C, "RW", "l2p_bank12_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{16, 19, 0x000000000000000C, "RW", "l2p_bank12_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x000000000000000B, "RW", "l2p_bank11_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{12, 15, 0x000000000000000B, "RW", "l2p_bank11_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000A, "RW", "l2p_bank10_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{8, 11, 0x000000000000000A, "RW", "l2p_bank10_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000009, "RW", "l2p_bank9_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{4, 7, 0x0000000000000009, "RW", "l2p_bank9_mapping", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000008, "RW", "l2p_bank8_mapping", "Defines what physical Bank address (Memory Controller Bank Mapping) is mapped to this logical Bank address (Sequence Address Logic Domain)."},
#else
{0, 3, 0x0000000000000008, "RW", "l2p_bank8_mapping", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo308[] = {{"CPGC_SEQ_BANK_L2P_MAPPING_B", "", 0x000002C0, 8, 0x00000000FFFFFFFF, 0x00000000FEDCBA98}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields309[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x000000000000000F, "RW", "l2p_rank3_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other.  Only Rank address bits available to the memory controller are valid, others should be set to 0xF."},
#else
{12, 15, 0x000000000000000F, "RW", "l2p_rank3_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000E, "RW", "l2p_rank2_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{8, 11, 0x000000000000000E, "RW", "l2p_rank2_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x000000000000000D, "RW", "l2p_rank1_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{4, 7, 0x000000000000000D, "RW", "l2p_rank1_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x000000000000000C, "RW", "l2p_rank0_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{0, 3, 0x000000000000000C, "RW", "l2p_rank0_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo309[] = {{"CPGC_SEQ_RANK_ADDR_SWIZZLE", "", 0x000002C4, 4, 0x000000000000FFFF, 0x000000000000FEDC}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields310[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x000000000000001B, "RW", "l2p_bank3_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Bank address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value. Only Bank address bits available to the memory controller are valid, others should be set to 0x1F."},
#else
{15, 19, 0x000000000000001B, "RW", "l2p_bank3_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x000000000000001A, "RW", "l2p_bank2_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Bank address. The bits are essentially swizzled with each other."},
#else
{10, 14, 0x000000000000001A, "RW", "l2p_bank2_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000019, "RW", "l2p_bank1_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Bank address. The bits are essentially swizzled with each other."},
#else
{5, 9, 0x0000000000000019, "RW", "l2p_bank1_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000018, "RW", "l2p_bank0_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Bank address. The bits are essentially swizzled with each other."},
#else
{0, 4, 0x0000000000000018, "RW", "l2p_bank0_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo310[] = {{"CPGC_SEQ_BANK_ADDR_SWIZZLE", "", 0x000002C8, 4, 0x00000000000FFFFF, 0x00000000000DEB38}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields311[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x0000000000000005, "RW", "l2p_row5_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{25, 29, 0x0000000000000005, "RW", "l2p_row5_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x0000000000000004, "RW", "l2p_row4_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{20, 24, 0x0000000000000004, "RW", "l2p_row4_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x0000000000000003, "RW", "l2p_row3_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{15, 19, 0x0000000000000003, "RW", "l2p_row3_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x0000000000000002, "RW", "l2p_row2_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{10, 14, 0x0000000000000002, "RW", "l2p_row2_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000001, "RW", "l2p_row1_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{5, 9, 0x0000000000000001, "RW", "l2p_row1_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "l2p_row0_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{0, 4, 0x0000000000000000, "RW", "l2p_row0_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo311[] = {{"CPGC_SEQ_ROW_ADDR_SWIZZLE_A", "", 0x000002CC, 6, 0x000000003FFFFFFF, 0x000000000A418820}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields312[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x000000000000000B, "RW", "l2p_row11_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{25, 29, 0x000000000000000B, "RW", "l2p_row11_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x000000000000000A, "RW", "l2p_row10_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{20, 24, 0x000000000000000A, "RW", "l2p_row10_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x0000000000000009, "RW", "l2p_row9_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{15, 19, 0x0000000000000009, "RW", "l2p_row9_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x0000000000000008, "RW", "l2p_row8_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{10, 14, 0x0000000000000008, "RW", "l2p_row8_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000007, "RW", "l2p_row7_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{5, 9, 0x0000000000000007, "RW", "l2p_row7_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000006, "RW", "l2p_row6_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{0, 4, 0x0000000000000006, "RW", "l2p_row6_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo312[] = {{"CPGC_SEQ_ROW_ADDR_SWIZZLE_B", "", 0x000002D0, 6, 0x000000003FFFFFFF, 0x0000000016A4A0E6}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields313[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 29, 0x0000000000000011, "RW", "l2p_row17_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value. Only Row address bits available to the memory controller are valid, others should be set to 0x1F."},
#else
{25, 29, 0x0000000000000011, "RW", "l2p_row17_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x0000000000000010, "RW", "l2p_row16_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{20, 24, 0x0000000000000010, "RW", "l2p_row16_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x000000000000000F, "RW", "l2p_row15_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{15, 19, 0x000000000000000F, "RW", "l2p_row15_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x000000000000000E, "RW", "l2p_row14_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{10, 14, 0x000000000000000E, "RW", "l2p_row14_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x000000000000000D, "RW", "l2p_row13_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{5, 9, 0x000000000000000D, "RW", "l2p_row13_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000000C, "RW", "l2p_row12_swizzle", "Defines how a particular Logical Row or Bank bit is remapped to a Physical Row address. The bits are essentially swizzled with each other. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{0, 4, 0x000000000000000C, "RW", "l2p_row12_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo313[] = {{"CPGC_SEQ_ROW_ADDR_SWIZZLE_C", "", 0x000002D4, 6, 0x000000003FFFFFFF, 0x000000002307B9AC}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields314[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "addr_dq_inv_en", "Enables the lookup table to invert the DQs based on select Row address bits."},
#else
{29, 29, 0x0000000000000000, "RW", "addr_dq_inv_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 19, 0x000000000000001F, "RW", "l2p_row3_xor_swizzle", "Row XOR source selection for lower order Row addresses. Select 31 if only using a direct mapping with no XOR."},
#else
{15, 19, 0x000000000000001F, "RW", "l2p_row3_xor_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 14, 0x000000000000001F, "RW", "l2p_row2_xor_swizzle", "Row XOR source selection for lower order Row addresses. Select 31 if only using a direct mapping with no XOR."},
#else
{10, 14, 0x000000000000001F, "RW", "l2p_row2_xor_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x000000000000001F, "RW", "l2p_row1_xor_swizzle", "Row XOR source selection for lower order Row addresses. Select 31 if only using a direct mapping with no XOR."},
#else
{5, 9, 0x000000000000001F, "RW", "l2p_row1_xor_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "l2p_row0_xor_swizzle", "Row XOR source selection for lower order Row addresses. Select 31 if only using a direct mapping with no XOR. Bank Bits start at select value of 24. A value of 31 will select a constant '0' value."},
#else
{0, 4, 0x000000000000001F, "RW", "l2p_row0_xor_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo314[] = {{"CPGC_SEQ_ROW_ADDR_SWIZZLE_X", "", 0x000002D8, 5, 0x000000003FFFFFFF, 0x00000000000FFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields315[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000006, "RW", "l2p_col6_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other. Rank Bits start at select value of 12. A value of 11 will select a constant '0' value. "},
#else
{28, 31, 0x0000000000000006, "RW", "l2p_col6_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000005, "RW", "l2p_col5_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{24, 27, 0x0000000000000005, "RW", "l2p_col5_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000004, "RW", "l2p_col4_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{20, 23, 0x0000000000000004, "RW", "l2p_col4_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000003, "RW", "l2p_col3_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{16, 19, 0x0000000000000003, "RW", "l2p_col3_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000002, "RW", "l2p_col2_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{12, 15, 0x0000000000000002, "RW", "l2p_col2_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000001, "RW", "l2p_col1_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{8, 11, 0x0000000000000001, "RW", "l2p_col1_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "l2p_col0_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other. Column Address Bit 0 always corresponds to the logical A[6] for 64B requests and A[5] for 32B requests."},
#else
{4, 7, 0x0000000000000000, "RW", "l2p_col0_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo315[] = {{"CPGC_SEQ_COL_ADDR_SWIZZLE_A", "", 0x000002DC, 7, 0x00000000FFFFFFFF, 0x0000000065432100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields316[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000008, "RW", "l2p_col8_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other. Rank Bits start at select value of 12. A value of 11 will select a constant '0' value. Only Row address bits available to the memory controller are valid, others should be set to 11."},
#else
{4, 7, 0x0000000000000008, "RW", "l2p_col8_swizzle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000007, "RW", "l2p_col7_swizzle", "Defines how a particular Logical COL or RANK bit is remapped to a Physical COL address. The bits are essentially swizzled with each other."},
#else
{0, 3, 0x0000000000000007, "RW", "l2p_col7_swizzle", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo316[] = {{"CPGC_SEQ_COL_ADDR_SWIZZLE_B", "", 0x000002E0, 2, 0x00000000000000FF, 0x0000000000000087}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields317[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "Data written to this register will be placed in the DQ Map register as a stack. Data is read from the bottom of the stack (higher locations). The last write covers Row addresses of Row[11:4] = (0..31).[br]\r\n"
"Reading requires you to write into the stack to get the next location. Since this is destructive, if the data is to be preserved, then the data read should be used for the write. See documentation for details.[br]\r\n"
""},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo317[] = {{"CPGC_SEQ_ROW_ADDR_DQ_MAP0", "", 0x000002E8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields318[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "Data written to this register will be placed in the DQ Map register as a stack. Data is read from the bottom of the stack (higher locations). The last write covers Row addresses of Row[11:4] = (32..63).[br]\r\n"
"Reading requires you to write into the stack to get the next location. Since this is destructive, if the data is to be preserved, then the data read should be used for the write. See documentation for details."},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo318[] = {{"CPGC_SEQ_ROW_ADDR_DQ_MAP1", "", 0x000002EC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields319[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "cmd_deselect_stall", "(Not Implemented in BXT) TBD."},
#else
{31, 31, 0x0000000000000000, "RW", "cmd_deselect_stall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "cmd_deselect_restart", "If set, the CADB pattern will reload each time the chosen CMD_DESELECT_START condition is met. Please refer to CMD_DESLECT_START field for more info."},
#else
{29, 29, 0x0000000000000000, "RW", "cmd_deselect_restart", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "cadb_dbl_pump", "Setting bit 28 - Command and address are driven in a double-phase pattern (data changes on both halves of the DDR clock).  Clearing bit 28 - Command and address are driven in a single-phase pattern (data changes every full clock cycle)."},
#else
{28, 28, 0x0000000000000000, "RW", "cadb_dbl_pump", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "reload_starting_seed", "Reload_Starting_Seed will reload the 16bit CADB unisequencer starting seeds for LFSR/PB engines used for Select and Deselect chunk choosing to current seeds synchronous with particular commands (PRE/ACT/RD/WR) that are indicated to cause the reload to happen.  The reload seed must be used as the CADB output in the same cycle as the command which causes the reload to happen.[br][br]\r\n"
"Setting Bit 24 - Reload the starting seed to current seed on WR.[br][br]\r\n"
"Setting Bit 25 - Reload the starting seed to current seed on RD.[br][br]\r\n"
"Setting Bit 26 - Reload the starting seed to current seed on ACT.[br][br]\r\n"
"Setting Bit 27 - Reload the starting seed to current seed on PR."},
#else
{24, 27, 0x0000000000000000, "RW", "reload_starting_seed", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "save_current_seed", "Save_Current_Seed when qualified with Subsequence_Deselect_Save_Enable from REUT engine indicates which command triggers saving the current LFSR/PB values for Select and Deselect logic to the starting seed copy.[br][br]\r\n"
"Setting Bit 20 - Save the current seed to starting seed on WR.[br][br]\r\n"
"Setting Bit 21 - Save the current seed to starting seed on RD.[br][br]\r\n"
"Setting Bit 22 - Save the current seed to starting seed on ACT.[br][br]\r\n"
"Setting Bit 23 - Save the current seed to starting seed on PR."},
#else
{20, 23, 0x0000000000000000, "RW", "save_current_seed", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "pre_select_enable", "PRE_Select_Enable - Drive CADB generated patterns during all Precharge Select cycles on pins that are enabled based on the description below.[br][br]\r\n"
"Setting Bit 18 - Drive CADB patterns on MA pins except AP bit during a PRE command.[br][br]\r\n"
"Setting Bit 19 - Drive CADB patterns on BA pins during a PRE command.[br]\r\n"
""},
#else
{18, 19, 0x0000000000000000, "RW", "pre_select_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "act_select_enable", "ACT_Select_Enable - Drive CADB generated patterns during all ACT CMD Select cycles on pins that are enabled based on the description below.[br][br]\r\n"
"Setting Bit 16 - Drive CADB patterns on MA pins during an ACT cmd.[br][br]\r\n"
"Setting Bit 17 - Drive CADB patterns on BA pins during an ACT cmd.[br]\r\n"
""},
#else
{16, 17, 0x0000000000000000, "RW", "act_select_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "cas_select_enable", "CAS_Select_Enable - Drive CADB generated patterns during all CAS CMD Select cycles on pins that are enabled based on the description below.[br][br]\r\n"
"Setting Bit 14 - Drive CADB patterns on MA[11] and MA[9:0] pins during a CAS cmd.[br][br]\r\n"
"Setting Bit 15 - Drive CADB patterns on BA pins during a CAS cmd.[br][br]\r\n"
""},
#else
{14, 15, 0x0000000000000000, "RW", "cas_select_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x0000000000000000, "RW", "lane_deselect_en", "Setting Bit 10 - Drive CADB pattern on MA pins during Deselect cycles.[br][br]\r\n"
"Setting Bit 11 - Drive CADB pattern on BA pins during Deselect cycles.[br][br]\r\n"
"Setting Bit 12 - Drive CADB pattern on CMD pins during Deselect cycles.[br][br]\r\n"
"Setting Bit 13 - Drive CADB pattern on CS pins during Deselect cycles.[br][br]\r\n"
"Note: If CS is set than and CADB entry that also has CS set to one, the logic overrides CMD signals w/NOP encoding, thus making CMD and CS mutually exclusive to ensure no DDR functional violations occur."},
#else
{10, 13, 0x0000000000000000, "RW", "lane_deselect_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 9, 0x0000000000000000, "RW", "cmd_deselect_stop", "Setting Bit 6 - Stop driving CADB Deselect pattern on the following cycle after a WR CMD.[br][br]\r\n"
"Setting Bit 7 - Stop driving CADB Deselect pattern on the following cycle after a RD CMD.[br][br]\r\n"
"Setting Bit 8 - Stop driving CADB Deselect pattern on the following cycle after an ACT CMD.[br][br]\r\n"
"Setting Bit 9 - Stop driving CADB Deselect pattern on the following cycle after a PRE CMD.[br][br]\r\n"
"Note: If Deselect was off before the command that is supposed to stop it, it will remain in the off state."},
#else
{6, 9, 0x0000000000000000, "RW", "cmd_deselect_stop", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 5, 0x0000000000000000, "RW", "cmd_deselect_start", "Setting Bit 2 - Start Driving Deselects on the following cycle after a WR CMD if CADB_Deselect_Enable is high.[br][br]\r\n"
"Setting Bit 3 - Start Driving Deselects on the following cycle after a RD CMD if CADB_Deselect_Enable is high.[br][br]\r\n"
"Setting Bit 4 - Start Driving Deselects on the following cycle after a ACT CMD if CADB_Deselect_Enable is high.[br][br]\r\n"
"Setting Bit 5 - Start Driving Deselects on the following cycle after a PRE CMD if CADB_Deselect_Enable is high.[br]"},
#else
{2, 5, 0x0000000000000000, "RW", "cmd_deselect_start", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "cadb_mode", "The operation mode of the command/address pattern generator is encoded as follows:[br][br]\r\n"
"00 - Select and trigger-driven-Deselect : CADB will drive patterns during Select and Deselect cycles depending on the values programmed in Lane_Deselect_Enable and PRE_Select_Enable/ACT_Select_Enable/CAS_Select_Enable. Trigger-driven-Deselect allows start/stop of Deselect cycles to synchronize with various CMD events and/or Subsequence control bits.[br][br]\r\n"
"01 - Global Deselect : CADB generated pattern will be driven on the bus during deselect cycles only when SoC CPGC is in ACTIVE or NORMAL mode. SoC CPGC will drive out the pattern on all command and address signals (except CKE, and ODT). User can choose which ADDRESS/CMD lanes will be enabled for this mode. CS gets special treatment as mentioned in LANE_DESELECT_ENABLE description.[br][br]\r\n"
"10 - Always On: [br][br]\r\n"
"If INITIALIZATION_MODE is ACTIVE MODE, pattern stored in the command/address buffers will be driven on all command and address signals on every DCLK cycle. This is not a functional mode and should only be used for BDV purposes.[br][br]\r\n"
"If INITIALIZATION_MODE is MRS MODE, pattern stored in the command/address buffers will be driven on all command and address signals under the control of the CADB MRS state machine. This is the way to send MRS commands to DRAM devices using CPGC.[br][br]\r\n"
"11 - RESERVED:"},
#else
{0, 1, 0x0000000000000000, "RW", "cadb_mode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo319[] = {{"CPGC_CADB_CTL", "", 0x000002F0, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields320[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "mrs_cs_mode", "Only if it is set to 0, it will be deaserted at (1 or 2 cycles) number of cycles at the middle of Gap CS, is selected per entry and per rank.[br][br]\r\n"
"00 - No Override.[br][br]\r\n"
"01 - No Override.[br][br]\r\n"
"10 - One Cycle CS.[br][br]\r\n"
"11 - Two Cycles CS."},
#else
{28, 29, 0x0000000000000000, "RW", "mrs_cs_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000007, "RO/V", "mrs_curr_ptr", "Current MRS instruction pointer - Valid for LP3 only."},
#else
{24, 26, 0x0000000000000007, "RO/V", "mrs_curr_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000007, "RW", "mrs_end_ptr", "Pointer to the last CADB entry. To be used if in MRS mode.[br] Note: This indexing mode of the CADB buffer is only available if in CPGC_SEQ_CFG_0.INITIALIZATION_MODE=MRS_MODE. For MRS Double pump mode or 1/2N mode, the end pointer should be programmed to 3 or 7. Otherwise, the valid willl show up only for the first 40 bits which would be from BUF0- [9:0] bits, BUF1 [9:0] bits, BUF2 [9:0] bits and BUF3 [9:0] bits."},
#else
{16, 18, 0x0000000000000007, "RW", "mrs_end_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "mrs_start_ptr", "Pointer to the first CADB entry. To be used if in MRS mode.[br] Note: This indexing mode of the CADB buffer is only available if in CPGC_SEQ_CFG_0.INITIALIZATION_MODE=MRS_MODE."},
#else
{8, 10, 0x0000000000000000, "RW", "mrs_start_ptr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "mrs_gap_scale", "Linear or Exponential Scale for CADB_GAP value.[br]\r\n"
"[b]Note: This is not implemented in Reference RTL yet. [/b]]"},
#else
{4, 4, 0x0000000000000000, "RW", "mrs_gap_scale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "mrs_gap", "2^(MRS_GAP) clock cycles between changing to the next MRS CADB entry. Value Zero is prohibited.[br] Note: This GAP is applicable to both, MRS mode or normal CADB pattern gen. When used for non MRS CADB pattern generation, a value of Zero is allowed."},
#else
{0, 3, 0x0000000000000000, "RW", "mrs_gap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo320[] = {{"CPGC_CADB_MRSCFG", "", 0x000002F4, 6, 0x000000003FFFFFFF, 0x0000000007070000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields321[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000001, "RW", "sel_uniseq2_mode", "Defines the operational mode for select unified sequence 2 as follows:[br][br]\r\n"
"00 - Reserved for future use.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{24, 25, 0x0000000000000001, "RW", "sel_uniseq2_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000001, "RW", "sel_uniseq1_mode", "Defines the operational mode for select unified sequence 1 as follows:[br][br]\r\n"
"00 - Reserved for future use.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{20, 21, 0x0000000000000001, "RW", "sel_uniseq1_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000001, "RW", "sel_uniseq0_mode", "Defines the operational mode for select unified sequence 0 as follows:[br][br]\r\n"
"00 - Reserved for future use.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{16, 17, 0x0000000000000001, "RW", "sel_uniseq0_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000001, "RW", "uniseq2_mode", "Defines the operational mode for unified sequence 2 as follows:[br][br]\r\n"
"00 - LMN Mode.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{8, 9, 0x0000000000000001, "RW", "uniseq2_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000001, "RW", "uniseq1_mode", "Defines the operational mode for unified sequence 1 as follows:[br][br]\r\n"
"00 - LMN Mode.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{4, 5, 0x0000000000000001, "RW", "uniseq1_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "uniseq0_mode", "Defines the operational mode for unified sequence 0 as follows:[br][br]\r\n"
"00 - LMN Mode.[br][br]\r\n"
"01 - Pattern Buffer Mode.[br][br]\r\n"
"10 - LFSR Mode.[br][br]\r\n"
"11 - Reserved for future use."},
#else
{0, 1, 0x0000000000000001, "RW", "uniseq0_mode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo321[] = {{"CPGC_CADB_CFG", "", 0x000002F8, 6, 0x0000000003FFFFFF, 0x0000000001110111}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields322[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x000000000000AA55, "RW", "cmd", "The initial content of the rotating pattern buffer for the unified sequencer."},
#else
{0, 15, 0x000000000000AA55, "RW", "cmd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo322[] = {{"CPGC_CADB_UNISEQ0_PBUF", "", 0x000002FC, 1, 0x000000000000FFFF, 0x000000000000AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields323[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x000000000000AA55, "RW", "cmd", "The initial content of the rotating pattern buffer for the unified sequencer."},
#else
{0, 15, 0x000000000000AA55, "RW", "cmd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo323[] = {{"CPGC_CADB_UNISEQ1_PBUF", "", 0x00000300, 1, 0x000000000000FFFF, 0x000000000000AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields324[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x000000000000AA55, "RW", "cmd", "The initial content of the rotating pattern buffer for the unified sequencer."},
#else
{0, 15, 0x000000000000AA55, "RW", "cmd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo324[] = {{"CPGC_CADB_UNISEQ2_PBUF", "", 0x00000304, 1, 0x000000000000FFFF, 0x000000000000AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields325[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000005, "RW", "m_cnt", "Number of UIs that the unisequencer will drive logic '1'."},
#else
{24, 26, 0x0000000000000005, "RW", "m_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000002, "RW", "n_cnt", "Number of UIs that the unisequencer will drive logic '0'."},
#else
{16, 18, 0x0000000000000002, "RW", "n_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000004, "RW", "l_cnt", "Number of UIs that the unisequencer will drive the logic value selected through L_SEL before entering the steady state periodic phase."},
#else
{8, 10, 0x0000000000000004, "RW", "l_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000005, "RW", "cnt_scale", "Values for L_CNT, M_CNT, and N_CNT are scaled by a factor of 2^CNT_SCALE."},
#else
{4, 6, 0x0000000000000005, "RW", "cnt_scale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "en_sweep_freq", "0 - Disable Sweep Frequency. 1 - Enable Sweep Frequency. [br][br]\r\n"
"[b]Note: This is not implemented in Reference RTL yet. [/b]]"},
#else
{1, 1, 0x0000000000000000, "RW", "en_sweep_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "l_sel", "The initial logic output of the sequencer is defined as follows:[br][br]\r\n"
"                        0 - Output Logic '0' for L_CNT UIs.[br][br]\r\n"
"                        1 - Output Logic '1' for L_CNT UIs."},
#else
{0, 0, 0x0000000000000001, "RW", "l_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo325[] = {{"CPGC_CADB_UNISEQ0_LMN", "", 0x00000308, 6, 0x0000000007FFFFFF, 0x0000000005020451}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields326[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000005, "RW", "m_cnt", "Number of UIs that the unisequencer will drive logic '1'."},
#else
{24, 26, 0x0000000000000005, "RW", "m_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000002, "RW", "n_cnt", "Number of UIs that the unisequencer will drive logic '0'."},
#else
{16, 18, 0x0000000000000002, "RW", "n_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000004, "RW", "l_cnt", "Number of UIs that the unisequencer will drive the logic value selected through L_SEL before entering the steady state periodic phase."},
#else
{8, 10, 0x0000000000000004, "RW", "l_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000005, "RW", "cnt_scale", "Values for L_CNT, M_CNT, and N_CNT are scaled by a factor of 2^CNT_SCALE."},
#else
{4, 6, 0x0000000000000005, "RW", "cnt_scale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "en_sweep_freq", "0 - Disable Sweep Frequency. 1 - Enable Sweep Frequency. [br][br]\r\n"
"[b]Note: This is not implemented in Reference RTL yet. [/b]]"},
#else
{1, 1, 0x0000000000000000, "RW", "en_sweep_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "l_sel", "The initial logic output of the sequencer is defined as follows:[br][br]\r\n"
"                        0 - Output Logic '0' for L_CNT UIs.[br][br]\r\n"
"                        1 - Output Logic '1' for L_CNT UIs."},
#else
{0, 0, 0x0000000000000001, "RW", "l_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo326[] = {{"CPGC_CADB_UNISEQ1_LMN", "", 0x0000030C, 6, 0x0000000007FFFFFF, 0x0000000005020451}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields327[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000005, "RW", "m_cnt", "Number of UIs that the unisequencer will drive logic '1'."},
#else
{24, 26, 0x0000000000000005, "RW", "m_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000002, "RW", "n_cnt", "Number of UIs that the unisequencer will drive logic '0'."},
#else
{16, 18, 0x0000000000000002, "RW", "n_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000004, "RW", "l_cnt", "Number of UIs that the unisequencer will drive the logic value selected through L_SEL before entering the steady state periodic phase."},
#else
{8, 10, 0x0000000000000004, "RW", "l_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000005, "RW", "cnt_scale", "Values for L_CNT, M_CNT, and N_CNT are scaled by a factor of 2^CNT_SCALE."},
#else
{4, 6, 0x0000000000000005, "RW", "cnt_scale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "en_sweep_freq", "0 - Disable Sweep Frequency. 1 - Enable Sweep Frequency. [br][br]\r\n"
"[b]Note: This is not implemented in Reference RTL yet. [/b]]"},
#else
{1, 1, 0x0000000000000000, "RW", "en_sweep_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "l_sel", "The initial logic output of the sequencer is defined as follows:[br][br]\r\n"
"                        0 - Output Logic '0' for L_CNT UIs.[br][br]\r\n"
"                        1 - Output Logic '1' for L_CNT UIs."},
#else
{0, 0, 0x0000000000000001, "RW", "l_sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo327[] = {{"CPGC_CADB_UNISEQ2_LMN", "", 0x00000310, 6, 0x0000000007FFFFFF, 0x0000000005020451}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields328[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x000000000000AA55, "RW", "cmd", "The initial content of the rotating pattern buffer for the select unified sequencer."},
#else
{0, 15, 0x000000000000AA55, "RW", "cmd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo328[] = {{"CPGC_CADB_SEL_UNISEQ0_PBUF", "", 0x00000314, 1, 0x000000000000FFFF, 0x000000000000AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields329[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x000000000000AA55, "RW", "cmd", "The initial content of the rotating pattern buffer for the select unified sequencer."},
#else
{0, 15, 0x000000000000AA55, "RW", "cmd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo329[] = {{"CPGC_CADB_SEL_UNISEQ1_PBUF", "", 0x00000318, 1, 0x000000000000FFFF, 0x000000000000AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields330[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x000000000000AA55, "RW", "cmd", "The initial content of the rotating pattern buffer for the select unified sequencer."},
#else
{0, 15, 0x000000000000AA55, "RW", "cmd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo330[] = {{"CPGC_CADB_SEL_UNISEQ2_PBUF", "", 0x0000031C, 1, 0x000000000000FFFF, 0x000000000000AA55}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields331[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo331[] = {{"CPGC_CADB_BUFA_0_", "", 0x00000320, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields332[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo332[] = {{"CPGC_CADB_BUFA_1_", "", 0x00000324, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields333[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo333[] = {{"CPGC_CADB_BUFA_2_", "", 0x00000328, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields334[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo334[] = {{"CPGC_CADB_BUFA_3_", "", 0x0000032C, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields335[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo335[] = {{"CPGC_CADB_BUFA_4_", "", 0x00000330, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields336[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo336[] = {{"CPGC_CADB_BUFA_5_", "", 0x00000334, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields337[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo337[] = {{"CPGC_CADB_BUFA_6_", "", 0x00000338, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields338[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "bank_addr", "The DRAM bank address.[br] Note: Not used in LPDDR2/3."},
#else
{24, 27, 0x0000000000000000, "RW", "bank_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "row_col_addr", "The DRAM row/column address.[br][br]\r\n"
"LPDDR2/3 Maps the following:[br][br]\r\n"
"CA[9:0] rise=ROW_COL_ADDR[9:0][br][br]\r\n"
"CA[9:0] fall=ROW_COL_ADDR[19:10][br][br]\r\n"
"Note: Shared for DDR3 and LPDDR2/3. See ANN/CHV Dunit HAS for further information on the mapping."},
#else
{0, 19, 0x0000000000000000, "RW", "row_col_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo338[] = {{"CPGC_CADB_BUFA_7_", "", 0x0000033C, 2, 0x000000000FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields339[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo339[] = {{"CPGC_CADB_BUFB_0_", "", 0x00000340, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields340[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo340[] = {{"CPGC_CADB_BUFB_1_", "", 0x00000344, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields341[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo341[] = {{"CPGC_CADB_BUFB_2_", "", 0x00000348, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields342[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo342[] = {{"CPGC_CADB_BUFB_3_", "", 0x0000034C, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields343[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo343[] = {{"CPGC_CADB_BUFB_4_", "", 0x00000350, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields344[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo344[] = {{"CPGC_CADB_BUFB_5_", "", 0x00000354, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields345[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo345[] = {{"CPGC_CADB_BUFB_6_", "", 0x00000358, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields346[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "par", "Used to write the parity invert CADB data. [br][br]\r\n"
"When working with DDR4 if this bit is set and the CADB entry is selected, the parity value is inverted to reflect a C/A parity error.[br][br]\r\n"
"See CADB Read_Write_Pointer for programming details."},
#else
{31, 31, 0x0000000000000000, "RW", "par", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "val", "Used to write the valid CADB data."},
#else
{30, 30, 0x0000000000000000, "RW", "val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "cke", "The DRAM Clock Enable signals."},
#else
{24, 27, 0x0000000000000000, "RW", "cke", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "odt", "The DRAM On-Die Termination Signals.[br] Note: Not used in LPDDR2/3."},
#else
{16, 19, 0x0000000000000000, "RW", "odt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000007, "RW", "cmd", "The DRAM command signals [ACT#,RAS#,CAS#,WE#]. All three signals are active low and hence default to '1's on reset.[br] Note: Not used in LPDDR2/3."},
#else
{8, 11, 0x0000000000000007, "RW", "cmd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "cid", "The DRAM Chip ID."},
#else
{2, 4, 0x0000000000000000, "RW", "cid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000003, "RW", "cs", "The DRAM Chip Select signals [CS#]. These signals are active low and hence default is '1' on reset."},
#else
{0, 1, 0x0000000000000003, "RW", "cs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo346[] = {{"CPGC_CADB_BUFB_7_", "", 0x0000035C, 7, 0x00000000FFFFFFFF, 0x0000000000000703}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields347[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO/V", "uniseq_stat", "The current contents of the command/address pattern unified sequencer buffer.  In case a stop condition occurs, this register will contain the last value that was used to generate the command/address pattern.  Bit 0 represents the value used for the current chunk."},
#else
{0, 15, 0x0000000000000000, "RO/V", "uniseq_stat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo347[] = {{"CPGC_CADB_UNISEQ0STAT", "", 0x00000360, 1, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields348[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO/V", "uniseq_stat", "The current contents of the command/address pattern unified sequencer buffer.  In case a stop condition occurs, this register will contain the last value that was used to generate the command/address pattern.  Bit 0 represents the value used for the current chunk."},
#else
{0, 15, 0x0000000000000000, "RO/V", "uniseq_stat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo348[] = {{"CPGC_CADB_UNISEQ1STAT", "", 0x00000364, 1, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields349[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO/V", "uniseq_stat", "The current contents of the command/address pattern unified sequencer buffer.  In case a stop condition occurs, this register will contain the last value that was used to generate the command/address pattern.  Bit 0 represents the value used for the current chunk."},
#else
{0, 15, 0x0000000000000000, "RO/V", "uniseq_stat", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo349[] = {{"CPGC_CADB_UNISEQ2STAT", "", 0x00000368, 1, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields350[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "memtech", "Memory Technology\r\n"
"Bit 3:0: DRAM Technology\r\n"
"0000: LPDDR3\r\n"
"0001: LPDDR4\r\n"
"0010: DDR3/L/U\r\n"
"0011: DDR4/L\r\n"
"0100: WIO2\r\n"
"0101: FMI\r\n"
"0110: DDR-T\r\n"
"0111: HBM"},
#else
{28, 31, 0x0000000000000000, "RW", "memtech", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "memfreq", "Memory frequency\r\n"
"Bit 3:0 DRAM Frequency\r\n"
"0000: 800\r\n"
"0001: 1066\r\n"
"0010: 1333\r\n"
"0011: 1600\r\n"
"0100: 1866\r\n"
"0101: 2133\r\n"
"0110: 2400"},
#else
{24, 27, 0x0000000000000000, "RW", "memfreq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "phyupd_dly", "Delay between the phy update request to ack \r\n"
"in terms of SPID clocks."},
#else
{16, 23, 0x0000000000000000, "RW", "phyupd_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "stretchmode", "This is the stretch mode signal.\r\n"
"00- normal read\r\n"
"01- x4 stretch mode \r\n"
"10- x8 stretch mode\r\n"
"11- x16 stretch mode"},
#else
{13, 14, 0x0000000000000000, "RW", "stretchmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 12, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "slowpath", "When enabled, SPID wrcmd is delayed by 1 spidclk before writing into the fifo.\r\n"
"Set to 1 if clock gating is enabled. Else set it to 0. \r\n"
"\r\n"
"1: 1 spidclk delay \r\n"
"0: no delay"},
#else
{11, 11, 0x0000000000000000, "RW", "slowpath", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{10, 10, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "rdmcpsel", "Programmable MCP for Tx FIFO read pointer path.\r\n"
"\r\n"
"1: Enable MCP path \r\n"
"0: Disable MCP path"},
#else
{9, 9, 0x0000000000000000, "RW", "rdmcpsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 8, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ca_training", "CA training mode"},
#else
{6, 6, 0x0000000000000000, "RW", "ca_training", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "bl1632xbl48b", "This is the burstlength configuration register\r\n"
"1:BL16 and BL32\r\n"
"0:BL4 and BL8"},
#else
{5, 5, 0x0000000000000000, "RW", "bl1632xbl48b", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RW", "spidclksel", "SPID clk sel \r\n"
"00: 0.5xmode\r\n"
"01: 0.25x mode\r\n"
"10: 0.1x mode\r\n"
"11: NA"},
#else
{3, 4, 0x0000000000000000, "RW", "spidclksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "lpddr34mode", "Single data rate v/s Double Data rate \r\n"
"0: Double data rate (LP3)\r\n"
"1: Single data rate (LP4)"},
#else
{2, 2, 0x0000000000000000, "RW", "lpddr34mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo350[] = {{"DIGCTL", "", 0x00000000, 15, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields351[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "siggrp02_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4 Mode)"},
#else
{30, 30, 0x0000000000000000, "RW", "siggrp02_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "siggrp01_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4 Mode)"},
#else
{29, 29, 0x0000000000000000, "RW", "siggrp01_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "siggrp00_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4 Mode)"},
#else
{28, 28, 0x0000000000000000, "RW", "siggrp00_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "compclkrdptrinit", "DLL comp init configuration."},
#else
{24, 27, 0x0000000000000000, "RW", "compclkrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RW", "compclkrdptroffset", "DLL comp read pointer offset."},
#else
{21, 23, 0x0000000000000000, "RW", "compclkrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 20, 0x0000000000000000, "RW", "ref1xrdptrinit", "This is the ref1x read pointer init configuration."},
#else
{17, 20, 0x0000000000000000, "RW", "ref1xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dqxccb", "Configure DQCCC as DQ or CCC\r\n"
"0: CCC\r\n"
"1: DQ\r\n"
"This signal is invalid for BXT-P"},
#else
{16, 16, 0x0000000000000000, "RW", "dqxccb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ref1xrdptroffset", "This is the ref1xread pointer offset configuration."},
#else
{13, 15, 0x0000000000000000, "RW", "ref1xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ref2xrdptrinit", "This is the ref2x read pointer init configuration."},
#else
{8, 12, 0x0000000000000000, "RW", "ref2xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "cc_doublefifooffset", "This is the double FIFO offset configuration(in terms of 2xclock)."},
#else
{4, 7, 0x0000000000000000, "RW", "cc_doublefifooffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "bl_doublefifooffset", "This is the double FIFO offset configuration(in terms of 2xclock)."},
#else
{0, 3, 0x0000000000000000, "RW", "bl_doublefifooffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo351[] = {{"FIFOPTRCTL", "", 0x00000004, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields352[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rxfiforst_b", "Rxfifo reset (active low)\r\n"
"1: deasserted\r\n"
"0 : asserted"},
#else
{1, 1, 0x0000000000000000, "RW", "rxfiforst_b", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "spidrst_b", "Reset for functional logic in upartition (except compensation and power management logic)  \r\n"
"0: Reset assertion  \r\n"
"1: Reset de-assertion"},
#else
{0, 0, 0x0000000000000000, "RW", "spidrst_b", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo352[] = {{"DIGRSTCTL", "", 0x00000008, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields353[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "wrptren", "Tx FIFO write pointer enable. \r\n"
"0: Disable\r\n"
"1: Enable"},
#else
{0, 0, 0x0000000000000000, "RW", "wrptren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo353[] = {{"FIFOPTREN", "", 0x0000000C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields354[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lvl_cc_iobufactafe", "IO buffer activate - DQ BL1 Analog\r\n"
"Tristates DQ and DQS IO buffers \r\n"
"Disable Rx sections of IO buffers \r\n"
"0 : Disable IO buffers \r\n"
"1 : Enable IO buffers"},
#else
{1, 1, 0x0000000000000000, "RW", "lvl_cc_iobufactafe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lvl_bl_iobufactafe", "IO buffer activate - DQ BL0 Analog\r\n"
"Tristates DQ and DQS IO buffers \r\n"
"Disable Rx sections of IO buffers \r\n"
"0 : Disable IO buffers \r\n"
"1 : Enable IO buffers"},
#else
{0, 0, 0x0000000000000000, "RW", "lvl_bl_iobufactafe", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo354[] = {{"IOBUFACT_AFE", "", 0x00000010, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields355[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "cc_iobufactdig", "IO buffer activate - DQ BL1 Digital.\r\n"
"This resets the intermediate/final flops in the transmit path.\r\n"
"\r\n"
"0 : Assert reset \r\n"
"1 : De-assert reset"},
#else
{1, 1, 0x0000000000000000, "RW", "cc_iobufactdig", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "bl_iobufactdig", "IO buffer activate - DQ BL0 Digital.\r\n"
"This resets the intermediate/final flops in the transmit path.\r\n"
"\r\n"
"0 : Assert reset \r\n"
"1 : De-assert reset"},
#else
{0, 0, 0x0000000000000000, "RW", "bl_iobufactdig", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo355[] = {{"IOBUFACT_DIG", "", 0x00000014, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields356[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "spid_init_complete", "SPID init complete"},
#else
{0, 0, 0x0000000000000000, "RW", "spid_init_complete", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo356[] = {{"SPIDIC", "", 0x00000018, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields357[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "early_dqen", "Early DQ Enable"},
#else
{16, 16, 0x0000000000000000, "RW", "early_dqen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "cc_dqdrvenbph1", "First data phase setting for BL1 DQ driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{14, 15, 0x0000000000000000, "RW", "cc_dqdrvenbph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "cc_dqdrvenbpream1", "Preamble 1 setting for BL1 DQ driver enable. This is applicable only if 2tCK write preamble mode is enabled.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{12, 13, 0x0000000000000000, "RW", "cc_dqdrvenbpream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "cc_dqdrvenblastph", "Last data phase setting for BL1 DQ driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{10, 11, 0x0000000000000000, "RW", "cc_dqdrvenblastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "cc_dqdrvenbpream0", "Preamble 0 setting for BL1 DQ driver enable\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{8, 9, 0x0000000000000000, "RW", "cc_dqdrvenbpream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "bl_dqdrvenbph1", "First data phase setting for BL0 DQ driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{6, 7, 0x0000000000000000, "RW", "bl_dqdrvenbph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "bl_dqdrvenbpream1", "Preamble 1 setting for BL0 DQ driver enable. This is applicable only if 2tCK write preamble mode is enabled.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{4, 5, 0x0000000000000000, "RW", "bl_dqdrvenbpream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "bl_dqdrvenblastph", "Last data phase setting for BL0 DQ driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{2, 3, 0x0000000000000000, "RW", "bl_dqdrvenblastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "bl_dqdrvenbpream0", "Preamble 0 setting for BL0 DQ driver enable\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{0, 1, 0x0000000000000000, "RW", "bl_dqdrvenbpream0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo357[] = {{"WRDQCTL", "", 0x0000001C, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields358[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "cc_dqsdrvenbph1", "First data phase setting for BL1 DQS driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{30, 31, 0x0000000000000000, "RW", "cc_dqsdrvenbph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "cc_dqsdrvenbpream1", "Preamble 1 setting for BL1 DQS driver enable. This is applicable only if 2tCK write preamble mode is enabled.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{28, 29, 0x0000000000000000, "RW", "cc_dqsdrvenbpream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "cc_dqsdrvenblastph", "Last data phase setting for BL1 DQS driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{26, 27, 0x0000000000000000, "RW", "cc_dqsdrvenblastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "cc_dqsdrvenbpream0", "Preamble 0 setting for BL1 DQS driver enable\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{24, 25, 0x0000000000000000, "RW", "cc_dqsdrvenbpream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "cc_dmdrven", "BL1 Data mask drive enable\r\n"
"1: Enable DM buffer\r\n"
"0: Tristate DM buffer"},
#else
{20, 20, 0x0000000000000000, "RW", "cc_dmdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "cc_wrpream0en", "2tCK write preamble mode for BL1\r\n"
"0 : 1 tCK write preamble mode\r\n"
"1 : 2 tCK write preamble mode"},
#else
{19, 19, 0x0000000000000000, "RW", "cc_wrpream0en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "reserved", "TBD"},
#else
{18, 18, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000003, "RW", "cc_dqsdrvenbidle", "Idle phase setting for BL1 DQS data. \r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{16, 17, 0x0000000000000003, "RW", "cc_dqsdrvenbidle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "cc_dqsdataph1", "First data phase setting for BL1 DQS data. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{14, 15, 0x0000000000000000, "RW", "cc_dqsdataph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "cc_dqsdatapream1", "Preamble 1 setting for BL1 DQS data. This is applicable only in case of 2tCK write preamble case.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{12, 13, 0x0000000000000000, "RW", "cc_dqsdatapream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "cc_dqsdatalastph", "Last data phase setting for BL1 DQS data. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{10, 11, 0x0000000000000000, "RW", "cc_dqsdatalastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "cc_dqsdatapream0", "Preamble 0 setting for BL1 DQS data\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{8, 9, 0x0000000000000000, "RW", "cc_dqsdatapream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "cc_wrcmd2dqsstart", "Write command to BL1 DQS start delay. This is in ref1xclks."},
#else
{0, 5, 0x0000000000000000, "RW", "cc_wrcmd2dqsstart", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo358[] = {{"WRDQSCTL_CC", "", 0x00000020, 15, 0x00000000FFFFFFFF, 0x0000000000030000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields359[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "bl_dqsdrvenbph1", "First data phase setting for BL0 DQS driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{30, 31, 0x0000000000000000, "RW", "bl_dqsdrvenbph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "bl_dqsdrvenbpream1", "Preamble 1 setting for BL0 DQS driver enable. This is applicable only if 2tCK write preamble mode is enabled.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{28, 29, 0x0000000000000000, "RW", "bl_dqsdrvenbpream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "bl_dqsdrvenblastph", "Last data phase setting for BL0 DQS driver enable. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{26, 27, 0x0000000000000000, "RW", "bl_dqsdrvenblastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "bl_dqsdrvenbpream0", "Preamble 0 setting for BL0 DQS driver enable\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{24, 25, 0x0000000000000000, "RW", "bl_dqsdrvenbpream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "bl_dmdrven", "BL0 Data mask drive enable\r\n"
"1: Enable DM buffer\r\n"
"0: Tristate DM buffer"},
#else
{20, 20, 0x0000000000000000, "RW", "bl_dmdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "bl_wrpream0en", "2tCK write preamble mode for BL0\r\n"
"0 : 1 tCK write preamble mode\r\n"
"1 : 2 tCK write preamble mode"},
#else
{19, 19, 0x0000000000000000, "RW", "bl_wrpream0en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "reserved", "TBD"},
#else
{18, 18, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000003, "RW", "bl_dqsdrvenbidle", "Idle phase setting for BL0 DQS data. \r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{16, 17, 0x0000000000000003, "RW", "bl_dqsdrvenbidle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "bl_dqsdataph1", "First data phase setting for BL0 DQS data. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{14, 15, 0x0000000000000000, "RW", "bl_dqsdataph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "bl_dqsdatapream1", "Preamble 1 setting for BL0 DQS data. This is applicable only in case of 2tCK write preamble case.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{12, 13, 0x0000000000000000, "RW", "bl_dqsdatapream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "bl_dqsdatalastph", "Last data phase setting for BL0 DQS data. For regular writes, this needs to be set to 00.\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{10, 11, 0x0000000000000000, "RW", "bl_dqsdatalastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "bl_dqsdatapream0", "Preamble 0 setting for BL0 DQS data\r\n"
"\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 (illegal)\r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{8, 9, 0x0000000000000000, "RW", "bl_dqsdatapream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "bl_wrcmd2dqsstart", "Write command to BL0 DQS start delay. This is in ref1xclks."},
#else
{0, 5, 0x0000000000000000, "RW", "bl_wrcmd2dqsstart", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo359[] = {{"WRDQSCTL_BL", "", 0x00000024, 15, 0x00000000FFFFFFFF, 0x0000000000030000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields360[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "rdcmd2rdvld_bonus", "Read command 2 read bonus bits."},
#else
{16, 23, 0x0000000000000000, "RW", "rdcmd2rdvld_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "rdcmd2rdvld_plus1sel", "Read command 2 read valid plus 1 sel."},
#else
{12, 14, 0x0000000000000000, "RW", "rdcmd2rdvld_plus1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "earlyrdvld", "This controls the delay between the read valid assertion to SOC and the actual read valid assertion\r\n"
"0: Normal\r\n"
"1: 1 spidclk early \r\n"
"2: 2 spidclk early\r\n"
"3: 3 spidclk early\r\n"
"4: 4 spidclk early\r\n"
"4+: Illegal"},
#else
{8, 10, 0x0000000000000000, "RW", "earlyrdvld", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdcmd2rdvld", "This is the read command to read valid register.\r\n"
"This is in terms of spidclk."},
#else
{0, 5, 0x0000000000000000, "RW", "rdcmd2rdvld", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo360[] = {{"RDVLDCTL", "", 0x00000028, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields361[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{14, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "dqx_rk2rkswitch_dlyen", "Adds an extra 1x clock of delay between rdptr freeze and dq/dqs PI code change during write based rk2rk switch.\r\n"
"1: Add 1 extra ref1xclk of delay \r\n"
"0: No delay"},
#else
{13, 13, 0x0000000000000000, "RW", "dqx_rk2rkswitch_dlyen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "rcv_rk2rkswitch_dlyen", "Adds an extra 1x clock of delay between rdptr freeze and rcven PI code change during read based rk2rk switch.\r\n"
"1: Add 1 extra ref1xclk of delay \r\n"
"0: No delay"},
#else
{12, 12, 0x0000000000000000, "RW", "rcv_rk2rkswitch_dlyen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_iodrven", "Adds an extra 2x clock of delay between rdptr freeze and dq/dqs drive enable override during write based rk2rk switch.\r\n"
"1: Add 1 extra 2xclk of delay\r\n"
"0: No delay"},
#else
{10, 10, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_iodrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrden", "Adds an extra 2x clock of delay between rdptr freeze and rcven override assertion during read based rk2rk switch.\r\n"
"1: Add 1 extra 2xclk of delay \r\n"
"0: No delay"},
#else
{9, 9, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrcven", "Adds an extra clock of delay between rdptr freeze and rcven/rxodten pushout code change during read based rk2rk switch.\r\n"
"1: Add 1 extra 2xclk of delay \r\n"
"0: No delay\r\n"
"\r\n"
"This is applicable for rcven coarse/fine/dbsel/2xrdptroffset and rxodten 2xrdptroffset"},
#else
{8, 8, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrcven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "cc_rk2rken_txdqs_pi", "Rank to Rank switch enable for BL1 tx dqs\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{7, 7, 0x0000000000000000, "RW", "cc_rk2rken_txdqs_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "cc_rk2rken_txdq_pi", "Rank to Rank switch enable for Bl1 tx dq\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{6, 6, 0x0000000000000000, "RW", "cc_rk2rken_txdq_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "bl_rk2rken_txdqs_pi", "Rank to Rank switch enable for BL0 tx dqs\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{5, 5, 0x0000000000000000, "RW", "bl_rk2rken_txdqs_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "bl_rk2rken_txdq_pi", "Rank to Rank switch enable for BL0 tx dq\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{4, 4, 0x0000000000000000, "RW", "bl_rk2rken_txdq_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "cc_rk2rken_rxdq_pi", "Rank to Rank switch enable for BL1 rx dqs\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{3, 3, 0x0000000000000000, "RW", "cc_rk2rken_rxdq_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "cc_rk2rken_txrcven", "Rank to Rank switch enable for BL1 rcven\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{2, 2, 0x0000000000000000, "RW", "cc_rk2rken_txrcven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "bl_rk2rken_rxdq_pi", "Rank to Rank switch enable for BL0 rx dqs\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{1, 1, 0x0000000000000000, "RW", "bl_rk2rken_rxdq_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "bl_rk2rken_txrcven", "Rank to Rank switch enable for BL0 rcven\r\n"
"0 : Disable rk2rk switch\r\n"
"1 : Disable rk2rk switch"},
#else
{0, 0, 0x0000000000000000, "RW", "bl_rk2rken_txrcven", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo361[] = {{"RK2RKCTL1", "", 0x0000002C, 15, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields362[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rk2rkdrvenbcode_3rd", "Length of dq/dqs drv enable override during write based rk2rk switching. This, along with preamble and postamble \r\n"
"setting, contributes to the total length of the dq/dqs drv enable override during rk2rk switching.\r\n"
"This is in ref1xclks."},
#else
{28, 31, 0x0000000000000000, "RW", "rk2rkdrvenbcode_3rd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rk2rkrdencode_3rd", "Length of rcven override during read based rk2rk switching. This, along with preamble and postamble setting, \r\n"
"contributes to the total length of the rcven override during rk2rk switching.\r\n"
"This is in ref1xclks."},
#else
{24, 27, 0x0000000000000000, "RW", "rk2rkrdencode_3rd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_rxdq", "Adds an extra clock of delay between rcven override and Rx DQS DLL pushout code change during read based rk2rk switch.\r\n"
"1: Add 1 extra 2xclk of delay \r\n"
"0: No delay\r\n"
"\r\n"
"This is applicable for Rx DLL DQS HI/LO fine/coarse."},
#else
{23, 23, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_rxdq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdqs", "Adds an extra clock of delay between rdptr freeze and DQS data/ DQS drive enable pushout code change during write based rk2rk switch.\r\n"
"1: Add 1 extra 2xclk of delay \r\n"
"0: No delay\r\n"
"\r\n"
"This is applicable for dqs coarse/fine/dbsel/2xrdptroffset and dqs second rdport's 2xrdptroffset"},
#else
{22, 22, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdq", "Adds an extra clock of delay between rdptr freeze and DQ data/DQ drive enable pushout code change during write based rk2rk switch.\r\n"
"1: Add 1 extra 2xclk of delay \r\n"
"0: No delay\r\n"
"\r\n"
"This is applicable for dq data's and dq drive enable's coarse/fine/dbsel/2xrdptroffset and also their second rdport's 2xrdptroffset"},
#else
{21, 21, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "wrcmd2rkchglatency", "Delay between spid wrcmd (that requires a rank switch) and rank change detection logic.\r\n"
"This is in terms of ref1xclks."},
#else
{15, 20, 0x0000000000000000, "RW", "wrcmd2rkchglatency", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{14, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "rdcmd2rkchglatency", "Delay between spid rdcmd (that requires a rank switch) and rank change detection logic.\r\n"
"This is in terms of ref1xclks."},
#else
{8, 13, 0x0000000000000000, "RW", "rdcmd2rkchglatency", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "rk2rkdrvenbcode_2nd", "Postamble setting for dq/dqs drv enable override during rk2rk switching\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1 (illegal)\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 \r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{6, 7, 0x0000000000000000, "RW", "rk2rkdrvenbcode_2nd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rk2rkdrvenbcode_1st", "Preamble setting for dq/dqs drv enable override during rk2rk switching\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1 (illegal)\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 \r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{4, 5, 0x0000000000000000, "RW", "rk2rkdrvenbcode_1st", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rk2rkrdencode_2nd", "Postamble setting for rcven override during rk2rk switching\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1 (illegal)\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 \r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{2, 3, 0x0000000000000000, "RW", "rk2rkrdencode_2nd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "rk2rkrdencode_1st", "Preamble setting for rcven override during rk2rk switching\r\n"
"00 : Drive 0 for UI0, Drive 0 for UI1\r\n"
"01 : Drive 1 for UI0, Drive 0 for UI1 (illegal)\r\n"
"10 : Drive 0 for UI0, Drive 1 for UI1 \r\n"
"11 : Drive 1 for UI0, Drive 1 for UI1"},
#else
{0, 1, 0x0000000000000000, "RW", "rk2rkrdencode_1st", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo362[] = {{"RK2RKCTL0", "", 0x00000030, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields363[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RW", "cc_rxodtsegovrval", "Receive ODT segment enable override value."},
#else
{29, 31, 0x0000000000000000, "RW", "cc_rxodtsegovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "cc_rxodtsegovrsel", "Receive ODT segment enable override select.\r\n"
"0= Dynamic  control\r\n"
"1= Static  control"},
#else
{28, 28, 0x0000000000000000, "RW", "cc_rxodtsegovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 27, 0x0000000000000000, "RW", "rk1_odtsegenrdptroffset", "Receive ODT segment enable read pointer offset."},
#else
{23, 27, 0x0000000000000000, "RW", "rk1_odtsegenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 22, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "cc_rxodtsegtwohot", "This is the RXODTSEGEN one hot enable\r\n"
"0- rxodtsegen: 001->010->100\r\n"
"1-rxodtsegen: 011->110->101"},
#else
{21, 21, 0x0000000000000000, "RW", "cc_rxodtsegtwohot", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "cc_rxodtseglenbl4", "This is the receive ODT segment enable length configuration register.\r\n"
"It's in number of 1x clocks."},
#else
{15, 20, 0x0000000000000000, "RW", "cc_rxodtseglenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "cc_rxodtsegpst1", "This is the receive ODT segment enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{13, 14, 0x0000000000000000, "RW", "cc_rxodtsegpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000000, "RW", "cc_rxodtsegpre1", "This is the receive ODT segment enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{11, 12, 0x0000000000000000, "RW", "cc_rxodtsegpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "cc_rxodtsegpst0", "This is the receive ODT segment enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{9, 10, 0x0000000000000000, "RW", "cc_rxodtsegpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "cc_rxodtsegpre0", "This is the receive ODT segment enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{7, 8, 0x0000000000000000, "RW", "cc_rxodtsegpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2rxodtseg", "This is the receive ODT segment enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2rxodtseg", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo363[] = {{"RXODTSEGCTL_BL13", "", 0x00000034, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields364[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RW", "bl_rxodtsegovrval", "Receive ODT segment enable override value. \r\n"
"0: De-assert receive ODT enable \r\n"
"1: Assert receive ODT enable"},
#else
{29, 31, 0x0000000000000000, "RW", "bl_rxodtsegovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "bl_rxodtsegovrsel", "Receive ODT segment enable override select.\r\n"
"0= Dynamic  receive ODT control\r\n"
"1= Static  receive ODT control"},
#else
{28, 28, 0x0000000000000000, "RW", "bl_rxodtsegovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 27, 0x0000000000000000, "RW", "rk0_odtsegenrdptroffset", "Receive ODT segment enable read pointer offset."},
#else
{23, 27, 0x0000000000000000, "RW", "rk0_odtsegenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "reserved", "Reseved bits"},
#else
{22, 22, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "bl_rxodtsegtwohot", "This is the RXODTSEGEN one hot enable\r\n"
"0- rxodtsegen: 001->010->100\r\n"
"1-rxodtsegen: 011->110->101"},
#else
{21, 21, 0x0000000000000000, "RW", "bl_rxodtsegtwohot", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "bl_rxodtseglenbl4", "This is the receive ODT segment enable length configuration register.\r\n"
"It's in number of 1x clocks."},
#else
{15, 20, 0x0000000000000000, "RW", "bl_rxodtseglenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "bl_rxodtsegpst1", "This is the receive ODT segment enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{13, 14, 0x0000000000000000, "RW", "bl_rxodtsegpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000000, "RW", "bl_rxodtsegpre1", "This is the receive ODT segment enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{11, 12, 0x0000000000000000, "RW", "bl_rxodtsegpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "bl_rxodtsegpst0", "This is the receive ODT segment enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{9, 10, 0x0000000000000000, "RW", "bl_rxodtsegpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "bl_rxodtsegpre0", "This is the receive ODT segment enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{7, 8, 0x0000000000000000, "RW", "bl_rxodtsegpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2rxodtseg", "This is the receive ODT segment enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2rxodtseg", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo364[] = {{"RXODTSEGCTL_BL02", "", 0x00000038, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields365[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RW", "rk1_odtenrdptroffset", "This is receive ODT enable read pointer offset."},
#else
{27, 31, 0x0000000000000000, "RW", "rk1_odtenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "cc_dqsrxodtenovrval", "Rx DQS odt enable override value - DQ BL1 lane \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{26, 26, 0x0000000000000000, "RW", "cc_dqsrxodtenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "cc_dqsrxodtenovrsel", "Rx DQS odt enable override select- DQ BL1 lane \r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{25, 25, 0x0000000000000000, "RW", "cc_dqsrxodtenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "cc_rxodtenovrval", "Receive ODT enable override value. \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{24, 24, 0x0000000000000000, "RW", "cc_rxodtenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "cc_rxodtenovrsel", "Receive ODT enable override select.\r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{23, 23, 0x0000000000000000, "RW", "cc_rxodtenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 22, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "cc_rxodtenlenbl4", "This is the receive ODT enable length configuration register.\r\n"
"It's in number of 1x clocks."},
#else
{15, 20, 0x0000000000000000, "RW", "cc_rxodtenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "cc_rxodtenpst1", "This is the receive ODT enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{13, 14, 0x0000000000000000, "RW", "cc_rxodtenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000000, "RW", "cc_rxodtenpre1", "This is the receive ODT enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{11, 12, 0x0000000000000000, "RW", "cc_rxodtenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "cc_rxodtenpst0", "This is the receive ODT enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{9, 10, 0x0000000000000000, "RW", "cc_rxodtenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "cc_rxodtenpre0", "This is the receive ODT enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{7, 8, 0x0000000000000000, "RW", "cc_rxodtenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2rxodten", "This is the receive ODT enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2rxodten", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo365[] = {{"RXODTCTL_BL13", "", 0x0000003C, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields366[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RW", "rk0_odtenrdptroffset", "This is receive ODT enable read pointer offset."},
#else
{27, 31, 0x0000000000000000, "RW", "rk0_odtenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "bl_dqsrxodtenovrval", "Rx DQS odt enable override value - DQ BL0 lane \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{26, 26, 0x0000000000000000, "RW", "bl_dqsrxodtenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "bl_dqsrxodtenovrsel", "Rx DQS odt enable override select- DQ BL0 lane \r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{25, 25, 0x0000000000000000, "RW", "bl_dqsrxodtenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "bl_rxodtenovrval", "Receive ODT enable override value. \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{24, 24, 0x0000000000000000, "RW", "bl_rxodtenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "bl_rxodtenovrsel", "Receive ODT enable override select.\r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{23, 23, 0x0000000000000000, "RW", "bl_rxodtenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 22, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "bl_rxodtenlenbl4", "This is the receive ODT enable length configuration register.\r\n"
"It's in number of 1x clocks."},
#else
{15, 20, 0x0000000000000000, "RW", "bl_rxodtenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "bl_rxodtenpst1", "This is the receive ODT enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{13, 14, 0x0000000000000000, "RW", "bl_rxodtenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000000, "RW", "bl_rxodtenpre1", "This is the receive ODT enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{11, 12, 0x0000000000000000, "RW", "bl_rxodtenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "bl_rxodtenpst0", "This is the receive ODT enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{9, 10, 0x0000000000000000, "RW", "bl_rxodtenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "bl_rxodtenpre0", "This is the receive ODT enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{7, 8, 0x0000000000000000, "RW", "bl_rxodtenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2rxodten", "This is the receive ODT enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2rxodten", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo366[] = {{"RXODTCTL_DQ", "", 0x00000040, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields367[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "drx_cc_rcvsmpl", "AFE status register - RCVSMPL - CC"},
#else
{31, 31, 0x0000000000000000, "RO", "drx_cc_rcvsmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 30, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "drx_cc_rcvenflopbypass", "DQS counter flop override"},
#else
{28, 28, 0x0000000000000000, "RW", "drx_cc_rcvenflopbypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "drx_cc_dqscountrstb", "DQS counter reset"},
#else
{27, 27, 0x0000000000000000, "RW", "drx_cc_dqscountrstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "cc_rcvenmargin", "Receive enable margining data"},
#else
{26, 26, 0x0000000000000000, "RW", "cc_rcvenmargin", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "cc_rcvenovrval", "Receive enable override value. \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{25, 25, 0x0000000000000000, "RW", "cc_rcvenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "cc_rcvenovrsel", "Receive enable override select.\r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{24, 24, 0x0000000000000000, "RW", "cc_rcvenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "cc_rcvenlenbl4", "This is the receive enable length(number of 1x clock) configuration register."},
#else
{16, 21, 0x0000000000000000, "RW", "cc_rcvenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "cc_rcvenpst1", "This is the receive enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{14, 15, 0x0000000000000000, "RW", "cc_rcvenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "cc_rcvenpre1", "This is the receive enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{12, 13, 0x0000000000000000, "RW", "cc_rcvenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "cc_rcvenpst0", "This is the receive enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{10, 11, 0x0000000000000000, "RW", "cc_rcvenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "cc_rcvenpre0", "This is the receive enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{8, 9, 0x0000000000000000, "RW", "cc_rcvenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2rcven", "This is the receive enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2rcven", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo367[] = {{"RCVENCTL_BL13", "", 0x00000044, 15, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields368[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "drx_bl_rcvsmpl", "AFE status register - RCVSMPL - DQ"},
#else
{31, 31, 0x0000000000000000, "RO", "drx_bl_rcvsmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 30, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "drx_bl_rcvenflopbypass", "DQS counter flop override"},
#else
{28, 28, 0x0000000000000000, "RW", "drx_bl_rcvenflopbypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "drx_bl_dqscountrstb", "DQS counter reset"},
#else
{27, 27, 0x0000000000000000, "RW", "drx_bl_dqscountrstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "bl_rcvenmargin", "Receive enable margining data"},
#else
{26, 26, 0x0000000000000000, "RW", "bl_rcvenmargin", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "bl_rcvenovrval", "Receive enable override value. \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{25, 25, 0x0000000000000000, "RW", "bl_rcvenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "bl_rcvenovrsel", "Receive enable override select.\r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{24, 24, 0x0000000000000000, "RW", "bl_rcvenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "bl_rcvenlenbl4", "This is the receive enable length(number of 1x clock) configuration register."},
#else
{16, 21, 0x0000000000000000, "RW", "bl_rcvenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "bl_rcvenpst1", "This is the receive enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{14, 15, 0x0000000000000000, "RW", "bl_rcvenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "bl_rcvenpre1", "This is the receive enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{12, 13, 0x0000000000000000, "RW", "bl_rcvenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "bl_rcvenpst0", "This is the receive enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{10, 11, 0x0000000000000000, "RW", "bl_rcvenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "bl_rcvenpre0", "This is the receive enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{8, 9, 0x0000000000000000, "RW", "bl_rcvenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2rcven", "This is the receive enable latency configuration register.\r\n"
"RL - 1: maps to DRAM RL."},
#else
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2rcven", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo368[] = {{"RCVENCTL_BL02", "", 0x00000048, 15, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields369[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RW", "rk1_diffampenrdptroffset", "Differential amplifier read pointer offset control."},
#else
{27, 31, 0x0000000000000000, "RW", "rk1_diffampenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "cc_dqsdiffampenovrval", "Override value for DQS Diffamp enable - DQ Lane"},
#else
{26, 26, 0x0000000000000000, "RW", "cc_dqsdiffampenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "cc_dqsdiffampenovrsel", "Override select for DQS Diffamp enable - DQ Lane"},
#else
{25, 25, 0x0000000000000000, "RW", "cc_dqsdiffampenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "cc_dqdmdiffampenovrval", "Override value for DQ/DM Diffamp enable - DQ Lane"},
#else
{24, 24, 0x0000000000000000, "RW", "cc_dqdmdiffampenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "cc_dqdmdiffampenovrsel", "Override select for DQ/DM Diffamp enable - DQ Lane"},
#else
{23, 23, 0x0000000000000000, "RW", "cc_dqdmdiffampenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "cc_diffampenpst1", "This is the diffamp enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{21, 22, 0x0000000000000000, "RW", "cc_diffampenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW", "cc_diffampenpre1", "This is the diffamp enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{19, 20, 0x0000000000000000, "RW", "cc_diffampenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 18, 0x0000000000000000, "RW", "cc_diffampenpst0", "This is the diffamp enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{17, 18, 0x0000000000000000, "RW", "cc_diffampenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 16, 0x0000000000000000, "RW", "cc_diffampenpre0", "This is the diffamp enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{15, 16, 0x0000000000000000, "RW", "cc_diffampenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 12, 0x0000000000000000, "RW", "cc_diffampenlenbl4", "This is the diffamp enable length(number of 1x clock) configuration register."},
#else
{7, 12, 0x0000000000000000, "RW", "cc_diffampenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2diffampen", "This is the Diffamp enable latency register."},
#else
{0, 5, 0x0000000000000000, "RW", "cc_rdcmd2diffampen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo369[] = {{"DIFFAMPCTL_BL13", "", 0x0000004C, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields370[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RW", "rk0_diffampenrdptroffset", "Differential amplifier read pointer offset control."},
#else
{27, 31, 0x0000000000000000, "RW", "rk0_diffampenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "bl_dqsdiffampenovrval", "Override value for DQS Diffamp enable - DQ Lane"},
#else
{26, 26, 0x0000000000000000, "RW", "bl_dqsdiffampenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "bl_dqsdiffampenovrsel", "Override select for DQS Diffamp enable - DQ Lane"},
#else
{25, 25, 0x0000000000000000, "RW", "bl_dqsdiffampenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "bl_dqdmdiffampenovrval", "Override value for DQ/DM Diffamp enable - DQ Lane"},
#else
{24, 24, 0x0000000000000000, "RW", "bl_dqdmdiffampenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "bl_dqdmdiffampenovrsel", "Override select for DQ/DM Diffamp enable - DQ Lane"},
#else
{23, 23, 0x0000000000000000, "RW", "bl_dqdmdiffampenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "bl_diffampenpst1", "This is the diffamp enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{21, 22, 0x0000000000000000, "RW", "bl_diffampenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW", "bl_diffampenpre1", "This is the diffamp enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{19, 20, 0x0000000000000000, "RW", "bl_diffampenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 18, 0x0000000000000000, "RW", "bl_diffampenpst0", "This is the diffamp enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{17, 18, 0x0000000000000000, "RW", "bl_diffampenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 16, 0x0000000000000000, "RW", "bl_diffampenpre0", "This is the diffamp enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{15, 16, 0x0000000000000000, "RW", "bl_diffampenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 12, 0x0000000000000000, "RW", "bl_diffampenlenbl4", "This is the diffamp enable length(number of 1x clock) configuration register."},
#else
{7, 12, 0x0000000000000000, "RW", "bl_diffampenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2diffampen", "This is the Diffamp enable latency register."},
#else
{0, 5, 0x0000000000000000, "RW", "bl_rdcmd2diffampen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo370[] = {{"DIFFAMPCTL_BL02", "", 0x00000050, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields371[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{26, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "cc_wrlvl", "Write Levelization enable - DQ 1/3 Byte Lane"},
#else
{25, 25, 0x0000000000000000, "RW", "cc_wrlvl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "bl_wrlvl", "Write Levelization enable - DQ 0/2 Byte Lane"},
#else
{24, 24, 0x0000000000000000, "RW", "bl_wrlvl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO", "wrlvl_sample_b1", "DQTRAINSTS - WRLVL sampling from all DQ bit lanes of Bytelane 1"},
#else
{16, 23, 0x0000000000000000, "RO", "wrlvl_sample_b1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "wrlvl_sample_b0", "DQTRAINSTS - WRLVL sampling from all DQ bit lanes of Bytelane 0"},
#else
{8, 15, 0x0000000000000000, "RO", "wrlvl_sample_b0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "wrlvl_and_sample_b1", "DQTRAINSTS - WRLVL Byte1 sample AND combination"},
#else
{3, 3, 0x0000000000000000, "RO", "wrlvl_and_sample_b1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO", "wrlvl_and_sample_b0", "DQTRAINSTS - WRLVL Byte0 sample AND combination"},
#else
{2, 2, 0x0000000000000000, "RO", "wrlvl_and_sample_b0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "wrlvl_or_sample_b1", "DQTRAINSTS - WRLVL Byte1 sample OR combination"},
#else
{1, 1, 0x0000000000000000, "RO", "wrlvl_or_sample_b1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "wrlvl_or_sample_b0", "DQTRAINSTS - WRLVL Byte0 sample OR combination"},
#else
{0, 0, 0x0000000000000000, "RO", "wrlvl_or_sample_b0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo371[] = {{"WRLVL", "", 0x00000054, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields372[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dynreadsiggrpen", "Enable Dynamic SIGGRP 2x clock control. \r\n"
"1= SIGGRPEN  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled SIGGRPEN"},
#else
{19, 19, 0x0000000000000000, "RW", "dynreadsiggrpen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dynreadref2xclken", "Enable Dynamic REF2XCLK control. \r\n"
"1= ref2xclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled REF2XCLKEN"},
#else
{18, 18, 0x0000000000000000, "RW", "dynreadref2xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dynreadref1xclken", "Enable Dynamic REF1XCLK control. \r\n"
"1= ref1xclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled REF1XCLKEN"},
#else
{17, 17, 0x0000000000000000, "RW", "dynreadref1xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynreadspidclken", "Enable Dynamic SPIDCLK control. \r\n"
"1= spidclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled SPIDCLKEN"},
#else
{16, 16, 0x0000000000000000, "RW", "dynreadspidclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "read_stoprden", "This is the delay in terms of clocks the dven is disabled before clock gated."},
#else
{12, 14, 0x0000000000000000, "RW", "read_stoprden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "read_startrden", "This is the delay in terms of clocks the drven is enabled, once wrcmd/rdcmd is received."},
#else
{8, 10, 0x0000000000000000, "RW", "read_startrden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "readclkgate_maxcntr", "IDLE timer counter max value for clock gating on rx . \r\n"
"Counter timeout based on last RDCMD received."},
#else
{0, 5, 0x000000000000003F, "RW", "readclkgate_maxcntr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo372[] = {{"CLKGATERDCTL", "", 0x00000058, 11, 0x00000000FFFFFFFF, 0x000000000000003F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields373[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dynwritesiggrpen", "Enable Dynamic SIGGRP 2x clock control (writes)\r\n"
"1= SIGGRPEN  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled SIGGRPEN"},
#else
{19, 19, 0x0000000000000000, "RW", "dynwritesiggrpen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dynwriteref2xclken", "Enable Dynamic REF2XCLK control  (writes)\r\n"
"1= ref2xclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled REF2XCLKEN"},
#else
{18, 18, 0x0000000000000000, "RW", "dynwriteref2xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dynwriteref1xclken", "Enable Dynamic REF1XCLK control  (writes)\r\n"
"1= ref1xclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled REF1XCLKEN"},
#else
{17, 17, 0x0000000000000000, "RW", "dynwriteref1xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynwritespidclken", "Enable Dynamic SPIDCLK control  (writes)\r\n"
"1= spidclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled SPIDCLKEN"},
#else
{16, 16, 0x0000000000000000, "RW", "dynwritespidclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "write_stopdrv", "This is the delay in terms of clocks the dven is disabled before clock gated."},
#else
{12, 14, 0x0000000000000000, "RW", "write_stopdrv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "write_startdrv", "This is the delay in terms of clocks the drven is enabled, once wrcmd/rdcmd is received."},
#else
{8, 10, 0x0000000000000000, "RW", "write_startdrv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "writeclkgate_maxcntr", "IDLE timer counter max value for clock gating on tx . \r\n"
"Counter timeout based on last WRCMD received."},
#else
{0, 5, 0x000000000000003F, "RW", "writeclkgate_maxcntr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo373[] = {{"CLKGATEWRCTL", "", 0x0000005C, 11, 0x00000000FFFFFFFF, 0x000000000000003F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields374[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dynsiggrpen", "Enable Dynamic SIGGRP 2x clock control. 1= SIGGRPEN  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SIGGRPEN"},
#else
{19, 19, 0x0000000000000000, "RW", "dynsiggrpen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dynref2xclken", "Enable Dynamic REF2XCLK control. 1= ref2xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF2XCLKEN"},
#else
{18, 18, 0x0000000000000000, "RW", "dynref2xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dynref1xclken", "Enable Dynamic REF1XCLK control  (reads)\r\n"
"1= ref1xclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled REF1XCLKEN"},
#else
{17, 17, 0x0000000000000000, "RW", "dynref1xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynspidclken", "Enable Dynamic SPIDCLK control  (reads)\r\n"
"1= spidclken  controlled by the dynamic clock gating logic (DYNDLLFSM)\r\n"
"0= Statically-controlled SPIDCLKEN"},
#else
{16, 16, 0x0000000000000000, "RW", "dynspidclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "clkgate_maxcntr", "Clock Gating register : IDLE timer counter max value for clock gating on tx/rx . Counter timeout based on last WRCMD/RDCMD received. 6 bits are good enough since it increments in spidclk."},
#else
{0, 5, 0x000000000000003F, "RW", "clkgate_maxcntr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo374[] = {{"CLKGATECTL", "", 0x00000060, 7, 0x00000000FFFFFFFF, 0x000000000000003F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields375[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp05dbsel", "Deadband select for sig group 5 rank 1 maps to BL1 RCVEN"},
#else
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp05dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp05rdptroffset", "Read pointer offset for sig group 5 rank 1 maps to BL1 RCVEN"},
#else
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp05rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp05picode", "PI code for sig group 5 rank 1 maps to BL1 RCVEN"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp05picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp05dbsel", "Deadband select for sig group 5 rank 0 maps to BL1 RCVEN"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp05dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp05rdptroffset", "Read pointer offset for sig group 5 rank 0 maps to BL1 RCVEN"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp05rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp05picode", "PI code for sig group 5 rank 0 maps to BL1 RCVEN"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp05picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo375[] = {{"TXDLLSIGGRP5CTL", "", 0x00000064, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields376[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp04dbsel", "Deadband select for sig group 4 rank 1 maps to BL1 DQS"},
#else
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp04dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp04rdptroffset", "Read pointer offset for sig group 4 rank 1 maps to BL1 DQS"},
#else
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp04rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp04picode", "PI code for sig group 4 rank 1 maps to BL1 DQS"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp04picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp04dbsel", "Deadband select for sig group 4 rank 0 maps to BL1 DQS"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp04dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp04rdptroffset", "Read pointer offset for sig group 4 rank 0 maps to BL1 DQS"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp04rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp04picode", "PI code for sig group 4 rank 0 maps to BL1 DQS"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp04picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo376[] = {{"TXDLLSIGGRP4CTL", "", 0x00000068, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields377[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp03dbsel", "Deadband select for sig group 3 rank 1 maps to BL1 DQ"},
#else
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp03dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp03rdptroffset", "Read pointer offset for sig group 3 rank 1 maps to BL1 DQ"},
#else
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp03rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp03picode", "PI code for sig group 3 rank 1 maps to BL1 DQ"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp03picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp03dbsel", "Deadband select for sig group 3 rank 0 maps to BL1 DQ"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp03dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp03rdptroffset", "Read pointer offset for sig group 3 rank 0 maps to BL1 DQ"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp03rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp03picode", "PI code for sig group 3 rank 0 maps to BL1 DQ"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp03picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo377[] = {{"TXDLLSIGGRP3CTL", "", 0x0000006C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields378[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp02dbsel", "Deadband select for sig group 2 rank 1 maps to BL0 RCVEN"},
#else
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp02dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp02rdptroffset", "Read pointer offset for sig group 2 rank 1 maps to BL0 RCVEN"},
#else
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp02rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp02picode", "PI code for sig group 2 rank 1 maps to BL0 RCVEN"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp02picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp02dbsel", "Deadband select for sig group 2 rank 0 maps to BL0 RCVEN"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp02dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp02rdptroffset", "Read pointer offset for sig group 2 rank 0 maps to BL0 RCVEN"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp02rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp02picode", "PI code for sig group 2 rank 0 maps to BL0 RCVEN"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp02picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo378[] = {{"TXDLLSIGGRP2CTL", "", 0x00000070, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields379[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp01dbsel", "Deadband select for sig group 1 rank 1 maps to BL0 DQS"},
#else
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp01dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp01rdptroffset", "Read pointer offset for sig group 1 rank 1 maps to BL0 DQS"},
#else
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp01rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp01picode", "PI code for sig group 1 rank 1 maps to BL0 DQS"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp01picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp01dbsel", "Deadband select for sig group 1 rank 0 maps to BL0 DQS"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp01dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp01rdptroffset", "Read pointer offset for sig group 1 rank 0 maps to BL0 DQS"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp01rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp01picode", "PI code for sig group 1 rank 0 maps to BL0 DQS"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp01picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo379[] = {{"TXDLLSIGGRP1CTL", "", 0x00000074, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields380[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp00dbsel", "Deadband select for sig group 0 rank 1 maps to BL0 DQ"},
#else
{29, 30, 0x0000000000000000, "RW", "txdll_rk1siggrp00dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp00rdptroffset", "Read pointer offset for sig group 0 rank 1 maps to BL0 DQ"},
#else
{24, 28, 0x0000000000000000, "RW", "txdll_rk1siggrp00rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp00picode", "PI code for sig group 0 rank 1 maps to BL0 DQ"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_rk1siggrp00picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp00dbsel", "Deadband select for sig group 0 rank 0 maps to BL0 DQ"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp00dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp00rdptroffset", "Read pointer offset for sig group 0 rank 0 maps to BL0 DQ"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp00rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp00picode", "PI code for sig group 0 rank 0 maps to BL0 DQ"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp00picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo380[] = {{"TXDLLSIGGRP0CTL", "", 0x00000078, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields381[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "lvl_cc_weakpupstatic", "Weak Pull Up Control static bit for DQSB - DQ ByteLane 1/3"},
#else
{30, 30, 0x0000000000000000, "RW", "lvl_cc_weakpupstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "lvl_cc_weakpup", "Weak Pull Up Control code for DQSB - DQ ByteLane 1/3"},
#else
{24, 29, 0x0000000000000000, "RW", "lvl_cc_weakpup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "lvl_cc_weakpdnstatic", "Weak Pull Down Control static bit for DQS - DQ ByteLane 1/3"},
#else
{22, 22, 0x0000000000000000, "RW", "lvl_cc_weakpdnstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "lvl_cc_weakpdn", "Weak Pull Down Control code for DQS - DQ ByteLane 1/3"},
#else
{16, 21, 0x0000000000000000, "RW", "lvl_cc_weakpdn", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "lvl_bl_weakpupstatic", "Weak Pull Up Control static bit for DQSB - DQ ByteLane 0/2"},
#else
{14, 14, 0x0000000000000000, "RW", "lvl_bl_weakpupstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "lvl_bl_weakpup", "Weak Pull Up Control code for DQSB - DQ ByteLane 0/2"},
#else
{8, 13, 0x0000000000000000, "RW", "lvl_bl_weakpup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "lvl_bl_weakpdnstatic", "Weak Pull Down Control static bit for DQS - DQ ByteLane 0/2"},
#else
{6, 6, 0x0000000000000000, "RW", "lvl_bl_weakpdnstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lvl_bl_weakpdn", "Weak Pull Down Control code for DQS - DQ ByteLane 0/2"},
#else
{0, 5, 0x0000000000000000, "RW", "lvl_bl_weakpdn", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo381[] = {{"WKPUPPDNCTL", "", 0x0000007C, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields382[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "rx_modelp4ddr4", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - Common for all byte Lanes"},
#else
{31, 31, 0x0000000000000000, "RW", "rx_modelp4ddr4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000007, "RW", "dtx_cc_drvsegen", "Segment enable for BL 1/3 DQS buffer. Used for per leg testing in HVM"},
#else
{28, 30, 0x0000000000000007, "RW", "dtx_cc_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "tx_bl1_idlemode", "Disable idle mode logic = 1'b0, Enable = 1'b1 - BL1"},
#else
{27, 27, 0x0000000000000000, "RW", "tx_bl1_idlemode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000007, "RW", "tx_cc_drvsegen", "Segment enable for BL 1/3 DQ buffer. Used for per leg testing in HVM"},
#else
{24, 26, 0x0000000000000007, "RW", "tx_cc_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "tx_bl1_techselect", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - BL1"},
#else
{23, 23, 0x0000000000000000, "RW", "tx_bl1_techselect", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000007, "RW", "dtx_bl_drvsegen", "Segment enable for BL 0/2 DQS buffer. Used for per leg testing in HVM"},
#else
{20, 22, 0x0000000000000007, "RW", "dtx_bl_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "tx_bl0_idlemode", "Disable idle mode logic = 1'b0, Enable = 1'b1 - BL0"},
#else
{19, 19, 0x0000000000000000, "RW", "tx_bl0_idlemode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000007, "RW", "tx_bl_drvsegen", "Segment enable for BL 0/2 DQ buffer. Used for per leg testing in HVM"},
#else
{16, 18, 0x0000000000000007, "RW", "tx_bl_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "drx_cc_dqsnegedgemask", "masking out the first dqs negedge during rcven handling in ddr4 (0-ddr4;1-ddr3l,lp3/4)"},
#else
{15, 15, 0x0000000000000000, "RW", "drx_cc_dqsnegedgemask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000001, "RW", "rxdll_cc_picapsel", "set cap tuning for RxDLL BL 1/3 pi"},
#else
{12, 14, 0x0000000000000001, "RW", "rxdll_cc_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "drx_bl_dqsnegedgemask", "masking out the first dqs negedge during rcven handling in ddr4 (0-ddr4;1-ddr3l,lp3/4)"},
#else
{11, 11, 0x0000000000000000, "RW", "drx_bl_dqsnegedgemask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000001, "RW", "rxdll_bl_picapsel", "set cap tuning for RxDLL BL 0/2 pi"},
#else
{8, 10, 0x0000000000000001, "RW", "rxdll_bl_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "tx_bl0_techselect", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - BL0"},
#else
{7, 7, 0x0000000000000000, "RW", "tx_bl0_techselect", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000001, "RW", "txdll_picapsel", "set cap tuning for pi"},
#else
{4, 6, 0x0000000000000001, "RW", "txdll_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "dtx_cc_allfire", "Config Register space has been reallocated for RxBIASEN ECO HSD#1404029255\r\n"
"Override select for Rx bias enable - BL1 Lane"},
#else
{3, 3, 0x0000000000000000, "RW", "dtx_cc_allfire", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "dtx_bl_allfire", "Config Register space has been reallocated for RxBIASEN ECO HSD#1404029255\r\n"
"Override select for Rx bias enable - BL0 Lane"},
#else
{2, 2, 0x0000000000000000, "RW", "dtx_bl_allfire", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "tx_cc_allfire", "Config Register space has been reallocated for RxBIASEN ECO HSD#1404029255\r\n"
"Override value  for Rx bias enable - BL1 Lane"},
#else
{1, 1, 0x0000000000000000, "RW", "tx_cc_allfire", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "tx_bl_allfire", "Config Register space has been reallocated for RxBIASEN ECO HSD#1404029255\r\n"
"Override value for Rx bias enable - BL0 Lane"},
#else
{0, 0, 0x0000000000000000, "RW", "tx_bl_allfire", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo382[] = {{"AFEMISC1", "", 0x00000080, 18, 0x00000000FFFFFFFF, 0x0000000077771110}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields383[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "dtx_cc_drvenstretch", "Streches rising edge of drivenable to relax data to enable skew for BL 1/3 DQS Buffer."},
#else
{30, 31, 0x0000000000000000, "RW", "dtx_cc_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "dtx_bl_drvenstretch", "Streches rising edge of drivenable to relax data to enable skew for BL 0/2 DQS Buffer."},
#else
{28, 29, 0x0000000000000000, "RW", "dtx_bl_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "tx_cc_drvenstretch", "Streches rising edge of drivenable to relax data to enable skew for BL 1/3 DQ Buffer."},
#else
{26, 27, 0x0000000000000000, "RW", "tx_cc_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "tx_bl_drvenstretch", "Streches rising edge of drivenable to relax data to enable skew for BL 0/2 DQ Buffer."},
#else
{24, 25, 0x0000000000000000, "RW", "tx_bl_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "drx_cc_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{22, 23, 0x0000000000000000, "RW", "drx_cc_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "rx_cc_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{20, 21, 0x0000000000000000, "RW", "rx_cc_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "drx_bl_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{18, 19, 0x0000000000000000, "RW", "drx_bl_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rx_bl_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{16, 17, 0x0000000000000000, "RW", "rx_bl_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "txdll_2xclkskewsel", "TxDLL Skew Compensator clock mux select (Clock Select [1:0]/Sync Div Reset[3:2])\r\n"
"Below select descriptions apply to both clock and div reset but each one can be controlled independently\r\n"
"00 - Default path - No addditional Skew added\r\n"
"01 - Skew Path 1 - Add ~30-40ps of delay to TxDLL 2xclk input based on PVT\r\n"
"11 - Skew Path 2 - Add ~90-100ps of delay to TxDLL 2xclk input based on PVT"},
#else
{12, 15, 0x0000000000000000, "RW", "txdll_2xclkskewsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000001, "RW", "drx_cc_rxcommonmode", "changes the common mode of receiver  for BL 1/3 DQS Buffer from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{11, 11, 0x0000000000000001, "RW", "drx_cc_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000001, "RW", "drx_bl_rxcommonmode", "changes the common mode of receiver  for BL 0/2 DQS Buffer from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{10, 10, 0x0000000000000001, "RW", "drx_bl_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "rx_cc_rxcommonmode", "changes the common mode of receiver  for BL 1/3 DQ Buffer from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{9, 9, 0x0000000000000001, "RW", "rx_cc_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "rx_bl_rxcommonmode", "changes the common mode of receiver  for BL 0/2 DQ Buffer from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{8, 8, 0x0000000000000001, "RW", "rx_bl_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "pdndrvstatic", "Static pull down code - DRV DQ"},
#else
{7, 7, 0x0000000000000001, "RW", "pdndrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "pdndrvstaticdqs", "Static pull down code - DRV DQS/DQSB"},
#else
{6, 6, 0x0000000000000001, "RW", "pdndrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "pdnodtstatic", "Static pull down code - ODT DQ"},
#else
{5, 5, 0x0000000000000001, "RW", "pdnodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "pdnodtstaticdqs", "Static pull down code - ODT DQS/DQSB"},
#else
{4, 4, 0x0000000000000001, "RW", "pdnodtstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "pupdrvstatic", "Static pull up code - DRV DQ"},
#else
{3, 3, 0x0000000000000001, "RW", "pupdrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "pupdrvstaticdqs", "Static pull up code - DRV DQS/DQSB"},
#else
{2, 2, 0x0000000000000001, "RW", "pupdrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "pupodtstatic", "Static pull up code - ODT DQ"},
#else
{1, 1, 0x0000000000000001, "RW", "pupodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "pupodtstaticdqs", "Static pull up code - ODT DQS/DQSB"},
#else
{0, 0, 0x0000000000000001, "RW", "pupodtstaticdqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo383[] = {{"AFEMISC0", "", 0x00000084, 21, 0x00000000FFFFFFFF, 0x0000000000000FFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields384[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rx_bl0_bonus", "Bonus bits - RX BL 0/2 Lane"},
#else
{12, 15, 0x0000000000000000, "RW", "rx_bl0_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rx_bl1_bonus", "Bonus bits - RX BL 1/3 Lane"},
#else
{8, 11, 0x0000000000000000, "RW", "rx_bl1_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "lvl_cc_bonus", "Bonus bits - LVL BL 0/2 Lane"},
#else
{4, 7, 0x0000000000000000, "RW", "lvl_cc_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "lvl_bl_bonus", "Bonus bits - LVL BL 1/3 Lane"},
#else
{0, 3, 0x0000000000000000, "RW", "lvl_bl_bonus", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo384[] = {{"AFEBONUS", "", 0x00000088, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields385[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "txdll_digobs1sel", "Digital observation select mux port 1"},
#else
{28, 31, 0x0000000000000000, "RW", "txdll_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "txdll_digobs0sel", "Digital observation select mux port 0"},
#else
{24, 27, 0x0000000000000000, "RW", "txdll_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rxdll_cc_digobsen", "digital buf obs enable (1=enable;0=disable) for BL 1/3 RxDLL"},
#else
{23, 23, 0x0000000000000000, "RW", "rxdll_cc_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rxdll_bl_digobsen", "digital buf obs enable (1=enable;0=disable) for BL 0/2 RxDLL"},
#else
{22, 22, 0x0000000000000000, "RW", "rxdll_bl_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "dtx_cc_digobsen", "digital buf obs enable (1=enable;0=disable) for BL 1/3 DQS Buffer"},
#else
{21, 21, 0x0000000000000000, "RW", "dtx_cc_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 20, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "txdll_digobsen", "digital buf obs enable (1=enable;0=disable) for TxDLL"},
#else
{19, 19, 0x0000000000000000, "RW", "txdll_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dtx_bl_digobsen", "digital buf obs enable (1=enable;0=disable) for BL 0/2 DQS Buffer"},
#else
{18, 18, 0x0000000000000000, "RW", "dtx_bl_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rxdll_bl_digobs1sel", "Digital observation select mux port 1 for BL 0/2 RxDLL"},
#else
{12, 15, 0x0000000000000000, "RW", "rxdll_bl_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rxdll_bl_digobs0sel", "Digital observation select mux port 0 for BL 0/2 RxDLL"},
#else
{8, 11, 0x0000000000000000, "RW", "rxdll_bl_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rxdll_cc_digobs1sel", "Digital observation select mux port 1 for BL 1/3 RxDLL"},
#else
{4, 7, 0x0000000000000000, "RW", "rxdll_cc_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_cc_digobs0sel", "Digital observation select mux port 0 for BL 1/3 RxDLL"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_cc_digobs0sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo385[] = {{"DIGOBSCTL1", "", 0x0000008C, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields386[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "dqrx2monport_en", "DQ Post Rx FLOP to Digital MonPort Enable; 0 - DQRX to digital Monitor Port is disabled; 1 - DQRX Flop outputs routed to Digital Monitor Port"},
#else
{31, 31, 0x0000000000000000, "RW", "dqrx2monport_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "dtx_cc_digobs1sel", "Digital observation select mux port 1 for BL 1/3 DQS Buffer"},
#else
{28, 30, 0x0000000000000000, "RW", "dtx_cc_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "dtx_cc_digobs0sel", "Digital observation select mux port 0 for BL 1/3 DQS Buffer"},
#else
{24, 26, 0x0000000000000000, "RW", "dtx_cc_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000000, "RW", "dtx_bl_digobs1sel", "Digital observation select mux port 1 for BL 0/2 DQS Buffer"},
#else
{20, 22, 0x0000000000000000, "RW", "dtx_bl_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RW", "dtx_bl_digobs0sel", "Digital observation select mux port 0 for BL 0/2 DQS Buffer"},
#else
{16, 18, 0x0000000000000000, "RW", "dtx_bl_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "tx_cc_digobs1sel", "Digital observation select mux port 1 for BL 1/3 DQ Buffer"},
#else
{12, 14, 0x0000000000000000, "RW", "tx_cc_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "tx_cc_digobs0sel", "Digital observation select mux port 0 for BL 1/3 DQ Buffer"},
#else
{8, 10, 0x0000000000000000, "RW", "tx_cc_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "tx_bl_digobs1sel", "Digital observation select mux port 1 for BL 0/2 DQ Buffer"},
#else
{4, 6, 0x0000000000000000, "RW", "tx_bl_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "tx_bl_digobs0sel", "Digital observation select mux port 0 for BL 0/2 DQ Buffer"},
#else
{0, 2, 0x0000000000000000, "RW", "tx_bl_digobs0sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo386[] = {{"DIGOBSCTL0", "", 0x00000090, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields387[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "rxdll_rxmuxsel", "enable strobe output from rx sdll.for each byte"},
#else
{24, 28, 0x0000000000000000, "RW", "rxdll_rxmuxsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "txdll_dllfloprstb", "TxDLL flop reset"},
#else
{21, 21, 0x0000000000000000, "RW", "txdll_dllfloprstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "rxdll_dllfloprstb", "RxDLL flop reset"},
#else
{20, 20, 0x0000000000000000, "RW", "rxdll_dllfloprstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "rxdll_bl_dqsouten", "enable strobe output from rx sdll.for each byte"},
#else
{18, 18, 0x0000000000000000, "RW", "rxdll_bl_dqsouten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "rxdll_bl_rxdllen", "Rx DLL enable"},
#else
{16, 16, 0x0000000000000000, "RW", "rxdll_bl_rxdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo387[] = {{"RXDLLCTL_DQBLDM", "", 0x00000094, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields388[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{19, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "rxdll_cc_dqsouten", "enable strobe output from rx sdll.for each byte"},
#else
{18, 18, 0x0000000000000000, "RW", "rxdll_cc_dqsouten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "rxdll_cc_rxdllen", "Rx DLL enable"},
#else
{16, 16, 0x0000000000000000, "RW", "rxdll_cc_rxdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "txdll_ref2xph0pien", "enable tx ref pi phase 0 enable"},
#else
{0, 0, 0x0000000000000000, "RW", "txdll_ref2xph0pien", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo388[] = {{"RXDLLCTL_CCBLDM", "", 0x00000098, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields389[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{18, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{18, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "txdll_mdllen", "MDLL enable"},
#else
{16, 16, 0x0000000000000000, "RW", "txdll_mdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{14, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "txdll_siggrp05pien", "PI enable for sig group 5 rank 0"},
#else
{13, 13, 0x0000000000000000, "RW", "txdll_siggrp05pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "txdll_siggrp04pien", "PI enable for sig group 4 rank 0"},
#else
{12, 12, 0x0000000000000000, "RW", "txdll_siggrp04pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "txdll_siggrp03pien", "PI enable for sig group 3 rank 0"},
#else
{11, 11, 0x0000000000000000, "RW", "txdll_siggrp03pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "txdll_siggrp02pien", "PI enable for sig group 2 rank 0"},
#else
{10, 10, 0x0000000000000000, "RW", "txdll_siggrp02pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "txdll_siggrp01pien", "PI enable for sig group 1 rank 0"},
#else
{9, 9, 0x0000000000000000, "RW", "txdll_siggrp01pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "txdll_siggrp00pien", "PI enable for sig group 0 rank 0"},
#else
{8, 8, 0x0000000000000000, "RW", "txdll_siggrp00pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "txdll_ref2xph270pien", "enable tx ref pi phase 270 enable"},
#else
{3, 3, 0x0000000000000000, "RW", "txdll_ref2xph270pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "txdll_ref2xph180pien", "enable tx ref pi phase 180 enable"},
#else
{2, 2, 0x0000000000000000, "RW", "txdll_ref2xph180pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "txdll_ref2xph90pien", "enable tx ref pi phase 90 enable"},
#else
{1, 1, 0x0000000000000000, "RW", "txdll_ref2xph90pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 0, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo389[] = {{"TXDLLCTL", "", 0x0000009C, 15, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields390[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_ref2xph270picode", "pi code for ref pi phase 270 output"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_ref2xph270picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "txdll_ref2xph180picode", "pi code for ref pi phase 180 output"},
#else
{8, 15, 0x0000000000000000, "RW", "txdll_ref2xph180picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_ref2xph90picode", "pi code for ref pi phase 90 output"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_ref2xph90picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo390[] = {{"TXDLLREF2XCTL", "", 0x000000A0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields391[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "rxdll_bl_rk1dqshipicode", "Rank1 pi code for rx rising dqs edge - DQ 0/2 Lane"},
#else
{24, 31, 0x0000000000000000, "RW", "rxdll_bl_rk1dqshipicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "rxdll_bl_rk1dqslopicode", "Rank1 pi code for rx falling dqs edge - DQ 0/2 Lane"},
#else
{16, 23, 0x0000000000000000, "RW", "rxdll_bl_rk1dqslopicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "rxdll_cc_rk1dqshipicode", "Rank 1 pi code for rx rising dqs edge  - DQ 1/3 Lane"},
#else
{8, 15, 0x0000000000000000, "RW", "rxdll_cc_rk1dqshipicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "rxdll_cc_rk1dqslopicode", "Rank 1 pi code for rx falling dqs edge  - DQ 1/3 Lane"},
#else
{0, 7, 0x0000000000000000, "RW", "rxdll_cc_rk1dqslopicode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo391[] = {{"RXDLLDQSRK1CTL", "", 0x000000A4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields392[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "rxdll_bl_rk0dqshipicode", "Rank0 pi code for rx rising dqs edge  - DQ 0/2 Lane"},
#else
{24, 31, 0x0000000000000000, "RW", "rxdll_bl_rk0dqshipicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "rxdll_bl_rk0dqslopicode", "Rank0 pi code for rx falling dqs edge  - DQ 0/2 Lane"},
#else
{16, 23, 0x0000000000000000, "RW", "rxdll_bl_rk0dqslopicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "rxdll_cc_rk0dqshipicode", "Rank0 pi code for rx rising dqs edge  - DQ 1/3 Lane"},
#else
{8, 15, 0x0000000000000000, "RW", "rxdll_cc_rk0dqshipicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "rxdll_cc_rk0dqslopicode", "Rank0 pi code for rx falling dqs edge  - DQ 1/3 Lane"},
#else
{0, 7, 0x0000000000000000, "RW", "rxdll_cc_rk0dqslopicode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo392[] = {{"RXDLLDQSRK0CTL", "", 0x000000A8, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields393[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "txvref_cmn_vrefbufen", "enable signal for the tx vref unity gain buffer"},
#else
{0, 0, 0x0000000000000001, "RW", "txvref_cmn_vrefbufen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo393[] = {{"VREFCTL1", "", 0x000000AC, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields394[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "vref_txlcompvrefctrl", "vref decode signal for the lcomp"},
#else
{24, 31, 0x0000000000000000, "RW", "vref_txlcompvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "lvl_bl_vrefset", "vrefiobufact Set control - DQ BL0"},
#else
{23, 23, 0x0000000000000000, "RW", "lvl_bl_vrefset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "lvl_bl_vrefreset", "vrefiobufact Reset control - DQ BL0"},
#else
{22, 22, 0x0000000000000000, "RW", "lvl_bl_vrefreset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "lvl_cc_vrefset", "vrefiobufact Set control - DQ BL1"},
#else
{21, 21, 0x0000000000000000, "RW", "lvl_cc_vrefset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "lvl_cc_vrefreset", "vrefiobufact Reset control - DQ BL1"},
#else
{20, 20, 0x0000000000000000, "RW", "lvl_cc_vrefreset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{18, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "vref_vrefcmctrl", "common mode select to choose between lpddr3;lpddr4"},
#else
{16, 17, 0x0000000000000000, "RW", "vref_vrefcmctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000020, "RW", "vref_rxblvrefctrl", "vref decode signal for the b0/2 rx vref"},
#else
{8, 15, 0x0000000000000020, "RW", "vref_rxblvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000020, "RW", "vref_rxccvrefctrl", "vref decode signal for the b1/3 rx vref"},
#else
{0, 7, 0x0000000000000020, "RW", "vref_rxccvrefctrl", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo394[] = {{"VREFCTL0", "", 0x000000B0, 9, 0x00000000FFFFFFFF, 0x0000000000002020}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields395[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_cc_dq8rxpbdcode", "Rx Per bit De-skew code for BL 1/3 dbi valid codes"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_cc_dq8rxpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo395[] = {{"RXBL8PBDCTL1", "", 0x000000B4, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields396[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rxdll_cc_dq7rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq7 valid codes"},
#else
{28, 31, 0x0000000000000000, "RW", "rxdll_cc_dq7rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rxdll_cc_dq6rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq6 valid codes"},
#else
{24, 27, 0x0000000000000000, "RW", "rxdll_cc_dq6rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rxdll_cc_dq5rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq5 valid codes"},
#else
{20, 23, 0x0000000000000000, "RW", "rxdll_cc_dq5rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rxdll_cc_dq4rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq4 valid codes"},
#else
{16, 19, 0x0000000000000000, "RW", "rxdll_cc_dq4rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rxdll_cc_dq3rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq3 valid codes"},
#else
{12, 15, 0x0000000000000000, "RW", "rxdll_cc_dq3rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rxdll_cc_dq2rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq2 valid codes"},
#else
{8, 11, 0x0000000000000000, "RW", "rxdll_cc_dq2rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rxdll_cc_dq1rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq1 valid codes"},
#else
{4, 7, 0x0000000000000000, "RW", "rxdll_cc_dq1rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_cc_dq0rxpbdcode", "Rx Per bit De-skew code for BL1/3  dq0 valid codes"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_cc_dq0rxpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo396[] = {{"RXPBDBLCTL1", "", 0x000000B8, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields397[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_bl_dq8rxpbdcode", "Rx Per bit De-skew code for BL 0/2 dbi valid codes"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_bl_dq8rxpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo397[] = {{"RXBL8PBDCTL0", "", 0x000000BC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields398[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rxdll_bl_dq7rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq7 valid codes"},
#else
{28, 31, 0x0000000000000000, "RW", "rxdll_bl_dq7rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rxdll_bl_dq6rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq6 valid codes"},
#else
{24, 27, 0x0000000000000000, "RW", "rxdll_bl_dq6rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rxdll_bl_dq5rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq5 valid codes"},
#else
{20, 23, 0x0000000000000000, "RW", "rxdll_bl_dq5rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rxdll_bl_dq4rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq4 valid codes"},
#else
{16, 19, 0x0000000000000000, "RW", "rxdll_bl_dq4rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rxdll_bl_dq3rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq3 valid codes"},
#else
{12, 15, 0x0000000000000000, "RW", "rxdll_bl_dq3rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rxdll_bl_dq2rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq2 valid codes"},
#else
{8, 11, 0x0000000000000000, "RW", "rxdll_bl_dq2rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rxdll_bl_dq1rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq1 valid codes"},
#else
{4, 7, 0x0000000000000000, "RW", "rxdll_bl_dq1rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_bl_dq0rxpbdcode", "Rx Per bit De-skew code for BL0/2  dq0 valid codes"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_bl_dq0rxpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo398[] = {{"RXPBDBLCTL0", "", 0x000000C0, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields399[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rxdll_cc_rxpbden", "Rx Per Bit De-skew enable for BL1/3 (1=enable, 0=disable)"},
#else
{23, 23, 0x0000000000000000, "RW", "rxdll_cc_rxpbden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rxdll_bl_rxpbden", "Rx Per Bit De-skew enable for BL0/2 (1=enable, 0=disable)"},
#else
{22, 22, 0x0000000000000000, "RW", "rxdll_bl_rxpbden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 21, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 21, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "tx_cc_pbdstaticlegen", "Per bit deskew enable - TX - BL 1/3"},
#else
{3, 3, 0x0000000000000001, "RW", "tx_cc_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "tx_bl_pbdstaticlegen", "Per bit deskew enable - TX - BL 0/2"},
#else
{2, 2, 0x0000000000000001, "RW", "tx_bl_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "dtx_cc_pbdstaticlegen", "Per bit deskew enable - DTX - BL 1/3"},
#else
{1, 1, 0x0000000000000001, "RW", "dtx_cc_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "dtx_bl_pbdstaticlegen", "Per bit deskew enable - DTX - BL 0/2"},
#else
{0, 0, 0x0000000000000001, "RW", "dtx_bl_pbdstaticlegen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo399[] = {{"TXPBDCTL1", "", 0x000000C4, 8, 0x00000000FFFFFFFF, 0x000000000000000F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields400[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_ccdm_txpbdcode", "Tx Per Bit De-skew code for BL0/2 DM valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_ccdm_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "dtx_cc_dqsbpbdcode", "Tx Per Bit De-skew code for BL0/2 DQSB  valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "dtx_cc_dqsbpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "dtx_cc_dqspbdcode", "Tx Per Bit De-skew code for BL0/2 DQS  valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "dtx_cc_dqspbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo400[] = {{"TXPBDBLCTL5", "", 0x000000C8, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields401[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "tx_ccdq7_txpbdcode", "Tx Per Bit De-skew code for  BL0/2 dq7 valid codes"},
#else
{24, 28, 0x0000000000000000, "RW", "tx_ccdq7_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_ccdq6_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq6 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_ccdq6_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "tx_ccdq5_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq5 valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "tx_ccdq5_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_ccdq4_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq4 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_ccdq4_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo401[] = {{"TXPBDBLCTL4", "", 0x000000CC, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields402[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "tx_ccdq3_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq3 valid codes"},
#else
{24, 28, 0x0000000000000000, "RW", "tx_ccdq3_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_ccdq2_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq2 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_ccdq2_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "tx_ccdq1_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq1 valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "tx_ccdq1_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_ccdq0_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq0 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_ccdq0_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo402[] = {{"TXPBDBLCTL3", "", 0x000000D0, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields403[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_bldm_txpbdcode", "Tx Per Bit De-skew code for BL0/2 DM valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_bldm_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "dtx_bl_dqsbpbdcode", "Tx Per Bit De-skew code for BL0/2 DQSB  valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "dtx_bl_dqsbpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "dtx_bl_dqspbdcode", "Tx Per Bit De-skew code for BL0/2 DQS  valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "dtx_bl_dqspbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo403[] = {{"TXPBDBLCTL2", "", 0x000000D4, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields404[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "tx_bldq7_txpbdcode", "Tx Per Bit De-skew code for  BL0/2 dq7 valid codes"},
#else
{24, 28, 0x0000000000000000, "RW", "tx_bldq7_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_bldq6_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq6 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_bldq6_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "tx_bldq5_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq5 valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "tx_bldq5_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_bldq4_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq4 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_bldq4_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo404[] = {{"TXPBDBLCTL1", "", 0x000000D8, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields405[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "tx_bldq3_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq3 valid codes"},
#else
{24, 28, 0x0000000000000000, "RW", "tx_bldq3_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_bldq2_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq2 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_bldq2_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "tx_bldq1_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq1 valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "tx_bldq1_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_bldq0_txpbdcode", "Tx Per Bit De-skew code for BL0/2 dq0 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_bldq0_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo405[] = {{"TXPBDBLCTL0", "", 0x000000DC, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields406[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{10, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{10, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "drx_cc_ampoffseten", "Offset cancellation enable for Rx (not used for cc)"},
#else
{9, 9, 0x0000000000000001, "RW", "drx_cc_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "rx_cc_ampoffseten", "Offset cancellation enable for Rx (not used for cc)"},
#else
{8, 8, 0x0000000000000000, "RW", "rx_cc_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "drx_cc_ampoffset", "Offset cancellation code (DQS buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{4, 7, 0x0000000000000000, "RW", "drx_cc_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rx_ccdm_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{0, 3, 0x0000000000000000, "RW", "rx_ccdm_ampoffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo406[] = {{"OFFSETCNCLCTRL3", "", 0x000000E0, 5, 0x00000000FFFFFFFF, 0x0000000000000200}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields407[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rx_ccdq0_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{28, 31, 0x0000000000000000, "RW", "rx_ccdq0_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rx_ccdq1_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{24, 27, 0x0000000000000000, "RW", "rx_ccdq1_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rx_ccdq2_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{20, 23, 0x0000000000000000, "RW", "rx_ccdq2_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rx_ccdq3_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{16, 19, 0x0000000000000000, "RW", "rx_ccdq3_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rx_ccdq4_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{12, 15, 0x0000000000000000, "RW", "rx_ccdq4_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rx_ccdq5_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{8, 11, 0x0000000000000000, "RW", "rx_ccdq5_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rx_ccdq6_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{4, 7, 0x0000000000000000, "RW", "rx_ccdq6_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rx_ccdq7_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{0, 3, 0x0000000000000000, "RW", "rx_ccdq7_ampoffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo407[] = {{"OFFSETCNCLCTRL2", "", 0x000000E4, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields408[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{10, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{10, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "drx_bl_ampoffseten", "DQS Offset cancellation enable for Rx (1=enable, 0=disable)"},
#else
{9, 9, 0x0000000000000001, "RW", "drx_bl_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "rx_bl_ampoffseten", "DQ Offset cancellation enable for Rx (1=enable, 0=disable)"},
#else
{8, 8, 0x0000000000000000, "RW", "rx_bl_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "drx_bl_ampoffset", "Offset cancellation code (DQS buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{4, 7, 0x0000000000000000, "RW", "drx_bl_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rx_bldm_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{0, 3, 0x0000000000000000, "RW", "rx_bldm_ampoffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo408[] = {{"OFFSETCNCLCTRL1", "", 0x000000E8, 5, 0x00000000FFFFFFFF, 0x0000000000000200}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields409[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rx_bldq0_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{28, 31, 0x0000000000000000, "RW", "rx_bldq0_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rx_bldq1_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{24, 27, 0x0000000000000000, "RW", "rx_bldq1_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rx_bldq2_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{20, 23, 0x0000000000000000, "RW", "rx_bldq2_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rx_bldq3_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{16, 19, 0x0000000000000000, "RW", "rx_bldq3_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rx_bldq4_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{12, 15, 0x0000000000000000, "RW", "rx_bldq4_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rx_bldq5_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{8, 11, 0x0000000000000000, "RW", "rx_bldq5_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rx_bldq6_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{4, 7, 0x0000000000000000, "RW", "rx_bldq6_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rx_bldq7_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{0, 3, 0x0000000000000000, "RW", "rx_bldq7_ampoffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo409[] = {{"OFFSETCNCLCTRL0", "", 0x000000EC, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields410[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "rx_bl1_ctletune", "RX 1st Stage Amp CTLE Fine Tune - BL1"},
#else
{6, 7, 0x0000000000000000, "RW", "rx_bl1_ctletune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rx_bl1_ampcombtune", "RX 2nd Stage Amp Fine Tune - BL1"},
#else
{4, 5, 0x0000000000000000, "RW", "rx_bl1_ampcombtune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "drx_bl_casbiasctrl", "DRX Bias Command Control 00: Idle Mode Logic Disabled (LP3/4), Default Condition (DDR3L)   01: Idle Mode Logic Enabled (LP3/4), Illegal Condition (DDR3L)   10: Illegal Condition (ALL)   11: Illegal Condition (ALL)"},
#else
{2, 3, 0x0000000000000000, "RW", "drx_bl_casbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "drx_bl_nbiasctrl", "DRX N Bias Control - BL"},
#else
{0, 1, 0x0000000000000000, "RW", "drx_bl_nbiasctrl", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo410[] = {{"CTLECTL4", "", 0x000000F0, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields411[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000001, "RW", "drx_cc_ctleen", "Enable CTLE for DQS BL1/3(1=enable, 0=disable)"},
#else
{19, 19, 0x0000000000000001, "RW", "drx_cc_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000001, "RW", "drx_cc_biasen", "DRX Bias Enable - BL1/3"},
#else
{18, 18, 0x0000000000000001, "RW", "drx_cc_biasen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "drx_cc_casbiasctrl", "DRX Bias Command Control 00: Idle Mode Logic Disabled (LP3/4), Default Condition (DDR3L)   01: Idle Mode Logic Enabled (LP3/4), Illegal Condition (DDR3L)   10: Illegal Condition (ALL)   11: Illegal Condition (ALL)"},
#else
{16, 17, 0x0000000000000000, "RW", "drx_cc_casbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "drx_cc_nbiasctrl", "DRX N Bias Control - BL1/3"},
#else
{14, 15, 0x0000000000000000, "RW", "drx_cc_nbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 13, 0x0000000000000000, "RW", "drx_cc_ctlebiasctrl", "DRX Bias Ctle Control - BL1/3"},
#else
{11, 13, 0x0000000000000000, "RW", "drx_cc_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "drx_cc_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm for BL1/3"},
#else
{9, 10, 0x0000000000000000, "RW", "drx_cc_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000001, "RW", "drx_cc_ctlecap", "cap tuning;00 = 0.5pf;01 = 1pf;10 = 1.5pf;11 = 2pf for BL1/3"},
#else
{7, 8, 0x0000000000000001, "RW", "drx_cc_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "rx_cc_ctleen", "Enable CTLE for DQ BL1/3 (1=enable, 0=disable)"},
#else
{6, 6, 0x0000000000000001, "RW", "rx_cc_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rx_cc_ctlebiasctrl", "bias control for DQ BL1/3 ctle amp\r\n"
"00 2kΩ          0.25xnom\r\n"
"01 1kΩ          0.4xnom\r\n"
"10 0.5kΩ     1xnom\r\n"
"11 0.25kΩ  1.7xnom"},
#else
{4, 5, 0x0000000000000000, "RW", "rx_cc_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rx_ccdm_ctleres", "resistor tuning for DM BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{2, 3, 0x0000000000000000, "RW", "rx_ccdm_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "rx_ccdm_ctlecap", "cap tuning for DM BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{0, 1, 0x0000000000000001, "RW", "rx_ccdm_ctlecap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo411[] = {{"CTLECTL3", "", 0x000000F4, 12, 0x00000000FFFFFFFF, 0x00000000000C00C1}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields412[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "rx_ccdq0_ctleres", "resistor tuning for DQ0 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{30, 31, 0x0000000000000000, "RW", "rx_ccdq0_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "rx_ccdq1_ctleres", "resistor tuning for DQ1 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{28, 29, 0x0000000000000000, "RW", "rx_ccdq1_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "rx_ccdq2_ctleres", "resistor tuning for DQ2 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{26, 27, 0x0000000000000000, "RW", "rx_ccdq2_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "rx_ccdq3_ctleres", "resistor tuning for DQ3 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{24, 25, 0x0000000000000000, "RW", "rx_ccdq3_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "rx_ccdq4_ctleres", "resistor tuning for DQ4 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{22, 23, 0x0000000000000000, "RW", "rx_ccdq4_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "rx_ccdq5_ctleres", "resistor tuning for DQ5 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{20, 21, 0x0000000000000000, "RW", "rx_ccdq5_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rx_ccdq6_ctleres", "resistor tuning for DQ6 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{18, 19, 0x0000000000000000, "RW", "rx_ccdq6_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rx_ccdq7_ctleres", "resistor tuning for DQ7 BL1/3;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{16, 17, 0x0000000000000000, "RW", "rx_ccdq7_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000001, "RW", "rx_ccdq0_ctlecap", "cap tuning for DQ0 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{14, 15, 0x0000000000000001, "RW", "rx_ccdq0_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000001, "RW", "rx_ccdq1_ctlecap", "cap tuning for DQ1 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{12, 13, 0x0000000000000001, "RW", "rx_ccdq1_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000001, "RW", "rx_ccdq2_ctlecap", "cap tuning for DQ2 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{10, 11, 0x0000000000000001, "RW", "rx_ccdq2_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000001, "RW", "rx_ccdq3_ctlecap", "cap tuning for DQ3 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{8, 9, 0x0000000000000001, "RW", "rx_ccdq3_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000001, "RW", "rx_ccdq4_ctlecap", "cap tuning for DQ4 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{6, 7, 0x0000000000000001, "RW", "rx_ccdq4_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000001, "RW", "rx_ccdq5_ctlecap", "cap tuning for DQ5 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{4, 5, 0x0000000000000001, "RW", "rx_ccdq5_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000001, "RW", "rx_ccdq6_ctlecap", "cap tuning for DQ6 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{2, 3, 0x0000000000000001, "RW", "rx_ccdq6_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "rx_ccdq7_ctlecap", "cap tuning for DQ7 BL1/3;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{0, 1, 0x0000000000000001, "RW", "rx_ccdq7_ctlecap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo412[] = {{"CTLECTL2", "", 0x000000F8, 16, 0x00000000FFFFFFFF, 0x0000000000005555}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields413[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rx_bl0_ctletune", "RX 1st Stage Amp CTLE Fine Tune - BL0"},
#else
{18, 19, 0x0000000000000000, "RW", "rx_bl0_ctletune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rx_bl0_ampcombtune", "RX 2nd Stage Amp Fine Tune - BL0"},
#else
{16, 17, 0x0000000000000000, "RW", "rx_bl0_ampcombtune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000001, "RW", "drx_bl_ctleen", "Enable CTLE for DQS (1=enable, 0=disable)"},
#else
{15, 15, 0x0000000000000001, "RW", "drx_bl_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "drx_bl_ctlebiasctrl", "bias control for ctle amp\r\n"
"00 2kΩ          0.25xnom\r\n"
"01 1kΩ          0.4xnom\r\n"
"10 0.5kΩ     1xnom\r\n"
"11 0.25kΩ  1.7xnom"},
#else
{12, 14, 0x0000000000000000, "RW", "drx_bl_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "drx_bl_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{10, 11, 0x0000000000000000, "RW", "drx_bl_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000001, "RW", "drx_bl_ctlecap", "cap tuning;00 = 0.5pf;01 = 1pf;10 = 1.5pf;11 = 2pf"},
#else
{8, 9, 0x0000000000000001, "RW", "drx_bl_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "drx_bl_biasen", "DRX Bias Enable - BL0/2"},
#else
{7, 7, 0x0000000000000001, "RW", "drx_bl_biasen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "rx_bl_ctleen", "Enable CTLE for DQ BL0/2 (1=enable, 0=disable)"},
#else
{6, 6, 0x0000000000000001, "RW", "rx_bl_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rx_bl_ctlebiasctrl", "bias control for ctle amp for DQ BL0/2\r\n"
"00 2kΩ          0.25xnom\r\n"
"01 1kΩ          0.4xnom\r\n"
"10 0.5kΩ     1xnom\r\n"
"11 0.25kΩ  1.7xnom"},
#else
{4, 5, 0x0000000000000000, "RW", "rx_bl_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rx_bldm_ctleres", "resistor tuning for DM BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{2, 3, 0x0000000000000000, "RW", "rx_bldm_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "rx_bldm_ctlecap", "cap tuning for DM BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{0, 1, 0x0000000000000001, "RW", "rx_bldm_ctlecap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo413[] = {{"CTLECTL1", "", 0x000000FC, 12, 0x00000000FFFFFFFF, 0x00000000000081C1}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields414[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "rx_bldq0_ctleres", "resistor tuning for DQ0 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{30, 31, 0x0000000000000000, "RW", "rx_bldq0_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "rx_bldq1_ctleres", "resistor tuning for DQ1 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{28, 29, 0x0000000000000000, "RW", "rx_bldq1_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "rx_bldq2_ctleres", "resistor tuning for DQ2 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{26, 27, 0x0000000000000000, "RW", "rx_bldq2_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "rx_bldq3_ctleres", "resistor tuning for DQ3 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{24, 25, 0x0000000000000000, "RW", "rx_bldq3_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "rx_bldq4_ctleres", "resistor tuning for DQ4 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{22, 23, 0x0000000000000000, "RW", "rx_bldq4_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "rx_bldq5_ctleres", "resistor tuning for DQ5 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{20, 21, 0x0000000000000000, "RW", "rx_bldq5_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rx_bldq6_ctleres", "resistor tuning for DQ6 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{18, 19, 0x0000000000000000, "RW", "rx_bldq6_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rx_bldq7_ctleres", "resistor tuning for DQ7 BL0/2;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{16, 17, 0x0000000000000000, "RW", "rx_bldq7_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000001, "RW", "rx_bldq0_ctlecap", "cap tuning for DQ0 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{14, 15, 0x0000000000000001, "RW", "rx_bldq0_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000001, "RW", "rx_bldq1_ctlecap", "cap tuning for DQ1 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{12, 13, 0x0000000000000001, "RW", "rx_bldq1_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000001, "RW", "rx_bldq2_ctlecap", "cap tuning for DQ2 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{10, 11, 0x0000000000000001, "RW", "rx_bldq2_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000001, "RW", "rx_bldq3_ctlecap", "cap tuning for DQ3 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{8, 9, 0x0000000000000001, "RW", "rx_bldq3_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000001, "RW", "rx_bldq4_ctlecap", "cap tuning for DQ4 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{6, 7, 0x0000000000000001, "RW", "rx_bldq4_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000001, "RW", "rx_bldq5_ctlecap", "cap tuning for DQ5 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{4, 5, 0x0000000000000001, "RW", "rx_bldq5_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000001, "RW", "rx_bldq6_ctlecap", "cap tuning for DQ6 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{2, 3, 0x0000000000000001, "RW", "rx_bldq6_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "rx_bldq7_ctlecap", "cap tuning for DQ7 BL0/2;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{0, 1, 0x0000000000000001, "RW", "rx_bldq7_ctlecap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo414[] = {{"CTLECTL0", "", 0x00000100, 16, 0x00000000FFFFFFFF, 0x0000000000005555}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields415[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000001, "RW", "tx_bl_tcostaticlegen", "TX TCO enable - BL0/2"},
#else
{31, 31, 0x0000000000000001, "RW", "tx_bl_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 30, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "tx_bl_tcofall", "DQ TCO comp fall code - BL0/2"},
#else
{24, 28, 0x000000000000001F, "RW", "tx_bl_tcofall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "tx_bl_tcorise", "DQ TCO comp rise code - BL0/2"},
#else
{16, 20, 0x000000000000001F, "RW", "tx_bl_tcorise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000001, "RW", "tx_cc_tcostaticlegen", "TX TCO enable - BL1/3"},
#else
{15, 15, 0x0000000000000001, "RW", "tx_cc_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "tx_cc_tcofall", "DQ TCO comp fall code - BL1/3 Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "tx_cc_tcofall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "tx_cc_tcorise", "DQ TCO comp rise code - BL1/3 Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "tx_cc_tcorise", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo415[] = {{"TCOCTL_DQCC", "", 0x00000104, 10, 0x00000000FFFFFFFF, 0x000000009F1F9F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields416[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RW", "dtx_bl_tcostaticlegen", "DTX TCO enable - BL0/2"},
#else
{29, 29, 0x0000000000000001, "RW", "dtx_bl_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "dtx_bl_tcofalldqsb", "DQSB TCO comp fall code - BL0/2"},
#else
{24, 28, 0x000000000000001F, "RW", "dtx_bl_tcofalldqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "dtx_bl_tcorisedqsb", "DQS TCO comp fall code - BL0/2"},
#else
{16, 20, 0x000000000000001F, "RW", "dtx_bl_tcorisedqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "dtx_bl_tcofalldqs", "DQSB TCO comp rise code - BL0/2"},
#else
{8, 12, 0x000000000000001F, "RW", "dtx_bl_tcofalldqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "dtx_bl_tcorisedqs", "DQS TCO comp rise code - BL0/2"},
#else
{0, 4, 0x000000000000001F, "RW", "dtx_bl_tcorisedqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo416[] = {{"TCOCTL_DQ", "", 0x00000108, 9, 0x00000000FFFFFFFF, 0x000000003F1F1F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields417[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RW", "dtx_cc_tcostaticlegen", "DTX TCO enable - BL1/3"},
#else
{29, 29, 0x0000000000000001, "RW", "dtx_cc_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "dtx_cc_tcofalldqsb", "DQSB TCO comp fall code - BL1/3 Lane"},
#else
{24, 28, 0x000000000000001F, "RW", "dtx_cc_tcofalldqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "dtx_cc_tcorisedqsb", "DQSB TCO comp rise code - BL1/3 Lane"},
#else
{16, 20, 0x000000000000001F, "RW", "dtx_cc_tcorisedqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "dtx_cc_tcofalldqs", "DQS TCO comp fall code - BL1/3 Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "dtx_cc_tcofalldqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "dtx_cc_tcorisedqs", "DQS TCO comp rise code - BL1/3 Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "dtx_cc_tcorisedqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo417[] = {{"TCOCTL_CC", "", 0x0000010C, 9, 0x00000000FFFFFFFF, 0x000000003F1F1F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields418[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "txdll_rk1siggrp06dbsel", "Dead band select for sig grp 6 rank 1  - UNUSED FOR BXT-P"},
#else
{21, 22, 0x0000000000000000, "RW", "txdll_rk1siggrp06dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "txdll_rk1siggrp06rdptroffset", "Read pointer offset for sig group 6 rank 1"},
#else
{16, 20, 0x0000000000000000, "RW", "txdll_rk1siggrp06rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RW", "txdll_rk0siggrp06dbsel", "Dead band select for sig grp 6 rank 0  - UNUSED FOR BXT-P"},
#else
{5, 6, 0x0000000000000000, "RW", "txdll_rk0siggrp06dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "txdll_rk0siggrp06rdptroffset", "Read pointer offset for sig group 6 rank 0"},
#else
{0, 4, 0x0000000000000000, "RW", "txdll_rk0siggrp06rdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo418[] = {{"TXDLLSIGGRP6CTL", "", 0x00000110, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields419[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "txdll_rk1siggrp07dbsel", "Dead band select for sig grp 7 rank 1  - UNUSED FOR BXT-P"},
#else
{21, 22, 0x0000000000000000, "RW", "txdll_rk1siggrp07dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "txdll_rk1siggrp07rdptroffset", "Read pointer offset for sig group 7 rank 1"},
#else
{16, 20, 0x0000000000000000, "RW", "txdll_rk1siggrp07rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RW", "txdll_rk0siggrp07dbsel", "Dead band select for sig grp 7 rank 0  - UNUSED FOR BXT-P"},
#else
{5, 6, 0x0000000000000000, "RW", "txdll_rk0siggrp07dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "txdll_rk0siggrp07rdptroffset", "Read pointer offset for sig group 7 rank 0"},
#else
{0, 4, 0x0000000000000000, "RW", "txdll_rk0siggrp07rdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo419[] = {{"TXDLLSIGGRP7CTL", "", 0x00000114, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields420[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "cc_rk1dqdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQDMDRV - RK1."},
#else
{20, 23, 0x0000000000000000, "RW", "cc_rk1dqdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "cc_rk0dqdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQDMDRV - RK0."},
#else
{16, 19, 0x0000000000000000, "RW", "cc_rk0dqdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "cc_rk1dqsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{12, 15, 0x0000000000000000, "RW", "cc_rk1dqsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "cc_rk0dqsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{8, 11, 0x0000000000000000, "RW", "cc_rk0dqsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "cc_rk1dqsdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{4, 7, 0x0000000000000000, "RW", "cc_rk1dqsdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "cc_rk0dqsdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{0, 3, 0x0000000000000000, "RW", "cc_rk0dqsdrvsecondrdportref2xrdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo420[] = {{"LDOCTL1", "", 0x00000118, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields421[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "bl_rk1dqdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQDMDRV - RK1."},
#else
{20, 23, 0x0000000000000000, "RW", "bl_rk1dqdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "bl_rk0dqdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQDMDRV - RK0."},
#else
{16, 19, 0x0000000000000000, "RW", "bl_rk0dqdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "bl_rk1dqsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{12, 15, 0x0000000000000000, "RW", "bl_rk1dqsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "bl_rk0dqsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{8, 11, 0x0000000000000000, "RW", "bl_rk0dqsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "bl_rk1dqsdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{4, 7, 0x0000000000000000, "RW", "bl_rk1dqsdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "bl_rk0dqsdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{0, 3, 0x0000000000000000, "RW", "bl_rk0dqsdrvsecondrdportref2xrdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo421[] = {{"LDOCTL0", "", 0x0000011C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields422[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RW", "data0sel", "DRAM read data bit mux for DQ0. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{21, 23, 0x0000000000000000, "RW", "data0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 20, 0x0000000000000000, "RW", "data1sel", "DRAM read data bit mux for DQ1. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{18, 20, 0x0000000000000000, "RW", "data1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 17, 0x0000000000000000, "RW", "data2sel", "DRAM read data bit mux for DQ2. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{15, 17, 0x0000000000000000, "RW", "data2sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "data3sel", "DRAM read data bit mux for DQ3. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{12, 14, 0x0000000000000000, "RW", "data3sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000000, "RW", "data4sel", "DRAM read data bit mux for DQ4. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{9, 11, 0x0000000000000000, "RW", "data4sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000000, "RW", "data5sel", "DRAM read data bit mux for DQ5. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{6, 8, 0x0000000000000000, "RW", "data5sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "data6sel", "DRAM read data bit mux for DQ6. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{3, 5, 0x0000000000000000, "RW", "data6sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "data7sel", "DRAM read data bit mux for DQ7.  \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{0, 2, 0x0000000000000000, "RW", "data7sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo422[] = {{"PTDATAMUXSEL", "", 0x00000120, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields423[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "lpmode_dasrtdqcmddrvenb_dly", "This indicates the delay in spidclk cycles for DQ/DQS driver disable, during LP mode 1 entry"},
#else
{28, 30, 0x0000000000000000, "RW", "lpmode_dasrtdqcmddrvenb_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtdqcmdsigpien_dly", "This indicates the delay in spidclk cycles for DQ/DQS/CMD PI disable/enable, during LP mode 1 entry/exit"},
#else
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtdqcmdsigpien_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000000, "RW", "lpmode_asrtdqcmddrvenb_dly", "This indicates the delay in spidclk cycles for DQ/DQS driver enable, during LP mode  1 exit"},
#else
{20, 22, 0x0000000000000000, "RW", "lpmode_asrtdqcmddrvenb_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RW", "lpmode_dasrtiobufact_dly", "This indicates the delay in spidclk cycles for IOBUFACT disable, during LP mode 2  entry"},
#else
{16, 18, 0x0000000000000000, "RW", "lpmode_dasrtiobufact_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "lpmode_dasrtwrptren_dly", "This indicates the delay in spidclk cycles for write pointer disable, during LP mode  2 entry"},
#else
{12, 14, 0x0000000000000000, "RW", "lpmode_dasrtwrptren_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "lpmode_asrtref2xrstb_dly", "This indicates the delay in spidclk cycles for ref2xclk reset assertion, during LP mode 2  entry"},
#else
{8, 10, 0x0000000000000000, "RW", "lpmode_asrtref2xrstb_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "lpmode_dasrtref2xrstb_dly", "This indicates the delay in spidclk cycles for ref2xclk reset de-assertion, during LP mode 2 exit"},
#else
{0, 2, 0x0000000000000000, "RW", "lpmode_dasrtref2xrstb_dly", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo423[] = {{"LPMODECTL0", "", 0x00000124, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields424[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "lpmode_asrtwrptren_dly", "This indicates the delay in spidclk cycles for write pointer enable, during LP mode 2 exit"},
#else
{28, 30, 0x0000000000000000, "RW", "lpmode_asrtwrptren_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtiobufact_dly", "This indicates the delay in spidclk cycles for IOBUFACT enable, during LP mode 2 exit"},
#else
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtiobufact_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "lpmode_dqcmddrvenbovrd", "Override LP mode control for DQ/DQS/CMD driver"},
#else
{22, 22, 0x0000000000000000, "RW", "lpmode_dqcmddrvenbovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "lpmode_iobufactovrd", "Override LP mode control for IOBUFACT"},
#else
{21, 21, 0x0000000000000000, "RW", "lpmode_iobufactovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "lpmode_ref2xclkenovrd", "Override LP mode control for ref2xclk enable"},
#else
{20, 20, 0x0000000000000000, "RW", "lpmode_ref2xclkenovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "siggrpen_lpmode1ovrd", "Override LP mode control for signal PI enable"},
#else
{19, 19, 0x0000000000000000, "RW", "siggrpen_lpmode1ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "siggrpen_lpmode2or3ovrd", "Override LP mode control for signal PI enable"},
#else
{18, 18, 0x0000000000000000, "RW", "siggrpen_lpmode2or3ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "lpmode_wrptrenovrd", "Override LP mode control for write pointer enable"},
#else
{17, 17, 0x0000000000000000, "RW", "lpmode_wrptrenovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "lpmode_ref2xrstbovrd", "Override LP mode control for ref2xrstb"},
#else
{16, 16, 0x0000000000000000, "RW", "lpmode_ref2xrstbovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "lpmode_asrtref2xsigpien_dly", "This indicates the delay in spidclk cycles for DLL enable, during LP mode 2 exit"},
#else
{0, 7, 0x0000000000000000, "RW", "lpmode_asrtref2xsigpien_dly", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo424[] = {{"LPMODECTL1", "", 0x00000128, 14, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields425[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 23, 0x0000000000000000, "RW", "rdcmd2rxdllupdt", "Read command to RXDLL update."},
#else
{18, 23, 0x0000000000000000, "RW", "rdcmd2rxdllupdt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 17, 0x0000000000000000, "RW", "rxdllupdtlen", "RXDLL update enable."},
#else
{12, 17, 0x0000000000000000, "RW", "rxdllupdtlen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000000, "RW", "rdcmd2rdactive", "Read command to active delay."},
#else
{6, 11, 0x0000000000000000, "RW", "rdcmd2rdactive", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdactivelen", "Read active length."},
#else
{0, 5, 0x0000000000000000, "RW", "rdactivelen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo425[] = {{"RXDLLRDCMDCTL0", "", 0x0000012C, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields426[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dllcomprst_b", "Power-on or software reset0: reset state1: norma operationSet to 1 to enter normal operation."},
#else
{0, 0, 0x0000000000000000, "RW", "dllcomprst_b", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo426[] = {{"DLLCOMP_RESET", "", 0x00000600, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields427[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RWS", "txdll_init", "Activates initialization training sequence.0: initialization training sequence not active.1: initialization training sequence active.Self clearing after successful initialization training sequence."},
#else
{0, 0, 0x0000000000000000, "RWS", "txdll_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo427[] = {{"DLLCOMP_INIT", "", 0x00000604, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields428[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lpddr_type", "LPDDR speed target. 0: LPDDR3, 1600 MHz. 1: LPDDR4, 3200 MHz."},
#else
{0, 0, 0x0000000000000000, "RW", "lpddr_type", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo428[] = {{"DLLCOMP_LPDDRTYPE", "", 0x00000608, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields429[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "clkungate", "Internal Clock control. 0 = allow clock gating for low power; 1 = allow free running clock"},
#else
{0, 0, 0x0000000000000001, "RW", "clkungate", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo429[] = {{"DLLCOMP_CLKUNGATE", "", 0x0000060C, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields430[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "txdll_lock_error", "Set when initialization or fine periodic training failed the locking condition. Cleared on a read or writing a 0."},
#else
{7, 7, 0x0000000000000000, "RO/V", "txdll_lock_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "txdll_fine_error", "Set when fine code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{6, 6, 0x0000000000000000, "RO/V", "txdll_fine_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO/V", "txdll_coarsep_error", "Set when coarse code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{5, 5, 0x0000000000000000, "RO/V", "txdll_coarsep_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "txdll_error", "Set when Delay Cell count exceeds maximum value. Cleared on a read or writing a 0."},
#else
{4, 4, 0x0000000000000000, "RO/V", "txdll_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{2, 3, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "txdll_lock_flag", "Set when initialization or fine periodic training passed the locking condition. Valid only when scr_lockseq_en is set to 1.Cleared on a read or writing a 0."},
#else
{1, 1, 0x0000000000000000, "RO/V", "txdll_lock_flag", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "txdll_init_done", "Set when Initialization sequence is successful. Cleared on a read or writing a 0."},
#else
{0, 0, 0x0000000000000000, "RO/V", "txdll_init_done", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo430[] = {{"DLLCOMP_ERROR_STATUS", "", 0x00000610, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields431[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RO/V", "txdll_stat_fbmuxsel", "Delay Cell count value during normal operation"},
#else
{16, 20, 0x0000000000000000, "RO/V", "txdll_stat_fbmuxsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO/V", "txdll_stat_coarseicode", "Coarse code value at initialization training sequence completion."},
#else
{12, 15, 0x0000000000000000, "RO/V", "txdll_stat_coarseicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RO/V", "txdll_stat_coarsecode", "Coarse code value during normal operation"},
#else
{8, 11, 0x0000000000000000, "RO/V", "txdll_stat_coarsecode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "txdll_stat_finecode", "Fine code value during normal operation"},
#else
{0, 7, 0x0000000000000000, "RO/V", "txdll_stat_finecode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo431[] = {{"DLLCOMP_CODE_STATUS", "", 0x00000614, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields432[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "lock_seq_en", "Enable lock sequence after initialization or fine periodic training sequence. 0: disable lock sequence. 1: enable lock sequence."},
#else
{31, 31, 0x0000000000000000, "RW", "lock_seq_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "lockerror_ignore", "Ignore lock error. Valid when scr_lockseq_en = 1. 0: Exit and wait for initialization training sequence. 1: ignore lock error and proceed to normal operation."},
#else
{30, 30, 0x0000000000000000, "RW", "lockerror_ignore", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000003, "RW", "lockcount_size", "Maximum samples to count for lock condition. The counter decrements until the value reaches 0 yielding scr_lockcount_size + 1 samples."},
#else
{0, 3, 0x0000000000000003, "RW", "lockcount_size", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo432[] = {{"DLLCOMP_LOCKCTL", "", 0x00000618, 4, 0x00000000FFFFFFFF, 0x0000000000000003}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields433[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "muxcode_ovr_sel", "Override txdll_fbmuxsel[4:0] with scr_muxcode_ovr[4:0].0: disable override.1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "muxcode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "muxcode_ovr", "Delay cell fbmuxsel override value."},
#else
{16, 20, 0x0000000000000000, "RW", "muxcode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{13, 15, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "muxcode_max", "Delay cell maximum count value. Used in overflow check"},
#else
{8, 12, 0x0000000000000000, "RW", "muxcode_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{5, 7, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000009, "RW", "muxcode_min", "Delay cell minimum count value. Default start code."},
#else
{0, 4, 0x0000000000000009, "RW", "muxcode_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo433[] = {{"DLLCOMP_FBMUXSEL", "", 0x0000061C, 7, 0x00000000FFFFFFFF, 0x0000000000000009}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields434[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "coarsecode_ovr_sel", "Override txdll_coarsecode[3:0] with scr_coarsecode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{31, 31, 0x0000000000000000, "RW", "coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "coarseicode_ovr_sel", "Override txdll_coarseicode[3:0] with scr_coarseicode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{30, 30, 0x0000000000000000, "RW", "coarseicode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{28, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "coarseicode_ovr", "Coarsei code override value."},
#else
{24, 27, 0x0000000000000000, "RW", "coarseicode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{20, 23, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "coarsecode_ovr", "Coarse code override value."},
#else
{16, 19, 0x0000000000000000, "RW", "coarsecode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{12, 15, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "coarsecode_max", "Coarse code maximum count value. Default start value. Used in overflow check"},
#else
{8, 11, 0x0000000000000000, "RW", "coarsecode_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000002, "RW", "coarsecode_min", "Coarse code minimum count value. Used in underflow check."},
#else
{0, 3, 0x0000000000000002, "RW", "coarsecode_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo434[] = {{"DLLCOMP_COARSECODE", "", 0x00000620, 10, 0x00000000FFFFFFFF, 0x0000000000000002}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields435[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "finecodemax_limit", "Fine code limit - maximum value. Defines fine code drift allowed towards finecode maximum value before incrementing the coarse code for binary search training."},
#else
{24, 31, 0x0000000000000000, "RW", "finecodemax_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "finecodemin_limit", "Fine code limit - minimum value. Defines fine code drift allowed towards finecode minimum value before decrementing the coarse code for binary search training."},
#else
{16, 23, 0x0000000000000000, "RW", "finecodemin_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "finecode_max", "Fine code maximum value. Used in overflow check during fine continuous or fine periodic"},
#else
{8, 15, 0x0000000000000000, "RW", "finecode_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_min", "Underflow check during fine continuous or fine periodic training."},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo435[] = {{"DLLCOMP_FINECODE", "", 0x00000624, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields436[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_muxsel", "Two bit field selects one of 4 possible finecode values for each 8:1 mux input. Two bit field shared between -/+ index values (ex. -gf / +gf)"},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_muxsel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo436[] = {{"DLLCOMP_FINEMUXSEL", "", 0x00000628, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields437[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "finec_mode", "Fine continuous training enable after initialization training. 0: Fine continuous training disable. 1: Fine continuous training enable (default). When both finec_mode and finep_mode are set to 1, dllcomp functionality is unpredictable."},
#else
{31, 31, 0x0000000000000000, "RW", "finec_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "finep_mode", "Fine priodic training enable after initialization training. 0: Fine periodic disable (default). 1: Fine periodic enable. When both finec_mode and finep_mode are set to 1, dllcomp functionality is unpredictable."},
#else
{30, 30, 0x0000000000000000, "RW", "finep_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "searchalgo_long", "Propriety search algorithm version to apply during lock, fine continuous and fine periodic training. 0: Apply short version. 1: Apply long version."},
#else
{29, 29, 0x0000000000000000, "RW", "searchalgo_long", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 28, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 28, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_start", "Fine code start value to apply during binary search training"},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_start", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo437[] = {{"DLLCOMP_FINECTL", "", 0x0000062C, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields438[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "finecode_ovr_sel", "Fine code override select. 0: Apply computed fine code (default). 1: Apply scr_finecode_ovr[7:0] ."},
#else
{31, 31, 0x0000000000000000, "RW", "finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "finecode_updateovr_ovr", "When scr_finecode_ovr_sel is active high, this bit drives txdll_dllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_ovr", "Fine code to override with when scr_finecode_ovr_sel = 1"},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo438[] = {{"DLLCOMP_FINECODEOVR", "", 0x00000630, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields439[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "finepwait_interval", "Fine periodic interval timer start value. Defines the interval between back to back fine periodic training sequences."},
#else
{0, 15, 0x0000000000000000, "RW", "finepwait_interval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo439[] = {{"DLLCOMP_FPTIMER", "", 0x00000634, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields440[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{13, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{13, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000006, "RW", "samplewait_max", "Wait interval between code update and sample ready. Applied during lock, fine continuous and fine"},
#else
{8, 12, 0x0000000000000006, "RW", "samplewait_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{5, 7, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000002, "RW", "samplewait_min", "Wait interval between code update and sample ready. Applied during coarse initialization and fine"},
#else
{0, 4, 0x0000000000000002, "RW", "samplewait_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo440[] = {{"DLLCOMP_SAMPLEWAIT", "", 0x00000638, 4, 0x00000000FFFFFFFF, 0x0000000000000602}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields441[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "rxdll_coarsecode_ovr_sel", "Override rxdll_coarsecode[3:0] with scr_rxdll_coarsecode_ovr[3:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "rxdll_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_coarsecode_ovr", "Coarse code override value for rxdll_coarsecode[3:0]"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo441[] = {{"DLLCOMP_RXCOARSEOVR", "", 0x0000063C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields442[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "rxdll_finecode_ovr_sel", "Override rxdll_finecode[7:0] with scr_rxdll_finecode_ovr[7:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "rxdll_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "rxdll_finecode_updateovr_ovr", "When scr_rxdll_finecode_ovr_sel is active high, this bit drives rxdll_rxdqsdllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "rxdll_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "rxdll_finecode_ovr", "FIne code override value for rxdll_finecode[7:0]"},
#else
{0, 7, 0x0000000000000000, "RW", "rxdll_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo442[] = {{"DLLCOMP_RXFINEOVR", "", 0x00000640, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields443[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo443[] = {{"DFXVISA_ULM0PATTGEN", "", 0x00000700, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields444[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_bypass", "VISA Bypass ULM0LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_clksel", "VISA ULM0LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_datasel", "VISA ULM0LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo444[] = {{"DFXVISA_ULM0LN0", "", 0x00000704, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields445[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_bypass", "VISA Bypass ULM0LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_clksel", "VISA ULM0LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_datasel", "VISA ULM0LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo445[] = {{"DFXVISA_ULM0LN1", "", 0x00000708, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields446[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo446[] = {{"DFXVISA_ULM1PATTGEN", "", 0x0000070C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields447[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_bypass", "VISA Bypass ULM1LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_clksel", "VISA ULM1LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_datasel", "VISA ULM1LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo447[] = {{"DFXVISA_ULM1LN0", "", 0x00000710, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields448[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_bypass", "VISA Bypass ULM1LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_clksel", "VISA ULM1LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_datasel", "VISA ULM1LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo448[] = {{"DFXVISA_ULM1LN1", "", 0x00000714, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields449[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo449[] = {{"DFXVISA_ULM2PATTGEN", "", 0x00000718, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields450[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_bypass", "VISA Bypass ULM2LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_clksel", "VISA ULM2LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_datasel", "VISA ULM2LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo450[] = {{"DFXVISA_ULM2LN0", "", 0x0000071C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields451[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_bypass", "VISA Bypass ULM2LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_clksel", "VISA ULM2LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_datasel", "VISA ULM2LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo451[] = {{"DFXVISA_ULM2LN1", "", 0x00000720, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields452[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo452[] = {{"DFXVISA_ULM3PATTGEN", "", 0x00000724, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields453[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_bypass", "VISA Bypass ULM3LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_clksel", "VISA ULM3LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_datasel", "VISA ULM3LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo453[] = {{"DFXVISA_ULM3LN0", "", 0x00000728, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields454[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_bypass", "VISA Bypass ULM3LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_clksel", "VISA ULM3LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_datasel", "VISA ULM3LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo454[] = {{"DFXVISA_ULM3LN1", "", 0x0000072C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields455[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "bl_dfxmrgtxovren", "DQ Bytelane Tx FIFO Margin Mode config override enable for Tx data path and Latch enables via  DFXMRGTXFIFO[24:0]    1'b1  - Enable TxFIFO DFx overrides on Latch enables and TxData  1'b0 - Functional Mode of operation"},
#else
{11, 11, 0x0000000000000000, "RW", "bl_dfxmrgtxovren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "bl_dfxmrgtxwren", "DQ Bytelane TxFIFO Margin Mode Latch enable override value used to make TxFIFO latches transparent allowing the loading of all TxFIFO Latches with data programmed in DFXMRGTXFIFO[23:0], if dfxmrgtxovren is asserted(1'b1)  1'b1 - All DQ/DM/DQS Tx FIFO Latches Transparent  0'b0 - All DQ/DM/DQS TxFIFO Latches CLosed"},
#else
{10, 10, 0x0000000000000000, "RW", "bl_dfxmrgtxwren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsrise", "DQ Bytelane Tx FIFO Margin Mode DQS/B Rise Tx SubFIFO data load value. The value loaded will apply to all DQ Bytelane DQS/B Rise SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{9, 9, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsrise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsfall", "DQ Bytelane Tx FIFO Margin Mode DQS/B Fall Tx SubFIFO data load value. The value loaded will apply to all DQ Bytelane DQS/B Fall SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{8, 8, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsfall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph0", "DQ Bytelane Tx FIFO Margin Mode DQ Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 0 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{7, 7, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph1", "DQ Bytelane Tx FIFO Margin Mode DQ Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 1 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{6, 6, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph2", "DQ Bytelane Tx FIFO Margin Mode DQ Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 2 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{5, 5, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph3", "DQ Bytelane Tx FIFO Margin Mode DQ Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{4, 4, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph0", "DQ Bytelane Tx FIFO Margin Mode DQ Phase0 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 0 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{3, 3, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph1", "DQ Bytelane Tx FIFO Margin Mode DQ Phase1 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 1 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{2, 2, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph2", "DQ Bytelane Tx FIFO Margin Mode DQ Phase2 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 2 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{1, 1, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph3", "DQ Bytelane Tx FIFO Margin Mode DQ Phase3 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{0, 0, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo455[] = {{"DFXMRG_BL", "", 0x00000730, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields456[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "cc_dfxmrgtxovren", "DQCCC Bytelane Tx FIFO Margin Mode config override enable for Tx data path and Latch enables via  DFXMRGTXFIFO[24:0]    1'b1  - Enable TxFIFO DFx overrides on Latch enables and TxData  1'b0 - Functional Mode of operation"},
#else
{15, 15, 0x0000000000000000, "RW", "cc_dfxmrgtxovren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "cc_dfxmrgtxwren", "DQCCC Bytelane TxFIFO Margin Mode Latch enable override value used to make TxFIFO latches transparent allowing the loading of all TxFIFO Latches with data programmed in DFXMRGTXFIFO[23:0], if dfxmrgtxovren is asserted(1'b1)  1'b1 - All DQCCC/DM/DQCCCS Tx FIFO Latches Transparent  0'b0 - All DQCCC/DM/DQCCCS TxFIFO Latches CLosed"},
#else
{14, 14, 0x0000000000000000, "RW", "cc_dfxmrgtxwren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "cc_dfxmrgtxdqsrise", "DQCCC Bytelane Tx FIFO Margin Mode DQCCCS/B Rise Tx SubFIFO data load value. The value loaded will apply to all DQCCC Bytelane DQCCCS/B Rise SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{13, 13, 0x0000000000000000, "RW", "cc_dfxmrgtxdqsrise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "cc_dfxmrgtxdqsfall", "DQCCC Bytelane Tx FIFO Margin Mode DQCCCS/B Fall Tx SubFIFO data load value. The value loaded will apply to all DQCCC Bytelane DQCCCS/B Fall SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{12, 12, 0x0000000000000000, "RW", "cc_dfxmrgtxdqsfall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{11, 11, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{10, 10, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{9, 9, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{8, 8, 0x0000000000000000, "RW", "cc_dfxmrgtxdrise_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{7, 7, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{6, 6, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase2 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{5, 5, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase3 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{4, 4, 0x0000000000000000, "RW", "cc_dfxmrgtxdfall_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{3, 3, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{2, 2, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase2 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b11"},
#else
{1, 1, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase3 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{0, 0, 0x0000000000000000, "RW", "cc_dfxmrgtxdsdr_ph3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo456[] = {{"DFXMRG_CC", "", 0x00000734, 17, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields457[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "bl_dfxmrgrx_cmpval", "DFx Margin Mode DQ Bytelane Rx Compare value; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{0, 7, 0x0000000000000000, "RW", "bl_dfxmrgrx_cmpval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo457[] = {{"DFXMRG_BLRX", "", 0x00000738, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields458[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{25, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 24, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrsel", "DFx Margin Mode SDR vs DDR Rx Compare Values"},
#else
{16, 24, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "cc_dfxmrgrx_ddrcmpval", "DFx Margin Mode CCC Bytelane Rx Compare value for DDR pins; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{8, 15, 0x0000000000000000, "RW", "cc_dfxmrgrx_ddrcmpval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrcmpval", "DFx Margin Mode CCC Bytelane Rx Compare value for SDR pins; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{0, 7, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrcmpval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo458[] = {{"DFXMRG_CCRX", "", 0x0000073C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields459[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "This is the DQS configuration for first phase  - Bytelane 0[br](2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo459[] = {{"U32_WRDQCTL", "", 0x0000001C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields460[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "Phase 1 - DQS Drive enable"},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo460[] = {{"U32_WRDQSCTL_CC", "", 0x00000020, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields461[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "Phase 1 - DQS Drive enable"},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo461[] = {{"U32_WRDQSCTL_BL", "", 0x00000024, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields462[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", ""},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo462[] = {{"U32_WKPUPPDNCTL", "", 0x0000007C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields463[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", ""},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo463[] = {{"U32_RXODTCTL_BL13", "", 0x0000003C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields464[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", ""},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo464[] = {{"U32_RXODTCTL_DQ", "", 0x00000040, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields465[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "This is the DQS configuration for first phase [br](2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo465[] = {{"U32_WRDQCTL", "", 0x00000024, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields466[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", "Phase 1 - DQS Drive enable"},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo466[] = {{"U32_WRDQSCTL", "", 0x00000028, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields467[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data", ""},
#else
{0, 31, 0x0000000000000000, "RW", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo467[] = {{"U32_WKPUPPDNCTL", "", 0x00000068, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields468[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "memtech", "Memory Technology\r\n"
"Bit 3:0: DRAM Technology\r\n"
"0000: LPDDR3\r\n"
"0001: LPDDR4\r\n"
"0010: DDR3/L/U\r\n"
"0011: DDR4/L\r\n"
"0100: WIO2\r\n"
"0101: FMI\r\n"
"0110: DDR-T\r\n"
"0111: HBM"},
#else
{28, 31, 0x0000000000000000, "RW", "memtech", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "memfreq", "Indicates the Memory Frequency currently selected\r\n"
"within the PHY. This signal is valid after initialization\r\n"
"complete is set.\r\n"
"Bit 3:0 DRAM Frequency\r\n"
"0000: 800\r\n"
"0001: 1066\r\n"
"0010: 1333\r\n"
"0011: 1600\r\n"
"0100: 1866\r\n"
"0101: 2133\r\n"
"0110: 2400\r\n"
"1001: Reserved For Future Use (RFU)\r\n"
"101X: Reserved For Future Use (RFU)\r\n"
"11XX: Reserved For Future Use (RFU)"},
#else
{24, 27, 0x0000000000000000, "RW", "memfreq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "phyupd_dly", "Delay between the phy update request to ack \r\n"
"in terms of SPID clocks."},
#else
{16, 23, 0x0000000000000000, "RW", "phyupd_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "stretchmode", "This is the stretch mode signal.\r\n"
"00- normal read\r\n"
"01- x4 stretch mode \r\n"
"10- x8 stretch mode\r\n"
"11- x16 stretch mode"},
#else
{13, 14, 0x0000000000000000, "RW", "stretchmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 12, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "slowpath", "Delay the wrcmd 1 spidclk before write into the fifo.\r\n"
"1: 1 spidclk delay\r\n"
"0: no delay\r\n"
"With clock gating enable, the write pointer is only valid @ the next spid clock edge of write command. -> delay 1 spidclk so we can capture it into the fifo.\r\n"
"Set to 1 if do clock gate. Else set it to 0."},
#else
{11, 11, 0x0000000000000000, "RW", "slowpath", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "txfifo_csn_ffloppreseten", "This is the txFIFO final flop preset enable\r\n"
"1 - iobufact_b assert will preset the final flop, otherwise resets the final flop"},
#else
{10, 10, 0x0000000000000000, "RW", "txfifo_csn_ffloppreseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "rdmcpsel", "Programmable MCP for Tx FIFO read pointer path."},
#else
{9, 9, 0x0000000000000000, "RW", "rdmcpsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 8, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "bl1632xbl48b", "This is the burstlength configuration register\r\n"
"1:BL16 and BL32\r\n"
"0:BL4 and BL8"},
#else
{6, 6, 0x0000000000000000, "RW", "bl1632xbl48b", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "spidclksel", "SPID clk sel \r\n"
"00: 0.5xmode\r\n"
"01: 0.25x mode\r\n"
"10: 0.1x mode\r\n"
"11: NA"},
#else
{4, 5, 0x0000000000000000, "RW", "spidclksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "membus_loopback", "Membus Loopback Mode (For testing membus interface in a single family test environment.)  0=Not in Loopback 1=Loopback Mode"},
#else
{3, 3, 0x0000000000000000, "RW", "membus_loopback", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "lpddr34mode", "Single data rate v/s Double Data rate \r\n"
"0: Double data rate (LP3)\r\n"
"1: Single data rate (LP4)"},
#else
{2, 2, 0x0000000000000000, "RW", "lpddr34mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ddr3lmode", "Indicates DDR3L mode vs LPDDR* mode (1 - DDR3L mode 0 - Disabled)"},
#else
{1, 1, 0x0000000000000000, "RW", "ddr3lmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 0, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo468[] = {{"DIGCTL", "", 0x00000000, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields469[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "siggrp03_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes / DDR4 = 2400)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/(DDR4 < 2400) Mode)"},
#else
{31, 31, 0x0000000000000000, "RW", "siggrp03_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "siggrp02_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes / DDR4 = 2400)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/(DDR4 < 2400) Mode)"},
#else
{30, 30, 0x0000000000000000, "RW", "siggrp02_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "siggrp01_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes / DDR4 = 2400)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/(DDR4 < 2400) Mode)"},
#else
{29, 29, 0x0000000000000000, "RW", "siggrp01_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "siggrp00_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4 Mode)"},
#else
{28, 28, 0x0000000000000000, "RW", "siggrp00_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "compclkrdptrinit", "DLL comp init configuration."},
#else
{24, 27, 0x0000000000000000, "RW", "compclkrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RW", "compclkrdptroffset", "DLL comp read pointer offset."},
#else
{21, 23, 0x0000000000000000, "RW", "compclkrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 20, 0x0000000000000000, "RW", "ref1xrdptrinit", "This is the ref1x read pointer init configuration."},
#else
{17, 20, 0x0000000000000000, "RW", "ref1xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "dqxccb", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "dqxccb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ref1xrdptroffset", "This is the ref1xread pointer offset configuration."},
#else
{13, 15, 0x0000000000000000, "RW", "ref1xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ref2xrdptrinit", "This is the ref2x read pointer init configuration."},
#else
{8, 12, 0x0000000000000000, "RW", "ref2xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "cc_doublefifooffset", "This is the double FIFO offset configuration(in terms of 2xclock)."},
#else
{4, 7, 0x0000000000000000, "RW", "cc_doublefifooffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RO", "bl_doublefifooffset", "Reserved bits"},
#else
{0, 3, 0x0000000000000000, "RO", "bl_doublefifooffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo469[] = {{"FIFOPTRCTL", "", 0x00000004, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields470[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "ten_pad_sel", "Selects between CH0/CH1 CKE Pads for Test Mode Enable - One hot encoding {0001 - CH0 CKE[0], 0010 - CH0 CKE[1], 0100 - CH1 CKE[0], 1000 - CH1 CKE[1]}"},
#else
{28, 31, 0x0000000000000000, "RW", "ten_pad_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{26, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "ca_training", "CA training mode"},
#else
{25, 25, 0x0000000000000000, "RW", "ca_training", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 24, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 24, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "ckemasken", "CH0 CKE Mask Enable"},
#else
{22, 22, 0x0000000000000000, "RW", "ckemasken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "odttxdrven", "ODT buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{21, 21, 0x0000000000000000, "RW", "odttxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "clktxdrven", "CK buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{20, 20, 0x0000000000000000, "RW", "clktxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "cketxdrven", "CKE buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{19, 19, 0x0000000000000000, "RW", "cketxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "cstxdrven", "CS buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{18, 18, 0x0000000000000000, "RW", "cstxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 17, 0x0000000000000000, "RW", "cmdtxdrven", "CMD buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{7, 17, 0x0000000000000000, "RW", "cmdtxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ten_en", "TestMode Enable Pin"},
#else
{5, 5, 0x0000000000000000, "RW", "ten_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 4, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "clknegxposb", "Start phase of CK"},
#else
{2, 2, 0x0000000000000000, "RW", "clknegxposb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "cmdtristateovrval", "Command tristate override value"},
#else
{1, 1, 0x0000000000000000, "RW", "cmdtristateovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cmdtristateovrsel", "Command tristate override select"},
#else
{0, 0, 0x0000000000000000, "RW", "cmdtristateovrsel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo470[] = {{"CCCCTL", "", 0x00000008, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields471[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "rstbtx_enbrst", "Tri-state control for LP4 reset buffer"},
#else
{2, 2, 0x0000000000000000, "RW", "rstbtx_enbrst", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rstbtx_reset", "Reset for the LP4 reset buffer"},
#else
{1, 1, 0x0000000000000000, "RW", "rstbtx_reset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rstbtx_set", "Set for the LP4 reset buffer"},
#else
{0, 0, 0x0000000000000000, "RW", "rstbtx_set", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo471[] = {{"LP4RSTCTL", "", 0x0000000C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields472[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rxfiforst_b", "Rxfifo reset (active low)\r\n"
"1: deasserted\r\n"
"0 : asserted"},
#else
{1, 1, 0x0000000000000000, "RW", "rxfiforst_b", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "spidrst_b", "Reset for functional logic in upartition (except compensation and power management logic)  \r\n"
"0: Reset assertion  \r\n"
"1: Reset de-assertion"},
#else
{0, 0, 0x0000000000000000, "RW", "spidrst_b", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo472[] = {{"DIGRSTCTL", "", 0x00000010, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields473[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "wrptren", "Config-controlled Write pointer enable. 0=config control disabled, 1=config control enabled. This bit qualifies the pm_wrptren, which eventually goes to DQPTRGEN Fub."},
#else
{0, 0, 0x0000000000000000, "RW", "wrptren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo473[] = {{"FIFOPTREN", "", 0x00000014, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields474[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "lvl_dq_iobufactafe", "IO buffer activate - DQ Analog\r\n"
"Tristates DQ and DQS IO buffers \r\n"
"Disable Rx sections of IO buffers \r\n"
"0 : reset \r\n"
"1 : out of reset"},
#else
{2, 2, 0x0000000000000000, "RW", "lvl_dq_iobufactafe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lvl_cc1_iobufactafe", "IO buffer activate - CCC Analog\r\n"
"Tristates DQ and DQS IO buffers \r\n"
"Disable Rx sections of IO buffers \r\n"
"0 : reset \r\n"
"1 : out of reset"},
#else
{1, 1, 0x0000000000000000, "RW", "lvl_cc1_iobufactafe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lvl_cc0_iobufactafe", "IO buffer activate - DQ Analog\r\n"
"Tristates DQ and DQS IO buffers \r\n"
"Disable Rx sections of IO buffers \r\n"
"0 : reset \r\n"
"1 : out of reset"},
#else
{0, 0, 0x0000000000000000, "RW", "lvl_cc0_iobufactafe", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo474[] = {{"IOBUFACT_AFE", "", 0x00000018, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields475[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "dq_iobufactdig", "IO buffer activate - CCC Digital\r\n"
"Bytelane 1 SW reset for final TX flops in all upartitions."},
#else
{2, 2, 0x0000000000000000, "RW", "dq_iobufactdig", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "cc1_iobufactdig", "IO buffer activate - CCC Digital\r\n"
"Bytelane 1 SW reset for final TX flops in all upartitions."},
#else
{1, 1, 0x0000000000000000, "RW", "cc1_iobufactdig", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cc0_iobufactdig", "IO buffer activate - DQ Digital\r\n"
"Bytelane 1 SW reset for final TX flops in all upartitions."},
#else
{0, 0, 0x0000000000000000, "RW", "cc0_iobufactdig", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo475[] = {{"IOBUFACT_DIG", "", 0x0000001C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields476[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_spid_init_complete", "SPID init complete"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_spid_init_complete", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo476[] = {{"CH0_SPIDIC", "", 0x00000020, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields477[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{9, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{9, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "early_dqen", "Early DQ Enable Register"},
#else
{8, 8, 0x0000000000000000, "RW", "early_dqen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "dqdrvenbph1", "Data mask drive enable"},
#else
{6, 7, 0x0000000000000000, "RW", "dqdrvenbph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "dqdrvenbpream1", "This is the two write preambles enable"},
#else
{4, 5, 0x0000000000000000, "RW", "dqdrvenbpream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "dqdrvenblastph", "Last phase - DQ Drive Enable"},
#else
{2, 3, 0x0000000000000000, "RW", "dqdrvenblastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "dqdrvenbpream0", "This is the DQS configuration for first phase \r\n"
"(2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{0, 1, 0x0000000000000000, "RW", "dqdrvenbpream0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo477[] = {{"WRDQCTL", "", 0x00000024, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields478[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "dqsdrvenbph1", "Phase 1 - DQS Drive enable"},
#else
{30, 31, 0x0000000000000000, "RW", "dqsdrvenbph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "dqsdrvenbpream1", "Preamble 1 - DQS drive enable"},
#else
{28, 29, 0x0000000000000000, "RW", "dqsdrvenbpream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "dqsdrvenblastph", "Last phase - DQS Drive enable"},
#else
{26, 27, 0x0000000000000000, "RW", "dqsdrvenblastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "dqsdrvenbpream0", "Preamble 0 - DQS Drive enable"},
#else
{24, 25, 0x0000000000000000, "RW", "dqsdrvenbpream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "dmdrven", "Data mask drive enable"},
#else
{20, 20, 0x0000000000000000, "RW", "dmdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "wrpream0en", "This is the two write preambles enable"},
#else
{19, 19, 0x0000000000000000, "RW", "wrpream0en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{18, 18, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000003, "RW", "dqsdrvenbidle", "DQS Drive Enable - Idle"},
#else
{16, 17, 0x0000000000000003, "RW", "dqsdrvenbidle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "dqsdataph1", "This is the DQS configuration for first phase \r\n"
"(2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{14, 15, 0x0000000000000000, "RW", "dqsdataph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "dqsdatapream1", "This is the DQS configuration during second preamble\r\n"
"(2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{12, 13, 0x0000000000000000, "RW", "dqsdatapream1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "dqsdatalastph", "This is the DQS configuration for last phase \r\n"
"(2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{10, 11, 0x0000000000000000, "RW", "dqsdatalastph", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "dqsdatapream0", "This is the DQS configuration during first preamble\r\n"
"(2'b01-dqs_hi_lo,2'b00-dqs_lo_lo,2'b11-dqs_hi_hi)."},
#else
{8, 9, 0x0000000000000000, "RW", "dqsdatapream0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "wrcmd2dqsstart", "Write command to DQS start delay"},
#else
{0, 5, 0x0000000000000000, "RW", "wrcmd2dqsstart", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo478[] = {{"WRDQSCTL", "", 0x00000028, 15, 0x00000000FFFFFFFF, 0x0000000000030000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields479[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "rdcmd2rdvld_plus1sel", "Read command 2 read valid plus 1 sel."},
#else
{12, 14, 0x0000000000000000, "RW", "rdcmd2rdvld_plus1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "earlyrdvld", "This is the early read valid configuration register \r\n"
"0: no early read valid geneartion\r\n"
"1/2/3/4: 1/2/3/4/spidclk early valid\r\n"
" >4: Illegal"},
#else
{8, 10, 0x0000000000000000, "RW", "earlyrdvld", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdcmd2rdvld", "This is the read command to read valid register.\r\n"
"This is in terms of spidclk."},
#else
{0, 5, 0x0000000000000000, "RW", "rdcmd2rdvld", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo479[] = {{"RDVLDCTL", "", 0x0000002C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields480[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{14, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "dqx_rk2rkswitch_dlyen", "Adds an extra 1x clock of delay between rdptr freeze and dq/dqs PI code change during write based rk2rk switch.\r\n"
"1: Add 1 extra ref1xclk of delay \r\n"
"0: No delay"},
#else
{13, 13, 0x0000000000000000, "RW", "dqx_rk2rkswitch_dlyen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "rcv_rk2rkswitch_dlyen", "Adds an extra 1x clock of delay between rdptr freeze and rcven PI code change during read based rk2rk switch.\r\n"
"1: Add 1 extra ref1xclk of delay \r\n"
"0: No delay"},
#else
{12, 12, 0x0000000000000000, "RW", "rcv_rk2rkswitch_dlyen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_iodrven", "pushing out the update of rank information  for IO driver enable control 1 more 2xclk if set to 1."},
#else
{10, 10, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_iodrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrden", "pushing out the update of rank information for Tx rden control 1 more 2xclk if set to 1."},
#else
{9, 9, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrcven", "pushing out the update of rank information for Tx RCVEN control 1 more 2xclk if set to 1."},
#else
{8, 8, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txrcven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "rk2rken_txdqs_pi", "Rank2Rank Picode switching enabled for TxDLL DQS picodes (1- rk2rk picode switching enabled; 0 - disabled)"},
#else
{7, 7, 0x0000000000000000, "RW", "rk2rken_txdqs_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "rk2rken_txdq_pi", "Rank2Rank Picode switching enabled for TxDLL DQ picodes (1- rk2rk picode switching enabled; 0 - disabled)"},
#else
{6, 6, 0x0000000000000000, "RW", "rk2rken_txdq_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 5, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 5, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rk2rken_rxdq_pi", "Rank2Rank Picode switching enabled for RxDLL DQS picodes (1- rk2rk picode switching enabled; 0 - disabled)"},
#else
{1, 1, 0x0000000000000000, "RW", "rk2rken_rxdq_pi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rk2rken_txrcven", "Rank2Rank Picode switching enabled for TxDLL rcven picodes (1- rk2rk picode switching enabled; 0 - disabled)"},
#else
{0, 0, 0x0000000000000000, "RW", "rk2rken_txrcven", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo480[] = {{"RK2RKCTL1", "", 0x00000030, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields481[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rk2rkdrvenbcode_3rd", "This is the pattern for third 1x clock of rk2rk_rden\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value).\r\n"
"Applicable for both DQ and DQS drvenb."},
#else
{28, 31, 0x0000000000000000, "RW", "rk2rkdrvenbcode_3rd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rk2rkrdencode_3rd", "This is the pattern for third 1x clock of rk2rk_rden\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value)."},
#else
{24, 27, 0x0000000000000000, "RW", "rk2rkrdencode_3rd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_rxdq", "pushing out the update of rank information 1 more 2xclk if set to 1."},
#else
{23, 23, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_rxdq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdqs", "pushing out the update of rank information 1 more 2xclk if set to 1."},
#else
{22, 22, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdq", "pushing out the update of rank information 1 more 2xclk if set to 1."},
#else
{21, 21, 0x0000000000000000, "RW", "rk2rkmio2xclkpushout_txdq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "wrcmd2rkchglatency", "This is the pattern for second 1x clock of rk2rk_iodrvenb\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value)."},
#else
{15, 20, 0x0000000000000000, "RW", "wrcmd2rkchglatency", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{14, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "rdcmd2rkchglatency", "This is the pattern for first 1x clock of rk2rk_iodrvenb\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value)."},
#else
{8, 13, 0x0000000000000000, "RW", "rdcmd2rkchglatency", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "rk2rkdrvenbcode_2nd", "This is the pattern for second 1x clock of rk2rk_rden\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value).\r\n"
"Applicable for both DQ and DQS drvenb."},
#else
{6, 7, 0x0000000000000000, "RW", "rk2rkdrvenbcode_2nd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rk2rkdrvenbcode_1st", "This is the pattern for first 1x clock of rk2rk_rden\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value).\r\n"
"Applicable for both DQ and DQS drvenb."},
#else
{4, 5, 0x0000000000000000, "RW", "rk2rkdrvenbcode_1st", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rk2rkrdencode_2nd", "This is the pattern for second 1x clock of rk2rk_rden\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value)."},
#else
{2, 3, 0x0000000000000000, "RW", "rk2rkrdencode_2nd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "rk2rkrdencode_1st", "This is the pattern for first 1x clock of rk2rk_rden\r\n"
"(bit[0] - 1xhigh phase value, bit[1] - 1xlow phase value)."},
#else
{0, 1, 0x0000000000000000, "RW", "rk2rkrdencode_1st", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo481[] = {{"RK2RKCTL0", "", 0x00000034, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields482[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RW", "rxodtsegovrval", "Receive ODT segment enable override value."},
#else
{29, 31, 0x0000000000000000, "RW", "rxodtsegovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "rxodtsegovrsel", "Receive ODT segment enable override select.\r\n"
"0= Dynamic  control\r\n"
"1= Static  control"},
#else
{28, 28, 0x0000000000000000, "RW", "rxodtsegovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 27, 0x0000000000000000, "RW", "odtsegenrdptroffset", "Receive ODT segment enable read pointer offset."},
#else
{23, 27, 0x0000000000000000, "RW", "odtsegenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 22, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "rxodtsegtwohot", "This is the RXODTSEGEN one hot enable\r\n"
"0- rxodtsegen: 001->010->100\r\n"
"1-rxodtsegen: 011->110->101"},
#else
{21, 21, 0x0000000000000000, "RW", "rxodtsegtwohot", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 20, 0x0000000000000000, "RW", "rxodtseglenbl4", "This is the receive ODT segment enable length configuration register.\r\n"
"It's in number of 1x clocks."},
#else
{15, 20, 0x0000000000000000, "RW", "rxodtseglenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RW", "rxodtsegpst1", "This is the receive ODT segment enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{13, 14, 0x0000000000000000, "RW", "rxodtsegpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 12, 0x0000000000000000, "RW", "rxodtsegpre1", "This is the receive ODT segment enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{11, 12, 0x0000000000000000, "RW", "rxodtsegpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 10, 0x0000000000000000, "RW", "rxodtsegpst0", "This is the receive ODT segment enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{9, 10, 0x0000000000000000, "RW", "rxodtsegpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "rxodtsegpre0", "This is the receive ODT segment enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{7, 8, 0x0000000000000000, "RW", "rxodtsegpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdcmd2rxodtseg", "This is the receive ODT segment enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "rdcmd2rxodtseg", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo482[] = {{"RXODTSEGCTL", "", 0x00000038, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields483[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RW", "odtenrdptroffset", "This is receive ODT enable read pointer offset."},
#else
{27, 31, 0x0000000000000000, "RW", "odtenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "dqsrxodtenovrval", "Rx DQS odt enable override value - DQ BL0 lane \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{26, 26, 0x0000000000000000, "RW", "dqsrxodtenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "dqsrxodtenovrsel", "Rx DQS odt enable override select- DQ BL0 lane \r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{25, 25, 0x0000000000000000, "RW", "dqsrxodtenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "rxodtenovrval", "Receive ODT enable override value. \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{24, 24, 0x0000000000000000, "RW", "rxodtenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rxodtenovrsel", "Receive ODT enable override select.\r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{23, 23, 0x0000000000000000, "RW", "rxodtenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 22, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "rxodtenlenbl4", "This is the receive ODT enable length configuration register.\r\n"
"It's in number of 1x clocks."},
#else
{16, 21, 0x0000000000000000, "RW", "rxodtenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "rxodtenpst1", "This is the receive ODT enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{14, 15, 0x0000000000000000, "RW", "rxodtenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "rxodtenpre1", "This is the receive ODT enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{12, 13, 0x0000000000000000, "RW", "rxodtenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "rxodtenpst0", "This is the receive ODT enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{10, 11, 0x0000000000000000, "RW", "rxodtenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "rxodtenpre0", "This is the receive ODT enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{8, 9, 0x0000000000000000, "RW", "rxodtenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdcmd2rxodten", "This is the receive ODT enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "rdcmd2rxodten", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo483[] = {{"RXODTCTL", "", 0x0000003C, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields484[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "ch0_drx_rcvsmpl", "AFE status register - RCVSMPL - CCC0"},
#else
{31, 31, 0x0000000000000000, "RO", "ch0_drx_rcvsmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO", "ch1_drx_rcvsmpl", "AFE status register - RCVSMPL - CCC1"},
#else
{30, 30, 0x0000000000000000, "RO", "ch1_drx_rcvsmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "ecc_drx_rcvsmpl", "AFE status register - RCVSMPL - ECC"},
#else
{29, 29, 0x0000000000000000, "RO", "ecc_drx_rcvsmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RO", "drx_cmn_bonus", "AFE status register - Bonus"},
#else
{28, 28, 0x0000000000000000, "RO", "drx_cmn_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "drx_rcvenflopbypass", "DQS counter flop override"},
#else
{27, 27, 0x0000000000000000, "RW", "drx_rcvenflopbypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "drx_dqscountrstb", "DQS counter reset"},
#else
{26, 26, 0x0000000000000000, "RW", "drx_dqscountrstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "rcvenovrval", "Receive enable override value. \r\n"
"0: De-assert receive enable \r\n"
"1: Assert receive enable"},
#else
{25, 25, 0x0000000000000000, "RW", "rcvenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "rcvenovrsel", "Receive enable override select.\r\n"
"0= Dynamic RCVEN control\r\n"
"1= Static RCVEN control"},
#else
{24, 24, 0x0000000000000000, "RW", "rcvenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "rcvenlenbl4", "This is the receive enable length(number of 1x clock) configuration register."},
#else
{16, 21, 0x0000000000000000, "RW", "rcvenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "rcvenpst1", "This is the receive enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{14, 15, 0x0000000000000000, "RW", "rcvenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "rcvenpre1", "This is the receive enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{12, 13, 0x0000000000000000, "RW", "rcvenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "rcvenpst0", "This is the receive enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{10, 11, 0x0000000000000000, "RW", "rcvenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "rcvenpre0", "This is the receive enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{8, 9, 0x0000000000000000, "RW", "rcvenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdcmd2rcven", "This is the receive enable latency configuration register."},
#else
{0, 5, 0x0000000000000000, "RW", "rdcmd2rcven", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo484[] = {{"RCVENCTL", "", 0x00000040, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields485[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RW", "diffampenrdptroffset", "Differential amplifier read pointer offset control."},
#else
{27, 31, 0x0000000000000000, "RW", "diffampenrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "dqsdiffampenovrval", "Override value for DQS Diffamp enable - DQ Lane"},
#else
{26, 26, 0x0000000000000000, "RW", "dqsdiffampenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "dqsdiffampenovrsel", "Override select for DQS Diffamp enable - DQ Lane"},
#else
{25, 25, 0x0000000000000000, "RW", "dqsdiffampenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "dqdmdiffampenovrval", "Override value for DQ/DM Diffamp enable - DQ Lane"},
#else
{24, 24, 0x0000000000000000, "RW", "dqdmdiffampenovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "dqdmdiffampenovrsel", "Override select for DQ/DM Diffamp enable - DQ Lane"},
#else
{23, 23, 0x0000000000000000, "RW", "dqdmdiffampenovrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "diffampenpst1", "This is the diffamp enable configuration register - postamble 1 -  new(rise & fall). \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{21, 22, 0x0000000000000000, "RW", "diffampenpst1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW", "diffampenpre1", "This is the diffamp enable configuration register - preamble 1(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{19, 20, 0x0000000000000000, "RW", "diffampenpre1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 18, 0x0000000000000000, "RW", "diffampenpst0", "This is the diffamp enable configuration register - postamble 0 - new(rise & fall)\r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{17, 18, 0x0000000000000000, "RW", "diffampenpst0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 16, 0x0000000000000000, "RW", "diffampenpre0", "This is the diffamp enable configuration register - preamble 0(rise & fall) \r\n"
"00 - Rise & Fall - Low & Low\r\n"
"01 - Rise & Fall - High & Low\r\n"
"10 - Rise & Fall - Low & High\r\n"
"11 - Rise & Fall - High & High"},
#else
{15, 16, 0x0000000000000000, "RW", "diffampenpre0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{14, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "diffampenlenbl4", "This is the diffamp enable length(number of 1x clock) configuration register."},
#else
{8, 13, 0x0000000000000000, "RW", "diffampenlenbl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdcmd2diffampen", "This is the Diffamp enable latency register."},
#else
{0, 5, 0x0000000000000000, "RW", "rdcmd2diffampen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo485[] = {{"DIFFAMPCTL", "", 0x00000044, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields486[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{28, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "cc0_wrlvl", "Write Levelization enable - CC0 Lane"},
#else
{27, 27, 0x0000000000000000, "RW", "cc0_wrlvl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "cc1_wrlvl", "Write Levelization enable - CC1 Lane"},
#else
{26, 26, 0x0000000000000000, "RW", "cc1_wrlvl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "bl_wrlvl", "Write Levelization enable - DQ Byte Lane"},
#else
{25, 25, 0x0000000000000000, "RW", "bl_wrlvl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 24, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO", "wrlvl_sample_b1", "DQTRAINSTS - WRLVL sampling from all DQ bit lanes of Bytelane 1 - Not Used"},
#else
{16, 23, 0x0000000000000000, "RO", "wrlvl_sample_b1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "wrlvl_sample_b0", "DQTRAINSTS - WRLVL sampling from all DQ bit lanes of Bytelane 0"},
#else
{8, 15, 0x0000000000000000, "RO", "wrlvl_sample_b0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "wrlvl_and_sample_b1", "DQTRAINSTS - WRLVL Byte1 sample AND combination - Not Used"},
#else
{3, 3, 0x0000000000000000, "RO", "wrlvl_and_sample_b1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO", "wrlvl_and_sample_b0", "DQTRAINSTS - WRLVL Byte0 sample AND combination"},
#else
{2, 2, 0x0000000000000000, "RO", "wrlvl_and_sample_b0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "wrlvl_or_sample_b1", "DQTRAINSTS - WRLVL Byte1 sample OR combination"},
#else
{1, 1, 0x0000000000000000, "RO", "wrlvl_or_sample_b1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "wrlvl_or_sample_b0", "DQTRAINSTS - WRLVL Byte0 sample OR combination"},
#else
{0, 0, 0x0000000000000000, "RO", "wrlvl_or_sample_b0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo486[] = {{"WRLVL", "", 0x00000048, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields487[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dynreadsiggrpen", "Enable Dynamic SIGGRP 2x clock control. 1= SIGGRPEN  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SIGGRPEN"},
#else
{19, 19, 0x0000000000000000, "RW", "dynreadsiggrpen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dynreadref2xclken", "Enable Dynamic REF2XCLK control. 1= ref2xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF2XCLKEN"},
#else
{18, 18, 0x0000000000000000, "RW", "dynreadref2xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dynreadref1xclken", "Enable Dynamic REF1XCLK read clock gating. 1= ref1xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF1XCLKEN"},
#else
{17, 17, 0x0000000000000000, "RW", "dynreadref1xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynreadspidclken", "Enable Dynamic SPIDCLK read clock gating. 1= spidclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SPIDCLKEN"},
#else
{16, 16, 0x0000000000000000, "RW", "dynreadspidclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "read_stoprden", "This is the delay in terms of clocks the dven is disabled before clock gated."},
#else
{12, 14, 0x0000000000000000, "RW", "read_stoprden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "read_startrden", "This is the delay in terms of clocks the drven is enabled, once wrcmd/rdcmd is received."},
#else
{8, 10, 0x0000000000000000, "RW", "read_startrden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "readclkgate_maxcntr", "Clock Gating register : IDLE timer counter max value for clock gating on tx/rx . Counter timeout based on last WRCMD/RDCMD received. 6 bits are good enough since it increments in spidclk."},
#else
{0, 5, 0x000000000000003F, "RW", "readclkgate_maxcntr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo487[] = {{"CLKGATERDCTL", "", 0x0000004C, 11, 0x00000000FFFFFFFF, 0x000000000000003F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields488[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dynwritesiggrpen", "Enable Dynamic SIGGRP 2x clock control. 1= SIGGRPEN  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SIGGRPEN"},
#else
{19, 19, 0x0000000000000000, "RW", "dynwritesiggrpen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dynwriteref2xclken", "Enable Dynamic REF2XCLK control. 1= ref2xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF2XCLKEN"},
#else
{18, 18, 0x0000000000000000, "RW", "dynwriteref2xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dynwriteref1xclken", "Enable Dynamic REF1XCLK Tx(write) clock gating. 1= ref1xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF1XCLKEN"},
#else
{17, 17, 0x0000000000000000, "RW", "dynwriteref1xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynwritespidclken", "Enable Dynamic SPIDCLK Tx(write) clock gating. 1= spidclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SPIDCLKEN"},
#else
{16, 16, 0x0000000000000000, "RW", "dynwritespidclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "write_stopdrv", "This is the delay in terms of clocks the dven is disabled before clock gated."},
#else
{12, 14, 0x0000000000000000, "RW", "write_stopdrv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "write_startdrv", "This is the delay in terms of clocks the drven is enabled, once wrcmd/rdcmd is received."},
#else
{8, 10, 0x0000000000000000, "RW", "write_startdrv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "writeclkgate_maxcntr", "Clock Gating register : IDLE timer counter max value for clock gating on tx/rx . Counter timeout based on last WRCMD/RDCMD received. 6 bits are good enough since it increments in spidclk."},
#else
{0, 5, 0x000000000000003F, "RW", "writeclkgate_maxcntr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo488[] = {{"CLKGATEWRCTL", "", 0x00000050, 11, 0x00000000FFFFFFFF, 0x000000000000003F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields489[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "ldoffdyncg_en", "Enable Dynamic LDO FF clock control. 1= LDOFF clock controlled by dynamic clock gating logic; 0 = Clock gating disabled"},
#else
{20, 20, 0x0000000000000000, "RW", "ldoffdyncg_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dynsiggrpen", "Enable Dynamic SIGGRP 2x clock control. 1= SIGGRPEN  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SIGGRPEN"},
#else
{19, 19, 0x0000000000000000, "RW", "dynsiggrpen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dynref2xclken", "Enable Dynamic REF2XCLK control. 1= ref2xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF2XCLKEN"},
#else
{18, 18, 0x0000000000000000, "RW", "dynref2xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dynref1xclken", "Enable Dynamic REF1XCLK global clock gating. 1= ref1xclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled REF1XCLKEN"},
#else
{17, 17, 0x0000000000000000, "RW", "dynref1xclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dynspidclken", "Enable Dynamic SPIDCLK global clock gating. 1= spidclken  controlled by the dynamic clock gating logic (DYNDLLFSM), 0= Statically-controlled SPIDCLKEN"},
#else
{16, 16, 0x0000000000000000, "RW", "dynspidclken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{9, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000007, "RW", "ldoffclkgate_maxcntr", "Clock Gating register : IDLE timer counter max value for clock gating on LDO FF . Counter timeout based on last datavalid recieved."},
#else
{6, 8, 0x0000000000000007, "RW", "ldoffclkgate_maxcntr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "clkgate_maxcntr", "Clock Gating register : IDLE timer counter max value for clock gating on tx/rx . Counter timeout based on last WRCMD/RDCMD received. 6 bits are good enough since it increments in spidclk."},
#else
{0, 5, 0x000000000000003F, "RW", "clkgate_maxcntr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo489[] = {{"CLKGATECTL", "", 0x00000054, 9, 0x00000000FFFFFFFF, 0x00000000000001FF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields490[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp03dbsel", "Deadband select for sig group 3 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp03dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp03rdptroffset", "Read pointer offset for sig group 3 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp03rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp03picode", "PI code for sig group 3 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp03picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo490[] = {{"TXDLLSIGGRP3CTL", "", 0x00000058, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields491[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp02dbsel", "Deadband select for sig group 2 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp02dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp02rdptroffset", "Read pointer offset for sig group 2 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp02rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp02picode", "PI code for sig group 2 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp02picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo491[] = {{"TXDLLSIGGRP2CTL", "", 0x0000005C, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields492[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp01dbsel", "Deadband select for sig group 1 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp01dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp01rdptroffset", "Read pointer offset for sig group 1 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp01rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp01picode", "PI code for sig group 1 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp01picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo492[] = {{"TXDLLSIGGRP1CTL", "", 0x00000060, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields493[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp00dbsel", "Deadband select for sig group 0 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "txdll_rk0siggrp00dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp00rdptroffset", "Read pointer offset for sig group 0 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "txdll_rk0siggrp00rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp00picode", "PI code for sig group 0 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_rk0siggrp00picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo493[] = {{"TXDLLSIGGRP0CTL", "", 0x00000064, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields494[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "lvl_bl0_weakpupstatic", "Weak Pull Up Control - CC Lane - UNUSED in BXTP"},
#else
{30, 30, 0x0000000000000000, "RW", "lvl_bl0_weakpupstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "lvl_bl0_weakpup", "Weak Pull Up Control - CC Lane - UNUSED in BXTP"},
#else
{24, 29, 0x0000000000000000, "RW", "lvl_bl0_weakpup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "lvl_bl0_weakpdnstatic", "Weak Pull Down Control - CC Lane - UNUSED in BXTP"},
#else
{22, 22, 0x0000000000000000, "RW", "lvl_bl0_weakpdnstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "lvl_bl0_weakpdn", "Weak Pull Down Control - CC Lane - UNUSED in BXTP"},
#else
{16, 21, 0x0000000000000000, "RW", "lvl_bl0_weakpdn", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "lvl_bl1_weakpupstatic", "Weak Pull Up Control static bit for DQS - DQ Lane - UNUSED in BXTP"},
#else
{14, 14, 0x0000000000000000, "RW", "lvl_bl1_weakpupstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "lvl_bl1_weakpup", "Weak Pull Up Control code for DQS - DQ Lane - UNUSED in BXTP"},
#else
{8, 13, 0x0000000000000000, "RW", "lvl_bl1_weakpup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "lvl_bl1_weakpdnstatic", "Weak Pull Down Control static bit for DQS - DQ Lane - UNUSED in BXTP"},
#else
{6, 6, 0x0000000000000000, "RW", "lvl_bl1_weakpdnstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lvl_bl1_weakpdn", "Weak Pull Down Control code for DQS - DQ Lane - UNUSED in BXTP"},
#else
{0, 5, 0x0000000000000000, "RW", "lvl_bl1_weakpdn", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo494[] = {{"WKPUPPDNCTL", "", 0x00000068, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields495[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000007, "RW", "dtx_cc0_drvsegen", "Segment enable for CC buffer. Used for per leg testing in HVM"},
#else
{28, 30, 0x0000000000000007, "RW", "dtx_cc0_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000007, "RW", "tx_cc0_drvsegen", "Segment enable for CC buffer. Used for per leg testing in HVM"},
#else
{24, 26, 0x0000000000000007, "RW", "tx_cc0_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000007, "RW", "dtx_cc1_drvsegen", "Segment enable for CC buffer. Used for per leg testing in HVM"},
#else
{20, 22, 0x0000000000000007, "RW", "dtx_cc1_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000007, "RW", "tx_cc1_drvsegen", "Segment enable for CC buffer. Used for per leg testing in HVM"},
#else
{16, 18, 0x0000000000000007, "RW", "tx_cc1_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000001, "RW", "rxdll_bl0_picapsel", "set cap tuning for pi"},
#else
{12, 14, 0x0000000000000001, "RW", "rxdll_bl0_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000001, "RW", "rxdll_bl1_picapsel", "set cap tuning for pi  - UNUSED in BXTP"},
#else
{8, 10, 0x0000000000000001, "RW", "rxdll_bl1_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000001, "RW", "txdll_picapsel", "set cap tuning for pi"},
#else
{4, 6, 0x0000000000000001, "RW", "txdll_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo495[] = {{"AFEMISC1", "", 0x0000006C, 15, 0x00000000FFFFFFFF, 0x0000000077771110}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields496[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "tx_cc0_techselect", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - CC0"},
#else
{26, 26, 0x0000000000000000, "RW", "tx_cc0_techselect", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000001, "RW", "tx_cc0_scompdelaysel", "Mux Select for DCOMP update block - 2'b00 or 2'b01 used values - CC0"},
#else
{24, 25, 0x0000000000000001, "RW", "tx_cc0_scompdelaysel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "tx_cc0_idlemode", "Disable idle mode logic = 1'b0, Enable = 1'b1 - CC0"},
#else
{23, 23, 0x0000000000000000, "RW", "tx_cc0_idlemode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rx_cc0_modelp4ddr4", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - CC0"},
#else
{22, 22, 0x0000000000000000, "RW", "rx_cc0_modelp4ddr4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "dtx_cc0_drvenstretch", "Channel 0 CCC CKP/N Stretches rising edge of drivenable to relax data to enable skew."},
#else
{20, 21, 0x0000000000000000, "RW", "dtx_cc0_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "tx_cc0_drvenstretch", "Channel 0 CA/CTL Stretches rising edge of drivenable to relax data to enable skew."},
#else
{18, 19, 0x0000000000000000, "RW", "tx_cc0_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "drx_cc0_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{16, 17, 0x0000000000000000, "RW", "drx_cc0_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "rx_cc0_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{14, 15, 0x0000000000000000, "RW", "rx_cc0_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x0000000000000000, "RW", "txdll_cc0_2xclkskewsel", "Channel 0 TxDLL Skew Compensator clock mux select (Clock Select [1:0]/Sync Div Reset[3:2])\r\n"
"Below select descriptions apply to both clock and div reset but each one can be controlled independently\r\n"
"00 - Default path - No addditional Skew added\r\n"
"01 - Skew Path 1 - Add ~30-40ps of delay to TxDLL 2xclk input based on PVT\r\n"
"11 - Skew Path 2 - Add ~90-100ps of delay to TxDLL 2xclk input based on PVT"},
#else
{10, 13, 0x0000000000000000, "RW", "txdll_cc0_2xclkskewsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "drx_cc0_rxcommonmode", "changes the common mode of receiver from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{9, 9, 0x0000000000000001, "RW", "drx_cc0_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "rx_cc0_rxcommonmode", "changes the common mode of receiver from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{8, 8, 0x0000000000000001, "RW", "rx_cc0_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "ch0_pdndrvstatic", "Static pull down code - DRV DQ"},
#else
{7, 7, 0x0000000000000001, "RW", "ch0_pdndrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "ch0_pdndrvstaticdqs", "Channel 0 Static pull down Enable - DRV CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{6, 6, 0x0000000000000001, "RW", "ch0_pdndrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "ch0_pdnodtstatic", "Static pull down code - ODT DQ"},
#else
{5, 5, 0x0000000000000001, "RW", "ch0_pdnodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "ch0_pdnodtstaticdqs", "Channel 0 Static pull down Enable - ODT CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{4, 4, 0x0000000000000001, "RW", "ch0_pdnodtstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "ch0_pupdrvstatic", "Static pull up code - DRV DQ"},
#else
{3, 3, 0x0000000000000001, "RW", "ch0_pupdrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ch0_pupdrvstaticdqs", "Channel 0 Static pull up code - DRV CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{2, 2, 0x0000000000000001, "RW", "ch0_pupdrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "ch0_pupodtstatic", "Static pull up code - ODT DQ"},
#else
{1, 1, 0x0000000000000001, "RW", "ch0_pupodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "ch0_pupodtstaticdqs", "Channel 0 Static pull up code - ODT CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{0, 0, 0x0000000000000001, "RW", "ch0_pupodtstaticdqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo496[] = {{"CH0_AFEMISC0", "", 0x00000070, 20, 0x00000000FFFFFFFF, 0x00000000010003FF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields497[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rx_cc0_bonus", "Bonus Bits - RX CC0"},
#else
{20, 23, 0x0000000000000000, "RW", "rx_cc0_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rx_cc1_bonus", "Bonus Bits - RX CC1"},
#else
{16, 19, 0x0000000000000000, "RW", "rx_cc1_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rx_ecc_bonus", "Bonus Bits - RX ECC"},
#else
{12, 15, 0x0000000000000000, "RW", "rx_ecc_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "lvl_cc0_bonus", "Bonus bits - LVL CC0"},
#else
{8, 11, 0x0000000000000000, "RW", "lvl_cc0_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "lvl_cc1_bonus", "Bonus bits - LVL CC1"},
#else
{4, 7, 0x0000000000000000, "RW", "lvl_cc1_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "lvl_ecc_bonus", "Bonus bits - LVL ECC"},
#else
{0, 3, 0x0000000000000000, "RW", "lvl_ecc_bonus", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo497[] = {{"AFEBONUS", "", 0x00000074, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields498[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "txdll_digobs1sel", "Digital observation select mux port 1"},
#else
{28, 31, 0x0000000000000000, "RW", "txdll_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "txdll_digobs0sel", "Digital observation select mux port 0"},
#else
{24, 27, 0x0000000000000000, "RW", "txdll_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rxdll_bl0_digobsen", "digital buf obs enable (1=enable;0=disable)"},
#else
{23, 23, 0x0000000000000000, "RW", "rxdll_bl0_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rxdll_bl1_digobsen", "digital buf obs enable (1=enable;0=disable)  - UNUSED in BXTP"},
#else
{22, 22, 0x0000000000000000, "RW", "rxdll_bl1_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "dtx_cc1_digobsen", "CCC Channel 1 digital buf obs enable (1=enable;0=disable)"},
#else
{21, 21, 0x0000000000000000, "RW", "dtx_cc1_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{20, 20, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "txdll_digobsen", "digital buf obs enable (1=enable;0=disable)"},
#else
{19, 19, 0x0000000000000000, "RW", "txdll_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "dtx_cc0_digobsen", "CCC Channel 1 digital buf obs enable (1=enable;0=disable)"},
#else
{18, 18, 0x0000000000000000, "RW", "dtx_cc0_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rxdll_bl1_digobs1sel", "Digital observation select mux port 1  - UNUSED in BXTP"},
#else
{12, 15, 0x0000000000000000, "RW", "rxdll_bl1_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rxdll_bl1_digobs0sel", "Digital observation select mux port 0  - UNUSED in BXTP"},
#else
{8, 11, 0x0000000000000000, "RW", "rxdll_bl1_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rxdll_bl0_digobs1sel", "Digital observation select mux port 1"},
#else
{4, 7, 0x0000000000000000, "RW", "rxdll_bl0_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_bl0_digobs0sel", "Digital observation select mux port 0"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_bl0_digobs0sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo498[] = {{"DIGOBSCTL1", "", 0x00000078, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields499[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "dtx_dq_digobsen", "ECC digital buf obs enable (1=enable;0=disable)"},
#else
{15, 15, 0x0000000000000000, "RW", "dtx_dq_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "rxdll_dq_digobsen", "digital buf obs enable (1=enable;0=disable)"},
#else
{11, 11, 0x0000000000000000, "RW", "rxdll_dq_digobsen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 10, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rxdll_dq_digobs1sel", "Digital observation select mux port 1"},
#else
{4, 7, 0x0000000000000000, "RW", "rxdll_dq_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_dq_digobs0sel", "Digital observation select mux port 0"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_dq_digobs0sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo499[] = {{"ECC_DIGOBSCTL1", "", 0x0000007C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields500[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "dtx_dq_digobs1sel", "ECC DQS Digital observation select mux port 1"},
#else
{13, 15, 0x0000000000000000, "RW", "dtx_dq_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 12, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000000, "RW", "dtx_dq_digobs0sel", "ECC DQS Digital observation select mux port 0"},
#else
{9, 11, 0x0000000000000000, "RW", "dtx_dq_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 8, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RW", "tx_dq_digobs1sel", "ECC DQ Digital observation select mux port 1"},
#else
{5, 7, 0x0000000000000000, "RW", "tx_dq_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 4, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x0000000000000000, "RW", "tx_dq_digobs0sel", "ECC DQ Digital observation select mux port 0"},
#else
{1, 3, 0x0000000000000000, "RW", "tx_dq_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 0, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo500[] = {{"ECC_DIGOBSCTL0", "", 0x00000080, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields501[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "dtx_cc0_digobs1sel", "Channel 0 CK Digital observation select mux port 1"},
#else
{28, 30, 0x0000000000000000, "RW", "dtx_cc0_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "dtx_cc0_digobs0sel", "Channel 0 CK Digital observation select mux port 0"},
#else
{24, 26, 0x0000000000000000, "RW", "dtx_cc0_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000000, "RW", "dtx_cc1_digobs1sel", "Channel 1 CK Digital observation select mux port 1"},
#else
{20, 22, 0x0000000000000000, "RW", "dtx_cc1_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RW", "dtx_cc1_digobs0sel", "Channel 1 CK Digital observation select mux port 0"},
#else
{16, 18, 0x0000000000000000, "RW", "dtx_cc1_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "tx_cc0_digobs1sel", "Channel 0 CA/CTL Digital observation select mux port 1"},
#else
{12, 14, 0x0000000000000000, "RW", "tx_cc0_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "tx_cc0_digobs0sel", "Channel 0 CA/CTL Digital observation select mux port 0"},
#else
{8, 10, 0x0000000000000000, "RW", "tx_cc0_digobs0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "tx_cc1_digobs1sel", "Channel 1 CA/CTL Digital observation select mux port 1"},
#else
{4, 6, 0x0000000000000000, "RW", "tx_cc1_digobs1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "tx_cc1_digobs0sel", "Channel 1 CA/CTL Digital observation select mux port 0"},
#else
{0, 2, 0x0000000000000000, "RW", "tx_cc1_digobs0sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo501[] = {{"DIGOBSCTL0", "", 0x00000084, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields502[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "rxdll_rxmuxsel", "enable strobe output from rx sdll.for each byte"},
#else
{24, 28, 0x0000000000000000, "RW", "rxdll_rxmuxsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "txdll_dllfloprstb", "TxDLL flop reset"},
#else
{21, 21, 0x0000000000000000, "RW", "txdll_dllfloprstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "rxdll_dllfloprstb", "RxDLL flop reset"},
#else
{20, 20, 0x0000000000000000, "RW", "rxdll_dllfloprstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "rxdll_bl_dqsouten", "enable strobe output from rx sdll.for each byte"},
#else
{18, 18, 0x0000000000000000, "RW", "rxdll_bl_dqsouten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "rxdll_bl_rxdllen", "Rx DLL enable"},
#else
{16, 16, 0x0000000000000000, "RW", "rxdll_bl_rxdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo502[] = {{"RXDLLCTL_DQBLDM", "", 0x00000088, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields503[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ecc_txdll_ref2xph0pien", "enable tx ref pi phase 0 enable for ECC Bytelane"},
#else
{1, 1, 0x0000000000000000, "RW", "ecc_txdll_ref2xph0pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_txdll_ref2xph0pien", "enable tx ref pi phase 0 enable for CC0 Bytelane"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_txdll_ref2xph0pien", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo503[] = {{"RXDLLCTL_CCBLDM", "", 0x0000008C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields504[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{18, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{18, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "txdll_cc0_mdllen", "MDLL enable"},
#else
{16, 16, 0x0000000000000000, "RW", "txdll_cc0_mdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "txdll_cc1_mdllen", "MDLL enable"},
#else
{15, 15, 0x0000000000000000, "RW", "txdll_cc1_mdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "ch0_txdll_siggrp03pien", "PI enable for sig group 3 rank 0"},
#else
{11, 11, 0x0000000000000000, "RW", "ch0_txdll_siggrp03pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch0_txdll_siggrp02pien", "PI enable for sig group 2 rank 0"},
#else
{10, 10, 0x0000000000000000, "RW", "ch0_txdll_siggrp02pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch0_txdll_siggrp01pien", "PI enable for sig group 1 rank 0"},
#else
{9, 9, 0x0000000000000000, "RW", "ch0_txdll_siggrp01pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ch0_txdll_siggrp00pien", "PI enable for sig group 0 rank 0"},
#else
{8, 8, 0x0000000000000000, "RW", "ch0_txdll_siggrp00pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch0_txdll_ref2xph180pien", "enable tx ref pi phase 180 enable"},
#else
{2, 2, 0x0000000000000000, "RW", "ch0_txdll_ref2xph180pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 0, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo504[] = {{"TXDLLCTL", "", 0x00000090, 14, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields505[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "txdll_ref2xph270picode", "pi code for ref pi phase 270 output"},
#else
{16, 23, 0x0000000000000000, "RW", "txdll_ref2xph270picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "txdll_ref2xph180picode", "pi code for ref pi phase 180 output"},
#else
{8, 15, 0x0000000000000000, "RW", "txdll_ref2xph180picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "txdll_ref2xph90picode", "pi code for ref pi phase 90 output"},
#else
{0, 7, 0x0000000000000000, "RW", "txdll_ref2xph90picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo505[] = {{"TXDLLREF2XCTL", "", 0x00000094, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields506[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "rxdll_rk1dqshipicode", "pi code for rx rising dqs edge - DQ Lane"},
#else
{24, 31, 0x0000000000000000, "RW", "rxdll_rk1dqshipicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "rxdll_rk1dqslopicode", "pi code for rx falling dqs edge - DQ Lane"},
#else
{16, 23, 0x0000000000000000, "RW", "rxdll_rk1dqslopicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo506[] = {{"RXDLLDQSRK1CTL", "", 0x00000098, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields507[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "rxdll_bl0_rk0dqshipicode", "pi code for rx rising dqs edge  - CC Lane"},
#else
{8, 15, 0x0000000000000000, "RW", "rxdll_bl0_rk0dqshipicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "rxdll_bl0_rk0dqslopicode", "pi code for rx falling dqs edge  - CC Lane"},
#else
{0, 7, 0x0000000000000000, "RW", "rxdll_bl0_rk0dqslopicode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo507[] = {{"RXDLLDQSRK0CTL", "", 0x0000009C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields508[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000020, "RW", "vref_dq_rxblvrefctrl", "ECC Rx vref decode signal for ECC bytelane Rx Vref circuit"},
#else
{24, 31, 0x0000000000000020, "RW", "vref_dq_rxblvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000020, "RW", "vref_dq_rxccvrefctrl", "ECC Rx vref decode signal for ECC bytelane Rx Vref circuit - UNUSED in BXTP"},
#else
{16, 23, 0x0000000000000020, "RW", "vref_dq_rxccvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000020, "RW", "vref_cc1_rxblvrefctrl", "Channel 1 Rx vref decode signal for the CC1 bl rx vref"},
#else
{8, 15, 0x0000000000000020, "RW", "vref_cc1_rxblvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000020, "RW", "vref_cc1_rxccvrefctrl", "Tx VREF vref decode signal - This RxVref was re-purposed for the TxVref Control per HSD#1204294748"},
#else
{0, 7, 0x0000000000000020, "RW", "vref_cc1_rxccvrefctrl", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo508[] = {{"VREFCTL2", "", 0x000000A0, 4, 0x00000000FFFFFFFF, 0x0000000020202020}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields509[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "txvref_cmn_vrefbufen", "enable signal for the tx vref unity gain buffer"},
#else
{0, 0, 0x0000000000000001, "RW", "txvref_cmn_vrefbufen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo509[] = {{"VREFCTL1", "", 0x000000A4, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields510[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "vref_txlcompvrefctrl", "vref decode signal for the lcomp"},
#else
{24, 31, 0x0000000000000000, "RW", "vref_txlcompvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000020, "RW", "vref_cc0_rxblvrefctrl", "Channel 0 Rx vref decode signal for the CC0 bl rx vref"},
#else
{16, 23, 0x0000000000000020, "RW", "vref_cc0_rxblvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000020, "RW", "vref_cc0_rxccvrefctrl", "Channel 1 Rx vref decode signal for the CC0 cc rx vref"},
#else
{8, 15, 0x0000000000000020, "RW", "vref_cc0_rxccvrefctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "vref_dq_vrefcmctrl", "common mode select to choose between lpddr3;lpddr4"},
#else
{6, 7, 0x0000000000000000, "RW", "vref_dq_vrefcmctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "lvl_bl_vrefset", "vrefiobufact Set control - ECC Lane"},
#else
{5, 5, 0x0000000000000000, "RW", "lvl_bl_vrefset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "lvl_bl_vrefreset", "vrefiobufact Reset control - ECC Lane"},
#else
{4, 4, 0x0000000000000000, "RW", "lvl_bl_vrefreset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "lvl_cc1_vrefset", "vrefiobufact Set control - CCC1 Lane"},
#else
{3, 3, 0x0000000000000000, "RW", "lvl_cc1_vrefset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "lvl_cc1_vrefreset", "vrefiobufact Reset control - CCC1 Lane"},
#else
{2, 2, 0x0000000000000000, "RW", "lvl_cc1_vrefreset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lvl_cc0_vrefset", "vrefiobufact Set control - CCC0 Lane"},
#else
{1, 1, 0x0000000000000000, "RW", "lvl_cc0_vrefset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lvl_cc0_vrefreset", "vrefiobufact Reset control - CCC0 Lane"},
#else
{0, 0, 0x0000000000000000, "RW", "lvl_cc0_vrefreset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo510[] = {{"VREFCTL0", "", 0x000000A8, 10, 0x00000000FFFFFFFF, 0x0000000000202000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields511[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_dq_dq8rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_dq_dq8rxpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo511[] = {{"RXBL8PBDCTL", "", 0x000000AC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields512[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rxdll_dq_dq7rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{28, 31, 0x0000000000000000, "RW", "rxdll_dq_dq7rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rxdll_dq_dq6rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{24, 27, 0x0000000000000000, "RW", "rxdll_dq_dq6rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rxdll_dq_dq5rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{20, 23, 0x0000000000000000, "RW", "rxdll_dq_dq5rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rxdll_dq_dq4rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{16, 19, 0x0000000000000000, "RW", "rxdll_dq_dq4rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rxdll_dq_dq3rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{12, 15, 0x0000000000000000, "RW", "rxdll_dq_dq3rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rxdll_dq_dq2rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{8, 11, 0x0000000000000000, "RW", "rxdll_dq_dq2rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rxdll_dq_dq1rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{4, 7, 0x0000000000000000, "RW", "rxdll_dq_dq1rxpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rxdll_dq_dq0rxpbdcode", "Rx Per bit De-skew code for dq0 valid codes"},
#else
{0, 3, 0x0000000000000000, "RW", "rxdll_dq_dq0rxpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo512[] = {{"RXPBDBLCTL", "", 0x000000B0, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields513[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "rxdll_bl0_rxpbden", "Rx Per Bit De-skew enable (1=enable, 0=disable), 0 for cc always"},
#else
{23, 23, 0x0000000000000000, "RW", "rxdll_bl0_rxpbden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rxdll_bl1_rxpbden", "Rx Per Bit De-skew enable (1=enable, 0=disable) - UNUSED in BXTP"},
#else
{22, 22, 0x0000000000000000, "RW", "rxdll_bl1_rxpbden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 21, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 21, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "tx_cc0_pbdstaticlegen", "Per bit deskew enable - TX - CC Channel 0"},
#else
{3, 3, 0x0000000000000000, "RW", "tx_cc0_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "tx_cc1_pbdstaticlegen", "Per bit deskew enable - TX - CC Channel 1"},
#else
{2, 2, 0x0000000000000000, "RW", "tx_cc1_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "dtx_cc0_pbdstaticlegen", "Per bit deskew enable - DTX - CC Channel 0"},
#else
{1, 1, 0x0000000000000000, "RW", "dtx_cc0_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dtx_cc1_pbdstaticlegen", "Per bit deskew enable - DTX - Channel 1"},
#else
{0, 0, 0x0000000000000000, "RW", "dtx_cc1_pbdstaticlegen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo513[] = {{"TXPBDCTL1", "", 0x000000B4, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields514[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_bldm_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_bldm_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo514[] = {{"TXPBDRK0CTL1", "", 0x000000B8, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields515[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "dtx_dq_dqsbpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "dtx_dq_dqsbpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "dtx_dq_dqspbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "dtx_dq_dqspbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo515[] = {{"TXPBDRK0CTL0", "", 0x000000BC, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields516[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "tx_bldq7_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{24, 28, 0x0000000000000000, "RW", "tx_bldq7_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_bldq6_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_bldq6_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "tx_bldq5_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "tx_bldq5_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_bldq4_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_bldq4_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo516[] = {{"TXPBDBLCTL1", "", 0x000000C0, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields517[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "tx_bldq3_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{24, 28, 0x0000000000000000, "RW", "tx_bldq3_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "tx_bldq2_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{16, 20, 0x0000000000000000, "RW", "tx_bldq2_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "tx_bldq1_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{8, 12, 0x0000000000000000, "RW", "tx_bldq1_txpbdcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "tx_bldq0_txpbdcode", "Tx Per Bit De-skew code for dq0 valid codes"},
#else
{0, 4, 0x0000000000000000, "RW", "tx_bldq0_txpbdcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo517[] = {{"TXPBDBLCTL0", "", 0x000000C4, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields518[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000001, "RW", "rx_dq_ampoffseten", "ECC Offset cancellation enable for Rx (not used for cc)"},
#else
{23, 23, 0x0000000000000001, "RW", "rx_dq_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rx_cc0_ampoffseten", "CCC Channel 0 Offset cancellation enable for Rx (not used for cc)"},
#else
{22, 22, 0x0000000000000000, "RW", "rx_cc0_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000001, "RW", "drx_dq_ampoffseten", "ECC DQS Offset cancellation enable for Rx (1=enable, 0=disable)"},
#else
{21, 21, 0x0000000000000001, "RW", "drx_dq_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "rx_cc1_ampoffseten", "CCC Channel 1 Offset cancellation enable for Rx (1=enable, 0=disable)"},
#else
{20, 20, 0x0000000000000000, "RW", "rx_cc1_ampoffseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "drx_ccck0_ampoffset", "tuning bits for offset cancellation (can be tied off for CC)"},
#else
{16, 19, 0x0000000000000000, "RW", "drx_ccck0_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rx_cc0_ampoffset", "tuning bits for offset cancellation (can be tied off for CC)"},
#else
{12, 15, 0x0000000000000000, "RW", "rx_cc0_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rx_cc1_ampoffset", "Offset cancellation code (DQS buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{8, 11, 0x0000000000000000, "RW", "rx_cc1_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rx_bldm_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{4, 7, 0x0000000000000000, "RW", "rx_bldm_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "drx_dq_ampoffset", "tuning bits for offset cancellation (can be tied off for CC)"},
#else
{0, 3, 0x0000000000000000, "RW", "drx_dq_ampoffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo518[] = {{"OFFSETCNCLCTRL1", "", 0x000000C8, 10, 0x00000000FFFFFFFF, 0x0000000000A00000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields519[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "rx_bldq0_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{28, 31, 0x0000000000000000, "RW", "rx_bldq0_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rx_bldq1_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{24, 27, 0x0000000000000000, "RW", "rx_bldq1_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rx_bldq2_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{20, 23, 0x0000000000000000, "RW", "rx_bldq2_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rx_bldq3_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{16, 19, 0x0000000000000000, "RW", "rx_bldq3_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rx_bldq4_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{12, 15, 0x0000000000000000, "RW", "rx_bldq4_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rx_bldq5_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{8, 11, 0x0000000000000000, "RW", "rx_bldq5_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rx_bldq6_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{4, 7, 0x0000000000000000, "RW", "rx_bldq6_ampoffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "rx_bldq7_ampoffset", "Offset cancellation code (DM/DQ buffers)\r\n"
"1111 -8\r\n"
"1110 -7\r\n"
"1101 -6\r\n"
"1100 -5\r\n"
"1011 -4\r\n"
"1010 -3\r\n"
"1001 -2\r\n"
"1000 -1\r\n"
"0000 +1\r\n"
"0001 +2\r\n"
"0010 +3\r\n"
"0011 +4\r\n"
"0100 +5\r\n"
"0101 +6\r\n"
"0110 +7\r\n"
"0111 +8"},
#else
{0, 3, 0x0000000000000000, "RW", "rx_bldq7_ampoffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo519[] = {{"OFFSETCNCLCTRL0", "", 0x000000CC, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields520[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "rx_dq_ampcombtune", "RX 2nd Stage Amp Fine Tune - ECC"},
#else
{30, 31, 0x0000000000000000, "RW", "rx_dq_ampcombtune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "rx_dq_ctletune", "RX 1st Stage Amp CTLE Fine Tune - ECC"},
#else
{28, 29, 0x0000000000000000, "RW", "rx_dq_ctletune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "rx_cc1_ampcombtune", "RX 2nd Stage Amp Fine Tune - CC1"},
#else
{26, 27, 0x0000000000000000, "RW", "rx_cc1_ampcombtune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "rx_cc1_ctletune", "RX 1st Stage Amp CTLE Fine Tune - CC1"},
#else
{24, 25, 0x0000000000000000, "RW", "rx_cc1_ctletune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "drx_cc1_casbiasctrl", "DRX Bias Command Control 00: Idle Mode Logic Disabled (LP3/4), Default Condition (DDR3L)   01: Idle Mode Logic Enabled (LP3/4), Illegal Condition (DDR3L)   10: Illegal Condition (ALL)   11: Illegal Condition (ALL)  - UNUSED"},
#else
{22, 23, 0x0000000000000000, "RW", "drx_cc1_casbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "drx_cc1_nbiasctrl", "DRX N Bias Control - BL"},
#else
{20, 21, 0x0000000000000000, "RW", "drx_cc1_nbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rx_cc1_ctleres", "CCC Channel 1 resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{18, 19, 0x0000000000000000, "RW", "rx_cc1_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rx_cc1_ctlecap", "CCC Channel 1 cap tuning;00 = 0.5pf;01 = 1pf;10 = 1.5pf;11 = 2pf"},
#else
{16, 17, 0x0000000000000000, "RW", "rx_cc1_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "rx_dq_ctlebiasctrl", "bias control for ctle amp\r\n"
"00 2kΩ          0.25xnom\r\n"
"01 1kΩ          0.4xnom\r\n"
"10 0.5kΩ     1xnom\r\n"
"11 0.25kΩ  1.7xnom"},
#else
{14, 15, 0x0000000000000000, "RW", "rx_dq_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "drx_dq_casbiasctrl", "DRX Bias Command Control 00: Idle Mode Logic Disabled (LP3/4), Default Condition (DDR3L)   01: Idle Mode Logic Enabled (LP3/4), Illegal Condition (DDR3L)   10: Illegal Condition (ALL)   11: Illegal Condition (ALL)"},
#else
{12, 13, 0x0000000000000000, "RW", "drx_dq_casbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000000, "RW", "drx_dq_ctlebiasctrl", "DRX Bias Ctle Control - CC"},
#else
{9, 11, 0x0000000000000000, "RW", "drx_dq_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 8, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "drx_dq_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{6, 7, 0x0000000000000000, "RW", "drx_dq_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "drx_dq_ctlecap", "cap tuning;00 = 0.5pf;01 = 1pf;10 = 1.5pf;11 = 2pf"},
#else
{4, 5, 0x0000000000000000, "RW", "drx_dq_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "drx_dq_nbiasctrl", "DRX N Bias Control - CC"},
#else
{2, 3, 0x0000000000000000, "RW", "drx_dq_nbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo520[] = {{"CTLECTL2", "", 0x000000D0, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields521[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "rx_dq_ctleen", "Enable CTLE for DQ (1=enable, 0=disable)"},
#else
{31, 31, 0x0000000000000000, "RW", "rx_dq_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000001, "RW", "drx_dq_biasen", "DRX Bias Enable - DQ"},
#else
{30, 30, 0x0000000000000001, "RW", "drx_dq_biasen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "drx_cc0_casbiasctrl", "DRX Bias Command Control 00: Idle Mode Logic Disabled (LP3/4), Default Condition (DDR3L)   01: Idle Mode Logic Enabled (LP3/4), Illegal Condition (DDR3L)   10: Illegal Condition (ALL)   11: Illegal Condition (ALL)  - UNUSED"},
#else
{28, 29, 0x0000000000000000, "RW", "drx_cc0_casbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "drx_cc0_nbiasctrl", "DRX N Bias Control - CC"},
#else
{26, 27, 0x0000000000000000, "RW", "drx_cc0_nbiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 25, 0x0000000000000000, "RW", "drx_bl0_ctlebiasctrl", "Config Register space has been reallocated for RxBIASEN ECO HSD#1404029255\r\n"
"DQ Rx BIASEN Static Override\r\n"
"drx_bl0_ctlebiasctrl[0] - Controls the override select for biasen\r\n"
"drx_bl0_ctlebiasctrl[1] - Controls the override value for biasen\r\n"
"drc_bl0_ctlebiasctrl[2] - Unused/Reserved"},
#else
{23, 25, 0x0000000000000000, "RW", "drx_bl0_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000001, "RW", "rx_cc0_ctleen", "Enable CTLE (not used for CC)"},
#else
{22, 22, 0x0000000000000001, "RW", "rx_cc0_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "rx_cc0_ctlebiasctrl", "bias control for ctle amp\r\n"
"00 2kΩ          0.25xnom\r\n"
"01 1kΩ          0.4xnom\r\n"
"10 0.5kΩ     1xnom\r\n"
"11 0.25kΩ  1.7xnom"},
#else
{20, 21, 0x0000000000000000, "RW", "rx_cc0_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rx_cc0_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{18, 19, 0x0000000000000000, "RW", "rx_cc0_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000001, "RW", "rx_cc0_ctlecap", "cap tuning;00 = 0.5pf;01 = 1pf;10 = 1.5pf;11 = 2pf"},
#else
{16, 17, 0x0000000000000001, "RW", "rx_cc0_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000001, "RW", "drx_dq_ctleen", "Enable CTLE for DQS (1=enable, 0=disable)"},
#else
{15, 15, 0x0000000000000001, "RW", "drx_dq_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "drx_bl1_ctlebiasctrl", "Config Register space has been reallocated for LDO MainDIG ECO HSD#1403935840\r\n"
"(Register was previously unused and unconnected)\r\n"
"LDO maindig driver enable override for mode switching logic. Asserting a given bit will override the driver enable input to the LDO maindig, imod_func_ldomaindig_cmn_*drven, to be always enabled\r\n"
"3'b??1 - DQ Channel 0 driver enable override (0 - No override, 1 - Always enable driver enable)\r\n"
"3'b?1? - DQ Channel 1 driver enable override (0 - No override, 1 - Always enable driver enable)\r\n"
"3'b1?? - CLK driver enable override (0 - No override, 1 - Always enable driver enable)"},
#else
{12, 14, 0x0000000000000000, "RW", "drx_bl1_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "rx_cc0_ampcombtune", "RX 2nd Stage Amp Fine Tune - CC0"},
#else
{10, 11, 0x0000000000000000, "RW", "rx_cc0_ampcombtune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "rx_cc0_ctletune", "RX 1st Stage Amp CTLE Fine Tune - CC0"},
#else
{8, 9, 0x0000000000000000, "RW", "rx_cc0_ctletune", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "drx_bl1_biasen", "DRX Bias Enable - BL - UNUSED IN BXTP"},
#else
{7, 7, 0x0000000000000001, "RW", "drx_bl1_biasen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "rx_cc1_ctleen", "CCC Channel 1 Enable CTLE for Rx (1=enable, 0=disable)"},
#else
{6, 6, 0x0000000000000001, "RW", "rx_cc1_ctleen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rx_cc1_ctlebiasctrl", "CCC Channel 1 bias control for ctle amp\r\n"
"00 2kΩ          0.25xnom\r\n"
"01 1kΩ          0.4xnom\r\n"
"10 0.5kΩ     1xnom\r\n"
"11 0.25kΩ  1.7xnom"},
#else
{4, 5, 0x0000000000000000, "RW", "rx_cc1_ctlebiasctrl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rx_bldm_ctleres", "Currently used for ODTMASK_EN (Previously used for resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm)"},
#else
{2, 3, 0x0000000000000000, "RW", "rx_bldm_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "rx_bldm_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{0, 1, 0x0000000000000001, "RW", "rx_bldm_ctlecap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo521[] = {{"CTLECTL1", "", 0x000000D4, 18, 0x00000000FFFFFFFF, 0x00000000404180C1}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields522[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "rx_bldq0_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{30, 31, 0x0000000000000000, "RW", "rx_bldq0_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "rx_bldq1_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{28, 29, 0x0000000000000000, "RW", "rx_bldq1_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "rx_bldq2_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{26, 27, 0x0000000000000000, "RW", "rx_bldq2_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "rx_bldq3_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{24, 25, 0x0000000000000000, "RW", "rx_bldq3_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "rx_bldq4_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{22, 23, 0x0000000000000000, "RW", "rx_bldq4_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "rx_bldq5_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{20, 21, 0x0000000000000000, "RW", "rx_bldq5_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rx_bldq6_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{18, 19, 0x0000000000000000, "RW", "rx_bldq6_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rx_bldq7_ctleres", "resistor tuning;00=0.5kohm;01=1kohm;10=1.5kohm;11=2kohm"},
#else
{16, 17, 0x0000000000000000, "RW", "rx_bldq7_ctleres", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000001, "RW", "rx_bldq0_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{14, 15, 0x0000000000000001, "RW", "rx_bldq0_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000001, "RW", "rx_bldq1_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{12, 13, 0x0000000000000001, "RW", "rx_bldq1_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000001, "RW", "rx_bldq2_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{10, 11, 0x0000000000000001, "RW", "rx_bldq2_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000001, "RW", "rx_bldq3_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{8, 9, 0x0000000000000001, "RW", "rx_bldq3_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000001, "RW", "rx_bldq4_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{6, 7, 0x0000000000000001, "RW", "rx_bldq4_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000001, "RW", "rx_bldq5_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{4, 5, 0x0000000000000001, "RW", "rx_bldq5_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000001, "RW", "rx_bldq6_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{2, 3, 0x0000000000000001, "RW", "rx_bldq6_ctlecap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "rx_bldq7_ctlecap", "cap tuning;00 = 0.1pf;01 = 0.2pf;10 = 0.3pf;11 = 0.4pf"},
#else
{0, 1, 0x0000000000000001, "RW", "rx_bldq7_ctlecap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo522[] = {{"CTLECTL0", "", 0x000000D8, 16, 0x00000000FFFFFFFF, 0x0000000000005555}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields523[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "tx_ecc_tcostaticlegen", "TX TCO enable - BL"},
#else
{31, 31, 0x0000000000000000, "RW", "tx_ecc_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{29, 30, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "tx_ecc_tcofall", "DQ TCO comp fall code - DQ Lane"},
#else
{24, 28, 0x000000000000001F, "RW", "tx_ecc_tcofall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "tx_ecc_tcorise", "DQ TCO comp rise code - DQ Lane"},
#else
{16, 20, 0x000000000000001F, "RW", "tx_ecc_tcorise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "tx_cc0_tcostaticlegen", "TX TCO enable - CC"},
#else
{15, 15, 0x0000000000000000, "RW", "tx_cc0_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "tx_cc0_tcofall", "DQ TCO comp fall code - CC Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "tx_cc0_tcofall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "tx_cc0_tcorise", "DQ TCO comp rise code - CC Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "tx_cc0_tcorise", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo523[] = {{"TCOCTL_DQCC", "", 0x000000DC, 10, 0x00000000FFFFFFFF, 0x000000001F1F1F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields524[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "dtx_dq_tcostaticlegen", "DTX TCO enable - BL"},
#else
{29, 29, 0x0000000000000000, "RW", "dtx_dq_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "dtx_dq_tcofalldqsb", "DQSB TCO comp fall code - DQ Lane"},
#else
{24, 28, 0x000000000000001F, "RW", "dtx_dq_tcofalldqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "dtx_dq_tcorisedqsb", "DQS TCO comp fall code - DQ Lane"},
#else
{16, 20, 0x000000000000001F, "RW", "dtx_dq_tcorisedqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "dtx_dq_tcofalldqs", "DQSB TCO comp rise code - DQ Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "dtx_dq_tcofalldqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "dtx_dq_tcorisedqs", "DQS TCO comp rise code - DQ Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "dtx_dq_tcorisedqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo524[] = {{"TCOCTL", "", 0x000000E0, 9, 0x00000000FFFFFFFF, 0x000000001F1F1F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields525[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 21, 0x0000000000000000, "RW", "txdll_rk0cke1siggrp06rdptroffset", "Read pointer offset for sig group CKE rank CH1"},
#else
{17, 21, 0x0000000000000000, "RW", "txdll_rk0cke1siggrp06rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 16, 0x0000000000000000, "RW", "txdll_rk0cke0siggrp06rdptroffset", "Read pointer offset for sig group CKE rank CH0"},
#else
{12, 16, 0x0000000000000000, "RW", "txdll_rk0cke0siggrp06rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 10, 0x0000000000000000, "RW", "txdll_rk1siggrp06rdptroffset", "Read pointer offset for sig group 6 rank 1"},
#else
{6, 10, 0x0000000000000000, "RW", "txdll_rk1siggrp06rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 5, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "txdll_rk0siggrp06rdptroffset", "Read pointer offset for sig group 6 rank 0"},
#else
{0, 4, 0x0000000000000000, "RW", "txdll_rk0siggrp06rdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo525[] = {{"TXDLLSIGGRP6CTL", "", 0x000000E4, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields526[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{28, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "rk1dqdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQDMDRV - RK1."},
#else
{24, 27, 0x0000000000000000, "RW", "rk1dqdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "rk0dqdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQDMDRV - RK0."},
#else
{20, 23, 0x0000000000000000, "RW", "rk0dqdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rk1dqsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{16, 19, 0x0000000000000000, "RW", "rk1dqsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rk0dqsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{12, 15, 0x0000000000000000, "RW", "rk0dqsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "rk1dqsdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{8, 11, 0x0000000000000000, "RW", "rk1dqsdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "rk0dqsdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{4, 7, 0x0000000000000000, "RW", "rk0dqsdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ckdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{0, 3, 0x0000000000000000, "RW", "ckdrvsecondrdportref2xrdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo526[] = {{"LDOCTL0", "", 0x000000E8, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields527[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{8, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "cssecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{4, 7, 0x0000000000000000, "RW", "cssecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "cmddrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{0, 3, 0x0000000000000000, "RW", "cmddrvsecondrdportref2xrdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo527[] = {{"LDOCTL1", "", 0x000000EC, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields528[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RW", "data0sel", "DRAM read data bit mux for DQ0. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{21, 23, 0x0000000000000000, "RW", "data0sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 20, 0x0000000000000000, "RW", "data1sel", "DRAM read data bit mux for DQ1. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{18, 20, 0x0000000000000000, "RW", "data1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 17, 0x0000000000000000, "RW", "data2sel", "DRAM read data bit mux for DQ2. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{15, 17, 0x0000000000000000, "RW", "data2sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "data3sel", "DRAM read data bit mux for DQ3. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{12, 14, 0x0000000000000000, "RW", "data3sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000000, "RW", "data4sel", "DRAM read data bit mux for DQ4. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{9, 11, 0x0000000000000000, "RW", "data4sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000000, "RW", "data5sel", "DRAM read data bit mux for DQ5. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{6, 8, 0x0000000000000000, "RW", "data5sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "data6sel", "DRAM read data bit mux for DQ6. \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{3, 5, 0x0000000000000000, "RW", "data6sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "data7sel", "DRAM read data bit mux for DQ7.  \r\n"
"This needs to be programmed based on the how DRAM data pins get swizzled at the DRAM package.\r\n"
"000:  Use DQ0\r\n"
"001:  Use DQ1\r\n"
"010:  Use DQ2\r\n"
"011:  Use DQ3\r\n"
"100:  Use DQ4\r\n"
"101:  Use DQ5\r\n"
"110:  Use DQ6\r\n"
"111:  Use DQ7"},
#else
{0, 2, 0x0000000000000000, "RW", "data7sel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo528[] = {{"PTDATAMUXSEL", "", 0x000000F0, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields529[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "lpmode_dasrtdqcmddrvenb_dly", "This indicates the delay in spidclk cycles for DQ/DQS driver disable, during LP mode 1 entry"},
#else
{28, 30, 0x0000000000000000, "RW", "lpmode_dasrtdqcmddrvenb_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtdqcmdsigpien_dly", "This indicates the delay in spidclk cycles for DQ/DQS/CMD PI disable/enable, during LP mode 1 entry/exit"},
#else
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtdqcmdsigpien_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000000, "RW", "lpmode_asrtdqcmddrvenb_dly", "This indicates the delay in spidclk cycles for DQ/DQS driver enable, during LP mode  1 exit"},
#else
{20, 22, 0x0000000000000000, "RW", "lpmode_asrtdqcmddrvenb_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{19, 19, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RW", "lpmode_dasrtiobufact_dly", "This indicates the delay in spidclk cycles for IOBUFACT disable, during LP mode 2  entry"},
#else
{16, 18, 0x0000000000000000, "RW", "lpmode_dasrtiobufact_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "lpmode_dasrtwrptren_dly", "This indicates the delay in spidclk cycles for write pointer disable, during LP mode  2 entry"},
#else
{12, 14, 0x0000000000000000, "RW", "lpmode_dasrtwrptren_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "lpmode_asrtref2xrstb_dly", "This indicates the delay in spidclk cycles for ref2xclk reset assertion, during LP mode 2  entry"},
#else
{8, 10, 0x0000000000000000, "RW", "lpmode_asrtref2xrstb_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "lpmode_dasrtref2xrstb_dly", "This indicates the delay in spidclk cycles for ref2xclk reset de-assertion, during LP mode 2 exit"},
#else
{0, 2, 0x0000000000000000, "RW", "lpmode_dasrtref2xrstb_dly", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo529[] = {{"LPMODECTL0", "", 0x000000F4, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields530[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "lpmode_asrtwrptren_dly", "This indicates the delay in spidclk cycles for write pointer enable, during LP mode 2 exit"},
#else
{28, 30, 0x0000000000000000, "RW", "lpmode_asrtwrptren_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtiobufact_dly", "This indicates the delay in spidclk cycles for IOBUFACT enable, during LP mode 2 exit"},
#else
{24, 26, 0x0000000000000000, "RW", "lpmode_asrtiobufact_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "lpmode_dqcmddrvenbovrd", "Override LP mode control for DQ/DQS/CMD driver"},
#else
{22, 22, 0x0000000000000000, "RW", "lpmode_dqcmddrvenbovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "lpmode_iobufactovrd", "Override LP mode control for IOBUFACT"},
#else
{21, 21, 0x0000000000000000, "RW", "lpmode_iobufactovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "lpmode_ref2xclkenovrd", "Override LP mode control for ref2xclk enable"},
#else
{20, 20, 0x0000000000000000, "RW", "lpmode_ref2xclkenovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "siggrpen_lpmode1ovrd", "Override LP mode control for signal PI enable"},
#else
{19, 19, 0x0000000000000000, "RW", "siggrpen_lpmode1ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "siggrpen_lpmode2or3ovrd", "Override LP mode control for signal PI enable"},
#else
{18, 18, 0x0000000000000000, "RW", "siggrpen_lpmode2or3ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "lpmode_wrptrenovrd", "Override LP mode control for write pointer enable"},
#else
{17, 17, 0x0000000000000000, "RW", "lpmode_wrptrenovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "lpmode_ref2xrstbovrd", "Override LP mode control for ref2xrstb"},
#else
{16, 16, 0x0000000000000000, "RW", "lpmode_ref2xrstbovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "lpmode_asrtref2xsigpien_dly", "This indicates the delay in spidclk cycles for DLL enable, during LP mode 2 exit"},
#else
{0, 2, 0x0000000000000000, "RW", "lpmode_asrtref2xsigpien_dly", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo530[] = {{"LPMODECTL1", "", 0x000000F8, 14, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields531[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 23, 0x0000000000000000, "RW", "rdcmd2rxdllupdt", "Delay between spid rdcmd and Rx dll update\r\n"
"This is in terms of ref1xclks."},
#else
{18, 23, 0x0000000000000000, "RW", "rdcmd2rxdllupdt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 17, 0x0000000000000000, "RW", "rxdllupdtlen", "Length of Rx DLL update indication. \r\n"
"This is in ref1xclks."},
#else
{12, 17, 0x0000000000000000, "RW", "rxdllupdtlen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000000, "RW", "rdcmd2rdactive", "Delay between spid rdcmd and read active indication\r\n"
"This is in terms of ref1xclks."},
#else
{6, 11, 0x0000000000000000, "RW", "rdcmd2rdactive", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "rdactivelen", "Length of read active indication. \r\n"
"This is in ref1xclks."},
#else
{0, 5, 0x0000000000000000, "RW", "rdactivelen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo531[] = {{"RXDLLRDCMDCTL0", "", 0x000000FC, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields532[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "ch1_memtech", "Memory Technology\r\n"
"Bit 3:0: DRAM Technology\r\n"
"0000: LPDDR3\r\n"
"0001: LPDDR4\r\n"
"0010: DDR3/L/U\r\n"
"0011: DDR4/L\r\n"
"0100: WIO2\r\n"
"0101: FMI\r\n"
"0110: DDR-T\r\n"
"0111: HBM"},
#else
{28, 31, 0x0000000000000000, "RW", "ch1_memtech", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "ch1_memfreq", "Indicates the Memory Frequency currently selected\r\n"
"within the PHY. This signal is valid after initialization\r\n"
"complete is set.\r\n"
"Bit 3:0 DRAM Frequency\r\n"
"0000: 800\r\n"
"0001: 1066\r\n"
"0010: 1333\r\n"
"0011: 1600\r\n"
"0100: 1866\r\n"
"0101: 2133\r\n"
"0110: 2400\r\n"
"1001: Reserved For Future Use (RFU)\r\n"
"101X: Reserved For Future Use (RFU)\r\n"
"11XX: Reserved For Future Use (RFU)"},
#else
{24, 27, 0x0000000000000000, "RW", "ch1_memfreq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch1_txfifo_csn_ffloppreseten", "This is the txFIFO final flop preset enable\r\n"
"1 - iobufact_b assert will preset the final flop, otherwise resets the final flop"},
#else
{10, 10, 0x0000000000000000, "RW", "ch1_txfifo_csn_ffloppreseten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch1_rdmcpsel", "Programmable MCP for Tx FIFO read pointer path."},
#else
{9, 9, 0x0000000000000000, "RW", "ch1_rdmcpsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 8, 0x0000000000000000, "RO", "ch1_reserved", "Reserved bits"},
#else
{5, 8, 0x0000000000000000, "RO", "ch1_reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RW", "ch1_spidclksel", "SPID clk sel \r\n"
"00: 0.5xmode\r\n"
"01: 0.25x mode\r\n"
"10: 0.1x mode\r\n"
"11: NA"},
#else
{3, 4, 0x0000000000000000, "RW", "ch1_spidclksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_lpddr34mode", "Single data rate v/s Double Data rate \r\n"
"0: Double data rate (LP3)\r\n"
"1: Single data rate (LP4)"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_lpddr34mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo532[] = {{"CH1_DIGCTL", "", 0x00000100, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields533[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 20, 0x0000000000000000, "RW", "ch1_ref1xrdptrinit", "This is the ref1x read pointer init configuration."},
#else
{17, 20, 0x0000000000000000, "RW", "ch1_ref1xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ch1_ref1xrdptroffset", "This is the ref1xread pointer offset configuration."},
#else
{13, 15, 0x0000000000000000, "RW", "ch1_ref1xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ch1_ref2xrdptrinit", "This is the ref2x read pointer init configuration."},
#else
{8, 12, 0x0000000000000000, "RW", "ch1_ref2xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ch1_cc_doublefifooffset", "This is the double FIFO offset configuration(in terms of 2xclock)."},
#else
{0, 3, 0x0000000000000000, "RW", "ch1_cc_doublefifooffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo533[] = {{"CH1_FIFOPTRCTL", "", 0x00000104, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields534[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "ch1_odttxdrven", "ODT buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{21, 21, 0x0000000000000000, "RW", "ch1_odttxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "ch1_clktxdrven", "CK buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{20, 20, 0x0000000000000000, "RW", "ch1_clktxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "ch1_cketxdrven", "CKE buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{19, 19, 0x0000000000000000, "RW", "ch1_cketxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "ch1_cstxdrven", "CS buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{18, 18, 0x0000000000000000, "RW", "ch1_cstxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 17, 0x0000000000000000, "RW", "ch1_cmdtxdrven", "CMD buffer enable\r\n"
"1: Enable buffer\r\n"
"0: Tristate buffer"},
#else
{7, 17, 0x0000000000000000, "RW", "ch1_cmdtxdrven", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 6, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch1_ckemasken", "CH1 CKE Mask Enable"},
#else
{3, 3, 0x0000000000000000, "RW", "ch1_ckemasken", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_clknegxposb", "Start phase of CK"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_clknegxposb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch1_cmdtristateovrval", "Command tristate override value"},
#else
{1, 1, 0x0000000000000000, "RW", "ch1_cmdtristateovrval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_cmdtristateovrsel", "Command tristate override select"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_cmdtristateovrsel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo534[] = {{"CH1_CCCCTL", "", 0x00000108, 11, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields535[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch1_rxfiforst_b", "Rxfifo reset (active low)\r\n"
"1: deasserted\r\n"
"0 : asserted"},
#else
{1, 1, 0x0000000000000000, "RW", "ch1_rxfiforst_b", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_spidrst_b", "Reset for functional logic in upartition (except compensation and power management logic)  \r\n"
"0: Reset assertion  \r\n"
"1: Reset de-assertion"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_spidrst_b", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo535[] = {{"CH1_DIGRSTCTL", "", 0x0000010C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields536[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_wrptren", "Channel 1 Config-controlled Write pointer enable. 0=config control disabled, 1=config control enabled. This bit qualifies the pm_wrptren, which eventually goes to CCC Channel 1 PTRGEN Fub."},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_wrptren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo536[] = {{"CH1_FIFOPTREN", "", 0x00000110, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields537[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{28, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "ch1_drx_dqscountrstb", "DQS counter reset"},
#else
{27, 27, 0x0000000000000000, "RW", "ch1_drx_dqscountrstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 26, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 26, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo537[] = {{"CH1_RCVENCTL", "", 0x00000114, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields538[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "ch1_txdll_dllfloprstb", "TxDLL flop reset"},
#else
{21, 21, 0x0000000000000000, "RW", "ch1_txdll_dllfloprstb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 20, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 20, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo538[] = {{"CH1_RXDLLCTL_DQBLDM", "", 0x00000118, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields539[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_txdll_ref2xph0pien", "enable tx ref pi phase 0 enable"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_txdll_ref2xph0pien", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo539[] = {{"CH1_RXDLLCTL_CCBLDM", "", 0x0000011C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields540[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "ch1_txdll_siggrp03pien", "PI enable for sig group 3 rank 0"},
#else
{11, 11, 0x0000000000000000, "RW", "ch1_txdll_siggrp03pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch1_txdll_siggrp02pien", "PI enable for sig group 2 rank 0"},
#else
{10, 10, 0x0000000000000000, "RW", "ch1_txdll_siggrp02pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch1_txdll_siggrp01pien", "PI enable for sig group 1 rank 0"},
#else
{9, 9, 0x0000000000000000, "RW", "ch1_txdll_siggrp01pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ch1_txdll_siggrp00pien", "PI enable for sig group 0 rank 0"},
#else
{8, 8, 0x0000000000000000, "RW", "ch1_txdll_siggrp00pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_txdll_ref2xph180pien", "enable tx ref pi phase 180 enable"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_txdll_ref2xph180pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo540[] = {{"CH1_TXDLLCTL", "", 0x00000120, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields541[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "ch1_ckdrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{8, 11, 0x0000000000000000, "RW", "ch1_ckdrvsecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "ch1_cssecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK0."},
#else
{4, 7, 0x0000000000000000, "RW", "ch1_cssecondrdportref2xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ch1_cmddrvsecondrdportref2xrdptroffset", "Read pointer offset for second port for LDO integration - DQ - RK1."},
#else
{0, 3, 0x0000000000000000, "RW", "ch1_cmddrvsecondrdportref2xrdptroffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo541[] = {{"CH1_LDOCTL1", "", 0x00000124, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields542[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_spid_init_complete", "SPID init complete"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_spid_init_complete", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo542[] = {{"CH1_SPIDIC", "", 0x00000128, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields543[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "lvl_ecc_weakpupstatic", "Weak Pull Up Control - CC Lane"},
#else
{30, 30, 0x0000000000000000, "RW", "lvl_ecc_weakpupstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "lvl_ecc_weakpup", "Weak Pull Up Control - CC Lane"},
#else
{24, 29, 0x0000000000000000, "RW", "lvl_ecc_weakpup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "lvl_ecc_weakpdnstatic", "Weak Pull Down Control - CC Lane"},
#else
{22, 22, 0x0000000000000000, "RW", "lvl_ecc_weakpdnstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "lvl_ecc_weakpdn", "Weak Pull Down Control - CC Lane"},
#else
{16, 21, 0x0000000000000000, "RW", "lvl_ecc_weakpdn", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo543[] = {{"ECC_WKPUPPDNCTL", "", 0x0000012C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields544[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "tx_cc1_techselect", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - CC1"},
#else
{26, 26, 0x0000000000000000, "RW", "tx_cc1_techselect", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000001, "RW", "tx_cc1_scompdelaysel", "Mux Select for DCOMP update block - 2'b00 or 2'b01 used values - CC1"},
#else
{24, 25, 0x0000000000000001, "RW", "tx_cc1_scompdelaysel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "tx_cc1_idlemode", "Disable idle mode logic = 1'b0, Enable = 1'b1 - CC1"},
#else
{23, 23, 0x0000000000000000, "RW", "tx_cc1_idlemode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "rx_cc1_modelp4ddr4", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - CC1"},
#else
{22, 22, 0x0000000000000000, "RW", "rx_cc1_modelp4ddr4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "dtx_cc1_drvenstretch", "Channel 1 CCC CKP/N Stretches rising edge of drivenable to relax data to enable skew."},
#else
{20, 21, 0x0000000000000000, "RW", "dtx_cc1_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "tx_cc1_drvenstretch", "Channel 1 CA/CTL Stretches rising edge of drivenable to relax data to enable skew."},
#else
{18, 19, 0x0000000000000000, "RW", "tx_cc1_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "drx_cc1_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{16, 17, 0x0000000000000000, "RW", "drx_cc1_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "rx_cc1_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{14, 15, 0x0000000000000000, "RW", "rx_cc1_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x0000000000000000, "RW", "txdll_cc1_2xclkskewsel", "Channel 1 TxDLL Skew Compensator clock mux select (Clock Select [1:0]/Sync Div Reset[3:2])\r\n"
"Below select descriptions apply to both clock and div reset but each one can be controlled independently\r\n"
"00 - Default path - No addditional Skew added\r\n"
"01 - Skew Path 1 - Add ~30-40ps of delay to TxDLL 2xclk input based on PVT\r\n"
"11 - Skew Path 2 - Add ~90-100ps of delay to TxDLL 2xclk input based on PVT"},
#else
{10, 13, 0x0000000000000000, "RW", "txdll_cc1_2xclkskewsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "drx_cc1_rxcommonmode", "changes the common mode of receiver from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{9, 9, 0x0000000000000001, "RW", "drx_cc1_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "rx_cc1_rxcommonmode", "changes the common mode of receiver from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{8, 8, 0x0000000000000001, "RW", "rx_cc1_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "ch1_pdndrvstatic", "Static pull down code - DRV DQ"},
#else
{7, 7, 0x0000000000000001, "RW", "ch1_pdndrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "ch1_pdndrvstaticdqs", "Channel 1 Static pull down code - DRV CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{6, 6, 0x0000000000000001, "RW", "ch1_pdndrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "ch1_pdnodtstatic", "Static pull down code - ODT DQ"},
#else
{5, 5, 0x0000000000000001, "RW", "ch1_pdnodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "ch1_pdnodtstaticdqs", "Channel 1 Static pull down code - ODT CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{4, 4, 0x0000000000000001, "RW", "ch1_pdnodtstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "ch1_pupdrvstatic", "Static pull up code - DRV DQ"},
#else
{3, 3, 0x0000000000000001, "RW", "ch1_pupdrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ch1_pupdrvstaticdqs", "Channel 1 Static pull up code - DRV CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{2, 2, 0x0000000000000001, "RW", "ch1_pupdrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "ch1_pupodtstatic", "Static pull up code - ODT DQ"},
#else
{1, 1, 0x0000000000000001, "RW", "ch1_pupodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "ch1_pupodtstaticdqs", "Channel 1 Static pull up code - ODT CK and CTL (DQS buffer swapped with CLK buffer; config names were not changed but re-used)"},
#else
{0, 0, 0x0000000000000001, "RW", "ch1_pupodtstaticdqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo544[] = {{"CH1_AFEMISC0", "", 0x00000130, 20, 0x00000000FFFFFFFF, 0x00000000010003FF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields545[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "ecc_dtx_bl0_drvenstretch", "ECC DQS Stretches rising edge of drivenable to relax data to enable skew."},
#else
{20, 21, 0x0000000000000000, "RW", "ecc_dtx_bl0_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "ecc_tx_bl0_drvenstretch", "ECC DQ Stretches rising edge of drivenable to relax data to enable skew."},
#else
{18, 19, 0x0000000000000000, "RW", "ecc_tx_bl0_drvenstretch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "ecc_drx_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{16, 17, 0x0000000000000000, "RW", "ecc_drx_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "ecc_rx_rxpwrmode", "Modulates the Volatge seen by the RX Amplifier\r\n"
"00 - Default; 01,10,11 - Illegal Values"},
#else
{14, 15, 0x0000000000000000, "RW", "ecc_rx_rxpwrmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x0000000000000000, "RW", "txdll_dq_2xclkskewsel", "ECC TxDLL Skew Compensator clock mux select (Clock Select [1:0]/Sync Div Reset[3:2])\r\n"
"Below select descriptions apply to both clock and div reset but each one can be controlled independently\r\n"
"00 - Default path - No addditional Skew added\r\n"
"01 - Skew Path 1 - Add ~30-40ps of delay to TxDLL 2xclk input based on PVT\r\n"
"11 - Skew Path 2 - Add ~90-100ps of delay to TxDLL 2xclk input based on PVT"},
#else
{10, 13, 0x0000000000000000, "RW", "txdll_dq_2xclkskewsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "ecc_drx_rxcommonmode", "changes the common mode of receiver from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{9, 9, 0x0000000000000001, "RW", "ecc_drx_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "ecc_rx_rxcommonmode", "changes the common mode of receiver from low common mode to vcc/2 based on lpddr3/ lpddr4."},
#else
{8, 8, 0x0000000000000001, "RW", "ecc_rx_rxcommonmode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "ecc_pdndrvstatic", "Static pull down code - DRV DQ"},
#else
{7, 7, 0x0000000000000001, "RW", "ecc_pdndrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "ecc_pdndrvstaticdqs", "ECC Static pull down code - DRV DQS/DQSB"},
#else
{6, 6, 0x0000000000000001, "RW", "ecc_pdndrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "ecc_pdnodtstatic", "Static pull down code - ODT DQ"},
#else
{5, 5, 0x0000000000000001, "RW", "ecc_pdnodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "ecc_pdnodtstaticdqs", "ECC Static pull down code - ODT DQS/DQSB"},
#else
{4, 4, 0x0000000000000001, "RW", "ecc_pdnodtstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "ecc_pupdrvstatic", "Static pull up code - DRV DQ"},
#else
{3, 3, 0x0000000000000001, "RW", "ecc_pupdrvstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ecc_pupdrvstaticdqs", "ECC Static pull up code - DRV DQS/DQSB"},
#else
{2, 2, 0x0000000000000001, "RW", "ecc_pupdrvstaticdqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "ecc_pupodtstatic", "Static pull up code - ODT DQ"},
#else
{1, 1, 0x0000000000000001, "RW", "ecc_pupodtstatic", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "ecc_pupodtstaticdqs", "ECC Static pull up code - ODT DQS/DQSB"},
#else
{0, 0, 0x0000000000000001, "RW", "ecc_pupodtstaticdqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo545[] = {{"ECC_AFEMISC0", "", 0x00000134, 16, 0x00000000FFFFFFFF, 0x00000000000003FF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields546[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "ch1_tx_cc1_tcostaticlegen", "TX TCO enable - CC"},
#else
{15, 15, 0x0000000000000000, "RW", "ch1_tx_cc1_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 14, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 14, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "ch1_tx_cc1_tcofall", "DQ TCO comp fall code - CC Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "ch1_tx_cc1_tcofall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "ch1_tx_cc1_tcorise", "DQ TCO comp rise code - CC Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "ch1_tx_cc1_tcorise", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo546[] = {{"CH1_TCOCTL_DQCC", "", 0x00000138, 6, 0x00000000FFFFFFFF, 0x0000000000001F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields547[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ccc0_dtx_tcostaticlegen", "DTX TCO enable - BL"},
#else
{29, 29, 0x0000000000000000, "RW", "ccc0_dtx_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "ccc0_dtx_tcofalldqsb", "DQSB TCO comp fall code - CCC0 Lane"},
#else
{24, 28, 0x000000000000001F, "RW", "ccc0_dtx_tcofalldqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "ccc0_dtx_tcorisedqsb", "DQS TCO comp fall code - CCC1 Lane"},
#else
{16, 20, 0x000000000000001F, "RW", "ccc0_dtx_tcorisedqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "ccc0_dtx_tcofalldqs", "DQSB TCO comp rise code - CCC0 Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "ccc0_dtx_tcofalldqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "ccc0_dtx_tcorisedqs", "DQS TCO comp rise code - CCC1 Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "ccc0_dtx_tcorisedqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo547[] = {{"CCC0_TCOCTL", "", 0x0000013C, 9, 0x00000000FFFFFFFF, 0x000000001F1F1F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields548[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ccc1_dtx_tcostaticlegen", "DTX TCO enable - BL"},
#else
{29, 29, 0x0000000000000000, "RW", "ccc1_dtx_tcostaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x000000000000001F, "RW", "ccc1_dtx_tcofalldqsb", "DQSB TCO comp fall code - CCC0 Lane"},
#else
{24, 28, 0x000000000000001F, "RW", "ccc1_dtx_tcofalldqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x000000000000001F, "RW", "ccc1_dtx_tcorisedqsb", "DQS TCO comp fall code - CCC1 Lane"},
#else
{16, 20, 0x000000000000001F, "RW", "ccc1_dtx_tcorisedqsb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{13, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000001F, "RW", "ccc1_dtx_tcofalldqs", "DQSB TCO comp rise code - CCC0 Lane"},
#else
{8, 12, 0x000000000000001F, "RW", "ccc1_dtx_tcofalldqs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x000000000000001F, "RW", "ccc1_dtx_tcorisedqs", "DQS TCO comp rise code - CCC1 Lane"},
#else
{0, 4, 0x000000000000001F, "RW", "ccc1_dtx_tcorisedqs", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo548[] = {{"CCC1_TCOCTL", "", 0x00000140, 9, 0x00000000FFFFFFFF, 0x000000001F1F1F1F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields549[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "ecc_rxdll_rxpbden", "Rx Per Bit De-skew enable (1=enable, 0=disable)"},
#else
{22, 22, 0x0000000000000000, "RW", "ecc_rxdll_rxpbden", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 21, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{2, 21, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ecc_tx_pbdstaticlegen", "Per bit deskew enable - TX - ECC"},
#else
{1, 1, 0x0000000000000000, "RW", "ecc_tx_pbdstaticlegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ecc_dtx_pbdstaticlegen", "Per bit deskew enable - DTX - ECC"},
#else
{0, 0, 0x0000000000000000, "RW", "ecc_dtx_pbdstaticlegen", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo549[] = {{"ECC_TXPBDCTL1", "", 0x00000144, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields550[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "tx_dq_techselect", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - ECC"},
#else
{21, 21, 0x0000000000000000, "RW", "tx_dq_techselect", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "tx_dq_idlemode", "Disable idle mode logic = 1'b0, Enable = 1'b1 - ECC"},
#else
{20, 20, 0x0000000000000000, "RW", "tx_dq_idlemode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "rx_dq_modelp4ddr4", "Selects between LP4/LP3 (1'b0) and DDR4 modes (1'b1) - ECC"},
#else
{19, 19, 0x0000000000000000, "RW", "rx_dq_modelp4ddr4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000007, "RW", "ecc_dtx_drvsegen", "Segment enable for CC buffer. Used for per leg testing in HVM"},
#else
{16, 18, 0x0000000000000007, "RW", "ecc_dtx_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "ecc_drx_dqsnegedgemask", "masking out the first dqs negedge during rcven handling in ddr4 (0-ddr4;1-ddr3l,lp3/4)"},
#else
{15, 15, 0x0000000000000000, "RW", "ecc_drx_dqsnegedgemask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000007, "RW", "ecc_tx_drvsegen", "Segment enable for CC buffer. Used for per leg testing in HVM"},
#else
{12, 14, 0x0000000000000007, "RW", "ecc_tx_drvsegen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{9, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000001, "RW", "ecc_rxdll_picapsel", "set cap tuning for pi"},
#else
{6, 8, 0x0000000000000001, "RW", "ecc_rxdll_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{5, 5, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000001, "RW", "ecc_txdll_picapsel", "set cap tuning for pi"},
#else
{2, 4, 0x0000000000000001, "RW", "ecc_txdll_picapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo550[] = {{"ECC_AFEMISC1", "", 0x00000148, 12, 0x00000000FFFFFFFF, 0x0000000000077044}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields551[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp03dbsel", "Deadband select for sig group 3 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp03dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp03rdptroffset", "Read pointer offset for sig group 3 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp03rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp03picode", "PI code for sig group 3 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp03picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo551[] = {{"CH1_TXDLLSIGGRP3CTL", "", 0x0000014C, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields552[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp02dbsel", "Deadband select for sig group 2 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp02dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp02rdptroffset", "Read pointer offset for sig group 2 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp02rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp02picode", "PI code for sig group 2 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp02picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo552[] = {{"CH1_TXDLLSIGGRP2CTL", "", 0x00000150, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields553[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp01dbsel", "Deadband select for sig group 1 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp01dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp01rdptroffset", "Read pointer offset for sig group 1 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp01rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp01picode", "PI code for sig group 1 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp01picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo553[] = {{"CH1_TXDLLSIGGRP1CTL", "", 0x00000154, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields554[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 16, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp00dbsel", "Deadband select for sig group 1 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp00dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp00rdptroffset", "Read pointer offset for sig group 0 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp00rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp00picode", "PI code for sig group 0 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_txdll_rk0siggrp00picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo554[] = {{"CH1_TXDLLSIGGRP0CTL", "", 0x00000158, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields555[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{18, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{18, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{17, 17, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ecc_txdll_mdllen", "MDLL enable"},
#else
{16, 16, 0x0000000000000000, "RW", "ecc_txdll_mdllen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 15, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{11, 11, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ecc_txdll_siggrp02pien", "PI enable for sig group 2 rank 0"},
#else
{10, 10, 0x0000000000000000, "RW", "ecc_txdll_siggrp02pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ecc_txdll_siggrp01pien", "PI enable for sig group 1 rank 0"},
#else
{9, 9, 0x0000000000000000, "RW", "ecc_txdll_siggrp01pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ecc_txdll_siggrp00pien", "PI enable for sig group 0 rank 0"},
#else
{8, 8, 0x0000000000000000, "RW", "ecc_txdll_siggrp00pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ecc_txdll_ref2xph180pien", "enable tx ref pi phase 180 enable"},
#else
{2, 2, 0x0000000000000000, "RW", "ecc_txdll_ref2xph180pien", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 1, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{0, 0, 0x0000000000000000, "RO", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo555[] = {{"ECC_TXDLLCTL", "", 0x0000015C, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields556[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp02dbsel", "Deadband select for sig group 2 rank 1"},
#else
{29, 30, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp02dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp02rdptroffset", "Read pointer offset for sig group 2 rank 1"},
#else
{24, 28, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp02rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp02picode", "PI code for sig group 2 rank 1"},
#else
{16, 23, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp02picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp02dbsel", "Deadband select for sig group 2 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp02dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp02rdptroffset", "Read pointer offset for sig group 2 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp02rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp02picode", "PI code for sig group 2 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp02picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo556[] = {{"ECC_TXDLLSIGGRP2CTL", "", 0x00000160, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields557[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp01dbsel", "Deadband select for sig group 1 rank 1"},
#else
{29, 30, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp01dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp01rdptroffset", "Read pointer offset for sig group 1 rank 1"},
#else
{24, 28, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp01rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp01picode", "PI code for sig group 1 rank 1"},
#else
{16, 23, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp01picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp01dbsel", "Deadband select for sig group 1 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp01dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp01rdptroffset", "Read pointer offset for sig group 1 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp01rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp01picode", "PI code for sig group 1 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp01picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo557[] = {{"ECC_TXDLLSIGGRP1CTL", "", 0x00000164, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields558[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp00dbsel", "Deadband select  for sig group 0 rank 1"},
#else
{29, 30, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp00dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp00rdptroffset", "Read pointer offset for sig group 0 rank 1"},
#else
{24, 28, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp00rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp00picode", "PI code for sig group 0 rank 1"},
#else
{16, 23, 0x0000000000000000, "RW", "ecc_txdll_rk1siggrp00picode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp00dbsel", "Deadband select  for sig group 0 rank 0"},
#else
{13, 15, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp00dbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp00rdptroffset", "Read pointer offset for sig group 0 rank 0"},
#else
{8, 12, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp00rdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp00picode", "PI code for sig group 0 rank 0"},
#else
{0, 7, 0x0000000000000000, "RW", "ecc_txdll_rk0siggrp00picode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo558[] = {{"ECC_TXDLLSIGGRP0CTL", "", 0x00000168, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields559[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rpdext", "Is external RCOMP resistor pad connected to this family. 0=Pad disconnected.  1=Pad populated."},
#else
{0, 0, 0x0000000000000000, "RW", "rpdext", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo559[] = {{"DIGCTL1663", "", 0x0000016C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields560[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ecc_siggrp02_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4  Mode)"},
#else
{30, 30, 0x0000000000000000, "RW", "ecc_siggrp02_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ecc_siggrp01_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4 Mode)"},
#else
{29, 29, 0x0000000000000000, "RW", "ecc_siggrp01_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "ecc_siggrp00_invph0to180", "DBMUX Phase 180 Clock Selection\r\n"
"0: Phase180 clock from DLL Phase Interpolator (LP* Modes)\r\n"
"1: Phase180 clock from Phase0 clock inversion (DDR3L/DDR4 Mode)"},
#else
{28, 28, 0x0000000000000000, "RW", "ecc_siggrp00_invph0to180", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RO", "reserved", "DLL comp init configuration."},
#else
{24, 27, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "reserved", "DLL comp read pointer offset."},
#else
{21, 23, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 20, 0x0000000000000000, "RW", "ecc_ref1xrdptrinit", "This is the ref1x read pointer init configuration."},
#else
{17, 20, 0x0000000000000000, "RW", "ecc_ref1xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ecc_dqxccb", "Configure DQCCC as DQ or CCC\r\n"
"0: CCC\r\n"
"1: DQ"},
#else
{16, 16, 0x0000000000000000, "RW", "ecc_dqxccb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RW", "ecc_ref1xrdptroffset", "This is the ref1xread pointer offset configuration."},
#else
{13, 15, 0x0000000000000000, "RW", "ecc_ref1xrdptroffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000000, "RW", "ecc_ref2xrdptrinit", "This is the ref2x read pointer init configuration."},
#else
{8, 12, 0x0000000000000000, "RW", "ecc_ref2xrdptrinit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{4, 7, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ecc_bl_doublefifooffset", "This is the double FIFO offset configuration(in terms of 2xclock)."},
#else
{0, 3, 0x0000000000000000, "RW", "ecc_bl_doublefifooffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo560[] = {{"ECC_FIFOPTRCTL", "", 0x00000170, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields561[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dllcomprst_b", "Power-on or software reset0: reset state1: norma operationSet to 1 to enter normal operation."},
#else
{0, 0, 0x0000000000000000, "RW", "dllcomprst_b", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo561[] = {{"DLLCOMP_RESET", "", 0x00000600, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields562[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RWS", "ch0_txdll_init", "Activates initialization training sequence.0: initialization training sequence not active.1: initialization training sequence active.Self clearing after successful initialization training sequence."},
#else
{0, 0, 0x0000000000000000, "RWS", "ch0_txdll_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo562[] = {{"DLLCOMP_INIT_CH0", "", 0x00000604, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields563[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RWS", "ch1_txdll_init", "Activates initialization training sequence.0: initialization training sequence not active.1: initialization training sequence active.Self clearing after successful initialization training sequence."},
#else
{0, 0, 0x0000000000000000, "RWS", "ch1_txdll_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo563[] = {{"DLLCOMP_INIT_CH1", "", 0x00000608, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields564[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RWS", "ecc_txdll_init", "Activates initialization training sequence.0: initialization training sequence not active.1: initialization training sequence active.Self clearing after successful initialization training sequence."},
#else
{0, 0, 0x0000000000000000, "RWS", "ecc_txdll_init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo564[] = {{"DLLCOMP_INIT_ECC", "", 0x0000060C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields565[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lpddr_type", "LPDDR speed target. 0: LPDDR3, 1600 MHz. 1: LPDDR4, 3200 MHz."},
#else
{0, 0, 0x0000000000000000, "RW", "lpddr_type", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo565[] = {{"DLLCOMP_LPDDRTYPE", "", 0x00000610, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields566[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "clkungate", "Internal Clock control. 0 = allow clock gating for low power; 1 = allow free running clock"},
#else
{0, 0, 0x0000000000000001, "RW", "clkungate", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo566[] = {{"DLLCOMP_CLKUNGATE", "", 0x00000614, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields567[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "ecc_clkungate", "Internal Clock control. 0 = allow clock gating for low power; 1 = allow free running clock"},
#else
{0, 0, 0x0000000000000001, "RW", "ecc_clkungate", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo567[] = {{"DLLCOMP_CLKUNGATE_ECC", "", 0x00000618, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields568[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "ch0_txdll_lock_error", "Set when initialization or fine periodic training failed the locking condition. Cleared on a read or writing a 0."},
#else
{7, 7, 0x0000000000000000, "RO/V", "ch0_txdll_lock_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "ch0_txdll_fine_error", "Set when fine code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{6, 6, 0x0000000000000000, "RO/V", "ch0_txdll_fine_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO/V", "ch0_txdll_coarsep_error", "Set when coarse code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{5, 5, 0x0000000000000000, "RO/V", "ch0_txdll_coarsep_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "ch0_txdll_error", "Set when Delay Cell count exceeds maximum value. Cleared on a read or writing a 0."},
#else
{4, 4, 0x0000000000000000, "RO/V", "ch0_txdll_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{2, 3, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "ch0_txdll_lock_flag", "Set when initialization or fine periodic training passed the locking condition. Valid only when scr_lockseq_en is set to 1.Cleared on a read or writing a 0."},
#else
{1, 1, 0x0000000000000000, "RO/V", "ch0_txdll_lock_flag", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "ch0_txdll_init_done", "Set when Initialization sequence is successful. Cleared on a read or writing a 0."},
#else
{0, 0, 0x0000000000000000, "RO/V", "ch0_txdll_init_done", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo568[] = {{"DLLCOMP_ERROR_STATUS_CH0", "", 0x0000061C, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields569[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "ch1_txdll_lock_error", "Set when initialization or fine periodic training failed the locking condition. Cleared on a read or writing a 0."},
#else
{7, 7, 0x0000000000000000, "RO/V", "ch1_txdll_lock_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "ch1_txdll_fine_error", "Set when fine code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{6, 6, 0x0000000000000000, "RO/V", "ch1_txdll_fine_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO/V", "ch1_txdll_coarsep_error", "Set when coarse code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{5, 5, 0x0000000000000000, "RO/V", "ch1_txdll_coarsep_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "ch1_txdll_error", "Set when Delay Cell count exceeds maximum value. Cleared on a read or writing a 0."},
#else
{4, 4, 0x0000000000000000, "RO/V", "ch1_txdll_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{2, 3, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "ch1_txdll_lock_flag", "Set when initialization or fine periodic training passed the locking condition. Valid only when scr_lockseq_en is set to 1.Cleared on a read or writing a 0."},
#else
{1, 1, 0x0000000000000000, "RO/V", "ch1_txdll_lock_flag", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "ch1_txdll_init_done", "Set when Initialization sequence is successful. Cleared on a read or writing a 0."},
#else
{0, 0, 0x0000000000000000, "RO/V", "ch1_txdll_init_done", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo569[] = {{"DLLCOMP_ERROR_STATUS_CH1", "", 0x00000620, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields570[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "ecc_txdll_lock_error", "Set when initialization or fine periodic training failed the locking condition. Cleared on a read or writing a 0."},
#else
{7, 7, 0x0000000000000000, "RO/V", "ecc_txdll_lock_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "ecc_txdll_fine_error", "Set when fine code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{6, 6, 0x0000000000000000, "RO/V", "ecc_txdll_fine_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO/V", "ecc_txdll_coarsep_error", "Set when coarse code underflow or overflow occurs. Cleared on a read or writing a 0."},
#else
{5, 5, 0x0000000000000000, "RO/V", "ecc_txdll_coarsep_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "ecc_txdll_error", "Set when Delay Cell count exceeds maximum value. Cleared on a read or writing a 0."},
#else
{4, 4, 0x0000000000000000, "RO/V", "ecc_txdll_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{2, 3, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "ecc_txdll_lock_flag", "Set when initialization or fine periodic training passed the locking condition. Valid only when scr_lockseq_en is set to 1.Cleared on a read or writing a 0."},
#else
{1, 1, 0x0000000000000000, "RO/V", "ecc_txdll_lock_flag", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "ecc_txdll_init_done", "Set when Initialization sequence is successful. Cleared on a read or writing a 0."},
#else
{0, 0, 0x0000000000000000, "RO/V", "ecc_txdll_init_done", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo570[] = {{"DLLCOMP_ERROR_STATUS_ECC", "", 0x00000624, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields571[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RO/V", "ch0_txdll_stat_fbmuxsel", "Delay Cell count value during normal operation"},
#else
{16, 20, 0x0000000000000000, "RO/V", "ch0_txdll_stat_fbmuxsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO/V", "ch0_txdll_stat_coarseicode", "Coarse code value at initialization training sequence completion."},
#else
{12, 15, 0x0000000000000000, "RO/V", "ch0_txdll_stat_coarseicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RO/V", "ch0_txdll_stat_coarsecode", "Coarse code value during normal operation"},
#else
{8, 11, 0x0000000000000000, "RO/V", "ch0_txdll_stat_coarsecode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "ch0_txdll_stat_finecode", "Fine code value during normal operation"},
#else
{0, 7, 0x0000000000000000, "RO/V", "ch0_txdll_stat_finecode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo571[] = {{"DLLCOMP_CODE_STATUS_CH0", "", 0x00000628, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields572[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RO/V", "ch1_txdll_stat_fbmuxsel", "Delay Cell count value during normal operation"},
#else
{16, 20, 0x0000000000000000, "RO/V", "ch1_txdll_stat_fbmuxsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO/V", "ch1_txdll_stat_coarseicode", "Coarse code value at initialization training sequence completion."},
#else
{12, 15, 0x0000000000000000, "RO/V", "ch1_txdll_stat_coarseicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RO/V", "ch1_txdll_stat_coarsecode", "Coarse code value during normal operation"},
#else
{8, 11, 0x0000000000000000, "RO/V", "ch1_txdll_stat_coarsecode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "ch1_txdll_stat_finecode", "Fine code value during normal operation"},
#else
{0, 7, 0x0000000000000000, "RO/V", "ch1_txdll_stat_finecode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo572[] = {{"DLLCOMP_CODE_STATUS_CH1", "", 0x0000062C, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields573[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RO/V", "ecc_txdll_stat_fbmuxsel", "Delay Cell count value during normal operation"},
#else
{16, 20, 0x0000000000000000, "RO/V", "ecc_txdll_stat_fbmuxsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RO/V", "ecc_txdll_stat_coarseicode", "Coarse code value at initialization training sequence completion."},
#else
{12, 15, 0x0000000000000000, "RO/V", "ecc_txdll_stat_coarseicode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RO/V", "ecc_txdll_stat_coarsecode", "Coarse code value during normal operation"},
#else
{8, 11, 0x0000000000000000, "RO/V", "ecc_txdll_stat_coarsecode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "ecc_txdll_stat_finecode", "Fine code value during normal operation"},
#else
{0, 7, 0x0000000000000000, "RO/V", "ecc_txdll_stat_finecode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo573[] = {{"DLLCOMP_CODE_STATUS_ECC", "", 0x00000630, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields574[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "lock_seq_en", "Enable lock sequence after initialization or fine periodic training sequence. 0: disable lock sequence. 1: enable lock sequence."},
#else
{31, 31, 0x0000000000000000, "RW", "lock_seq_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "lockerror_ignore", "Ignore lock error. Valid when scr_lockseq_en = 1. 0: Exit and wait for initialization training sequence. 1: ignore lock error and proceed to normal operation."},
#else
{30, 30, 0x0000000000000000, "RW", "lockerror_ignore", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000003, "RW", "lockcount_size", "Maximum samples to count for lock condition. The counter decrements until the value reaches 0 yielding scr_lockcount_size + 1 samples."},
#else
{0, 3, 0x0000000000000003, "RW", "lockcount_size", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo574[] = {{"DLLCOMP_LOCKCTL", "", 0x00000634, 4, 0x00000000FFFFFFFF, 0x0000000000000003}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields575[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch0_muxcode_ovr_sel", "Override txdll_fbmuxsel[4:0] with scr_muxcode_ovr[4:0].0: disable override.1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ch0_muxcode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "ch0_muxcode_ovr", "Delay cell fbmuxsel override value."},
#else
{16, 20, 0x0000000000000000, "RW", "ch0_muxcode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo575[] = {{"DLLCOMP_FBMUXSEL0_CH0", "", 0x00000638, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields576[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch1_muxcode_ovr_sel", "Override txdll_fbmuxsel[4:0] with scr_muxcode_ovr[4:0].0: disable override.1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ch1_muxcode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "ch1_muxcode_ovr", "Delay cell fbmuxsel override value."},
#else
{16, 20, 0x0000000000000000, "RW", "ch1_muxcode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo576[] = {{"DLLCOMP_FBMUXSEL0_CH1", "", 0x0000063C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields577[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ecc_muxcode_ovr_sel", "Override txdll_fbmuxsel[4:0] with scr_muxcode_ovr[4:0].0: disable override.1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ecc_muxcode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000000, "RW", "ecc_muxcode_ovr", "Delay cell fbmuxsel override value."},
#else
{16, 20, 0x0000000000000000, "RW", "ecc_muxcode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo577[] = {{"DLLCOMP_FBMUXSEL0_ECC", "", 0x00000640, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields578[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{29, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 28, 0x0000000000000000, "RW", "muxcode_max", "Delay cell maximum count value. Used in overflow check"},
#else
{24, 28, 0x0000000000000000, "RW", "muxcode_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 23, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000009, "RW", "muxcode_min", "Delay cell minimum count value. Default start code."},
#else
{16, 20, 0x0000000000000009, "RW", "muxcode_min", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo578[] = {{"DLLCOMP_FBMUXSEL1", "", 0x00000644, 5, 0x00000000FFFFFFFF, 0x0000000000090000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields579[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch0_coarsecode_ovr_sel", "Override txdll_coarsecode[3:0] with scr_coarsecode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{31, 31, 0x0000000000000000, "RW", "ch0_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ch0_coarseicode_ovr_sel", "Override txdll_coarseicode[3:0] with scr_coarseicode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{30, 30, 0x0000000000000000, "RW", "ch0_coarseicode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{28, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "ch0_coarseicode_ovr", "Coarsei code override value."},
#else
{24, 27, 0x0000000000000000, "RW", "ch0_coarseicode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 23, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 23, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ch0_coarsecode_ovr", "Coarse code override value."},
#else
{0, 3, 0x0000000000000000, "RW", "ch0_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo579[] = {{"DLLCOMP_COARSECODE0_CH0", "", 0x00000648, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields580[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch1_coarsecode_ovr_sel", "Override txdll_coarsecode[3:0] with scr_coarsecode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{31, 31, 0x0000000000000000, "RW", "ch1_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ch1_coarseicode_ovr_sel", "Override txdll_coarseicode[3:0] with scr_coarseicode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{30, 30, 0x0000000000000000, "RW", "ch1_coarseicode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{28, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "ch1_coarseicode_ovr", "Coarsei code override value."},
#else
{24, 27, 0x0000000000000000, "RW", "ch1_coarseicode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 23, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 23, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ch1_coarsecode_ovr", "Coarse code override value."},
#else
{0, 3, 0x0000000000000000, "RW", "ch1_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo580[] = {{"DLLCOMP_COARSECODE0_CH1", "", 0x0000064C, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields581[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ecc_coarsecode_ovr_sel", "Override txdll_coarsecode[3:0] with scr_coarsecode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{31, 31, 0x0000000000000000, "RW", "ecc_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ecc_coarseicode_ovr_sel", "Override txdll_coarseicode[3:0] with scr_coarseicode_ovr[3:0]. 0: disable override, 1: enable override"},
#else
{30, 30, 0x0000000000000000, "RW", "ecc_coarseicode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{28, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "ecc_coarseicode_ovr", "Coarsei code override value."},
#else
{24, 27, 0x0000000000000000, "RW", "ecc_coarseicode_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 23, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 23, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ecc_coarsecode_ovr", "Coarse code override value."},
#else
{0, 3, 0x0000000000000000, "RW", "ecc_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo581[] = {{"DLLCOMP_COARSECODE0_ECC", "", 0x00000650, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields582[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{28, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "coarsecode_max", "Coarse code maximum count value. Default start value. Used in overflow check"},
#else
{24, 27, 0x0000000000000000, "RW", "coarsecode_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 23, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 23, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000002, "RW", "coarsecode_min", "Coarse code minimum count value. Used in underflow check."},
#else
{0, 3, 0x0000000000000002, "RW", "coarsecode_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo582[] = {{"DLLCOMP_COARSECODE1", "", 0x00000654, 4, 0x00000000FFFFFFFF, 0x0000000000000002}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields583[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "finecodemax_limit", "Fine code limit - maximum value. Defines fine code drift allowed towards finecode maximum value before incrementing the coarse code for binary search training."},
#else
{24, 31, 0x0000000000000000, "RW", "finecodemax_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "finecodemin_limit", "Fine code limit - minimum value. Defines fine code drift allowed towards finecode minimum value before decrementing the coarse code for binary search training."},
#else
{16, 23, 0x0000000000000000, "RW", "finecodemin_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "finecode_max", "Fine code maximum value. Used in overflow check during fine continuous or fine periodic"},
#else
{8, 15, 0x0000000000000000, "RW", "finecode_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_min", "Underflow check during fine continuous or fine periodic training."},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo583[] = {{"DLLCOMP_FINECODE", "", 0x00000658, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields584[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_muxsel", "Two bit field selects one of 4 possible finecode values for each 8:1 mux input. Two bit field shared between -/+ index values (ex. -gf / +gf)"},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_muxsel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo584[] = {{"DLLCOMP_FINEMUXSEL", "", 0x0000065C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields585[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "finec_mode", "Fine continuous training enable after initialization training. 0: Fine continuous training disable. 1: Fine continuous training enable (default). When both finec_mode and finep_mode are set to 1, dllcomp functionality is unpredictable."},
#else
{31, 31, 0x0000000000000000, "RW", "finec_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "finep_mode", "Fine priodic training enable after initialization training. 0: Fine periodic disable (default). 1: Fine periodic enable. When both finec_mode and finep_mode are set to 1, dllcomp functionality is unpredictable."},
#else
{30, 30, 0x0000000000000000, "RW", "finep_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "searchalgo_long", "Propriety search algorithm version to apply during lock, fine continuous and fine periodic training. 0: Apply short version. 1: Apply long version."},
#else
{29, 29, 0x0000000000000000, "RW", "searchalgo_long", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 28, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 28, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "finecode_start", "Fine code start value to apply during binary search training"},
#else
{0, 7, 0x0000000000000000, "RW", "finecode_start", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo585[] = {{"DLLCOMP_FINECTL", "", 0x00000660, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields586[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch0_finecode_ovr_sel", "Fine code override select. 0: Apply computed fine code (default). 1: Apply scr_finecode_ovr[7:0] ."},
#else
{31, 31, 0x0000000000000000, "RW", "ch0_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ch0_finecode_updateovr_ovr", "When scr_finecode_ovr_sel is active high, this bit drives txdll_dllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "ch0_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch0_finecode_ovr", "Fine code to override with when scr_finecode_ovr_sel = 1"},
#else
{0, 7, 0x0000000000000000, "RW", "ch0_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo586[] = {{"DLLCOMP_FINECODEOVR_CH0", "", 0x00000664, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields587[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch1_finecode_ovr_sel", "Fine code override select. 0: Apply computed fine code (default). 1: Apply scr_finecode_ovr[7:0] ."},
#else
{31, 31, 0x0000000000000000, "RW", "ch1_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ch1_finecode_updateovr_ovr", "When scr_finecode_ovr_sel is active high, this bit drives txdll_dllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "ch1_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_finecode_ovr", "Fine code to override with when scr_finecode_ovr_sel = 1"},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo587[] = {{"DLLCOMP_FINECODEOVR_CH1", "", 0x00000668, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields588[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ecc_finecode_ovr_sel", "Fine code override select. 0: Apply computed fine code (default). 1: Apply scr_finecode_ovr[7:0] ."},
#else
{31, 31, 0x0000000000000000, "RW", "ecc_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ecc_finecode_updateovr_ovr", "When scr_finecode_ovr_sel is active high, this bit drives txdll_dllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "ecc_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ecc_finecode_ovr", "Fine code to override with when scr_finecode_ovr_sel = 1"},
#else
{0, 7, 0x0000000000000000, "RW", "ecc_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo588[] = {{"DLLCOMP_FINECODEOVR_ECC", "", 0x0000066C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields589[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "finepwait_interval", "Fine periodic interval timer start value. Defines the interval between back to back fine periodic training sequences."},
#else
{0, 15, 0x0000000000000000, "RW", "finepwait_interval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo589[] = {{"DLLCOMP_FPTIMER", "", 0x00000670, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields590[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{13, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{13, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x0000000000000006, "RW", "samplewait_max", "Wait interval between code update and sample ready. Applied during lock, fine continuous and fine"},
#else
{8, 12, 0x0000000000000006, "RW", "samplewait_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{5, 7, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000002, "RW", "samplewait_min", "Wait interval between code update and sample ready. Applied during coarse initialization and fine"},
#else
{0, 4, 0x0000000000000002, "RW", "samplewait_min", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo590[] = {{"DLLCOMP_SAMPLEWAIT", "", 0x00000674, 4, 0x00000000FFFFFFFF, 0x0000000000000602}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields591[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch0_rxdll_coarsecode_ovr_sel", "Override rxdll_coarsecode[3:0] with scr_rxdll_coarsecode_ovr[3:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ch0_rxdll_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ch0_rxdll_coarsecode_ovr", "Coarse code override value for rxdll_coarsecode[3:0]"},
#else
{0, 3, 0x0000000000000000, "RW", "ch0_rxdll_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo591[] = {{"DLLCOMP_RXCOARSEOVR_CH0", "", 0x00000678, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields592[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch1_rxdll_coarsecode_ovr_sel", "Override rxdll_coarsecode[3:0] with scr_rxdll_coarsecode_ovr[3:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ch1_rxdll_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ch1_rxdll_coarsecode_ovr", "Coarse code override value for rxdll_coarsecode[3:0]"},
#else
{0, 3, 0x0000000000000000, "RW", "ch1_rxdll_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo592[] = {{"DLLCOMP_RXCOARSEOVR_CH1", "", 0x0000067C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields593[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ecc_rxdll_coarsecode_ovr_sel", "Override rxdll_coarsecode[3:0] with scr_rxdll_coarsecode_ovr[3:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ecc_rxdll_coarsecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 30, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{4, 30, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "ecc_rxdll_coarsecode_ovr", "Coarse code override value for rxdll_coarsecode[3:0]"},
#else
{0, 3, 0x0000000000000000, "RW", "ecc_rxdll_coarsecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo593[] = {{"DLLCOMP_RXCOARSEOVR_ECC", "", 0x00000680, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields594[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch0_rxdll_finecode_ovr_sel", "Override rxdll_finecode[7:0] with scr_rxdll_finecode_ovr[7:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ch0_rxdll_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ch0_rxdll_finecode_updateovr_ovr", "When scr_rxdll_finecode_ovr_sel is active high, this bit drives rxdll_rxdqsdllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "ch0_rxdll_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch0_rxdll_finecode_ovr", "FIne code override value for rxdll_finecode[7:0]"},
#else
{0, 7, 0x0000000000000000, "RW", "ch0_rxdll_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo594[] = {{"DLLCOMP_RXFINEOVR_CH0", "", 0x00000684, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields595[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ch1_rxdll_finecode_ovr_sel", "Override rxdll_finecode[7:0] with scr_rxdll_finecode_ovr[7:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ch1_rxdll_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ch1_rxdll_finecode_updateovr_ovr", "When scr_rxdll_finecode_ovr_sel is active high, this bit drives rxdll_rxdqsdllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "ch1_rxdll_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_rxdll_finecode_ovr", "FIne code override value for rxdll_finecode[7:0]"},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_rxdll_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo595[] = {{"DLLCOMP_RXFINEOVR_CH1", "", 0x00000688, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields596[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "ecc_rxdll_finecode_ovr_sel", "Override rxdll_finecode[7:0] with scr_rxdll_finecode_ovr[7:0] . 0: disable override. 1: enable override."},
#else
{31, 31, 0x0000000000000000, "RW", "ecc_rxdll_finecode_ovr_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ecc_rxdll_finecode_updateovr_ovr", "When scr_rxdll_finecode_ovr_sel is active high, this bit drives rxdll_rxdqsdllupdateovr"},
#else
{30, 30, 0x0000000000000000, "RW", "ecc_rxdll_finecode_updateovr_ovr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 29, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 29, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ecc_rxdll_finecode_ovr", "FIne code override value for rxdll_finecode[7:0]"},
#else
{0, 7, 0x0000000000000000, "RW", "ecc_rxdll_finecode_ovr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo596[] = {{"DLLCOMP_RXFINEOVR_ECC", "", 0x0000068C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields597[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm1pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo597[] = {{"DFXVISA_ULM1PATTGEN", "", 0x00000700, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields598[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_bypass", "VISA Bypass ULM1LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_clksel", "VISA ULM1LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_datasel", "VISA ULM1LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo598[] = {{"DFXVISA_ULM1LN0", "", 0x00000704, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields599[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_bypass", "VISA Bypass ULM1LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_clksel", "VISA ULM1LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_datasel", "VISA ULM1LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm1ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo599[] = {{"DFXVISA_ULM1LN1", "", 0x00000708, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields600[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm2pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo600[] = {{"DFXVISA_ULM2PATTGEN", "", 0x0000070C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields601[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_bypass", "VISA Bypass ULM2LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_clksel", "VISA ULM2LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_datasel", "VISA ULM2LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo601[] = {{"DFXVISA_ULM2LN0", "", 0x00000710, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields602[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_bypass", "VISA Bypass ULM2LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_clksel", "VISA ULM2LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_datasel", "VISA ULM2LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm2ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo602[] = {{"DFXVISA_ULM2LN1", "", 0x00000714, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields603[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm3pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo603[] = {{"DFXVISA_ULM3PATTGEN", "", 0x00000718, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields604[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_bypass", "VISA Bypass ULM3LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_clksel", "VISA ULM3LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_datasel", "VISA ULM3LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo604[] = {{"DFXVISA_ULM3LN0", "", 0x0000071C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields605[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_bypass", "VISA Bypass ULM3LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_clksel", "VISA ULM3LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_datasel", "VISA ULM3LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm3ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo605[] = {{"DFXVISA_ULM3LN1", "", 0x00000720, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields606[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm4pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm4pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm4pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm4pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo606[] = {{"DFXVISA_ULM4PATTGEN", "", 0x00000724, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields607[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm4ln0_bypass", "VISA Bypass ULM4LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm4ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm4ln0_clksel", "VISA ULM4LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm4ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm4ln0_datasel", "VISA ULM4LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm4ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo607[] = {{"DFXVISA_ULM4LN0", "", 0x00000728, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields608[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm4ln1_bypass", "VISA Bypass ULM4LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm4ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm4ln1_clksel", "VISA ULM4LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm4ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm4ln1_datasel", "VISA ULM4LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm4ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo608[] = {{"DFXVISA_ULM4LN1", "", 0x0000072C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields609[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm5pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm5pattgen_msb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm5pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm5pattgen_lsb", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo609[] = {{"DFXVISA_ULM5PATTGEN", "", 0x00000730, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields610[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm5ln0_bypass", "VISA Bypass ULM5LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm5ln0_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm5ln0_clksel", "VISA ULM5LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm5ln0_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm5ln0_datasel", "VISA ULM5LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm5ln0_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo610[] = {{"DFXVISA_ULM5LN0", "", 0x00000734, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields611[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm5ln1_bypass", "VISA Bypass ULM5LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm5ln1_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm5ln1_clksel", "VISA ULM5LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm5ln1_clksel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm5ln1_datasel", "VISA ULM5LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm5ln1_datasel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo611[] = {{"DFXVISA_ULM5LN1", "", 0x00000738, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields612[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{12, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "bl_dfxmrgtxovren", "DQ Bytelane Tx FIFO Margin Mode config override enable for Tx data path and Latch enables via  DFXMRGTXFIFO[24:0]    1'b1  - Enable TxFIFO DFx overrides on Latch enables and TxData  1'b0 - Functional Mode of operation"},
#else
{11, 11, 0x0000000000000000, "RW", "bl_dfxmrgtxovren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "bl_dfxmrgtxwren", "DQ Bytelane TxFIFO Margin Mode Latch enable override value used to make TxFIFO latches transparent allowing the loading of all TxFIFO Latches with data programmed in DFXMRGTXFIFO[23:0], if dfxmrgtxovren is asserted(1'b1)  1'b1 - All DQ/DM/DQS Tx FIFO Latches Transparent  0'b0 - All DQ/DM/DQS TxFIFO Latches CLosed"},
#else
{10, 10, 0x0000000000000000, "RW", "bl_dfxmrgtxwren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsrise", "DQ Bytelane Tx FIFO Margin Mode DQS/B Rise Tx SubFIFO data load value. The value loaded will apply to all DQ Bytelane DQS/B Rise SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{9, 9, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsrise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsfall", "DQ Bytelane Tx FIFO Margin Mode DQS/B Fall Tx SubFIFO data load value. The value loaded will apply to all DQ Bytelane DQS/B Fall SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{8, 8, 0x0000000000000000, "RW", "bl_dfxmrgtxdqsfall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph0", "DQ Bytelane Tx FIFO Margin Mode DQ Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 0 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{7, 7, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph1", "DQ Bytelane Tx FIFO Margin Mode DQ Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 1 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{6, 6, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph2", "DQ Bytelane Tx FIFO Margin Mode DQ Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 2 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{5, 5, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph3", "DQ Bytelane Tx FIFO Margin Mode DQ Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{4, 4, 0x0000000000000000, "RW", "bl_dfxmrgtxdrise_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph0", "DQ Bytelane Tx FIFO Margin Mode DQ Phase0 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 0 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{3, 3, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph1", "DQ Bytelane Tx FIFO Margin Mode DQ Phase1 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 1 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{2, 2, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph2", "DQ Bytelane Tx FIFO Margin Mode DQ Phase2 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 2 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{1, 1, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph3", "DQ Bytelane Tx FIFO Margin Mode DQ Phase3 Fall Tx SubFIFO load value. The value loaded will apply to all DQ BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{0, 0, 0x0000000000000000, "RW", "bl_dfxmrgtxdfall_ph3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo612[] = {{"DFXMRG_BL", "", 0x0000073C, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields613[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxovren", "DQCCC Bytelane Tx FIFO Margin Mode config override enable for Tx data path and Latch enables via  DFXMRGTXFIFO[24:0]    1'b1  - Enable TxFIFO DFx overrides on Latch enables and TxData  1'b0 - Functional Mode of operation"},
#else
{15, 15, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxovren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxwren", "DQCCC Bytelane TxFIFO Margin Mode Latch enable override value used to make TxFIFO latches transparent allowing the loading of all TxFIFO Latches with data programmed in DFXMRGTXFIFO[23:0], if dfxmrgtxovren is asserted(1'b1)  1'b1 - All DQCCC/DM/DQCCCS Tx FIFO Latches Transparent  0'b0 - All DQCCC/DM/DQCCCS TxFIFO Latches CLosed"},
#else
{14, 14, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxwren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdqsrise", "DQCCC Bytelane Tx FIFO Margin Mode DQCCCS/B Rise Tx SubFIFO data load value. The value loaded will apply to all DQCCC Bytelane DQCCCS/B Rise SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{13, 13, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdqsrise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdqsfall", "DQCCC Bytelane Tx FIFO Margin Mode DQCCCS/B Fall Tx SubFIFO data load value. The value loaded will apply to all DQCCC Bytelane DQCCCS/B Fall SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{12, 12, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdqsfall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{11, 11, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{10, 10, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{9, 9, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{8, 8, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdrise_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{7, 7, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{6, 6, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase2 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{5, 5, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase3 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{4, 4, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdfall_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{3, 3, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{2, 2, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase2 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b11"},
#else
{1, 1, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase3 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_cc_dfxmrgtxdsdr_ph3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo613[] = {{"CH0_DFXMRG_CC", "", 0x00000740, 17, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields614[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "bl_dfxmrgrx_cmpval", "DFx Margin Mode DQ Bytelane Rx Compare value; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{16, 23, 0x0000000000000000, "RW", "bl_dfxmrgrx_cmpval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "cc_dfxmrgrx_db_ddrcmpval", "DFx Margin Mode CCC DDR Deadband Rx Compare value; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{8, 15, 0x0000000000000000, "RW", "cc_dfxmrgrx_db_ddrcmpval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "cc_dfxmrgrx_db_sdrsdrcmpval", "DFx Margin Mode CCC SDR deadband Rx Compare value; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{0, 7, 0x0000000000000000, "RW", "cc_dfxmrgrx_db_sdrsdrcmpval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo614[] = {{"DFXMRG_CCBLRX", "", 0x00000744, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields615[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrsel", "DFx Margin Mode SDR vs DDR Rx Compare Values"},
#else
{16, 31, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "cc_dfxmrgrx_ddrcmpval", "DFx Margin Mode CCC Bytelane Rx Compare value for DDR pins; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{8, 15, 0x0000000000000000, "RW", "cc_dfxmrgrx_ddrcmpval", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrcmpval", "DFx Margin Mode CCC Bytelane Rx Compare value for SDR pins; Used to compare Actual RxFIFO value vs Expected Rx FIFO value(TxFIFO Unloaded)"},
#else
{0, 7, 0x0000000000000000, "RW", "cc_dfxmrgrx_sdrcmpval", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo615[] = {{"DFXMRG_CCRX", "", 0x00000748, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields616[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxovren", "DQCCC Bytelane Tx FIFO Margin Mode config override enable for Tx data path and Latch enables via  DFXMRGTXFIFO[24:0]    1'b1  - Enable TxFIFO DFx overrides on Latch enables and TxData  1'b0 - Functional Mode of operation"},
#else
{15, 15, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxovren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxwren", "DQCCC Bytelane TxFIFO Margin Mode Latch enable override value used to make TxFIFO latches transparent allowing the loading of all TxFIFO Latches with data programmed in DFXMRGTXFIFO[23:0], if dfxmrgtxovren is asserted(1'b1)  1'b1 - All DQCCC/DM/DQCCCS Tx FIFO Latches Transparent  0'b0 - All DQCCC/DM/DQCCCS TxFIFO Latches CLosed"},
#else
{14, 14, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxwren", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdqsrise", "DQCCC Bytelane Tx FIFO Margin Mode DQCCCS/B Rise Tx SubFIFO data load value. The value loaded will apply to all DQCCC Bytelane DQCCCS/B Rise SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{13, 13, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdqsrise", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdqsfall", "DQCCC Bytelane Tx FIFO Margin Mode DQCCCS/B Fall Tx SubFIFO data load value. The value loaded will apply to all DQCCC Bytelane DQCCCS/B Fall SubFIFOs. Recommended setting for HVM = 2'b00"},
#else
{12, 12, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdqsfall", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{11, 11, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{10, 10, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{9, 9, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Rise Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{8, 8, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdrise_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{7, 7, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{6, 6, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase2 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 Fall SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{5, 5, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase3 Fall Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{4, 4, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdfall_ph3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph0", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase0 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 0 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{3, 3, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph1", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase1 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 1 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph2", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase2 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 2 SDR SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b11"},
#else
{1, 1, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph3", "DQCCC Bytelane Tx FIFO Margin Mode DQCCC Phase3 SDR Tx SubFIFO load value. The value loaded will apply to all DQCCC BL Phase 3 Rise SubFIFOs  There isnt a valid or invalid value for this field, recommended setting for HVM = 2'b00"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_cc_dfxmrgtxdsdr_ph3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo616[] = {{"CH1_DFXMRG_CC", "", 0x0000074C, 17, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields617[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "temp", "IO buffer activate - DQ Digital[br]Bytelane 1 SW reset for final TX flops in all upartitions."},
#else
{0, 31, 0x0000000000000000, "RW", "temp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo617[] = {{"IOBUFACT_DIGx", "", 0x0000001C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields618[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "temp", "IO buffer activate - DQ Analog[br]Tristates DQ and DQS IO buffers [br]Disable Rx sections of IO buffers [br]0 : reset [br]1 : out of reset"},
#else
{0, 31, 0x0000000000000000, "RW", "temp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo618[] = {{"IOBUFACT_AFEx", "", 0x00000018, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields619[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000061010202, "RW", "sai_ctrl_policy", "SAI Control Policy for Group 1 (LSB)"},
#else
{0, 31, 0x0000000061010202, "RW", "sai_ctrl_policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo619[] = {{"SAI_CTRL_REG0", "", 0x0000F840, 1, 0x00000000FFFFFFFF, 0x0000000061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields620[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000C00, "RW", "sai_ctrl_policy_1", "SAI Control Policy for Group 1 (MSB)"},
#else
{0, 31, 0x0000000000000C00, "RW", "sai_ctrl_policy_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo620[] = {{"SAI_CTRL_REG0_1", "", 0x0000F844, 1, 0x00000000FFFFFFFF, 0x0000000000000C00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields621[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000001000212, "RW", "sai_rw_policy0", "SAI Read/Write Policy for Group 1: policy0"},
#else
{0, 31, 0x0000000001000212, "RW", "sai_rw_policy0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo621[] = {{"SAI_RW_REG0", "", 0x0000F848, 1, 0x00000000FFFFFFFF, 0x0000000001000212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields622[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000C00, "RW", "sai_rw_policy0_1", "SAI Read/Write Policy for Group 2: policy0"},
#else
{0, 31, 0x0000000000000C00, "RW", "sai_rw_policy0_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo622[] = {{"SAI_RW_REG0_1", "", 0x0000F84C, 1, 0x00000000FFFFFFFF, 0x0000000000000C00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields623[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy1", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo623[] = {{"SAI_RW_REG1", "", 0x0000F850, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields624[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy1_1", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy1_1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo624[] = {{"SAI_RW_REG1_1", "", 0x0000F854, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields625[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy2", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo625[] = {{"SAI_RW_REG2", "", 0x0000F858, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields626[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy2_1", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "sai_rw_policy2_1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo626[] = {{"SAI_RW_REG2_1", "", 0x0000F85C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields627[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000003, "RW", "region_policy0", "CR Region Policy0: [br] 1'b1 (applicable for all indexes): The corresponding configuration register region is locked and only accessible by trusted agents associated with policy0 [br]1'b0 (applicable for all indexes): The corresponding configuration register region is unlocked - all agents (trusted or untrusted) are allowed to access this region."},
#else
{0, 31, 0x0000000000000003, "RW", "region_policy0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo627[] = {{"REG_POLICY0", "", 0x0000F860, 1, 0x00000000FFFFFFFF, 0x0000000000000003}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields628[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "region_policy1", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "region_policy1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo628[] = {{"REG_POLICY1", "", 0x0000F864, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields629[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "region_policy2", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "region_policy2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo629[] = {{"REG_POLICY2", "", 0x0000F868, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields630[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "reg_RSVD", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "reg_RSVD", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo630[] = {{"REG_RSVD", "", 0x0000F86C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields631[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW/V", "i_fbdivratio", "generic 8bit feedback divider ratio. N=i_fbdivratio"},
#else
{24, 31, 0x0000000000000000, "RW/V", "i_fbdivratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000064, "RW", "int_fbdiv", "This register will be used to set the c73p1ddrlp34l64x1top_ADPLL internal FB divider value when using long loop (external) division. At this mode the value in i_fbdivratio[7:0] should reflect the true total division ratio (including the long loop division) for the c73p1ddrlp34l64x1top_ADPLL calibration process"},
#else
{16, 23, 0x0000000000000064, "RW", "int_fbdiv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW/V", "i_ndiv", "Currently reserved bits. pre divider control.  M=i_ndiv (only 1 to 7 are valid)"},
#else
{12, 15, 0x0000000000000000, "RW/V", "i_ndiv", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo631[] = {{"PLLDIVRATIOS_0", "", 0x00000000, 3, 0x00000000FFFFFFFF, 0x0000000000640000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields632[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO/V", "o_errorflag", "General Error flag."},
#else
{31, 31, 0x0000000000000000, "RO/V", "o_errorflag", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO/V", "o_plllock", "PLL Lock indicator signal. "},
#else
{30, 30, 0x0000000000000000, "RO/V", "o_plllock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO/V", "o_refclk_req_h", "c73p1ddrlp34l64x1top_ADPLL's Refclk request bit. "},
#else
{29, 29, 0x0000000000000000, "RO/V", "o_refclk_req_h", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RO/V", "o_locktimer", "Lock time expected Indication bit."},
#else
{28, 28, 0x0000000000000000, "RO/V", "o_locktimer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 27, 0x0000000000000000, "RO/V", "dcoclk_edge_cnt", "DCO edge's counter"},
#else
{18, 27, 0x0000000000000000, "RO/V", "dcoclk_edge_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 17, 0x0000000000000000, "RO/V", "locktime_final", "Locktime counter per refclk cycles, stops at overflow / lock."},
#else
{8, 17, 0x0000000000000000, "RO/V", "locktime_final", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo632[] = {{"PLLSEQUENCE_0", "", 0x00000004, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields633[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/V", "i_force_tdccalib", "force tdc calibration in normal locking"},
#else
{31, 31, 0x0000000000000000, "RW/V", "i_force_tdccalib", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/V", "i_force_pwrgateoff", "force power gating off in all modes"},
#else
{30, 30, 0x0000000000000000, "RW/V", "i_force_pwrgateoff", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW/V", "i_force_clkgateoff", "force clock gating off in all modes"},
#else
{29, 29, 0x0000000000000000, "RW/V", "i_force_clkgateoff", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "force_boot", "EV: forces boot locking instead of normal locking"},
#else
{28, 28, 0x0000000000000000, "RW", "force_boot", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "force_dcoen", "EV: forces dco enable even if PLL is off. Need this for example in openloop mode"},
#else
{27, 27, 0x0000000000000000, "RW", "force_dcoen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "force_digcoreen", "EV: forces digital core reset off (unless pwrgood=0)"},
#else
{26, 26, 0x0000000000000000, "RW", "force_digcoreen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW/V", "i_lockwdet_win", "phase error threshold at which  PLL is unlocked: \r\n"
"'2'b11': -16<pe<15\r\n"
"'2'b10': -15<pe<14\r\n"
"'2'b01': -13<pe<12\r\n"
"'2'b00': -9<pe<8"},
#else
{24, 25, 0x0000000000000000, "RW/V", "i_lockwdet_win", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW/V", "i_lockdet_cnt", "lock counter window configuration:\r\n"
"'1'b0' - 32 cycles\r\n"
"'1'b1' - 64 cycles"},
#else
{23, 23, 0x0000000000000000, "RW/V", "i_lockdet_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW/V", "i_fine_limit", "defines distance of fine code from edges that would trigger SFR trimming. Distance defined by 2^(fine_limit+5)"},
#else
{21, 22, 0x0000000000000000, "RW/V", "i_fine_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW/V", "i_refclkdly_sel", "control delay of refclk_dly clock that is used by DCO latches"},
#else
{19, 20, 0x0000000000000000, "RW/V", "i_refclkdly_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "refclk2fnlch_sel", "Selects refproc's delayed clock / inverted version of refclk2dig for DCO latches n DS."},
#else
{18, 18, 0x0000000000000000, "RW", "refclk2fnlch_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 17, 0x0000000000000000, "RW/V", "i_int_coeff", "Ki filter coefficient, 2^n. Two's complement"},
#else
{13, 17, 0x0000000000000000, "RW/V", "i_int_coeff", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 12, 0x0000000000000000, "RW/V", "i_prop_coeff", "Kp filter coefficient, 2^n. Two's complement"},
#else
{9, 12, 0x0000000000000000, "RW/V", "i_prop_coeff", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo633[] = {{"CONFIG_0", "", 0x00000008, 13, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields634[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/V", "i_fbclk_extsel", "external feedback clock select (allowing use of external feedback divider). In this case, user must set fbdivratio to the feedback ratio he uses"},
#else
{31, 31, 0x0000000000000000, "RW/V", "i_fbclk_extsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/V", "i_dcoclk_extsel", "long loop clock select through dcoclk_ext clock"},
#else
{30, 30, 0x0000000000000000, "RW/V", "i_dcoclk_extsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 29, 0x0000000000000004, "RW", "clkgdly_cnt", "Delay for clock gating (0 menas no delay)."},
#else
{27, 29, 0x0000000000000004, "RW", "clkgdly_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "config_1_bonus", "Bonus Cells"},
#else
{26, 26, 0x0000000000000000, "RW", "config_1_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW/V", "i_dcodither_en", "enable sigma delta"},
#else
{25, 25, 0x0000000000000000, "RW/V", "i_dcodither_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 24, 0x0000000000000000, "RW/V", "i_dcodither_clk_sel", "select sigma delta over sampling clock"},
#else
{23, 24, 0x0000000000000000, "RW/V", "i_dcodither_clk_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "dcodither_ovrd", "bypass sigma delta dithering bit with external bit"},
#else
{22, 22, 0x0000000000000000, "RW", "dcodither_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "dcodither_val", "sigma delta dithering external bit"},
#else
{21, 21, 0x0000000000000000, "RW", "dcodither_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 20, 0x0000000000000000, "RW", "pemod_frq", "EV: pe modulation frequency. \r\n"
"4'b0: no frequency modulation\r\n"
"4'bxxx: Fmod = Frefclk/2^(pemode_frq+1)"},
#else
{17, 20, 0x0000000000000000, "RW", "pemod_frq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 16, 0x0000000000000000, "RW", "pemod_amp", "EV: pe modulation amplitude. This register is Two's complementry.\r\n"
"The value of this register sets the pe_offset value.\r\n"
"NOTE: if pemod_frq[3:0] = 4'b0, this value will set the pe_offset 'as is' otherwise its LSB will be overidden to 1'b1 by HW"},
#else
{11, 16, 0x0000000000000000, "RW", "pemod_amp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo634[] = {{"CONFIG_1", "", 0x0000000C, 10, 0x00000000FFFFFFFF, 0x0000000020000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields635[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "digconfig", "Digital's internal spare config."},
#else
{16, 31, 0x0000000000000000, "RW", "digconfig", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW/V", "i_pllconfig", "Bonus Cells"},
#else
{0, 15, 0x0000000000000000, "RW/V", "i_pllconfig", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo635[] = {{"CONFIG_2", "", 0x00000010, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields636[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW/V", "i_sfrcalib_fmincnt", "set to round(1.1GHz/Fref)-1 for proper SFR calibration"},
#else
{24, 31, 0x0000000000000000, "RW/V", "i_sfrcalib_fmincnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW/V", "i_sfrcalib_fmaxcnt", "set to round(3.43GHz/Fref)-1 for proper SFR calibration"},
#else
{16, 23, 0x0000000000000000, "RW/V", "i_sfrcalib_fmaxcnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW/V", "i_tdccalib_osccnt", "set to round(1.47GHz/Frefclk)-1 for proper TDC calibration"},
#else
{8, 15, 0x0000000000000000, "RW/V", "i_tdccalib_osccnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 7, 0x0000000000000000, "RW/V", "i_locktimercnt_th", "Set this bus to the number of refclk cycles after which the o_locktimer is asserted,"},
#else
{1, 7, 0x0000000000000000, "RW/V", "i_locktimercnt_th", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo636[] = {{"CONFIG_3", "", 0x00000014, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields637[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x00000000000001FF, "RO/V", "fine_min", "DCO's fine code min sampled value."},
#else
{23, 31, 0x00000000000001FF, "RO/V", "fine_min", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x000000000000000F, "RO/V", "pe_min", "Phase error min sampled value."},
#else
{18, 22, 0x000000000000000F, "RO/V", "pe_min", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 17, 0x0000000000000000, "RO/V", "fine_max", "DCO's fine code max sampled value."},
#else
{9, 17, 0x0000000000000000, "RO/V", "fine_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 8, 0x0000000000000010, "RO/V", "pe_max", "Phase error max sampled value."},
#else
{4, 8, 0x0000000000000010, "RO/V", "pe_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "spare_filter", "Spare registers for Filter"},
#else
{0, 3, 0x0000000000000000, "RW", "spare_filter", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo637[] = {{"FILTER_OBS", "", 0x00000018, 5, 0x00000000FFFFFFFF, 0x00000000FFBC0100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields638[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO/V", "odfx_avisa_dbgbus", "Visa lane's 1 n 0"},
#else
{16, 31, 0x0000000000000000, "RO/V", "odfx_avisa_dbgbus", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo638[] = {{"VISA_OUT", "", 0x0000001C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields639[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000008, "RW", "tdctrim_val", "TDC trim override value"},
#else
{28, 31, 0x0000000000000008, "RW", "tdctrim_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "tdctrim_ovrd", "TDC trim override select"},
#else
{27, 27, 0x0000000000000000, "RW", "tdctrim_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 26, 0x0000000000000100, "RW", "dcofine_val", "EV: DCO fine override value"},
#else
{18, 26, 0x0000000000000100, "RW", "dcofine_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dcofine_ovrd", "EV: DCO fine override select"},
#else
{17, 17, 0x0000000000000000, "RW", "dcofine_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 16, 0x000000000000003F, "RW", "dcocoarse_val", "EV: DCO coarse override value"},
#else
{10, 16, 0x000000000000003F, "RW", "dcocoarse_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "dcocoarse_ovrd", "EV: bypass coarse calibration code with coarse_val"},
#else
{9, 9, 0x0000000000000000, "RW", "dcocoarse_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 8, 0x0000000000000000, "RW/V", "i_sfr_spare", "Spare bit for the SFR"},
#else
{5, 8, 0x0000000000000000, "RW/V", "i_sfr_spare", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "fine_minmax_selcnt", "EV:\r\n"
"1' - use fine min max loggin window counter from (cfg_lockdet_cnt), \r\n"
"'0'- select narrow lock counter value (cfg_strict_lockwin)"},
#else
{4, 4, 0x0000000000000000, "RW", "fine_minmax_selcnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "fine_minmax_timer", "EV:\r\n"
"1' - disable minmax sampling by counter. \r\n"
"'0'- disbale by falling minmaxen bit"},
#else
{3, 3, 0x0000000000000000, "RW", "fine_minmax_timer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo639[] = {{"DFT_0", "", 0x00000020, 9, 0x00000000FFFFFFFF, 0x000000008400FC00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields640[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "dcolat_byp", "Makes DCO latches transparent. Allows open loop checks without refclk."},
#else
{31, 31, 0x0000000000000000, "RW", "dcolat_byp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tdcbbpd_en", "Enable bbpd in the sign bit of the TDC instead of FFPD"},
#else
{30, 30, 0x0000000000000000, "RW", "tdcbbpd_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000003, "RW", "o_dcsense_chopsel", "div_farm clock chooper: '00' = refclk. '01', '11' = vss, '10' = vcc"},
#else
{28, 29, 0x0000000000000003, "RW", "o_dcsense_chopsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "force_cloopen", "EV: forces PLL into close loop mode and final filter coefficient"},
#else
{27, 27, 0x0000000000000000, "RW", "force_cloopen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "force_tdcosc", "EV: configures TDC chain as ring oscillator"},
#else
{26, 26, 0x0000000000000000, "RW", "force_tdcosc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW/V", "i_force_fbdivrstoff", "force feedback divider reset off in all modes"},
#else
{25, 25, 0x0000000000000000, "RW/V", "i_force_fbdivrstoff", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "dcocalib_cnthalf", "dco calibration (and tdc calibration?) counter counts half of default count for faster calibration"},
#else
{24, 24, 0x0000000000000000, "RW", "dcocalib_cnthalf", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "narrow_lockwin", "Strict Lock window config. \r\n"
"'1' = -5<pe_tdc<4 for 16 cycles.\r\n"
"'0' = -3<pe_tdc<2 for 8 cycles."},
#else
{23, 23, 0x0000000000000000, "RW", "narrow_lockwin", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "fine_pe_minmaxen", "when '1', min/max values of fine/pe code are monitored this mechanism is disabled by HW when lock signal is de-asserted"},
#else
{22, 22, 0x0000000000000000, "RW", "fine_pe_minmaxen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "fine_pe_minmaxrst", "resets the fine minmax value"},
#else
{21, 21, 0x0000000000000000, "RW", "fine_pe_minmaxrst", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "p2p_fine_pe_select", "Select which peak to peak value will be written to 'fine_pe_minmax_p2p[8:0]'. \r\n"
"'0' - log fine values,\r\n"
"'1' - log PE values."},
#else
{20, 20, 0x0000000000000000, "RW", "p2p_fine_pe_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "dft_1_bonus", "Bonus Cells"},
#else
{19, 19, 0x0000000000000000, "RW", "dft_1_bonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "fine_sweepen", "EV: sweep fine code (triangle sweep)"},
#else
{18, 18, 0x0000000000000000, "RW", "fine_sweepen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "coarsesweep_en", "Coarse sweep bit."},
#else
{17, 17, 0x0000000000000000, "RW", "coarsesweep_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "tdcsweep_en", "TDC sweep bit."},
#else
{16, 16, 0x0000000000000000, "RW", "tdcsweep_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW/V", "i_kpscale", "Kp scaling during startup for faster lock (2^n)"},
#else
{14, 15, 0x0000000000000000, "RW/V", "i_kpscale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW/V", "i_kiscale", "Ki scaling during startup for faster lock (2^n)"},
#else
{12, 13, 0x0000000000000000, "RW/V", "i_kiscale", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW/V", "i_kpkiscale_cnt", "controls number of refclk cycles at startup at which Kp and Ki are scaled up for faster lock (kpscale, kiscale)"},
#else
{10, 11, 0x0000000000000000, "RW/V", "i_kpkiscale_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 9, 0x0000000000000000, "RO/V", "fine_pe_minmax_p2p", "EV: EV: fine/pe (depends on p2p_fine_pe_selsect cfg) min - max values peak to peak"},
#else
{1, 9, 0x0000000000000000, "RO/V", "fine_pe_minmax_p2p", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lock_boost_en", "if asserted: FSM stays in gain boost, without time limit, till PLL is locked."},
#else
{0, 0, 0x0000000000000000, "RW", "lock_boost_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo640[] = {{"DFT_1", "", 0x00000024, 20, 0x00000000FFFFFFFF, 0x0000000030000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields641[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO/V", "o_digtop_obs", "Digital Obs out."},
#else
{28, 31, 0x0000000000000000, "RO/V", "o_digtop_obs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO/V", "tdc_scan_err", "TDC scan test error flag."},
#else
{27, 27, 0x0000000000000000, "RO/V", "tdc_scan_err", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO/V", "narrow_lock", "Indicator signal for narrow criteria c73p1ddrlp34l64x1top_ADPLL locking.\r\n"
"This signal behaviour is defined by 'narrow_lockwin' cfg bit"},
#else
{26, 26, 0x0000000000000000, "RO/V", "narrow_lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RO/V", "lock_fail", "PLL went out of lock."},
#else
{25, 25, 0x0000000000000000, "RO/V", "lock_fail", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO/V", "sequence_fail", "Calib procedure fail flag."},
#else
{24, 24, 0x0000000000000000, "RO/V", "sequence_fail", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO/V", "fn_ovrfl_pos", "Fine Positive code overflow."},
#else
{23, 23, 0x0000000000000000, "RO/V", "fn_ovrfl_pos", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO/V", "fn_ovrfl_neg", "Fine Negative code overflow."},
#else
{22, 22, 0x0000000000000000, "RO/V", "fn_ovrfl_neg", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RO/V", "p1_ovrflw_pos", "Filter's Integrator Positive code overflow."},
#else
{21, 21, 0x0000000000000000, "RO/V", "p1_ovrflw_pos", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO/V", "p1_ovrflw_neg", "Filter's Integrator Negative code overflow."},
#else
{20, 20, 0x0000000000000000, "RO/V", "p1_ovrflw_neg", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO/V", "sfrcalib_ovrfl", "SFR calib overflow."},
#else
{19, 19, 0x0000000000000000, "RO/V", "sfrcalib_ovrfl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO/V", "sfrtrim_ovrfl", "SFR trim overflow."},
#else
{18, 18, 0x0000000000000000, "RO/V", "sfrtrim_ovrfl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x0000000000000008, "RW", "obs_sel3", "obs(3) muxing control bits.\r\n"
"Same control settings apply as noted in obs_sel0[3:0]"},
#else
{14, 17, 0x0000000000000008, "RW", "obs_sel3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x000000000000000B, "RW", "obs_sel2", "obs(2) muxing control bits.\r\n"
"Same control settings apply as noted in obs_sel0[3:0]"},
#else
{10, 13, 0x000000000000000B, "RW", "obs_sel2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 9, 0x0000000000000000, "RW", "obs_sel1", "obs(1)muxing control bits.\r\n"
"Same control settings apply as noted in obs_sel0[3:0]"},
#else
{6, 9, 0x0000000000000000, "RW", "obs_sel1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 5, 0x0000000000000003, "RW", "obs_sel0", "obs(0) muxing control bits.\r\n"
"--------------------------------------------\r\n"
"|    i_obs_sel[0] |      o_obs[0]     |\r\n"
"---------------------------------------------\r\n"
"|        0xxx          | digtop_obs[0] |\r\n"
"--------------------------------------------\r\n"
"|        1000          |      dcoclk          |\r\n"
"--------------------------------------------\r\n"
"|        1001          |    dcoclk_div2  |\r\n"
"--------------------------------------------\r\n"
"|        1010          |   dcoclk_div4   |\r\n"
"--------------------------------------------\r\n"
"|        1011          |          fbclk         |\r\n"
"--------------------------------------------\r\n"
"|        1100          |          refclk       |\r\n"
"--------------------------------------------\r\n"
"|        1101          |          fbclk16    |\r\n"
"--------------------------------------------\r\n"
"|        1110          |         refclk16   |\r\n"
"--------------------------------------------\r\n"
"|        1111          |      dither_bit   |\r\n"
"--------------------------------------------"},
#else
{2, 5, 0x0000000000000003, "RW", "obs_sel0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "narrow_lock_late", "Narrow lock time indicator signals, this signal asserts in case the narrow lock asserts after o_locktimer assertion"},
#else
{1, 1, 0x0000000000000000, "RO/V", "narrow_lock_late", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo641[] = {{"DFT_2", "", 0x00000028, 16, 0x00000000FFFFFFFF, 0x0000000000022C0C}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields642[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "sfr_monsel", "Select for SFR analog monitor"},
#else
{24, 31, 0x0000000000000000, "RW", "sfr_monsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000008, "RW", "sfrcalib_val", "sfr calibration initial value. Also used as override value when calib_ovrd is 1"},
#else
{20, 23, 0x0000000000000008, "RW", "sfrcalib_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000008, "RW", "sfrtrim_val", "EV: sfr trim override value"},
#else
{16, 19, 0x0000000000000008, "RW", "sfrtrim_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "sfrcalib_ovrd", "EV: sfr calibration is bypassed with sfrcalib_val"},
#else
{15, 15, 0x0000000000000000, "RW", "sfrcalib_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "sfrtrim_ovrd", "EV: sfr trim override select"},
#else
{14, 14, 0x0000000000000000, "RW", "sfrtrim_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "sfren_ovrd", "EV: SFR enable override (bypass the power up sequence)"},
#else
{13, 13, 0x0000000000000000, "RW", "sfren_ovrd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "sfren_val", "EV: SFR enable value"},
#else
{12, 12, 0x0000000000000000, "RW", "sfren_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "sfr_bypass", "EV: SFR bypass control"},
#else
{11, 11, 0x0000000000000000, "RW", "sfr_bypass", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "sfrtimer_cnt2x", "EV: multiplies SFR counters by 2x"},
#else
{10, 10, 0x0000000000000000, "RW", "sfrtimer_cnt2x", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW/V", "i_sfrsupplymode", "SFR supply indicator. \r\n"
"00 - Not allowed\r\n"
"01 - 1.2V\r\n"
"10 - 1.25V\r\n"
"11 - 1.35V"},
#else
{8, 9, 0x0000000000000000, "RW/V", "i_sfrsupplymode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW/V", "i_sfrtimer_coef", "set this bus to round((Frefclk / 20MHz) - 1) to allow c73p1ddrlp34l64x1top_ADPLL generate an absolute timer for SFR trimming, SFR calibration, SFR on and DCO settle"},
#else
{4, 7, 0x0000000000000000, "RW/V", "i_sfrtimer_coef", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "sfrlpfres_ovrd_sel", "enable the override of the lpf resistor bypass control using  sfrlpfres_ovrd_val"},
#else
{3, 3, 0x0000000000000000, "RW", "sfrlpfres_ovrd_sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "sfrlpfres_ovrd_val", "disable the lpf resistor bypass"},
#else
{2, 2, 0x0000000000000000, "RW", "sfrlpfres_ovrd_val", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "digmode_en", "enable digmod during sfr_disable"},
#else
{1, 1, 0x0000000000000000, "RW", "digmode_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo642[] = {{"SFRCONFIG_0", "", 0x0000002C, 14, 0x00000000FFFFFFFF, 0x0000000000880000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields643[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "bisten", "HVM: Triggers bist block."},
#else
{31, 31, 0x0000000000000000, "RW", "bisten", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 30, 0x0000000000000000, "RW", "fbdivratio_bistmax", "HVM: Top bist sweep division value."},
#else
{23, 30, 0x0000000000000000, "RW", "fbdivratio_bistmax", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 22, 0x0000000000000000, "RW", "fbdivratio_bistmin", "HVM: Bottom bist sweep division value."},
#else
{15, 22, 0x0000000000000000, "RW", "fbdivratio_bistmin", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000001, "RW", "crs_precision", "Triggers another cycle of DCO calibration, and selects a more accurate coarse code."},
#else
{14, 14, 0x0000000000000001, "RW", "crs_precision", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000001, "RO/V", "fbdiv_shmoo_bist_flag", "HVM: This bit indicates if the fbdiv shmoo BIST passes. Its value is valid only in case 'bist_done' = 1'b1.\r\n"
"1'b0: test faild\r\n"
"1'b1: test passed"},
#else
{13, 13, 0x0000000000000001, "RO/V", "fbdiv_shmoo_bist_flag", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO/V", "bist_done", "HVM: this is an auto set bit (set by HW) indicating that a full fbdiv shmoo BIST cycle has completed.\r\n"
"1'b0: BIST is either in progress or did not triggered\r\n"
"1'b1: BIST test has completed\r\n"
"NOTE: This bit does not indicated wether the test passed/failed."},
#else
{12, 12, 0x0000000000000000, "RO/V", "bist_done", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo643[] = {{"DFT_BIST", "", 0x00000030, 6, 0x00000000FFFFFFFF, 0x0000000000006000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields644[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000008, "RO/V", "o_sfr_calib_out", "SFR fast trim code."},
#else
{28, 31, 0x0000000000000008, "RO/V", "o_sfr_calib_out", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000008, "RO/V", "o_sfr_trim_out", "SFR slow trim code."},
#else
{24, 27, 0x0000000000000008, "RO/V", "o_sfr_trim_out", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000007, "RO/V", "o_tdc_trim_out", "TDC trim code."},
#else
{20, 23, 0x0000000000000007, "RO/V", "o_tdc_trim_out", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 19, 0x0000000000000000, "RO/V", "o_dco_coarse_out", "DCO coarse code."},
#else
{13, 19, 0x0000000000000000, "RO/V", "o_dco_coarse_out", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo644[] = {{"CALIB_MNTR", "", 0x00000034, 4, 0x00000000FFFFFFFF, 0x0000000088700000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields645[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pu_override", "grp0 pull up override code"},
#else
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pu_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pd_override", "grp0 pull down override code"},
#else
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pd_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{15, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pu_override", "grp1 pull up override code"},
#else
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pu_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 14, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved2", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pd_override", "grp1 pull down override code"},
#else
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pd_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo645[] = {{"DPIC_LRCOMP_OVR1", "", 0x00000000, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields646[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp2_pu_override", "grp2 pull up override code"},
#else
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp2_pu_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp2_pd_override", "grp2 pull down override code"},
#else
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp2_pd_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{15, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp3_pu_override", "grp3 pull up override code"},
#else
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp3_pu_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 14, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved2", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp3_pd_override", "grp3 pull down override code"},
#else
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp3_pd_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo646[] = {{"DPIC_LRCOMP_OVR2", "", 0x00000004, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields647[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp4_pu_override", "grp4 pull up override code"},
#else
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp4_pu_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp4_pd_override", "grp4 pull down override code"},
#else
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp4_pd_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{15, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp5_pu_override", "grp5 pull up override code"},
#else
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp5_pu_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 14, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved2", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp5_pd_override", "grp5 pull down override code"},
#else
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp5_pd_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo647[] = {{"DPIC_LRCOMP_OVR3", "", 0x00000008, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields648[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{14, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "lrcomppd_grp_override_en", "Pull down override enable"},
#else
{8, 13, 0x0000000000000000, "RW", "lrcomppd_grp_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lrcomppu_grp_override_en", "Pull up override enable"},
#else
{0, 5, 0x0000000000000000, "RW", "lrcomppu_grp_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo648[] = {{"DPIC_LRCOMP_PUPDOVR", "", 0x0000000C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields649[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp0", "PU / PD Code"},
#else
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp0", "PU / PD Code"},
#else
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp1", "PU / PD Code"},
#else
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp1", "PU / PD Code"},
#else
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo649[] = {{"DPIC_LRCOMP_CODES_0", "", 0x00000010, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields650[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp2", "PU / PD Code"},
#else
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp2", "PU / PD Code"},
#else
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp3", "PU / PD Code"},
#else
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp3", "PU / PD Code"},
#else
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo650[] = {{"DPIC_LRCOMP_CODES_1", "", 0x00000014, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields651[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp4", "PU / PD Code"},
#else
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp4", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp4", "PU / PD Code"},
#else
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp4", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp5", "PU / PD Code"},
#else
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp5", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp5", "PU / PD Code"},
#else
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp5", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo651[] = {{"DPIC_LRCOMP_CODES_2", "", 0x00000018, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields652[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{26, 30, 0x0000000000000001, "RW", "rcomp_numave", "Number of times to repeat and average the Rcomp compensation"},
#else
{26, 30, 0x0000000000000001, "RW", "rcomp_numave", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{26, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{26, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 25, 0x0000000000000020, "RW", "rcomp_initval", "Initial value for Rcomp binary search"},
#else
{19, 25, 0x0000000000000020, "RW", "rcomp_initval", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 25, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 25, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 18, 0x0000000000000010, "RW", "rcomp_initstep", "Initial step value for Rcomp binary search"},
#else
{12, 18, 0x0000000000000010, "RW", "rcomp_initstep", NULL},
#endif
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000A, "RW", "rcomp_numsteps", "Number of binary search steps"},
#else
{8, 11, 0x000000000000000A, "RW", "rcomp_numsteps", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x000000000000000E, "RW", "rcomp_enable_delay", "Delay after enabling Rcomp before starting measurement timer"},
#else
{0, 7, 0x000000000000000E, "RW", "rcomp_enable_delay", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo652[] = {{"DPIC_GRCOMP_CFG1", "", 0x0000001C, 6, 0x00000000FFFFFFFF, 0x0000000005010A0E}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields653[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{28, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 27, 0x000000000000000E, "RW", "rcomp_sampdel1", "Rcomp sample time 1"},
#else
{20, 27, 0x000000000000000E, "RW", "rcomp_sampdel1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 19, 0x000000000000000E, "RW", "rcomp_sampdel2", "Rcomp sample time 2"},
#else
{12, 19, 0x000000000000000E, "RW", "rcomp_sampdel2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 11, 0x000000000000000E, "RW", "rcomp_sampdel3", "Rcomp sample time 3"},
#else
{4, 11, 0x000000000000000E, "RW", "rcomp_sampdel3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{2, 3, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "comp_msgbus_clk_div", "indicates the division ratio of the c73p1ddrlp34l64x1top_comp clock w.r.t spid clk"},
#else
{0, 1, 0x0000000000000001, "RW", "comp_msgbus_clk_div", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo653[] = {{"DPIC_GRCOMP_CFG2", "", 0x00000020, 6, 0x00000000FFFFFFFF, 0x0000000000E0E0E1}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields654[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{12, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000F, "RW", "gcomp_ch_en", "Tells which channels are enabled. '1' channel enabled '0' channel disabled. This must be equal to the corresponding bits in the LCOMP"},
#else
{8, 11, 0x000000000000000F, "RW", "gcomp_ch_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x000000000000003F, "RW", "rcomp_max_code_val", "Rcomp max value of code. The live code wont go beyond this. If the c73p1ddrlp34l64x1top_comp sm gives a value greater than this, it will be capped to this value."},
#else
{0, 7, 0x000000000000003F, "RW", "rcomp_max_code_val", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo654[] = {{"DPIC_GRCOMP_CFG3", "", 0x00000024, 3, 0x00000000FFFFFFFF, 0x0000000000000F3F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields655[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000020, "RW", "comp_vref_grp0", "vrefctrl voltage"},
#else
{24, 31, 0x0000000000000020, "RW", "comp_vref_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000020, "RW", "comp_vref_grp1", "vrefctrl voltage"},
#else
{16, 23, 0x0000000000000020, "RW", "comp_vref_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000020, "RW", "comp_vref_grp2", "vrefctrl voltage"},
#else
{8, 15, 0x0000000000000020, "RW", "comp_vref_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000020, "RW", "comp_vref_grp3", "vrefctrl voltage"},
#else
{0, 7, 0x0000000000000020, "RW", "comp_vref_grp3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo655[] = {{"DPIC_GRCOMP_VREF_0", "", 0x00000028, 4, 0x00000000FFFFFFFF, 0x0000000020202020}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields656[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000020, "RW", "comp_vref_grp4", "vrefctrl voltage"},
#else
{8, 15, 0x0000000000000020, "RW", "comp_vref_grp4", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000020, "RW", "comp_vref_grp5", "vrefctrl voltage"},
#else
{0, 7, 0x0000000000000020, "RW", "comp_vref_grp5", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo656[] = {{"DPIC_GRCOMP_VREF_1", "", 0x0000002C, 3, 0x00000000FFFFFFFF, 0x0000000000002020}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields657[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 30, 0x0000000000000000, "RW", "comp_rcomp_pu_code_copy_bits", "tells the rcomp to copy the adjecent code instead of evaluating it"},
#else
{23, 30, 0x0000000000000000, "RW", "comp_rcomp_pu_code_copy_bits", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000001, "RW", "delta_timer_expire_cnt", "Number of clock cycles, for the design to wait before taking action on bus_quiet_time_gnt. This must be set the same as LCOMP bqt_settle_width"},
#else
{16, 22, 0x0000000000000001, "RW", "delta_timer_expire_cnt", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 15, 0x0000000000000960, "RW", "comp_rcomp_mstrcompctl_timer_exp_cnt", "This count estimates the number of cycles it would take for all LCOMP from the start of LCOMP evaluation to the finish of LCOMP evaluation."},
#else
{1, 15, 0x0000000000000960, "RW", "comp_rcomp_mstrcompctl_timer_exp_cnt", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "comprst_b", "async active low reset for gcomp"},
#else
{0, 0, 0x0000000000000000, "RW", "comprst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo657[] = {{"DPIC_GRCOMP_RSTCTL", "", 0x00000030, 5, 0x00000000FFFFFFFF, 0x00000000000112C0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields658[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rcomp_clkgate_en", "Clock gating contorl for rcomp."},
#else
{0, 0, 0x0000000000000000, "RW", "rcomp_clkgate_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo658[] = {{"DPIC_GRCOMP_CLKGATE", "", 0x00000034, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields659[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/1S/V", "rcomp_init_comp", "bit to start the initial rcomp"},
#else
{0, 0, 0x0000000000000000, "RW/1S/V", "rcomp_init_comp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo659[] = {{"DPIC_GRCOMP_INIT", "", 0x00000038, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields660[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{26, 30, 0x0000000000000001, "RW", "lrcomp_numave", "Number of times to repeat and average the Rcomp compensation"},
#else
{26, 30, 0x0000000000000001, "RW", "lrcomp_numave", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{26, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{26, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 25, 0x0000000000000020, "RW", "lrcomp_initval", "Initial value for Rcomp binary search"},
#else
{19, 25, 0x0000000000000020, "RW", "lrcomp_initval", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 25, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 25, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 18, 0x0000000000000010, "RW", "lrcomp_initstep", "Initial step value for Rcomp binary search"},
#else
{12, 18, 0x0000000000000010, "RW", "lrcomp_initstep", NULL},
#endif
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000A, "RW", "lrcomp_numsteps", "Number of binary search steps"},
#else
{8, 11, 0x000000000000000A, "RW", "lrcomp_numsteps", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x000000000000000E, "RW", "lrcomp_enable_delay", "Delay after enabling Rcomp before starting measurement timer"},
#else
{0, 7, 0x000000000000000E, "RW", "lrcomp_enable_delay", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo660[] = {{"DPIC_LRCOMP_CFG1", "", 0x0000003C, 6, 0x00000000FFFFFFFF, 0x0000000005010A0E}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields661[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 26, 0x000000000000000E, "RW", "lrcomp_sampdel1", "Rcomp sample time 1"},
#else
{19, 26, 0x000000000000000E, "RW", "lrcomp_sampdel1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{11, 18, 0x000000000000000E, "RW", "lrcomp_sampdel2", "Rcomp sample time 2"},
#else
{11, 18, 0x000000000000000E, "RW", "lrcomp_sampdel2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{11, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{11, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 10, 0x000000000000000E, "RW", "lrcomp_sampdel3", "Rcomp sample time 3"},
#else
{3, 10, 0x000000000000000E, "RW", "lrcomp_sampdel3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 10, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 10, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "lcomp_sel_membus_frm_gcomp", "set it to '1' to select the membus form gcomp, '0' to select it from previous module."},
#else
{2, 2, 0x0000000000000000, "RW", "lcomp_sel_membus_frm_gcomp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "lrcomp_msgbus_clk_div", "indicates the division ratio of the c73p1ddrlp34l64x1top_comp clock w.r.t spid clk"},
#else
{0, 1, 0x0000000000000001, "RW", "lrcomp_msgbus_clk_div", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo661[] = {{"DPIC_LRCOMP_CFG2", "", 0x00000040, 6, 0x00000000FFFFFFFF, 0x0000000000707071}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields662[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{12, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000F, "RW", "lcomp_ch_en", "Tells which channels are enabled. '1' channel enabled '0' channel disabled. This must be equal to the corresponding bits in the GCOMP"},
#else
{8, 11, 0x000000000000000F, "RW", "lcomp_ch_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x000000000000003F, "RW", "lrcomp_max_code_val", "Rcomp max value of code. The live code wont go beyond this. If the c73p1ddrlp34l64x1top_comp sm gives a value greater than this, it will be capped to this value."},
#else
{0, 7, 0x000000000000003F, "RW", "lrcomp_max_code_val", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo662[] = {{"DPIC_LRCOMP_CFG3", "", 0x00000044, 3, 0x00000000FFFFFFFF, 0x0000000000000F3F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields663[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{22, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{15, 21, 0x0000000000000001, "RW", "lrcomp_pd_live_override", "override for pull down live rcomp code going to AFE"},
#else
{15, 21, 0x0000000000000001, "RW", "lrcomp_pd_live_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{15, 21, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{15, 21, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "lrcomp_pd_live_override_en", "override enable for override for pull down live rcomp code going to AFE"},
#else
{14, 14, 0x0000000000000000, "RW", "lrcomp_pd_live_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 14, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{8, 13, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 7, 0x0000000000000000, "RW", "lrcomp_pd_puref_override", "not used"},
#else
{1, 7, 0x0000000000000000, "RW", "lrcomp_pd_puref_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lrcomp_pd_puref_override_en", "not used"},
#else
{0, 0, 0x0000000000000000, "RW", "lrcomp_pd_puref_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo663[] = {{"DPIC_LRCOMP_OVR0", "", 0x00000048, 6, 0x00000000FFFFFFFF, 0x0000000000008000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields664[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x0000000000000000, "RW", "clktx_rcompdelaysel", "CLKTX selects one of several clock inputs to get best update margin"},
#else
{29, 30, 0x0000000000000000, "RW", "clktx_rcompdelaysel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{29, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{29, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{28, 28, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 28, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{27, 27, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 26, 0x0000000000000001, "RW", "sel_bqt_for_lcomp", "selects the bus_quiet_time_gnt signal for lcomp buffer."},
#else
{25, 26, 0x0000000000000001, "RW", "sel_bqt_for_lcomp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000001, "RW", "lrcomp_pd_staticlive", "static live signal for PD c73p1ddrlp34l64x1top_comp buffer."},
#else
{24, 24, 0x0000000000000001, "RW", "lrcomp_pd_staticlive", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000001, "RW", "lrcomp_pu_static", "static leg signal for PD c73p1ddrlp34l64x1top_comp buffer."},
#else
{23, 23, 0x0000000000000001, "RW", "lrcomp_pu_static", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "Reserved2", "Reserved bits"},
#else
{22, 22, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{22, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "lrcomp_general_timer", "not used."},
#else
{16, 21, 0x0000000000000000, "RW", "lrcomp_general_timer", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 21, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "lrcomp_stg2_width", "no of cycles needed for stage 2 update."},
#else
{12, 15, 0x0000000000000000, "RW", "lrcomp_stg2_width", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000008, "RW", "lrcomp_update_len", "no of cycles needed for code update."},
#else
{8, 11, 0x0000000000000008, "RW", "lrcomp_update_len", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "lrcomp_update", "config control for updating rcomp codes."},
#else
{7, 7, 0x0000000000000000, "RW", "lrcomp_update", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "lrcomp_updtbyen", "enable for config concifg control for updating rcomp codes."},
#else
{6, 6, 0x0000000000000000, "RW", "lrcomp_updtbyen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lrcomp_grp_update_disable", "config contorl for disabling rcomp code per group."},
#else
{0, 5, 0x0000000000000000, "RW", "lrcomp_grp_update_disable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo664[] = {{"DPIC_LRCOMP_CTL0", "", 0x0000004C, 14, 0x00000000FFFFFFFF, 0x0000000003800800}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields665[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 16, 0x0000000000000000, "RW", "lcomp_pdcode_copy_bits", "tells the rcomp to copy the adjecent code instead of evaluating it"},
#else
{12, 16, 0x0000000000000000, "RW", "lcomp_pdcode_copy_bits", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x000000000000003F, "RW", "lrcomp_pdcode_valid_bits", "tells the rcomp which groups are valid."},
#else
{6, 11, 0x000000000000003F, "RW", "lrcomp_pdcode_valid_bits", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "lrcomp_en_indirect_update", "enable indirect update, when '1', it enables indirect update for respective group, when '0', it disables indirect update for that group."},
#else
{0, 5, 0x000000000000003F, "RW", "lrcomp_en_indirect_update", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo665[] = {{"DPIC_LRCOMP_CTL1", "", 0x00000050, 4, 0x00000000FFFFFFFF, 0x0000000000000FFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields666[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lcomprst_b", "active low reset for lcomp."},
#else
{0, 0, 0x0000000000000000, "RW", "lcomprst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo666[] = {{"DPIC_LRCOMP_RSTCTL", "", 0x00000054, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields667[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lrcomp_clkgate_en", "Clock gating control for rcomp."},
#else
{1, 1, 0x0000000000000000, "RW", "lrcomp_clkgate_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ltxdlycomp_clkgate_en", "Clock gating control for txdlycomp"},
#else
{0, 0, 0x0000000000000000, "RW", "ltxdlycomp_clkgate_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo667[] = {{"DPIC_TXDLYCOMP_CLKGATE", "", 0x00000058, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields668[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/1S/V", "ltxdlycomp_init_comp", "enable initial txdlycomp"},
#else
{0, 0, 0x0000000000000000, "RW/1S/V", "ltxdlycomp_init_comp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo668[] = {{"DPIC_TXDLYCOMP_INIT", "", 0x0000005C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields669[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "comp_dly_sample_delay", "Delay in compclks after sending timing reference pulse before sampling updn. Allows time for AFE circuit to resolve to appropriate updn result after asserting the reference pulse."},
#else
{24, 31, 0x0000000000000000, "RW", "comp_dly_sample_delay", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "comp_dly_setup_delay", "Delay in compclks before sending timing reference pulse. Allows time for new live code under test to propagate to AFE, before applying reference pulse."},
#else
{20, 23, 0x0000000000000000, "RW", "comp_dly_setup_delay", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 19, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{17, 19, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 16, 0x0000000000000000, "RW", "ltxdlycomp_live_override", "TX Delay c73p1ddrlp34l64x1top_comp live code override value"},
#else
{9, 16, 0x0000000000000000, "RW", "ltxdlycomp_live_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ltxdlycomp_live_override_en", "Enable for TX Delay ocmp live code override value."},
#else
{8, 8, 0x0000000000000000, "RW", "ltxdlycomp_live_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000007, "RW", "ltxdlycomp_coarse_max", "TX Delay c73p1ddrlp34l64x1top_comp MAX value of coarse code."},
#else
{4, 7, 0x0000000000000007, "RW", "ltxdlycomp_coarse_max", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000004, "RW", "ltxdlycomp_fine_max", "TX Delay c73p1ddrlp34l64x1top_comp MAX value of fine code."},
#else
{0, 3, 0x0000000000000004, "RW", "ltxdlycomp_fine_max", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo669[] = {{"DPIC_TXDLYCOMPOVR", "", 0x00000060, 7, 0x00000000FFFFFFFF, 0x0000000000000074}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields670[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{5, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 4, 0x0000000000000000, "RO/V", "lcomp_cmn_obonus", "read back value from AFE"},
#else
{1, 4, 0x0000000000000000, "RO/V", "lcomp_cmn_obonus", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "ltxdlycomp_limit_hit_error_set", "read back value of txdlycomp limit error set flag"},
#else
{0, 0, 0x0000000000000000, "RO/V", "ltxdlycomp_limit_hit_error_set", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo670[] = {{"DPIC_LCOMP_READBACK", "", 0x00000064, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields671[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{19, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 18, 0x0000000000000001, "RW", "lrcomp_bqt_settle_width", "the number of cycles after lcomp receives the bus_quiet_time_gnt signal, and before it takes any action. This allows the phy to finish off any running read/write cycles"},
#else
{12, 18, 0x0000000000000001, "RW", "lrcomp_bqt_settle_width", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000001, "RW", "lrcomp_setup_width", "For future designs, where there might be a need to generate a stage3 enable for AFE. It needs to be '1' otherwise."},
#else
{8, 11, 0x0000000000000001, "RW", "lrcomp_setup_width", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000001, "RW", "lrcomp_hold_width", "For future designs, where there might be a need to generate a stage3 enable for AFE. It needs to be '1' otherwise."},
#else
{4, 7, 0x0000000000000001, "RW", "lrcomp_hold_width", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000001, "RW", "lrcomp_enable_width", "For future designs, where there might be a need to generate a stage3 enable for AFE. It needs to be '1' otherwise."},
#else
{0, 3, 0x0000000000000001, "RW", "lrcomp_enable_width", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo671[] = {{"DPIC_LRCOMP_CTL2", "", 0x00000068, 5, 0x00000000FFFFFFFF, 0x0000000000001111}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields672[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "Reserved", "bit to start the initial rcomp"},
#else
{2, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "comp_periodiccntr_enable", "bit to start the initial rcomp"},
#else
{1, 1, 0x0000000000000000, "RW", "comp_periodiccntr_enable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "comp_periodic_enable", "bit to enable the periodic rcomp. It also enables the periodic txdlycomp"},
#else
{0, 0, 0x0000000000000000, "RW", "comp_periodic_enable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo672[] = {{"DPIC_GRCOMP_PERIODICCOMP", "", 0x0000006C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields673[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "clktx_rcompoverride", "CLKTX AFE Stg3 Rcomp override enable, used for non DDR3L modes"},
#else
{31, 31, 0x0000000000000000, "RW", "clktx_rcompoverride", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "clktx_scompoverride", "Config CLKTX AFE Stg3 txdly c73p1ddrlp34l64x1top_comp override enable, used for non DDR3L modes"},
#else
{30, 30, 0x0000000000000000, "RW", "clktx_scompoverride", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ltxdlycomp_update", "config update contorl for txdlyocmp code"},
#else
{29, 29, 0x0000000000000000, "RW", "ltxdlycomp_update", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{29, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "ltxdlycomp_updtbyen", "enable for config update contorl for txdlycomp code."},
#else
{28, 28, 0x0000000000000000, "RW", "ltxdlycomp_updtbyen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 28, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 27, 0x0000000000000006, "RW", "ltxdlycomp_grp0_tapsel", "select the delay tap node in AFE for group0"},
#else
{23, 27, 0x0000000000000006, "RW", "ltxdlycomp_grp0_tapsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "ltxdlycomp_grp0_update_disable", "bits to disable for group0 code update."},
#else
{22, 22, 0x0000000000000000, "RW", "ltxdlycomp_grp0_update_disable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{22, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "ltxdlycomp_grp0_override_en", "bits for override control of grp0 code"},
#else
{21, 21, 0x0000000000000000, "RW", "ltxdlycomp_grp0_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 21, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{13, 20, 0x0000000000000000, "RW", "ltxdlycomp_grp0_coarse_override", "config value for grp0 coarse code."},
#else
{13, 20, 0x0000000000000000, "RW", "ltxdlycomp_grp0_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{13, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{13, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 12, 0x0000000000000000, "RW", "ltxdlycomp_grp0_fine_override", "config value for grp0 fine code."},
#else
{5, 12, 0x0000000000000000, "RW", "ltxdlycomp_grp0_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 12, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 12, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ltxdlycomp_limit_hit_error", "TBD"},
#else
{4, 4, 0x0000000000000000, "RW", "ltxdlycomp_limit_hit_error", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "clktx_resetb", "CLKTX reset of OTF latches, active low"},
#else
{3, 3, 0x0000000000000000, "RW", "clktx_resetb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ltxdlycomp_continuous_en", "continuous enable mode for txdlycomp"},
#else
{2, 2, 0x0000000000000000, "RW", "ltxdlycomp_continuous_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ltxdlycomp_1group", "TBD"},
#else
{1, 1, 0x0000000000000000, "RW", "ltxdlycomp_1group", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ltxdlycomp_pmexit_enable", "TxDLY c73p1ddrlp34l64x1top_PM Exit Enable 0 - Do not re-eval TxDLY codes on PM3 Exit 1 - Re-eval txdly codes on PM3 Exit"},
#else
{0, 0, 0x0000000000000000, "RW", "ltxdlycomp_pmexit_enable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo673[] = {{"DPIC_TXDLYCOMP_0", "", 0x00000070, 14, 0x00000000FFFFFFFF, 0x0000000003000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields674[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp1_tapsel", "select the delay tap node in AFE for group1"},
#else
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp1_tapsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp1_update_disable", "bits to disable for group1 code update."},
#else
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp1_update_disable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp1_override_en", "bits for override control of grp1 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp1_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp1_coarse_override", "config value for grp1 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp1_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp1_fine_override", "config value for grp1 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp1_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo674[] = {{"DPIC_TXDLYCOMP_1", "", 0x00000074, 6, 0x00000000FFFFFFFF, 0x0000000000180000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields675[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp2_tapsel", "select the delay tap node in AFE for group2"},
#else
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp2_tapsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp2_update_disable", "bits to disable for group2 code update."},
#else
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp2_update_disable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp2_override_en", "bits for override control of grp2 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp2_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp2_coarse_override", "config value for grp2 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp2_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp2_fine_override", "config value for grp2 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp2_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo675[] = {{"DPIC_TXDLYCOMP_2", "", 0x00000078, 6, 0x00000000FFFFFFFF, 0x0000000000180000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields676[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp3_tapsel", "select the delay tap node in AFE for group3"},
#else
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp3_tapsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp3_update_disable", "bits to disable for group3 code update."},
#else
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp3_update_disable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp3_override_en", "bits for override control of grp3 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp3_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp3_coarse_override", "config value for grp3 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp3_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp3_fine_override", "config value for grp3 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp3_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo676[] = {{"DPIC_TXDLYCOMP_3", "", 0x0000007C, 6, 0x00000000FFFFFFFF, 0x0000000000180000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields677[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp4_tapsel", "select the delay tap node in AFE for group4"},
#else
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp4_tapsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp4_update_disable", "bits to disable for group4 code update."},
#else
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp4_update_disable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp4_override_en", "bits for override control of grp4 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp4_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp4_coarse_override", "config value for grp4 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp4_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp4_fine_override", "config value for grp4 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp4_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo677[] = {{"DPIC_TXDLYCOMP_4", "", 0x00000080, 6, 0x00000000FFFFFFFF, 0x0000000000180000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields678[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp0_override_en", "bits for override control of grp0 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp0_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp0_coarse_override", "config value for grp0 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp0_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp0_fine_override", "config value for grp0 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp0_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo678[] = {{"CH1_DPIC_TXDLYCOMP_0", "", 0x00000084, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields679[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp1_override_en", "bits for override control of grp1 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp1_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp1_coarse_override", "config value for grp1 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp1_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp1_fine_override", "config value for grp1 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp1_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo679[] = {{"CH1_DPIC_TXDLYCOMP_1", "", 0x00000088, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields680[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp2_override_en", "bits for override control of grp2 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp2_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp2_coarse_override", "config value for grp2 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp2_coarse_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp2_fine_override", "config value for grp2 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ch1_ltxdlycomp_grp2_fine_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo680[] = {{"CH1_DPIC_TXDLYCOMP_2", "", 0x0000008C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields681[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp0", "DQ coarse code value."},
#else
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp0", "DQ fine code value."},
#else
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp1", "DQS coarse code value."},
#else
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp1", "DQS fine code value."},
#else
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo681[] = {{"DPIC_LTXDLYCOMP_CODES_0", "", 0x00000090, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields682[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp2", "CA coarse code value."},
#else
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp2", "CA fine code value."},
#else
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp3", "CTL coarse code value."},
#else
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp3", "CTL fine code value."},
#else
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo682[] = {{"DPIC_LTXDLYCOMP_CODES_1", "", 0x00000094, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields683[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp4", "CK coarse code value."},
#else
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp4", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp4", "CK fine code value."},
#else
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp4", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_ch1_coarse_code_grp0", "CA coarse code value. (CH1)"},
#else
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_ch1_coarse_code_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_ch1_fine_code_grp0", "CA fine code value.  (CH1)"},
#else
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_ch1_fine_code_grp0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo683[] = {{"DPIC_LTXDLYCOMP_CODES_2", "", 0x00000098, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields684[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_ch1_coarse_code_grp1", "CTL coarse code value.  (CH1)"},
#else
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_ch1_coarse_code_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_ch1_fine_code_grp1", "CTL fine code value.  (CH1)"},
#else
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_ch1_fine_code_grp1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_ch1_coarse_code_grp2", "CK coarse code value.  (CH1)"},
#else
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_ch1_coarse_code_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_ch1_fine_code_grp2", "CK fine code value.  (CH1)"},
#else
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_ch1_fine_code_grp2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo684[] = {{"DPIC_LTXDLYCOMP_CODES_3", "", 0x0000009C, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields685[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ldomaindig_cmn_startldooffsetcomp", "LDO offset c73p1ddrlp34l64x1top_comp (LPDDR 3/4 Mode Indication)"},
#else
{16, 16, 0x0000000000000000, "RW", "ldomaindig_cmn_startldooffsetcomp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 15, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{10, 15, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "cgctrl_clkgaten", "Clock gate enable. When set to 1, enables the ISM to leave ACTIVE and gates the side_clk if in the IDLE state. When set to 0, the ISM never leaves ACTIVE once it gets to that state and the clock is never gated. Recommended value = 1."},
#else
{9, 9, 0x0000000000000000, "RW", "cgctrl_clkgaten", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "cgctrl_clkgatedef", "Clock gate defeature. When set to 1, disables side_clk gating within the endpoint when ISM is IDLE. Set to 0 for normal operation. Recommended value = 0"},
#else
{8, 8, 0x0000000000000000, "RW", "cgctrl_clkgatedef", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000010, "RW", "cgctrl_idlecnt", "Idle count limit for ISM which is determines when the block should transition to IDLE_REQ. Recommended value = 8'd16.[br]A value of zero breaks the design resulting in an unresponsive endpoint."},
#else
{0, 7, 0x0000000000000010, "RW", "cgctrl_idlecnt", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo685[] = {{"DPIC_CRI_CFG", "", 0x00000000, 6, 0x00000000FFFFFFFF, 0x0000000000000010}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields686[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{29, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "fbdivrst_b", "Feedback clock reset addition (used during power switch operation)"},
#else
{28, 28, 0x0000000000000000, "RW", "fbdivrst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 28, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{26, 27, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{26, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "pll_cmn_fbmuxsel", "mplldivs feedback multiplexer select (muxa). not part of adpll."},
#else
{24, 25, 0x0000000000000000, "RW", "pll_cmn_fbmuxsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 25, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 23, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{5, 23, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000002, "RW", "pll_cmn_refdivsel", "mplldivs reference divider ratio select (diva). not part of adpll."},
#else
{0, 4, 0x0000000000000002, "RW", "pll_cmn_refdivsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo686[] = {{"PLLDIVCTL", "", 0x00000004, 6, 0x00000000FFFFFFFF, 0x0000000000000002}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields687[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x0000000000000000, "RW", "pll_cmn_fbclktrim", "PLL feedback clock trim bits"},
#else
{20, 24, 0x0000000000000000, "RW", "pll_cmn_fbclktrim", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 19, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{17, 19, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "pll_cmn_2xclken", "2x clock tree drive output enable"},
#else
{16, 16, 0x0000000000000000, "RW", "pll_cmn_2xclken", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "Reserved1", "Reserved"},
#else
{14, 15, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000001, "RW", "pll_cmn_2xclkmuxsel", "mplldivs 2xclk multiplexer select (muxc). not part of adpll."},
#else
{12, 13, 0x0000000000000001, "RW", "pll_cmn_2xclkmuxsel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x0000000000000000, "RO", "Reserved2", "Reserved"},
#else
{9, 11, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "pll_cmn_mplldivsrstb", "mplldivs divider reset bar"},
#else
{8, 8, 0x0000000000000000, "RW", "pll_cmn_mplldivsrstb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x0000000000000000, "RO", "Reserved3", "Reserved"},
#else
{5, 7, 0x0000000000000000, "RO", "Reserved3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "pll_cmn_plltimerlock", "o_locktimer asserts after the coresponding ip pll lock time spec (in refclk cycles) starting from i_refclk_ack assertion and after all cold boot calibration sequence done. i_locktimercnt_th would determine the number of refclk cycles"},
#else
{4, 4, 0x0000000000000000, "RO/V", "pll_cmn_plltimerlock", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "pll_cmn_dcocal", "forces dco calibration when exiting deep sleep mode. required if changing feedback divider ratio or refclk frequency"},
#else
{3, 3, 0x0000000000000000, "RW", "pll_cmn_dcocal", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "pll_cmn_sfren", "forces sfr on even when pll is disabled (active standby mode)"},
#else
{2, 2, 0x0000000000000000, "RW", "pll_cmn_sfren", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "pll_cmn_plllock", "pll lock signal (hardware based)"},
#else
{1, 1, 0x0000000000000000, "RO/V", "pll_cmn_plllock", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pll_cmn_pllen", "pll enable signal"},
#else
{0, 0, 0x0000000000000000, "RW", "pll_cmn_pllen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo687[] = {{"PLLCTL", "", 0x00000008, 14, 0x00000000FFFFFFFF, 0x0000000000001000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields688[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000003, "RW", "cripg_clkgaten_stgdly", "Delay for staggered power gate enable. Determines the number of cycles interval between each power gate enable bit being asserted. Cripgctrl FSM is in PWRGATE state. Value of 0 not supported."},
#else
{8, 15, 0x0000000000000003, "RW", "cripg_clkgaten_stgdly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000001, "RW", "cripg_enable_stgdly", "Delay for staggered power gate enable. Determines the number of cycles interval between each power gate enable bit being asserted. Cripgctrl FSM is in PWRGATE state. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{4, 6, 0x0000000000000001, "RW", "cripg_enable_stgdly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "Reserved1", "Reserved"},
#else
{3, 3, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000001, "RW", "cripg_disable_stgdly", "Delay for staggered power gate disable. Determines the number of cycles interval between each power gate enable bit being de-asserted. Cripgctrl FSM is in PWRUNGATE state. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{0, 2, 0x0000000000000001, "RW", "cripg_disable_stgdly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo688[] = {{"CRIPG_DELAY1", "", 0x0000000C, 6, 0x00000000FFFFFFFF, 0x0000000000000311}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields689[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{26, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{26, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000002, "RW", "cripg_isol_en_dly", "No. of cycles after isolation cells are enabled/disabled before FSM moves on from ISOLEN/ISOLDIS. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{24, 25, 0x0000000000000002, "RW", "cripg_isol_en_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 25, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{23, 23, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x0000000000000002, "RW", "cripg_rst_asrt_dly", "No. of cycles after staggered reset assertion/de-assertion before FSM moves on from RSTASRT/RSTDSRT. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{20, 22, 0x0000000000000002, "RW", "cripg_rst_asrt_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "Reserved1", "Reserved"},
#else
{19, 19, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000003, "RW", "cripg_ism_lock_dly", "No. of cycles after agent ism idle lock/unlock before FSM moves on from ISMLOCK/ISMUNLOCK. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{16, 18, 0x0000000000000003, "RW", "cripg_ism_lock_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000003, "RW", "cripg_clkreq_dsrt_dly", "On wakeup, this indicates the no. of cycles that FSM stays in PWRUGCLKACK after receiving clkack. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{8, 15, 0x0000000000000003, "RW", "cripg_clkreq_dsrt_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000014, "RW", "cripg_ism_idle_dly", "When both fabric and agent ISMs are idle. This delay indicates the no. of cycle the FSMs need to be idle after receiving clkack before entering power gating flow. A value of zero breaks the design resulting in an unresponsive powergating control."},
#else
{0, 7, 0x0000000000000014, "RW", "cripg_ism_idle_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo689[] = {{"CRIPG_DELAY0", "", 0x00000010, 8, 0x00000000FFFFFFFF, 0x0000000002230314}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields690[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "cripg_clkgaten_ovr", "Config control for side clock req. This config value is used to override o_side_clkreq. When this config bit is set to '1', o_side_clkreq is set to '1' except when in CLKREQDSRT state of the CRIPG FSM"},
#else
{15, 15, 0x0000000000000000, "RW", "cripg_clkgaten_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{15, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "cripg_side_clkreq_ovr", "Config control for side clock req. This config value is used to override o_side_clkreq. When this config bit is set to '1', o_side_clkreq is set to '1' except when in CLKREQDSRT state of the CRIPG FSM"},
#else
{14, 14, 0x0000000000000000, "RW", "cripg_side_clkreq_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 14, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "cripg_isolen", "Config control for isolation enable. This config value is used for isol_en when config override in cripg_isolen_ovr is set to '1'. This value is ignored if cripg_isolen_ovr is set to '0'."},
#else
{13, 13, 0x0000000000000000, "RW", "cripg_isolen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{13, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "cripg_isolen_ovr", "Config override for isolation enable. This config value is used for isol_en when config override in cripg_isolen_ovr is set to '1'. This value is ignored if cripg_isolen_ovr is set to '0'."},
#else
{12, 12, 0x0000000000000000, "RW", "cripg_isolen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 12, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{8, 11, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "cripgen_staggered", "Config control for staggered power gate enable. This config value is used for the cripgen_staggered[3:0] when config override in cripgen_staggered_ovr is set to '1'. This value is ignored if cripgen_staggered_ovr is set to '0'."},
#else
{4, 7, 0x0000000000000000, "RW", "cripgen_staggered", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x0000000000000000, "RO", "Reserved1", "Reserved"},
#else
{1, 3, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cripgen_staggered_ovr", "Config override for staggered power gate enable. When set to '1' cripgen_staggered[3:0] is equal to the value set in cripgen_staggered register field. When set to '0', cripgen_staggered[3:0] is equal to the logic defined value."},
#else
{0, 0, 0x0000000000000000, "RW", "cripgen_staggered_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo690[] = {{"CRIPGCTL", "", 0x00000014, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields691[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cripgen", "CRI Power Gating Enable. When set to '1' - CRI Power gating logic is enabled. When set to '0' - CRI Power gating logic is disabled."},
#else
{0, 0, 0x0000000000000000, "RW", "cripgen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo691[] = {{"CRIPGEN_CTL", "", 0x00000018, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields692[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "func_mon_dq_anaobssel", "Analog Observation Control"},
#else
{28, 29, 0x0000000000000000, "RW", "func_mon_dq_anaobssel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "func_mon_dq_digobs1sel", "Digital Observation Control 1"},
#else
{24, 27, 0x0000000000000000, "RW", "func_mon_dq_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "func_mon_dq_digobs0sel", "Digital Observation Control 0"},
#else
{20, 23, 0x0000000000000000, "RW", "func_mon_dq_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "func_mon_cc1_anaobssel", "Analog Observation Control"},
#else
{18, 19, 0x0000000000000000, "RW", "func_mon_cc1_anaobssel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x0000000000000000, "RW", "func_mon_cc1_digobs1sel", "Digital Observation Control 1"},
#else
{14, 17, 0x0000000000000000, "RW", "func_mon_cc1_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x0000000000000000, "RW", "func_mon_cc1_digobs0sel", "Digital Observation Control 0"},
#else
{10, 13, 0x0000000000000000, "RW", "func_mon_cc1_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "func_mon_cc0_anaobssel", "Analog Observation Control"},
#else
{8, 9, 0x0000000000000000, "RW", "func_mon_cc0_anaobssel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "func_mon_cc0_digobs1sel", "Digital Observation Control 1"},
#else
{4, 7, 0x0000000000000000, "RW", "func_mon_cc0_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "func_mon_cc0_digobs0sel", "Digital Observation Control 0"},
#else
{0, 3, 0x0000000000000000, "RW", "func_mon_cc0_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo692[] = {{"OBSCTL0", "", 0x0000001C, 10, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields693[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO/V", "pll_cmn_errorflag", "PLL Error Flag"},
#else
{24, 24, 0x0000000000000000, "RO/V", "pll_cmn_errorflag", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{21, 23, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "pll_cmn_anaobsen", "PLL Analog Observation Enable"},
#else
{20, 20, 0x0000000000000000, "RW", "pll_cmn_anaobsen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 19, 0x0000000000000000, "RO", "Reserved1", "Reserved"},
#else
{17, 19, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "pll_cmn_digobsen", "PLL Digital Observation Enable"},
#else
{16, 16, 0x0000000000000000, "RW", "pll_cmn_digobsen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "Reserved2", "Reserved"},
#else
{14, 15, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "pll_cmn_anaobs1sel", "PLL Analog Observation Control 1"},
#else
{12, 13, 0x0000000000000000, "RW", "pll_cmn_anaobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO", "Reserved3", "Reserved"},
#else
{10, 11, 0x0000000000000000, "RO", "Reserved3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "pll_cmn_anaobs0sel", "PLL Analog Observation Control 0"},
#else
{8, 9, 0x0000000000000000, "RW", "pll_cmn_anaobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "pll_cmn_digobs1sel", "PLL Digital Observation Control 1"},
#else
{4, 7, 0x0000000000000000, "RW", "pll_cmn_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "pll_cmn_digobs0sel", "PLL Digital Observation Control 0"},
#else
{0, 3, 0x0000000000000000, "RW", "pll_cmn_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo693[] = {{"OBSCTL1", "", 0x00000020, 12, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields694[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{21, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000001, "RW", "clken_on_gsp", "Clock enable / disable on global sync point boundary."},
#else
{20, 20, 0x0000000000000001, "RW", "clken_on_gsp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "clken2clkack_dly", "Delay from clock enable to clock ack"},
#else
{16, 19, 0x0000000000000000, "RW", "clken2clkack_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "clkreqdasrt2clkoff_dly", "Delay from CLKREQDSRT to clock off"},
#else
{12, 15, 0x0000000000000000, "RW", "clkreqdasrt2clkoff_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "early_spidclkusync", "Early usync setting (with respect to global usync boundary)[br]2 : 2 clocks prior to global sync boundary[br]3 : 3 clocks prior to global sync boundary[br]and so on."},
#else
{8, 11, 0x0000000000000000, "RW", "early_spidclkusync", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{6, 7, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "usynccounter", "SPID Usync counter load value. This indicates the ratio between the mpllusync and spidclkusync"},
#else
{0, 5, 0x0000000000000000, "RW", "usynccounter", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo694[] = {{"SPIDCLKCTL0", "", 0x00000024, 7, 0x00000000FFFFFFFF, 0x0000000000100000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields695[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{10, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V", "ldomaindig_cmn_ldovccfarpwrgood", "When set, vccfar has converged to the target voltage and is ready to use."},
#else
{9, 9, 0x0000000000000000, "RO/V", "ldomaindig_cmn_ldovccfarpwrgood", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ldomaindig_cmn_iolbtest", "LDO IOLB Test Enable"},
#else
{8, 8, 0x0000000000000000, "RW", "ldomaindig_cmn_iolbtest", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RW", "ldomaindig_cmn_dvfsfreqselect", "LDO Self Refresh Exit"},
#else
{6, 6, 0x0000000000000001, "RW", "ldomaindig_cmn_dvfsfreqselect", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ldomaindig_cmn_selfrefreshexit", "LDO Self Refresh Exit"},
#else
{5, 5, 0x0000000000000000, "RW", "ldomaindig_cmn_selfrefreshexit", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ldoffdig_cc_ldoiobufact", "LDO IO Bufact - CC"},
#else
{4, 4, 0x0000000000000000, "RW", "ldoffdig_cc_ldoiobufact", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ldoffdig_bl_ldoiobufact", "LDO IO Bufact - BL"},
#else
{3, 3, 0x0000000000000000, "RW", "ldoffdig_bl_ldoiobufact", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ldoffdig_cc_ldoffclkenable", "LDO FF Clock Enable - CC"},
#else
{2, 2, 0x0000000000000001, "RW", "ldoffdig_cc_ldoffclkenable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "ldoffdig_bl_ldoffclkenable", "LDO FF Clock Enable - BL"},
#else
{1, 1, 0x0000000000000001, "RW", "ldoffdig_bl_ldoffclkenable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pll_cmn_ldoclken", "LDO Clock Enable"},
#else
{0, 0, 0x0000000000000000, "RW", "pll_cmn_ldoclken", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo695[] = {{"LDOCTL1", "", 0x00000028, 11, 0x00000000FFFFFFFF, 0x0000000000000046}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields696[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ldomaindig_cmn_ldoon", "LDO On"},
#else
{0, 0, 0x0000000000000000, "RW", "ldomaindig_cmn_ldoon", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo696[] = {{"LDOONCTL", "", 0x0000002C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields697[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ldomaindig_cmn_ldodigrstb", "LDO Reset"},
#else
{0, 0, 0x0000000000000000, "RW", "ldomaindig_cmn_ldodigrstb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo697[] = {{"LDORSTCTL", "", 0x00000030, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields698[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lvug_isolen", "vccaddrlvug -> vccsocvnn isolation control (1 - Isolation enabled, 0 - disabled)"},
#else
{0, 0, 0x0000000000000000, "RW", "lvug_isolen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo698[] = {{"LVUGSUPPLYCTL0", "", 0x00000034, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields699[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pll_cmn_divresetb", "PLL/DLL Feedback clock divider reset"},
#else
{0, 0, 0x0000000000000000, "RW", "pll_cmn_divresetb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo699[] = {{"PLLDIVCTL2", "", 0x00000038, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields700[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000001, "RW", "ldomaindig_cmn_clockratio", "LDO Clock Ratio"},
#else
{4, 7, 0x0000000000000001, "RW", "ldomaindig_cmn_clockratio", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{1, 3, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ldomain_cmn_clkvalid", "1x/2x Clock valid for LDOMAIN FUBs"},
#else
{0, 0, 0x0000000000000000, "RW", "ldomain_cmn_clkvalid", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo700[] = {{"LDOCLKVAL", "", 0x0000003C, 4, 0x00000000FFFFFFFF, 0x0000000000000010}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields701[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_pm_pmrst_b", "c73p1ddrlp34l64x1top_PM module reset from config register"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_pm_pmrst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo701[] = {{"DPIC_PM_CH0_RSTB", "", 0x00000100, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields702[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{3, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch0_pm_vccapwronstaggered_ovr", "PWR VCCA On Staggered Override"},
#else
{2, 2, 0x0000000000000000, "RW", "ch0_pm_vccapwronstaggered_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch0_pm_vnnapwronstaggered_ovr", "PWR VNNA On Staggered Override"},
#else
{1, 1, 0x0000000000000000, "RW", "ch0_pm_vnnapwronstaggered_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_pm_isolen_ovr", "Isolation Override"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_pm_isolen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo702[] = {{"DPIC_PM_CH0_PGOVR", "", 0x00000104, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields703[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "pm_txdlycomp_en_ovr", "c73p1ddrlp34l64x1top_PM TxDLY c73p1ddrlp34l64x1top_Comp Disable. When set to 1'b1(reset value), this results in c73p1ddrlp34l64x1top_PM preventing TxDLY code re-eval during PM3. Current recommendation is to disable this in PSMI mode only."},
#else
{31, 31, 0x0000000000000000, "RW", "pm_txdlycomp_en_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{31, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "pm_forceldooffsetcomp", "Force c73p1ddrlp34l64x1top_PM LDO c73p1ddrlp34l64x1top_Comp. When set to 1'b1, this results in c73p1ddrlp34l64x1top_PM forcing LDO Offset c73p1ddrlp34l64x1top_comp when exiting PM3. Current recommendation is to enable this in PSMI mode only."},
#else
{30, 30, 0x0000000000000000, "RW", "pm_forceldooffsetcomp", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 30, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ch0_pm_dllcomp_clkgate_ovr", "Channel 0 dll c73p1ddrlp34l64x1top_comp clock gate overiride"},
#else
{29, 29, 0x0000000000000000, "RW", "ch0_pm_dllcomp_clkgate_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{29, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "ch0_pm_ref2xph0_ovr", "ref2x phase 0 override"},
#else
{28, 28, 0x0000000000000000, "RW", "ch0_pm_ref2xph0_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 28, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "ch0_pm_ref2xrstb_ovr", "ref2xrstb override"},
#else
{27, 27, 0x0000000000000000, "RW", "ch0_pm_ref2xrstb_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "vcca_sel", "Select VCCA mode of operation"},
#else
{26, 26, 0x0000000000000000, "RW", "vcca_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{26, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "pswitch_cmn_vccapwron", "Power mux (ungated): Enable VCCA"},
#else
{25, 25, 0x0000000000000000, "RW", "pswitch_cmn_vccapwron", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 25, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000001, "RW", "pswitch_cmn_vnnpwron", "Power mux (ungated): Enable VNN"},
#else
{24, 24, 0x0000000000000001, "RW", "pswitch_cmn_vnnpwron", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "ch0_pm_vccapwronstaggered", "PWR VCCA On Staggered value"},
#else
{16, 23, 0x0000000000000000, "RW", "ch0_pm_vccapwronstaggered", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000FF, "RW", "ch0_pm_vnnapwronstaggered", "PWR VNNA On Staggered value"},
#else
{8, 15, 0x00000000000000FF, "RW", "ch0_pm_vnnapwronstaggered", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ch0_pm_clkgateen_ovr", "Clock Gate Override"},
#else
{6, 6, 0x0000000000000000, "RW", "ch0_pm_clkgateen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ch0_pm_isolen", "Isolation Enable Value"},
#else
{5, 5, 0x0000000000000000, "RW", "ch0_pm_isolen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ch0_pm_diffampenable_ovr", "DIFFAMP Enable Overide"},
#else
{4, 4, 0x0000000000000000, "RW", "ch0_pm_diffampenable_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch0_pm_iobufact_ovr", "IOBUFACT Override"},
#else
{3, 3, 0x0000000000000000, "RW", "ch0_pm_iobufact_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch0_pm_ckdll_sdllen_ovr", "SDLL Enable Override"},
#else
{2, 2, 0x0000000000000000, "RW", "ch0_pm_ckdll_sdllen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch0_pm_adpllen_ovr", "ADPLL Enable Override"},
#else
{1, 1, 0x0000000000000000, "RW", "ch0_pm_adpllen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_pm_adpll_sfron_ovr", "SFR On Override"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_pm_adpll_sfron_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo703[] = {{"DPIC_PM_CH0_CONFIG0", "", 0x00000108, 18, 0x00000000FFFFFFFF, 0x000000000100FF00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields704[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{22, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{22, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000001, "RW", "ch0_pm_spidclkreq_en", "c73p1ddrlp34l64x1top_PM Spid clkreq Enable"},
#else
{21, 21, 0x0000000000000001, "RW", "ch0_pm_spidclkreq_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 21, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "ch0_pm_spidclkreq_ovr", "c73p1ddrlp34l64x1top_PM Spid clkreq override"},
#else
{20, 20, 0x0000000000000000, "RW", "ch0_pm_spidclkreq_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "ch0_pm_spidrst_b_ovr", "c73p1ddrlp34l64x1top_PM Spid Reset Override"},
#else
{19, 19, 0x0000000000000000, "RW", "ch0_pm_spidrst_b_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW/1S/V", "ch0_pm_hvm_req", "HVM Request"},
#else
{18, 18, 0x0000000000000000, "RW/1S/V", "ch0_pm_hvm_req", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x0000000000000004, "RW", "ch0_pm_hvm_delay", "Delay between power off and power on in hvm mode"},
#else
{14, 17, 0x0000000000000004, "RW", "ch0_pm_hvm_delay", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "ch0_pm_ldopg_pwron_ovr", "LDO Power On Override"},
#else
{13, 13, 0x0000000000000000, "RW", "ch0_pm_ldopg_pwron_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{13, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "ch0_pm_spidclkenovrride", "SPID Clock Override"},
#else
{12, 12, 0x0000000000000000, "RW", "ch0_pm_spidclkenovrride", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 12, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "ch0_pm_adpllouten_ovr", "ADPLL-Out Output Enable Override"},
#else
{11, 11, 0x0000000000000000, "RW", "ch0_pm_adpllouten_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{11, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch0_pm_vrefiobufact_ovr", "VREF IO BUFACT Overide"},
#else
{10, 10, 0x0000000000000000, "RW", "ch0_pm_vrefiobufact_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 10, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch0_pm_vrefen_ovr", "VREFEN  Overide value"},
#else
{9, 9, 0x0000000000000000, "RW", "ch0_pm_vrefen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ch0_pm_dqrxfiforstb_ovr", "c73p1ddrlp34l64x1top_DQRX FIFO Reset Override"},
#else
{8, 8, 0x0000000000000000, "RW", "ch0_pm_dqrxfiforstb_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "ch0_pm_pien_ovr", "PI Enable Override"},
#else
{7, 7, 0x0000000000000000, "RW", "ch0_pm_pien_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ch0_pm_wrptren_ovr", "Write Pointer Enable Override"},
#else
{6, 6, 0x0000000000000000, "RW", "ch0_pm_wrptren_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ch0_pm_clkdll_floprstb_ovr", "Clock DLL Flop Reset Override"},
#else
{5, 5, 0x0000000000000000, "RW", "ch0_pm_clkdll_floprstb_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ch0_pm_clkdll_floprstb", "Clock DLL Flop Reset Value"},
#else
{4, 4, 0x0000000000000000, "RW", "ch0_pm_clkdll_floprstb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch0_pm_pg2xrst_b_ovr", "2x Reset Override"},
#else
{3, 3, 0x0000000000000000, "RW", "ch0_pm_pg2xrst_b_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch0_pm_pg2xrst_b", "2x Reset Value"},
#else
{2, 2, 0x0000000000000000, "RW", "ch0_pm_pg2xrst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "ch0_pm_adpll_lock", "c73p1ddrlp34l64x1top_PM adpll lock"},
#else
{1, 1, 0x0000000000000000, "RO/V", "ch0_pm_adpll_lock", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_pm_comp_en_ovr", "c73p1ddrlp34l64x1top_COMP Enable Overide"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_pm_comp_en_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo704[] = {{"DPIC_PM_CH0_CONFIG1", "", 0x0000010C, 20, 0x00000000FFFFFFFF, 0x0000000000210000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields705[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pm_ddrmode", "DDR Mode Selection 1: DDR3L (Single Channel) 0 : LP* (2 Channel)"},
#else
{0, 0, 0x0000000000000000, "RW", "pm_ddrmode", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo705[] = {{"DPIC_PM_CH0_CONFIG2", "", 0x00000110, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields706[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "ch0_pmclk_clkreq", "clk request"},
#else
{0, 0, 0x0000000000000001, "RW", "ch0_pmclk_clkreq", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo706[] = {{"DPIC_PM_CH0_CLKREQ", "", 0x00000114, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields707[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ch0_pm_stagger_bits_sel", "0 for 2 bit stagger ata time sel and 1 for 1 bit stagger at a time Channel 0"},
#else
{29, 29, 0x0000000000000000, "RW", "ch0_pm_stagger_bits_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{29, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "ch1_pm_stagger_bits_sel", "0 for 2 bit stagger ata time sel and 1 for 1 bit stagger at a time Channel 1"},
#else
{28, 28, 0x0000000000000000, "RW", "ch1_pm_stagger_bits_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 28, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "pm_acktime", "Wait timer for the message interface to provide delay before ack/nack is aaserted or deaaserted"},
#else
{24, 27, 0x0000000000000000, "RW", "pm_acktime", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000001, "RW", "pm_iobufact_dly", "Delay to assert/de-assert IO BUFFER ACTIVATE"},
#else
{16, 23, 0x0000000000000001, "RW", "pm_iobufact_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "pm_dllcompcg_enable_dly", "c73p1ddrlp34l64x1top_dllcomp clock enable  gate delay"},
#else
{12, 15, 0x0000000000000000, "RW", "pm_dllcompcg_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000000, "RW", "pm_ref2xph0_enable_dly", "ref2x phase 0 enable delay"},
#else
{8, 11, 0x0000000000000000, "RW", "pm_ref2xph0_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "pm_dllcompcg_disable_dly", "c73p1ddrlp34l64x1top_dllcomp clock disable  gate delay"},
#else
{4, 7, 0x0000000000000000, "RW", "pm_dllcompcg_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "pm_ref2xph0_disable_dly", "ref2x phase 0 disble delay"},
#else
{0, 3, 0x0000000000000000, "RW", "pm_ref2xph0_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo707[] = {{"DPIC_PM_DELAY0", "", 0x00000118, 9, 0x00000000FFFFFFFF, 0x0000000000010000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields708[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000002, "RW", "pm_wrptr_enable_dly", "Delay to turn on the PI's associated with the wrptr in each module"},
#else
{24, 31, 0x0000000000000002, "RW", "pm_wrptr_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000004, "RW", "pm_sdll_enable_dly", "Delay to turn on the PI's associated with the DLLs in each module"},
#else
{16, 23, 0x0000000000000004, "RW", "pm_sdll_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000190, "RW", "pm_comp_enable_dly", "Delay after which the pmseq state machine moves from en_comp state to en_sigref state"},
#else
{0, 15, 0x0000000000000190, "RW", "pm_comp_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo708[] = {{"DPIC_PM_DELAY1", "", 0x0000011C, 3, 0x00000000FFFFFFFF, 0x0000000002040190}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields709[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000000000C8, "RW", "pm_adpll_sfron_dly", "Delay after which the pmseq state machine moves from adpll_sfron state to adpll_on_hs state"},
#else
{16, 31, 0x00000000000000C8, "RW", "pm_adpll_sfron_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000002, "RW", "pm_wrptr_disable_dly", "Delay to turn off the PI's associated with the wrptr in each module"},
#else
{8, 15, 0x0000000000000002, "RW", "pm_wrptr_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000002, "RW", "pm_sdll_disable_dly", "Delay to turn off the PI's associated with the DLLs in each module"},
#else
{0, 7, 0x0000000000000002, "RW", "pm_sdll_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo709[] = {{"DPIC_PM_DELAY2", "", 0x00000120, 3, 0x00000000FFFFFFFF, 0x0000000000C80202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields710[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "pm_comp_disable_dly", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RW", "pm_comp_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "pm_adpll_sfroff_dly", "Delay after which the pmseq state machine moves from dis_comp state to adpll_off_hs state"},
#else
{0, 15, 0x0000000000000000, "RW", "pm_adpll_sfroff_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo710[] = {{"DPIC_PM_DELAY3", "", 0x00000124, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields711[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{28, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 27, 0x000000000000000A, "RW", "pm_pg_disable_stgdly", "Delay between each power un-gating stagger FSM state transition"},
#else
{20, 27, 0x000000000000000A, "RW", "pm_pg_disable_stgdly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 19, 0x000000000000000A, "RW", "pm_pg_enable_stgdly", "Delay between each power gating stagger FSM state transition"},
#else
{12, 19, 0x000000000000000A, "RW", "pm_pg_enable_stgdly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000002, "RW", "pm_isol2pgdly", "Delay for the isolate and un-isolate"},
#else
{8, 11, 0x0000000000000002, "RW", "pm_isol2pgdly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{4, 7, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000004, "RW", "pm_clkgate_wait_timer", "Delay for the clock gate or clock ungate"},
#else
{0, 3, 0x0000000000000004, "RW", "pm_clkgate_wait_timer", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo711[] = {{"DPIC_PM_DELAY4", "", 0x00000128, 6, 0x00000000FFFFFFFF, 0x0000000000A0A204}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields712[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000004, "RW", "pm_pg2xrstb_enable_dly", "Delay to deassert pg2xrstb"},
#else
{24, 31, 0x0000000000000004, "RW", "pm_pg2xrstb_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000004, "RW", "pm_pg2xrstb_disable_dly", "Delay to assert pg2xrst_b"},
#else
{16, 23, 0x0000000000000004, "RW", "pm_pg2xrstb_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000004, "RW", "pm_pgphyrstb_enable_dly", "Delay to deassert pgphyrst_b"},
#else
{8, 15, 0x0000000000000004, "RW", "pm_pgphyrstb_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000004, "RW", "pm_pgphyrstb_disable_dly", "Delay to assert pgphyrst_d"},
#else
{0, 7, 0x0000000000000004, "RW", "pm_pgphyrstb_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo712[] = {{"DPIC_PM_DELAY5", "", 0x0000012C, 4, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields713[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{24, 29, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 23, 0x0000000000000004, "RW", "pm_vrefiobufact_enable_dly", "Delay after vrefiobufact set to 1"},
#else
{12, 23, 0x0000000000000004, "RW", "pm_vrefiobufact_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 11, 0x0000000000000004, "RW", "pm_vrefiobufact_disable_dly", "Delay after vrefiobufact set to 0"},
#else
{0, 11, 0x0000000000000004, "RW", "pm_vrefiobufact_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo713[] = {{"DPIC_PM_DELAY6", "", 0x00000130, 4, 0x00000000FFFFFFFF, 0x0000000000004004}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields714[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{24, 29, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 23, 0x0000000000000004, "RW", "pm_vrefen_enable_dly", "Delay after vrefen set to 1"},
#else
{12, 23, 0x0000000000000004, "RW", "pm_vrefen_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 11, 0x0000000000000004, "RW", "pm_vrefen_disable_dly", "Delay after vrefen set to 0"},
#else
{0, 11, 0x0000000000000004, "RW", "pm_vrefen_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo714[] = {{"DPIC_PM_DELAY7", "", 0x00000134, 4, 0x00000000FFFFFFFF, 0x0000000000004004}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields715[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "reserved500", "Reserved"},
#else
{25, 31, 0x0000000000000000, "RO", "reserved500", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{22, 24, 0x0000000000000002, "RW", "pm_ref2xrstb_enable_dly", "enable ref2xrstb"},
#else
{22, 24, 0x0000000000000002, "RW", "pm_ref2xrstb_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{22, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{22, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 21, 0x0000000000000002, "RW", "pm_ref2xrstb_disable_dly", "disable ref2xrstb"},
#else
{19, 21, 0x0000000000000002, "RW", "pm_ref2xrstb_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 21, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 21, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{11, 18, 0x0000000000000000, "RW", "pm_disable_ldopg_dly", "Enable LDO Power gate delay"},
#else
{11, 18, 0x0000000000000000, "RW", "pm_disable_ldopg_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{11, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{11, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "pm_disable_isol_dly", "Enable LDO isol dleay"},
#else
{8, 10, 0x0000000000000000, "RW", "pm_disable_isol_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 10, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "pm_disable_ldovref_dly", "Enable LDO vref delay"},
#else
{4, 7, 0x0000000000000000, "RW", "pm_disable_ldovref_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "pm_pien_dly", "Enable PI delay"},
#else
{0, 3, 0x0000000000000000, "RW", "pm_pien_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo715[] = {{"DPIC_PM_DELAY8", "", 0x00000138, 7, 0x00000000FFFFFFFF, 0x0000000000900000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields716[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000FE, "RW", "pm_disable_adpll_lock_dly", "Disable ADPLL Lock Delay"},
#else
{24, 31, 0x00000000000000FE, "RW", "pm_disable_adpll_lock_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "pm_ldoselfrefreshexit", "LDO Self Refresh Exit Override"},
#else
{23, 23, 0x0000000000000000, "RW", "pm_ldoselfrefreshexit", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 22, 0x0000000000000000, "RW", "pm_enable_ldopg_dly", "Disable LDO Power gate delay"},
#else
{19, 22, 0x0000000000000000, "RW", "pm_enable_ldopg_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RW", "pm_enable_isol_dly", "Disable LDO isol dleay"},
#else
{16, 18, 0x0000000000000000, "RW", "pm_enable_isol_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "pm_enable_ldovref_dly", "Disable LDO vref delay"},
#else
{0, 15, 0x0000000000000000, "RW", "pm_enable_ldovref_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo716[] = {{"DPIC_PM_DELAY9", "", 0x0000013C, 5, 0x00000000FFFFFFFF, 0x00000000FE000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields717[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch0_pm_clkgateen", "Clock Gate Enable"},
#else
{0, 0, 0x0000000000000000, "RW", "ch0_pm_clkgateen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo717[] = {{"DPIC_PM_CH0_CLKGATE", "", 0x00000140, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields718[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000004, "RW", "ch0_hvm_pmmsg", "HVM c73p1ddrlp34l64x1top_PM Message"},
#else
{27, 31, 0x0000000000000004, "RW", "ch0_hvm_pmmsg", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 26, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 26, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x0000000000000000, "RO/V", "ch0_pm_cfg_status", "State of Power Management logic. [4]: busy. [3:0] : c73p1ddrlp34l64x1top_PM state"},
#else
{11, 15, 0x0000000000000000, "RO/V", "ch0_pm_cfg_status", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{11, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{8, 10, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 10, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "ch0_pmclk_ack", "c73p1ddrlp34l64x1top_PM clock ack"},
#else
{7, 7, 0x0000000000000000, "RO/V", "ch0_pmclk_ack", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "ch0_pm_sw_ack", "c73p1ddrlp34l64x1top_PM software acknowledge"},
#else
{6, 6, 0x0000000000000000, "RO/V", "ch0_pm_sw_ack", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW/1S/V", "ch0_pm_sw_req", "Config based Power Management Message Request"},
#else
{5, 5, 0x0000000000000000, "RW/1S/V", "ch0_pm_sw_req", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "ch0_pm_sw_msg", "Config based Power Management Message"},
#else
{0, 4, 0x0000000000000000, "RW", "ch0_pm_sw_msg", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo718[] = {{"DPIC_PMSWMSG_CH0", "", 0x00000144, 8, 0x00000000FFFFFFFF, 0x0000000020000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields719[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000004, "RW", "pm_divrst_enable_dly", "Delay to deassert divreset"},
#else
{8, 15, 0x0000000000000004, "RW", "pm_divrst_enable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000004, "RW", "pm_divrst_disable_dly", "Delay to assert divreset"},
#else
{0, 7, 0x0000000000000004, "RW", "pm_divrst_disable_dly", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo719[] = {{"DPIC_PM_DELAY10", "", 0x00000148, 3, 0x00000000FFFFFFFF, 0x0000000000000404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields720[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_pm_pmrst_b", "c73p1ddrlp34l64x1top_PM module reset from config register"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_pm_pmrst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo720[] = {{"DPIC_PM_CH1_RSTB", "", 0x0000014C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields721[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{3, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_pm_vccapwronstaggered_ovr", "PWR VCCA On Staggered Override"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_pm_vccapwronstaggered_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch1_pm_vnnapwronstaggered_ovr", "PWR VNNA On Staggered Override"},
#else
{1, 1, 0x0000000000000000, "RW", "ch1_pm_vnnapwronstaggered_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_pm_isolen_ovr", "Isolation Override"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_pm_isolen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo721[] = {{"DPIC_PM_CH1_PGOVR", "", 0x00000150, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields722[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ch1_pm_dllcomp_clkgate_ovr", "Channel 1 dll c73p1ddrlp34l64x1top_comp clock gate overiride"},
#else
{29, 29, 0x0000000000000000, "RW", "ch1_pm_dllcomp_clkgate_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{29, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "ch1_pm_ref2xph0_ovr", "ref2x phase 0 override"},
#else
{28, 28, 0x0000000000000000, "RW", "ch1_pm_ref2xph0_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{28, 28, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "ch1_pm_ref2xrstb_ovr", "ref2xrstb override"},
#else
{27, 27, 0x0000000000000000, "RW", "ch1_pm_ref2xrstb_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 27, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{26, 26, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{26, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RO", "Reserved1", "Reserved"},
#else
{25, 25, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 25, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO", "Reserved2", "Reserved"},
#else
{24, 24, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "ch1_pm_vccapwronstaggered", "PWR VCCA On Staggered value"},
#else
{16, 23, 0x0000000000000000, "RW", "ch1_pm_vccapwronstaggered", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000FF, "RW", "ch1_pm_vnnapwronstaggered", "PWR VNNA On Staggered value"},
#else
{8, 15, 0x00000000000000FF, "RW", "ch1_pm_vnnapwronstaggered", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved3", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved3", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ch1_pm_clkgateen_ovr", "Clock Gate Override"},
#else
{6, 6, 0x0000000000000000, "RW", "ch1_pm_clkgateen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ch1_pm_isolen", "Isolation Enable Value"},
#else
{5, 5, 0x0000000000000000, "RW", "ch1_pm_isolen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ch1_pm_diffampenable_ovr", "DIFFAMP Enable Overide"},
#else
{4, 4, 0x0000000000000000, "RW", "ch1_pm_diffampenable_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch1_pm_iobufact_ovr", "IOBUFACT Override"},
#else
{3, 3, 0x0000000000000000, "RW", "ch1_pm_iobufact_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_pm_ckdll_sdllen_ovr", "SDLL Enable Override"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_pm_ckdll_sdllen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ch1_pm_adpllen_ovr", "ADPLL Enable Override"},
#else
{1, 1, 0x0000000000000000, "RW", "ch1_pm_adpllen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_pm_adpll_sfron_ovr", "SFR On Override"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_pm_adpll_sfron_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo722[] = {{"DPIC_PM_CH1_CONFIG0", "", 0x00000154, 17, 0x00000000FFFFFFFF, 0x000000000000FF00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields723[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{22, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{22, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000001, "RW", "ch1_pm_spidclkreq_en", "c73p1ddrlp34l64x1top_PM Spid clkreq Enable"},
#else
{21, 21, 0x0000000000000001, "RW", "ch1_pm_spidclkreq_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 21, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW", "ch1_pm_spidclkreq_ovr", "c73p1ddrlp34l64x1top_PM Spid clkreq override"},
#else
{20, 20, 0x0000000000000000, "RW", "ch1_pm_spidclkreq_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "ch1_pm_spidrst_b_ovr", "c73p1ddrlp34l64x1top_PM Spid Reset Override"},
#else
{19, 19, 0x0000000000000000, "RW", "ch1_pm_spidrst_b_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW/1S/V", "ch1_pm_hvm_req", "HVM Request"},
#else
{18, 18, 0x0000000000000000, "RW/1S/V", "ch1_pm_hvm_req", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x0000000000000004, "RW", "ch1_pm_hvm_delay", "Delay between power off and power on in hvm mode"},
#else
{14, 17, 0x0000000000000004, "RW", "ch1_pm_hvm_delay", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "ch1_pm_ldopg_pwron_ovr", "LDO Power On Override"},
#else
{13, 13, 0x0000000000000000, "RW", "ch1_pm_ldopg_pwron_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{13, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "ch1_pm_spidclkenovrride", "SPID Clock Override"},
#else
{12, 12, 0x0000000000000000, "RW", "ch1_pm_spidclkenovrride", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{12, 12, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "ch1_pm_adpllouten_ovr", "ADPLL-Out Output Enable Override"},
#else
{11, 11, 0x0000000000000000, "RW", "ch1_pm_adpllouten_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{11, 11, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "ch1_pm_vrefiobufact_ovr", "VREF IO BUFACT Overide"},
#else
{10, 10, 0x0000000000000000, "RW", "ch1_pm_vrefiobufact_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 10, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "ch1_pm_vrefen_ovr", "VREFEN  Overide value"},
#else
{9, 9, 0x0000000000000000, "RW", "ch1_pm_vrefen_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ch1_pm_dqrxfiforstb_ovr", "c73p1ddrlp34l64x1top_DQRX FIFO Reset Override"},
#else
{8, 8, 0x0000000000000000, "RW", "ch1_pm_dqrxfiforstb_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "ch1_pm_pien_ovr", "PI Enable Override"},
#else
{7, 7, 0x0000000000000000, "RW", "ch1_pm_pien_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "ch1_pm_wrptren_ovr", "Write Pointer Enable Override"},
#else
{6, 6, 0x0000000000000000, "RW", "ch1_pm_wrptren_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "ch1_pm_clkdll_floprstb_ovr", "Clock DLL Flop Reset Override"},
#else
{5, 5, 0x0000000000000000, "RW", "ch1_pm_clkdll_floprstb_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ch1_pm_clkdll_floprstb", "Clock DLL Flop Reset Value"},
#else
{4, 4, 0x0000000000000000, "RW", "ch1_pm_clkdll_floprstb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ch1_pm_pg2xrst_b_ovr", "2x Reset Override"},
#else
{3, 3, 0x0000000000000000, "RW", "ch1_pm_pg2xrst_b_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ch1_pm_pg2xrst_b", "2x Reset Value"},
#else
{2, 2, 0x0000000000000000, "RW", "ch1_pm_pg2xrst_b", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "ch1_pm_adpll_lock", "c73p1ddrlp34l64x1top_PM adpll lock"},
#else
{1, 1, 0x0000000000000000, "RO/V", "ch1_pm_adpll_lock", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_pm_comp_en_ovr", "c73p1ddrlp34l64x1top_COMP Enable Overide"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_pm_comp_en_ovr", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo723[] = {{"DPIC_PM_CH1_CONFIG1", "", 0x00000158, 20, 0x00000000FFFFFFFF, 0x0000000000210000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields724[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "ch1_pmclk_clkreq", "clk request"},
#else
{0, 0, 0x0000000000000001, "RW", "ch1_pmclk_clkreq", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo724[] = {{"DPIC_PM_CH1_CLKREQ", "", 0x0000015C, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields725[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ch1_pm_clkgateen", "Clock Gate Enable"},
#else
{0, 0, 0x0000000000000000, "RW", "ch1_pm_clkgateen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo725[] = {{"DPIC_PM_CH1_CLKGATE", "", 0x00000160, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields726[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000004, "RW", "ch1_hvm_pmmsg", "HVM c73p1ddrlp34l64x1top_PM Message"},
#else
{27, 31, 0x0000000000000004, "RW", "ch1_hvm_pmmsg", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 26, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{16, 26, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x0000000000000000, "RO/V", "ch1_pm_cfg_status", "State of Power Management logic. [4]: busy. [3:0] : c73p1ddrlp34l64x1top_PM state"},
#else
{11, 15, 0x0000000000000000, "RO/V", "ch1_pm_cfg_status", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{11, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{8, 10, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 10, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "ch1_pmclk_ack", "c73p1ddrlp34l64x1top_PM clock ack"},
#else
{7, 7, 0x0000000000000000, "RO/V", "ch1_pmclk_ack", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "ch1_pm_sw_ack", "c73p1ddrlp34l64x1top_PM software acknowledge"},
#else
{6, 6, 0x0000000000000000, "RO/V", "ch1_pm_sw_ack", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{6, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW/1S/V", "ch1_pm_sw_req", "Config based Power Management Message Request"},
#else
{5, 5, 0x0000000000000000, "RW/1S/V", "ch1_pm_sw_req", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 5, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "ch1_pm_sw_msg", "Config based Power Management Message"},
#else
{0, 4, 0x0000000000000000, "RW", "ch1_pm_sw_msg", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo726[] = {{"DPIC_PMSWMSG_CH1", "", 0x00000164, 8, 0x00000000FFFFFFFF, 0x0000000020000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields727[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override", "override for pull up live rcomp code going to AFE"},
#else
{24, 29, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override_en", "override enable for override for pull up live rcomp code going to AFE"},
#else
{23, 23, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "gcomp_cmn_digobs0_sel", "debug observation signal to AFE"},
#else
{21, 22, 0x0000000000000000, "RW", "gcomp_cmn_digobs0_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW", "gcomp_cmn_digobs1_sel", "debug observation signal to AFE"},
#else
{19, 20, 0x0000000000000000, "RW", "gcomp_cmn_digobs1_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "gcomp_cmn_obsen", "debug observation signal to AFE"},
#else
{18, 18, 0x0000000000000000, "RW", "gcomp_cmn_obsen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 17, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{10, 17, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 9, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{0, 9, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo727[] = {{"DPIC_GRCOMP_OVR", "", 0x00000300, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields728[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 26, 0x0000000000000000, "RW", "rcomp_general_timer", "Not used."},
#else
{21, 26, 0x0000000000000000, "RW", "rcomp_general_timer", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 20, 0x0000000000007D00, "RW", "rcomp_wakeup_period", "this tells a timer to start the periodic c73p1ddrlp34l64x1top_comp cycle when this number of cycles are completed. Usually this is programmed to 'h7d00 for a 4us delay between two periodic c73p1ddrlp34l64x1top_comp cycles."},
#else
{1, 20, 0x0000000000007D00, "RW", "rcomp_wakeup_period", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rcomp_pu_staticlive", "static leg signal for the AFE"},
#else
{0, 0, 0x0000000000000000, "RW", "rcomp_pu_staticlive", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo728[] = {{"DPIC_GRCOMP_CTL", "", 0x00000304, 4, 0x00000000FFFFFFFF, 0x000000000000FA00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields729[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{25, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 24, 0x0000000000000000, "RW", "lrcomp_spare", "spare bits"},
#else
{9, 24, 0x0000000000000000, "RW", "lrcomp_spare", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "lrcomp_cmn_digobs0sel", "debug ctrl bits."},
#else
{7, 8, 0x0000000000000000, "RW", "lrcomp_cmn_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RW", "lrcomp_cmn_digobs1sel", "debug ctrl bits."},
#else
{5, 6, 0x0000000000000000, "RW", "lrcomp_cmn_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "lrcomp_cmn_obsen", "debug ctrl bits."},
#else
{4, 4, 0x0000000000000000, "RW", "lrcomp_cmn_obsen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "lrcomp_cmn_ibonus", "debug signal to AFE"},
#else
{0, 3, 0x0000000000000000, "RW", "lrcomp_cmn_ibonus", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo729[] = {{"DPIC_LRCOMP_DEBUG", "", 0x00000500, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields730[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved501", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved501", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_msb", "VISA Pattern Generation"},
#else
{4, 6, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_msb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_lsb", "VISA Pattern Generation"},
#else
{0, 3, 0x0000000000000000, "RW", "dfxvisa_ulm0pattgen_lsb", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo730[] = {{"DFXVISA_ULM0PATTGEN", "", 0x00000700, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields731[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved502", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved502", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_bypass", "VISA Bypass ULM0LN0"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_bypass", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_clksel", "VISA ULM0LN0 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_clksel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_datasel", "VISA ULM0LN0 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln0_datasel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo731[] = {{"DFXVISA_ULM0LN0", "", 0x00000704, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields732[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved503", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved503", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{17, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_bypass", "VISA Bypass ULM0LN1"},
#else
{16, 16, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_bypass", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 16, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_clksel", "VISA ULM0LN1 CLK Select"},
#else
{8, 15, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_clksel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_datasel", "VISA ULM0LN1 (DATA) Select"},
#else
{0, 7, 0x0000000000000000, "RW", "dfxvisa_ulm0ln1_datasel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo732[] = {{"DFXVISA_ULM0LN1", "", 0x00000708, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields733[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "pll_cmn_ldoclken", "LDO Clock Enable"},
#else
{0, 31, 0x0000000000000000, "RW", "pll_cmn_ldoclken", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo733[] = {{"LDOCTL1x", "", 0x00000028, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields734[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo734[] = {{"LDORSTCTLx", "", 0x00000030, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields735[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo735[] = {{"LDOCLKVALx", "", 0x0000003C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields736[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "Reserved0", "Reserved"},
#else
{0, 0, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo736[] = {{"DPIC_CRI_CFG", "", 0x00000000, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields737[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo737[] = {{"PLLDIVCTL", "", 0x00000004, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields738[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo738[] = {{"PLLCTL", "", 0x00000008, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields739[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo739[] = {{"CRIPG_DELAY1", "", 0x0000000C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields740[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo740[] = {{"CRIPG_DELAY0", "", 0x00000010, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields741[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo741[] = {{"CRIPGCTL", "", 0x00000014, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields742[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo742[] = {{"CRIPGEN_CTL", "", 0x00000018, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields743[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{20, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{20, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "func_mon_bl0_anaobssel", "Analog Observation Control"},
#else
{18, 19, 0x0000000000000000, "RW", "func_mon_bl0_anaobssel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 19, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x0000000000000000, "RW", "func_mon_bl0_digobs1sel", "Digital Observation Control 1"},
#else
{14, 17, 0x0000000000000000, "RW", "func_mon_bl0_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{14, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{14, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x0000000000000000, "RW", "func_mon_bl0_digobs0sel", "Digital Observation Control 0"},
#else
{10, 13, 0x0000000000000000, "RW", "func_mon_bl0_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 13, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 13, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "func_mon_bl1_anaobssel", "Analog Observation Control"},
#else
{8, 9, 0x0000000000000000, "RW", "func_mon_bl1_anaobssel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{8, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "func_mon_bl1_digobs1sel", "Digital Observation Control 1"},
#else
{4, 7, 0x0000000000000000, "RW", "func_mon_bl1_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 7, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "func_mon_bl1_digobs0sel", "Digital Observation Control 0"},
#else
{0, 3, 0x0000000000000000, "RW", "func_mon_bl1_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo743[] = {{"OBSCTL0", "", 0x0000001C, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields744[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo744[] = {{"OBSCTL1", "", 0x00000020, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields745[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo745[] = {{"SPIDCLKCTL0", "", 0x00000024, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields746[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "Reseved"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{16, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 15, 0x0000000000000000, "RO", "Reserved0", "Reseved"},
#else
{5, 15, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 15, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 15, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ldoffdig_cc_ldoiobufact", "LDO IO Bufact - CC"},
#else
{4, 4, 0x0000000000000000, "RW", "ldoffdig_cc_ldoiobufact", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "ldoffdig_bl_ldoiobufact", "LDO IO Bufact - BL"},
#else
{3, 3, 0x0000000000000000, "RW", "ldoffdig_bl_ldoiobufact", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{3, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ldoffdig_cc_ldoffclkenable", "LDO FF Clock Enable - CC"},
#else
{2, 2, 0x0000000000000001, "RW", "ldoffdig_cc_ldoffclkenable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{2, 2, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "ldoffdig_bl_ldoffclkenable", "LDO FF Clock Enable - BL"},
#else
{1, 1, 0x0000000000000001, "RW", "ldoffdig_bl_ldoffclkenable", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 1, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pll_cmn_ldoclken", "LDO Clock Enable"},
#else
{0, 0, 0x0000000000000000, "RW", "pll_cmn_ldoclken", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo746[] = {{"LDOCTL1", "", 0x00000028, 7, 0x00000000FFFFFFFF, 0x0000000000000006}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields747[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo747[] = {{"LDOONCTL", "", 0x0000002C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields748[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo748[] = {{"LDORSTCTL", "", 0x00000030, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields749[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reseved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lvug_isolen", "vccaddrug_lv to vccsocvnn_lv isolation control (1- isolation enabled; 0 - disabled)"},
#else
{0, 0, 0x0000000000000000, "RW", "lvug_isolen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo749[] = {{"LVUGSUPPLYCTL0", "", 0x00000034, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields750[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override", "override for pull up live rcomp code going to AFE"},
#else
{24, 29, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{24, 29, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override_en", "override enable for override for pull up live rcomp code going to AFE"},
#else
{23, 23, 0x0000000000000000, "RW", "comp_rcomp_pu_live_override_en", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{23, 23, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000000, "RW", "gcomp_cmn_digobs0_sel", "debug observation signal to AFE"},
#else
{21, 22, 0x0000000000000000, "RW", "gcomp_cmn_digobs0_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 22, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x0000000000000000, "RW", "gcomp_cmn_digobs1_sel", "debug observation signal to AFE"},
#else
{19, 20, 0x0000000000000000, "RW", "gcomp_cmn_digobs1_sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{19, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{19, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "gcomp_cmn_obsen", "debug observation signal to AFE"},
#else
{18, 18, 0x0000000000000000, "RW", "gcomp_cmn_obsen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{18, 18, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{10, 17, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{10, 17, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{10, 17, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{10, 17, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 9, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{0, 9, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 9, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 9, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo750[] = {{"DPIC_GRCOMP_OVR", "", 0x00000100, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields751[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{27, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{21, 26, 0x0000000000000000, "RW", "rcomp_general_timer", "Not used."},
#else
{21, 26, 0x0000000000000000, "RW", "rcomp_general_timer", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{21, 26, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{21, 26, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 20, 0x0000000000007D00, "RW", "rcomp_wakeup_period", "this tells a timer to start the periodic c73p1ddrlp34l64x1top_comp cycle when this number of cycles are completed. Usually this is programmed to 'h7d00 for a 4us delay between two periodic c73p1ddrlp34l64x1top_comp cycles."},
#else
{1, 20, 0x0000000000007D00, "RW", "rcomp_wakeup_period", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 20, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 20, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rcomp_pu_staticlive", "static leg signal for the AFE"},
#else
{0, 0, 0x0000000000000000, "RW", "rcomp_pu_staticlive", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo751[] = {{"DPIC_GRCOMP_CTL", "", 0x00000104, 4, 0x00000000FFFFFFFF, 0x000000000000FA00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields752[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{25, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{25, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{9, 24, 0x0000000000000000, "RW", "lrcomp_spare", "spare bits"},
#else
{9, 24, 0x0000000000000000, "RW", "lrcomp_spare", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{9, 24, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{9, 24, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x0000000000000000, "RW", "lrcomp_cmn_digobs0sel", "debug ctrl bits."},
#else
{7, 8, 0x0000000000000000, "RW", "lrcomp_cmn_digobs0sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{7, 8, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{7, 8, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RW", "lrcomp_cmn_digobs1sel", "debug ctrl bits."},
#else
{5, 6, 0x0000000000000000, "RW", "lrcomp_cmn_digobs1sel", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{5, 6, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "lrcomp_cmn_obsen", "debug ctrl bits."},
#else
{4, 4, 0x0000000000000000, "RW", "lrcomp_cmn_obsen", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{4, 4, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "lrcomp_cmn_ibonus", "debug signal to AFE"},
#else
{0, 3, 0x0000000000000000, "RW", "lrcomp_cmn_ibonus", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 3, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo752[] = {{"DPIC_LRCOMP_DEBUG", "", 0x00000300, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields753[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{1, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "Reserved0", "VISA Lower Level Bypass ULM0"},
#else
{0, 0, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 0, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo753[] = {{"LOWER_DFXVISAULM0", "", 0x00000500, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields754[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo754[] = {{"LOWER_DFXVISAULM1", "", 0x00000504, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields755[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo755[] = {{"LOWER_DFXVISAPATTGEN", "", 0x00000508, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields756[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo756[] = {{"TOP_DFXVISAULM0", "", 0x0000050C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields757[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo757[] = {{"TOP_DFXVISAULM1", "", 0x00000510, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields758[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo758[] = {{"TOP_DFXVISAPATTGEN", "", 0x00000514, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields759[] = {
#ifdef MEM_SV_HOOKS
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000001, "RW", "Rsvd", "LDO FF Clock Enable - CC"},
#else
{0, 31, 0x0000000000000001, "RW", "Rsvd", NULL},
#endif
#else
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000, "RO", "Reserved", "Reserved"},
#else
{0, 31, 0x00000000, "RO", "Reserved",  NULL},
#endif
#endif // MEM_SV_HOOKS
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo759[] = {{"LDOCTL1x", "", 0x00000028, 1, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields760[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "ptrdtype2rdvld", "LP4 Periodic Training Control 1"},
#else
{24, 29, 0x0000000000000000, "RW", "ptrdtype2rdvld", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 23, 0x0000000000000000, "RW", "rk1initialindex", "LP4 Periodic Training Control 1"},
#else
{17, 23, 0x0000000000000000, "RW", "rk1initialindex", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 16, 0x0000000000000000, "RW", "rk0initialindex", "LP4 Periodic Training Control 1"},
#else
{10, 16, 0x0000000000000000, "RW", "rk0initialindex", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 9, 0x0000000000000000, "RW", "ptloadcode_dly", "LP4 Periodic Training Control 1"},
#else
{6, 9, 0x0000000000000000, "RW", "ptloadcode_dly", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "ptrdtype2rdvld_plus1sel", "LP4 Periodic Training Control 1"},
#else
{3, 5, 0x0000000000000000, "RW", "ptrdtype2rdvld_plus1sel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "numpi_perindex", "LP4 Periodic Training Control 1"},
#else
{2, 2, 0x0000000000000000, "RW", "numpi_perindex", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "bytelane1datasel", "LP4 Periodic Training Control 1"},
#else
{1, 1, 0x0000000000000000, "RW", "bytelane1datasel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pten", "LP4 Periodic Training Control 1"},
#else
{0, 0, 0x0000000000000000, "RW", "pten", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo760[] = {{"PTCTL0", "", 0x00000000, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields761[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "Reserved", "LP4 Periodic Training Control 1"},
#else
{16, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 15, 0x0000000000000000, "RO/V", "rk1currentindex", "LP4 Periodic Training Control 1"},
#else
{9, 15, 0x0000000000000000, "RO/V", "rk1currentindex", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO", "Reserved0", "LP4 Periodic Training Control 1"},
#else
{8, 8, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 7, 0x0000000000000000, "RO/V", "rk0currentindex", "LP4 Periodic Training Control 1"},
#else
{1, 7, 0x0000000000000000, "RO/V", "rk0currentindex", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "Reserved1", "LP4 Periodic Training Control 1"},
#else
{0, 0, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo761[] = {{"PTCTL1", "", 0x00000004, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields762[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount1", "LP4 PT Ring Oscillator Count Pair 12"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount2", "LP4 PT Ring Oscillator Count Pair 12"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount2", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo762[] = {{"PTROCNT12", "", 0x00000008, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields763[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount3", "LP4 PT Ring Oscillator Count Pair 34"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount4", "LP4 PT Ring Oscillator Count Pair 34"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo763[] = {{"PTROCNT34", "", 0x0000000C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields764[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount5", "LP4 PT Ring Oscillator Count Pair 56"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount6", "LP4 PT Ring Oscillator Count Pair 56"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount6", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo764[] = {{"PTROCNT56", "", 0x00000010, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields765[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount7", "LP4 PT Ring Oscillator Count Pair 78"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount8", "LP4 PT Ring Oscillator Count Pair 78"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount8", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo765[] = {{"PTROCNT78", "", 0x00000014, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields766[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount9", "LP4 PT Ring Oscillator Count Pair 910"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount10", "LP4 PT Ring Oscillator Count Pair 910"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount10", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo766[] = {{"PTROCNT910", "", 0x00000018, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields767[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount11", "LP4 PT Ring Oscillator Count Pair 1112"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount12", "LP4 PT Ring Oscillator Count Pair 1112"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount12", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo767[] = {{"PTROCNT1112", "", 0x0000001C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields768[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount13", "LP4 PT Ring Oscillator Count Pair 1314"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount14", "LP4 PT Ring Oscillator Count Pair 1314"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount14", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo768[] = {{"PTROCNT1314", "", 0x00000020, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields769[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount15", "LP4 PT Ring Oscillator Count Pair 1516"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount16", "LP4 PT Ring Oscillator Count Pair 1516"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount16", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo769[] = {{"PTROCNT1516", "", 0x00000024, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields770[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount17", "LP4 PT Ring Oscillator Count Pair 1718"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount18", "LP4 PT Ring Oscillator Count Pair 1718"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount18", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo770[] = {{"PTROCNT1718", "", 0x00000028, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields771[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount19", "LP4 PT Ring Oscillator Count Pair 1920"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount20", "LP4 PT Ring Oscillator Count Pair 1920"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount20", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo771[] = {{"PTROCNT1920", "", 0x0000002C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields772[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount21", "LP4 PT Ring Oscillator Count Pair 2122"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount22", "LP4 PT Ring Oscillator Count Pair 2122"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount22", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo772[] = {{"PTROCNT2122", "", 0x00000030, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields773[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount23", "LP4 PT Ring Oscillator Count Pair 2324"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount24", "LP4 PT Ring Oscillator Count Pair 2324"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount24", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo773[] = {{"PTROCNT2324", "", 0x00000034, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields774[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount25", "LP4 PT Ring Oscillator Count Pair 2526"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount26", "LP4 PT Ring Oscillator Count Pair 2526"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount26", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo774[] = {{"PTROCNT2526", "", 0x00000038, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields775[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount27", "LP4 PT Ring Oscillator Count Pair 2728"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount28", "LP4 PT Ring Oscillator Count Pair 2728"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount28", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo775[] = {{"PTROCNT2728", "", 0x0000003C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields776[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount29", "LP4 PT Ring Oscillator Count Pair 2930"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount30", "LP4 PT Ring Oscillator Count Pair 2930"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount30", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo776[] = {{"PTROCNT2930", "", 0x00000040, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields777[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount31", "LP4 PT Ring Oscillator Count Pair 3132"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount32", "LP4 PT Ring Oscillator Count Pair 3132"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount32", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo777[] = {{"PTROCNT3132", "", 0x00000044, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields778[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount33", "LP4 PT Ring Oscillator Count Pair 3334"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount34", "LP4 PT Ring Oscillator Count Pair 3334"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount34", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo778[] = {{"PTROCNT3334", "", 0x00000048, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields779[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount35", "LP4 PT Ring Oscillator Count Pair 3536"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount36", "LP4 PT Ring Oscillator Count Pair 3536"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount36", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo779[] = {{"PTROCNT3536", "", 0x0000004C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields780[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount37", "LP4 PT Ring Oscillator Count Pair 3738"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount38", "LP4 PT Ring Oscillator Count Pair 3738"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount38", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo780[] = {{"PTROCNT3738", "", 0x00000050, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields781[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount39", "LP4 PT Ring Oscillator Count Pair 3940"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount40", "LP4 PT Ring Oscillator Count Pair 3940"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount40", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo781[] = {{"PTROCNT3940", "", 0x00000054, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields782[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount41", "LP4 PT Ring Oscillator Count Pair 4142"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount42", "LP4 PT Ring Oscillator Count Pair 4142"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount42", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo782[] = {{"PTROCNT4142", "", 0x00000058, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields783[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount43", "LP4 PT Ring Oscillator Count Pair 4344"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount44", "LP4 PT Ring Oscillator Count Pair 4344"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount44", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo783[] = {{"PTROCNT4344", "", 0x0000005C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields784[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount45", "LP4 PT Ring Oscillator Count Pair 4546"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount46", "LP4 PT Ring Oscillator Count Pair 4546"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount46", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo784[] = {{"PTROCNT4546", "", 0x00000060, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields785[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount47", "LP4 PT Ring Oscillator Count Pair 4748"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount48", "LP4 PT Ring Oscillator Count Pair 4748"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount48", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo785[] = {{"PTROCNT4748", "", 0x00000064, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields786[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount49", "LP4 PT Ring Oscillator Count Pair 4950"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount50", "LP4 PT Ring Oscillator Count Pair 4950"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount50", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo786[] = {{"PTROCNT4950", "", 0x00000068, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields787[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount51", "LP4 PT Ring Oscillator Count Pair 5152"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount52", "LP4 PT Ring Oscillator Count Pair 5152"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount52", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo787[] = {{"PTROCNT5152", "", 0x0000006C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields788[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount53", "LP4 PT Ring Oscillator Count Pair 5354"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount54", "LP4 PT Ring Oscillator Count Pair 5354"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount54", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo788[] = {{"PTROCNT5354", "", 0x00000070, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields789[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount55", "LP4 PT Ring Oscillator Count Pair 5556"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount56", "LP4 PT Ring Oscillator Count Pair 5556"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount56", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo789[] = {{"PTROCNT5556", "", 0x00000074, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields790[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount57", "LP4 PT Ring Oscillator Count Pair 5758"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount58", "LP4 PT Ring Oscillator Count Pair 5758"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount58", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo790[] = {{"PTROCNT5758", "", 0x00000078, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields791[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount59", "LP4 PT Ring Oscillator Count Pair 5960"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount60", "LP4 PT Ring Oscillator Count Pair 5960"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount60", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo791[] = {{"PTROCNT5960", "", 0x0000007C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields792[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount61", "LP4 PT Ring Oscillator Count Pair 6162"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount62", "LP4 PT Ring Oscillator Count Pair 6162"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount62", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo792[] = {{"PTROCNT6162", "", 0x00000080, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields793[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount63", "LP4 PT Ring Oscillator Count Pair 6364"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount64", "LP4 PT Ring Oscillator Count Pair 6364"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount64", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo793[] = {{"PTROCNT6364", "", 0x00000084, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields794[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount65", "LP4 PT Ring Oscillator Count Pair 6566"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount65", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount66", "LP4 PT Ring Oscillator Count Pair 6566"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount66", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo794[] = {{"PTROCNT6566", "", 0x00000088, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields795[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount67", "LP4 PT Ring Oscillator Count Pair 6768"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount67", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount68", "LP4 PT Ring Oscillator Count Pair 6768"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount68", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo795[] = {{"PTROCNT6768", "", 0x0000008C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields796[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rocount69", "LP4 PT Ring Oscillator Count Pair 6970"},
#else
{16, 31, 0x0000000000000000, "RW", "rocount69", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "rocount70", "LP4 PT Ring Oscillator Count Pair 6970"},
#else
{0, 15, 0x0000000000000000, "RW", "rocount70", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo796[] = {{"PTROCNT6970", "", 0x00000090, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields797[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "maxpi_per2xclk", "LP4 PT Dead Band Region MAXPI"},
#else
{24, 31, 0x0000000000000000, "RW", "maxpi_per2xclk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "dbregion1_marker", "LP4 PT Dead Band Region Region 1 Marker"},
#else
{16, 23, 0x0000000000000000, "RW", "dbregion1_marker", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dbregion2_marker", "LP4 PT Dead Band Region Region 2 Marker"},
#else
{8, 15, 0x0000000000000000, "RW", "dbregion2_marker", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dbregion3_marker", "LP4 PT Dead Band Region Region 3 Marker"},
#else
{0, 7, 0x0000000000000000, "RW", "dbregion3_marker", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo797[] = {{"DBREGIONCTL1", "", 0x00000094, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields798[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "dbregion4_marker", "LP4 PT Dead Band Region Region 4 Marker"},
#else
{24, 31, 0x0000000000000000, "RW", "dbregion4_marker", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "dbregion5_marker", "LP4 PT Dead Band Region Region 5 Marker"},
#else
{16, 23, 0x0000000000000000, "RW", "dbregion5_marker", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dbregion6_marker", "LP4 PT Dead Band Region Region 6 Marker"},
#else
{8, 15, 0x0000000000000000, "RW", "dbregion6_marker", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dbregion7_marker", "LP4 PT Dead Band Region Region 7 Marker"},
#else
{0, 7, 0x0000000000000000, "RW", "dbregion7_marker", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo798[] = {{"DBREGIONCTL2", "", 0x00000098, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields799[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "rk0dbregion0_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{30, 31, 0x0000000000000000, "RW", "rk0dbregion0_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 29, 0x0000000000000000, "RW", "rk0dbregion1_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{28, 29, 0x0000000000000000, "RW", "rk0dbregion1_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 27, 0x0000000000000000, "RW", "rk0dbregion2_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{26, 27, 0x0000000000000000, "RW", "rk0dbregion2_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "rk0dbregion3_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{24, 25, 0x0000000000000000, "RW", "rk0dbregion3_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "rk0dbregion4_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{22, 23, 0x0000000000000000, "RW", "rk0dbregion4_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 21, 0x0000000000000000, "RW", "rk0dbregion5_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{20, 21, 0x0000000000000000, "RW", "rk0dbregion5_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 19, 0x0000000000000000, "RW", "rk0dbregion6_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{18, 19, 0x0000000000000000, "RW", "rk0dbregion6_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rk0dbregion7_dyndqdbsel", "LP4 PT Dead Band Rk0 DB Control"},
#else
{16, 17, 0x0000000000000000, "RW", "rk0dbregion7_dyndqdbsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RW", "rk0dbregion0_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{14, 15, 0x0000000000000000, "RW", "rk0dbregion0_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "rk0dbregion1_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{12, 13, 0x0000000000000000, "RW", "rk0dbregion1_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RW", "rk0dbregion2_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{10, 11, 0x0000000000000000, "RW", "rk0dbregion2_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "rk0dbregion3_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{8, 9, 0x0000000000000000, "RW", "rk0dbregion3_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "rk0dbregion4_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{6, 7, 0x0000000000000000, "RW", "rk0dbregion4_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000000, "RW", "rk0dbregion5_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{4, 5, 0x0000000000000000, "RW", "rk0dbregion5_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rk0dbregion6_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{2, 3, 0x0000000000000000, "RW", "rk0dbregion6_dyndqdboffset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "rk0dbregion7_dyndqdboffset", "LP4 PT Dead Band Rk0 DB Offset Control"},
#else
{0, 1, 0x0000000000000000, "RW", "rk0dbregion7_dyndqdboffset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo799[] = {{"DBREGIONCTL3", "", 0x0000009C, 16, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields800[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{31, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pu_override", "grp0 pull up override code"},
#else
{24, 30, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pu_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{23, 23, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pd_override", "grp0 pull down override code"},
#else
{16, 22, 0x0000000000000000, "RW", "lrcomp_pdgrp0_pd_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{15, 15, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pu_override", "grp1 pull up override code"},
#else
{8, 14, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pu_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "Reserved2", "Reserved bits"},
#else
{7, 7, 0x0000000000000000, "RO", "Reserved2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pd_override", "grp1 pull down override code"},
#else
{0, 6, 0x0000000000000000, "RW", "lrcomp_pdgrp1_pd_override", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo800[] = {{"DPIC_LRCOMP_OVR1", "", 0x000000A0, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields801[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{14, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RW", "lrcomppd_grp_override_en", "Pull down override enable"},
#else
{8, 13, 0x0000000000000000, "RW", "lrcomppd_grp_override_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{6, 7, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lrcomppu_grp_override_en", "Pull up override enable"},
#else
{0, 5, 0x0000000000000000, "RW", "lrcomppu_grp_override_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo801[] = {{"DPIC_LRCOMP_PUPDOVR", "", 0x000000AC, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields802[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp0", "PU / PD Code"},
#else
{24, 31, 0x0000000000000000, "RO/V", "lrcomp_pu_code_grp0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp0", "PU / PD Code"},
#else
{16, 23, 0x0000000000000000, "RO/V", "lrcomp_pd_code_grp0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp1", "PU / PD Code"},
#else
{8, 15, 0x0000000000000007, "RO/V", "lrcomp_pu_code_grp1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp1", "PU / PD Code"},
#else
{0, 7, 0x0000000000000008, "RO/V", "lrcomp_pd_code_grp1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo802[] = {{"DPIC_LRCOMP_CODES_0", "", 0x000000B0, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields803[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 26, 0x000000000000000E, "RW", "lrcomp_sampdel1", "Rcomp sample time 1"},
#else
{19, 26, 0x000000000000000E, "RW", "lrcomp_sampdel1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 18, 0x000000000000000E, "RW", "lrcomp_sampdel2", "Rcomp sample time 2"},
#else
{11, 18, 0x000000000000000E, "RW", "lrcomp_sampdel2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 10, 0x000000000000000E, "RW", "lrcomp_sampdel3", "Rcomp sample time 3"},
#else
{3, 10, 0x000000000000000E, "RW", "lrcomp_sampdel3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "lcomp_sel_membus_frm_gcomp", "set it to '1' to select the membus form gcomp, '0' to select it from previous module."},
#else
{2, 2, 0x0000000000000000, "RW", "lcomp_sel_membus_frm_gcomp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "lrcomp_msgbus_clk_div", "indicates the division ratio of the c73p1ddrlp34l64x1top_comp clock w.r.t spid clk"},
#else
{0, 1, 0x0000000000000001, "RW", "lrcomp_msgbus_clk_div", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo803[] = {{"DPIC_LRCOMP_CFG2", "", 0x000000E0, 6, 0x00000000FFFFFFFF, 0x0000000000707071}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields804[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{22, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{22, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 21, 0x0000000000000001, "RW", "lrcomp_pd_live_override", "override for pull down live rcomp code going to AFE"},
#else
{15, 21, 0x0000000000000001, "RW", "lrcomp_pd_live_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "lrcomp_pd_live_override_en", "override enable for override for pull down live rcomp code going to AFE"},
#else
{14, 14, 0x0000000000000000, "RW", "lrcomp_pd_live_override_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{8, 13, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 7, 0x0000000000000000, "RW", "lrcomp_pd_puref_override", "not used"},
#else
{1, 7, 0x0000000000000000, "RW", "lrcomp_pd_puref_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lrcomp_pd_puref_override_en", "not used"},
#else
{0, 0, 0x0000000000000000, "RW", "lrcomp_pd_puref_override_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo804[] = {{"DPIC_LRCOMP_OVR0", "", 0x000000E8, 6, 0x00000000FFFFFFFF, 0x0000000000008000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields805[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{27, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 26, 0x0000000000000001, "RW", "sel_bqt_for_lcomp", "selects the bus_quiet_time_gnt signal for lcomp buffer."},
#else
{25, 26, 0x0000000000000001, "RW", "sel_bqt_for_lcomp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000001, "RW", "lrcomp_pd_staticlive", "static live signal for PD c73p1ddrlp34l64x1top_comp buffer."},
#else
{24, 24, 0x0000000000000001, "RW", "lrcomp_pd_staticlive", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000001, "RW", "lrcomp_pu_static", "static leg signal for PD c73p1ddrlp34l64x1top_comp buffer."},
#else
{23, 23, 0x0000000000000001, "RW", "lrcomp_pu_static", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{22, 22, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "lrcomp_general_timer", "not used."},
#else
{16, 21, 0x0000000000000000, "RW", "lrcomp_general_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "lrcomp_stg2_width", "no of cycles needed for stage 2 update."},
#else
{12, 15, 0x0000000000000000, "RW", "lrcomp_stg2_width", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000008, "RW", "lrcomp_update_len", "no of cycles needed for code update."},
#else
{8, 11, 0x0000000000000008, "RW", "lrcomp_update_len", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "lrcomp_update", "config control for updating rcomp codes."},
#else
{7, 7, 0x0000000000000000, "RW", "lrcomp_update", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "lrcomp_updtbyen", "enable for config concifg control for updating rcomp codes."},
#else
{6, 6, 0x0000000000000000, "RW", "lrcomp_updtbyen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lrcomp_grp_update_disable", "config contorl for disabling rcomp code per group."},
#else
{0, 5, 0x0000000000000000, "RW", "lrcomp_grp_update_disable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo805[] = {{"DPIC_LRCOMP_CTL0", "", 0x000000EC, 11, 0x00000000FFFFFFFF, 0x0000000003800800}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields806[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{17, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 16, 0x0000000000000000, "RW", "lcomp_pdcode_copy_bits", "tells the rcomp to copy the adjecent code instead of evaluating it"},
#else
{12, 16, 0x0000000000000000, "RW", "lcomp_pdcode_copy_bits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x000000000000003F, "RW", "lrcomp_pdcode_valid_bits", "tells the rcomp which groups are valid."},
#else
{6, 11, 0x000000000000003F, "RW", "lrcomp_pdcode_valid_bits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000003F, "RW", "lrcomp_en_indirect_update", "enable indirect update, when '1', it enables indirect update for respective group, when '0', it disables indirect update for that group."},
#else
{0, 5, 0x000000000000003F, "RW", "lrcomp_en_indirect_update", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo806[] = {{"DPIC_LRCOMP_CTL1", "", 0x000000F0, 4, 0x00000000FFFFFFFF, 0x0000000000000FFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields807[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lcomprst_b", "active low reset for lcomp."},
#else
{0, 0, 0x0000000000000000, "RW", "lcomprst_b", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo807[] = {{"DPIC_LRCOMP_RSTCTL", "", 0x000000F4, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields808[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lrcomp_clkgate_en", "Clock gating control for rcomp."},
#else
{1, 1, 0x0000000000000000, "RW", "lrcomp_clkgate_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ltxdlycomp_clkgate_en", "Clock gating control for txdlycomp"},
#else
{0, 0, 0x0000000000000000, "RW", "ltxdlycomp_clkgate_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo808[] = {{"DPIC_TXDLYCOMP_CLKGATE", "", 0x000000F8, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields809[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{1, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/1S/V", "ltxdlycomp_init_comp", "enable initial txdlycomp"},
#else
{0, 0, 0x0000000000000000, "RW/1S/V", "ltxdlycomp_init_comp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo809[] = {{"DPIC_TXDLYCOMP_INIT", "", 0x000000FC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields810[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{5, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 4, 0x0000000000000000, "RO/V", "lcomp_cmn_obonus", "read back value from AFE"},
#else
{1, 4, 0x0000000000000000, "RO/V", "lcomp_cmn_obonus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "ltxdlycomp_limit_hit_error_set", "read back value of txdlycomp limit error set flag"},
#else
{0, 0, 0x0000000000000000, "RO/V", "ltxdlycomp_limit_hit_error_set", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo810[] = {{"DPIC_LCOMP_READBACK", "", 0x00000104, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields811[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{19, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{19, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 18, 0x0000000000000001, "RW", "lrcomp_bqt_settle_width", "the number of cycles after lcomp receives the bus_quiet_time_gnt signal, and before it takes any action. This allows the phy to finish off any running read/write cycles"},
#else
{12, 18, 0x0000000000000001, "RW", "lrcomp_bqt_settle_width", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000001, "RW", "lrcomp_setup_width", "For future designs, where there might be a need to generate a stage3 enable for AFE. It needs to be '1' otherwise."},
#else
{8, 11, 0x0000000000000001, "RW", "lrcomp_setup_width", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000001, "RW", "lrcomp_hold_width", "For future designs, where there might be a need to generate a stage3 enable for AFE. It needs to be '1' otherwise."},
#else
{4, 7, 0x0000000000000001, "RW", "lrcomp_hold_width", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000001, "RW", "lrcomp_enable_width", "For future designs, where there might be a need to generate a stage3 enable for AFE. It needs to be '1' otherwise."},
#else
{0, 3, 0x0000000000000001, "RW", "lrcomp_enable_width", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo811[] = {{"DPIC_LRCOMP_CTL2", "", 0x00000108, 5, 0x00000000FFFFFFFF, 0x0000000000001111}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields812[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "ltxdlycomp_update", "config update contorl for txdlyocmp code"},
#else
{29, 29, 0x0000000000000000, "RW", "ltxdlycomp_update", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "ltxdlycomp_updtbyen", "enable for config update contorl for txdlycomp code."},
#else
{28, 28, 0x0000000000000000, "RW", "ltxdlycomp_updtbyen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 27, 0x0000000000000006, "RW", "ltxdlycomp_grp0_tapsel", "select the delay tap node in AFE for group0"},
#else
{23, 27, 0x0000000000000006, "RW", "ltxdlycomp_grp0_tapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW", "ltxdlycomp_grp0_update_disable", "bits to disable for group0 code update."},
#else
{22, 22, 0x0000000000000000, "RW", "ltxdlycomp_grp0_update_disable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "ltxdlycomp_grp0_override_en", "bits for override control of grp0 code"},
#else
{21, 21, 0x0000000000000000, "RW", "ltxdlycomp_grp0_override_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 20, 0x0000000000000000, "RW", "ltxdlycomp_grp0_coarse_override", "config value for grp0 coarse code."},
#else
{13, 20, 0x0000000000000000, "RW", "ltxdlycomp_grp0_coarse_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 12, 0x0000000000000000, "RW", "ltxdlycomp_grp0_fine_override", "config value for grp0 fine code."},
#else
{5, 12, 0x0000000000000000, "RW", "ltxdlycomp_grp0_fine_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ltxdlycomp_limit_hit_error", "read back value of txdlycomp limit error set flag"},
#else
{4, 4, 0x0000000000000000, "RW", "ltxdlycomp_limit_hit_error", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "Reserved0", "Reserved bits"},
#else
{3, 3, 0x0000000000000000, "RO", "Reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ltxdlycomp_continuous_en", "continuous enable mode for txdlycomp"},
#else
{2, 2, 0x0000000000000000, "RW", "ltxdlycomp_continuous_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ltxdlycomp_1group", "When set, Tx Delay c73p1ddrlp34l64x1top_Comp evaluation is restricted to only one group"},
#else
{1, 1, 0x0000000000000000, "RW", "ltxdlycomp_1group", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "Reserved1", "Reserved bits"},
#else
{0, 0, 0x0000000000000000, "RO", "Reserved1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo812[] = {{"DPIC_TXDLYCOMP_0", "", 0x00000110, 13, 0x00000000FFFFFFFF, 0x0000000003000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields813[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000000, "RO", "Reserved", "Reserved bits"},
#else
{23, 31, 0x0000000000000000, "RO", "Reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp1_tapsel", "select the delay tap node in AFE for group1"},
#else
{18, 22, 0x0000000000000006, "RW", "ltxdlycomp_grp1_tapsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp1_update_disable", "bits to disable for group1 code update."},
#else
{17, 17, 0x0000000000000000, "RW", "ltxdlycomp_grp1_update_disable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp1_override_en", "bits for override control of grp1 code"},
#else
{16, 16, 0x0000000000000000, "RW", "ltxdlycomp_grp1_override_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp1_coarse_override", "config value for grp1 coarse code."},
#else
{8, 15, 0x0000000000000000, "RW", "ltxdlycomp_grp1_coarse_override", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp1_fine_override", "config value for grp1 fine code."},
#else
{0, 7, 0x0000000000000000, "RW", "ltxdlycomp_grp1_fine_override", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo813[] = {{"DPIC_TXDLYCOMP_1", "", 0x00000114, 6, 0x00000000FFFFFFFF, 0x0000000000180000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields814[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp0", "DQ coarse code value."},
#else
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp0", "DQ fine code value."},
#else
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp1", "DQS coarse code value."},
#else
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp1", "DQS fine code value."},
#else
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo814[] = {{"DPIC_LTXDLYCOMP_CODES_0", "", 0x00000120, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields815[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp2", "Unused - Inputs for readout are tied to 'h0"},
#else
{24, 31, 0x0000000000000000, "RO/V", "ltxdlycomp_coarse_code_grp2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp2", "Unused - Inputs for readout are tied to 'h0"},
#else
{16, 23, 0x0000000000000000, "RO/V", "ltxdlycomp_fine_code_grp2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp3", "Unused - Inputs for readout are tied to 'h0"},
#else
{8, 15, 0x0000000000000007, "RO/V", "ltxdlycomp_coarse_code_grp3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp3", "Unused - Inputs for readout are tied to 'h0"},
#else
{0, 7, 0x0000000000000008, "RO/V", "ltxdlycomp_fine_code_grp3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo815[] = {{"DPIC_LTXDLYCOMP_CODES_1", "", 0x00000124, 4, 0x00000000FFFFFFFF, 0x0000000000000708}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields816[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{23, 31, 0x0000000000000015, "RW/V", "device_id_strap2", "The reset default value of this register is tied to the parameter DEVICE_ID_STRAP2. These  bits  can  be  rewritten  from SETIDVALUE message 1st DW data byte 2  byte3"},
#else
{23, 31, 0x0000000000000015, "RW/V", "device_id_strap2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 22, 0x0000000000000003, "RO", "device_id_strap1", "These bits are tied to a Cunit parameter DEVICE_ID_STRAP1."},
#else
{21, 22, 0x0000000000000003, "RO", "device_id_strap1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 20, 0x0000000000000010, "RO/V", "device_id_fuse", "These  bits  are fuse backed."},
#else
{16, 20, 0x0000000000000010, "RO/V", "device_id_fuse", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000008086, "RO", "vendor_id", "Hardwired to Intels VENDOR ID value"},
#else
{0, 15, 0x0000000000008086, "RO", "vendor_id", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo816[] = {{"DEVICE_ID_VENDOR_ID_0_0_0_PCI", "", 0x00000000, 4, 0x00000000FFFFFFFF, 0x000000000AF08086}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields817[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000007, "RO", "pci_status_and_command", "PCI Status and PCI Command. Hardwired to 32 h00000007"},
#else
{0, 31, 0x0000000000000007, "RO", "pci_status_and_command", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo817[] = {{"PCI_STATUS_COMMAND_0_0_0_PCI", "", 0x00000004, 1, 0x00000000FFFFFFFF, 0x0000000000000007}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields818[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000600, "RO", "class_code1", "Hardwired 16 h0600"},
#else
{16, 31, 0x0000000000000600, "RO", "class_code1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "class_code0", "Hardwired to 8 h00"},
#else
{8, 15, 0x0000000000000000, "RO", "class_code0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW/V", "revision_id_strap", "These  bits  can  be  rewritten  from SETIDVALUE message 1st DW data byte 0"},
#else
{0, 7, 0x0000000000000000, "RW/V", "revision_id_strap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo818[] = {{"REVISION_ID_CLASS_CODE_0_0_0_PCI", "", 0x00000008, 3, 0x00000000FFFFFFFF, 0x0000000006000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields819[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{24, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000080, "RO", "header_type", "Header Type"},
#else
{16, 23, 0x0000000000000080, "RO", "header_type", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "master_latency_timer", "Header Type   hardwired to 0"},
#else
{8, 15, 0x0000000000000000, "RO", "master_latency_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{0, 7, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo819[] = {{"MASTER_LATENCY_TIME_0_0_0_PCI", "", 0x0000000C, 4, 0x00000000FFFFFFFF, 0x0000000000800000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields820[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{15, 31, 0x0000000000000000, "RW", "tmmba", "This field corresponds to bits 31 to 15 of the base address TMBAR address space. BIOS will program this register resulting in a base address for a 32KB block of contiguous memory address space. This register ensures that a naturally aligned 32KB space is allocated within total addressable memory space. The DPTF driver uses this base address to program all Thermal and Throttling control register set."},
#else
{15, 31, 0x0000000000000000, "RW", "tmmba", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RO", "adm", "Hardwired to 0s to indicate at least 32KB address range."},
#else
{4, 14, 0x0000000000000000, "RO", "adm", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "pm", "Hardwired to 0 to prevent prefetching."},
#else
{3, 3, 0x0000000000000000, "RO", "pm", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000002, "RO", "mt", "Hardwired to 10 to indicate 64bit address."},
#else
{1, 2, 0x0000000000000002, "RO", "mt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "mios", "This register represents the lower 32bits of PCI CFG register for that defines the DPTF MMIO address space."},
#else
{0, 0, 0x0000000000000000, "RO", "mios", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo820[] = {{"TMBAR_LO_0_0_1_PCI", "", 0x00000010, 5, 0x00000000FFFFFFFF, 0x0000000000000004}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields821[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RW", "rsvdrw", "Must be set to 0 since addressing above 512GB is not supported."},
#else
{7, 31, 0x0000000000000000, "RW", "rsvdrw", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "tmmba", "This register represents the lower 32bits of PCI CFG register for that defines the DPTF MMIO address space."},
#else
{0, 6, 0x0000000000000000, "RW", "tmmba", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo821[] = {{"TMBAR_HI_0_0_1_PCI", "", 0x00000014, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields822[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "subsystem_id", "PCI Subsystem ID: This field should be programmed during BIOS initialization."},
#else
{16, 31, 0x0000000000000000, "RW", "subsystem_id", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "subsystem_vendor_id", "PCI Subsystem Vendor ID: This field shouldbe programmed by BIOS during bootup to indicate the vendor of the system board."},
#else
{0, 15, 0x0000000000000000, "RW", "subsystem_vendor_id", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo822[] = {{"SVID_SID_0_0_0_PCI", "", 0x0000002C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields823[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000E0, "RO", "base_addr", "Pointer to first capabilities register"},
#else
{0, 7, 0x00000000000000E0, "RO", "base_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo823[] = {{"CAPPTR_0_0_0_PCI", "", 0x00000034, 2, 0x00000000FFFFFFFF, 0x00000000000000E0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields824[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{15, 31, 0x0000000000000000, "RW", "base_addr", "Number of implemented bits used to indicated size of BAR 32kB"},
#else
{15, 31, 0x0000000000000000, "RW", "base_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RO", "base_addr_not_implemented", "Hardwired to 0 to indicate size of BAR 32kB"},
#else
{4, 14, 0x0000000000000000, "RO", "base_addr_not_implemented", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 3, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{1, 3, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "mchbaren", "0: MCHBAR is disabled and does not claim any memory  1: MCHBAR memory mapped accesses are claimed and decoded appropriately  Encoding Description  0b MCHBAR is disabled  1b MCHBAR is enabled"},
#else
{0, 0, 0x0000000000000000, "RW", "mchbaren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo824[] = {{"MCHBAR_LO_0_0_0_PCI", "", 0x00000048, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields825[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "base_addr", "Number of implemented bits used to indicated size of BAR 32kB"},
#else
{0, 6, 0x0000000000000000, "RW", "base_addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo825[] = {{"MCHBAR_HI_0_0_0_PCI", "", 0x0000004C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields826[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{16, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "gms", "This field is used to select the amount of Main Memory that is preallocated to support the Internal Graphics device in VGA nonlinear and Native linear modes. The BIOS ensures that memory is preallocated only when Internal graphics is enabled.  This register is also Intel TXT lockable.  Hardware does not clear or set any of these bits automatically based on IGD being disabled/enabled.  BIOS Requirement: BIOS must not set this field to 0h if IVD bit 1 of this register is 0.  0x00:0MB  0x01:32MB  0x02:64MB  0x03:96MB  0x04:128MB  0x05:160MB  0x06:192MB  0x07:224MB  0x08:256MB  0x09:288MB  0x0A:320MB  0x0B:352MB  0x0C:384MB  0x0D:416MB  0x0E:448MB  0x0F:480MB  0x10:512MB  0x20:...1024MB...  0x30:...1536MB...  0x3F:...2016MB  0x400xFF:Illegal value"},
#else
{8, 15, 0x0000000000000000, "RW", "gms", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "ggms", "This field is used to select the amount of Main Memory that is preallocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is preallocated only when Internal graphics is enabled.  GSM is assumed to be a contiguous physical DRAM space with DSM and BIOS needs to allocate a contiguous memory chunk. Hardware will derive the base of GSM from DSM only using the GSM size programmed in the register.  Hardware functionality in case of programming this value to Reserved is not guaranteed.  0x0:No Preallocated Memory  0x1:2MB of Preallocated Memory  0x2:4MB of Preallocated Memory  0x3:8MB of Preallocated Memory"},
#else
{6, 7, 0x0000000000000000, "RW", "ggms", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{3, 5, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO", "vamen", "Enables the use of the iGFX enbines for Versatile Acceleration.  1  iGFX engines are in Versatile Acceleration Mode. Device 2 Class Code is 048000h.  0  iGFX engines are in iGFX Mode. Device 2 Class Code is 030000h."},
#else
{2, 2, 0x0000000000000000, "RO", "vamen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/V", "ivd", "IGD VGA Disable  0: Enable. Device 2 IGD claims VGA memory and IO cycles the SubClass Code within Device 2 Class Code register is 00.  1: Disable. Device 2 IGD does not claim VGA cycles Mem and IO and the Sub Class Code field within Device 2 function 0 Class Code register is 80.  BIOS Requirement: BIOS must not set this bit to 0 if the GMS field bits 7:3 of this register preallocates no memory.  This bit MUST be set to 1 if Device 2 is disabled DEVEN_0_0_0_PCI.D2F0EN  0."},
#else
{1, 1, 0x0000000000000000, "RW/V", "ivd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "ggclck", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: This bit locks all other writeable bits in this register."},
#else
{0, 0, 0x0000000000000000, "RW", "ggclck", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo826[] = {{"GGC_0_0_0_PCI", "", 0x00000050, 7, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields827[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW/V", "d3f0en", "0:      Bus 0 Device 3 Function 0 is disabled and hidden  1:      Bus 0 Device 3 Function 0 is enabled and visible  This bit will be set to 0b and remain 0b if BDF0.3.0 capability is disabled."},
#else
{5, 5, 0x0000000000000001, "RW/V", "d3f0en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW/V", "d2f0en", "0:      Bus 0 Device 2 Function 0 is disabled and hidden  1:      Bus 0 Device 2 Function 0 is enabled and visible  This bit will be set to 0b and remain 0b if BDF0.2.0 capability is disabled."},
#else
{4, 4, 0x0000000000000001, "RW/V", "d2f0en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{2, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW/V", "d0f1en", "0:      Bus 0 Device 0 Function 1 is disabled and hidden  1:      Bus 0 Device 0 Function 1 is enabled and visible  This bit will be set to 0b and remain 0b if BDF0.0.1 capability is disabled."},
#else
{1, 1, 0x0000000000000001, "RW/V", "d0f1en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RO", "d0f0en", "Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1."},
#else
{0, 0, 0x0000000000000001, "RO", "d0f0en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo827[] = {{"DEVEN_0_0_0_PCI", "", 0x00000054, 6, 0x00000000FFFFFFFF, 0x0000000000000033}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields828[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RW", "pcmbase", "Sizes supported in BDW: 1M 2M 4M and 8M. Base value programmed from Top of Stolen Memory itself defines the size of the WOPCM. Separate WOPCM size programming is redundant information and not required. Default 1M size programming. 4M recommended for BDW."},
#else
{20, 31, 0x0000000000000000, "RW", "pcmbase", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 19, 0x0000000000000000, "RO", "rsvd2", "These bits are reserved for future use."},
#else
{7, 19, 0x0000000000000000, "RO", "rsvd2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "asmfen", "ASMF method enabled  0b Disabled default.   1b Enabled."},
#else
{6, 6, 0x0000000000000000, "RW", "asmfen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO", "rsvd1", "These bits are reserved for future use."},
#else
{5, 5, 0x0000000000000000, "RO", "rsvd1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "ovtattack", "Override of Unsolicited Connection State Attack and Terminate.  0: Disable Override. Attack Terminate allowed.  1: Enable Override. Attack Terminate disallowed."},
#else
{4, 4, 0x0000000000000000, "RW", "ovtattack", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "hvymodsel", "This bit is applicable only for PAVP2 operation mode with a chicken bit also set or for PAVP3 mode only if the perApp memory config is disabled due to the clearing of an additional chicken bit 9 in the Crypto Function Control_1 register address 0x320F0.  0: Lite Mode NonSerpent mode  1: Serpent Mode  For chickenbit enabled PAVP3 mode this one type boot time programming has been replaced by perApp programming through the Media Crypto Copy command. Note that PAVP2 or PAVP3 mode selection is done by programming bit 8 of the MFX_MODE  Video Mode register."},
#else
{3, 3, 0x0000000000000000, "RW", "hvymodsel", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "pavplck", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: This bit locks all writeable contents in this register when set including itself. Only a hardware reset can unlock the register again. This lock bit needs to be set only if PAVP is enabled bit 1 of this register is asserted."},
#else
{2, 2, 0x0000000000000000, "RW", "pavplck", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "pavpe", "0: PAVP functionality is disabled.  1: PAVP functionality is enabled."},
#else
{1, 1, 0x0000000000000000, "RW", "pavpe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pcme", "This field enables Protected Content Memory within Graphics Stolen Memory. This memory is the same as the WOPCM area whose size is defined by bit 5 of this register. This register is locked when PAVPLCK is set. A value of 0 in this field indicates that Protected Content Memory is disabled and cannot be programmed in this manner  when PAVP is enabled. A value of 1 in this field indicates that Protected Content Memory is enabled and is the only programming option available when PAVP is enabled. Note that the SNB legacy Lite mode programming of PCME bit  0 is not supported. For nonPAVP3 Mode even for Lite mode configuration this bit should be programmed to 1 and HVYMODESEL  0. This bit should always be programmed to 1 if bits 1 and 2 PAVPE and PAVP lock bits are both set. With perApp Memory configuration support the range check for the WOPCM memory area should always happen when this bit is set regardless of Lite or Serpent mode or PAVP2 or PAVP3 mode programming."},
#else
{0, 0, 0x0000000000000000, "RW", "pcme", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo828[] = {{"PAVPC_0_0_0_PCI", "", 0x00000058, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields829[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW", "pciexbar", "PCIEXBAR: PCIEXBAR[38:28] is PCIEXBAR_HI[6:0]PCIEXBAR_LO[31:28]. Describes bits [38:28] of the base address of the contiguous 256MB region for PCI Express Enhanced Configuration region.   If bits [38:28] of the request address matches the PCIEXBAR[38:28] then the request targets the PCI Express Enhanced Configuration Space region.  A posted memory operation from an IDI agent will be treated as a nonposted operation by the Tunit and Aunit."},
#else
{28, 31, 0x0000000000000000, "RW", "pciexbar", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "admsk128", "Reserved.  Unused by SoC since PCIEXBAR is a fixed 256MB region in SoCs."},
#else
{27, 27, 0x0000000000000000, "RO", "admsk128", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO", "admsk64", "Reserved.  Unused by SoC since PCIEXBAR is a fixed 256MB region in SoCs."},
#else
{26, 26, 0x0000000000000000, "RO", "admsk64", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 25, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{3, 25, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000000, "RO", "length", "Length of the region.  Reserved and set to 0 indicating a fixed 256 MB region."},
#else
{1, 2, 0x0000000000000000, "RO", "length", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "pciexbaren", "0: The PCIEXBAR register is disabled. Memory read and write transactions proceed s if there were no PCIEXBAR register. PCIEXBAR bits 38:26 are R/W with no functionality behind them.  1: The PCIEXBAR register is enabled. Memory read and write transactions whose address bits 38:26 match PCIEXBAR will be translated to configuration reads and writes within the Uncore. These Translated cycles are routed as shown in the above table."},
#else
{0, 0, 0x0000000000000000, "RW", "pciexbaren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo829[] = {{"PCIEXBAR_LO_0_0_0_PCI", "", 0x00000060, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields830[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "pciexbar_hi", "PCIEXBAR: PCIEXBAR[38:28] is PCIEXBAR_HI[6:0]PCIEXBAR_LO[31:28]. Describes bits [38:28] of the base address of the contiguous 256MB region for PCI Express Enhanced Configuration region.   If bits [38:28] of the request address matches the PCIEXBAR[38:28] then the request targets the PCI Express Enhanced Configuration Space region.  A posted memory operation from an IDI agent will be treated as a nonposted operation by the Tunit and Aunit."},
#else
{0, 6, 0x0000000000000000, "RW", "pciexbar_hi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo830[] = {{"PCIEXBAR_HI_0_0_0_PCI", "", 0x00000064, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields831[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RW", "touud", "This register contains bits 38  to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system. Configuration software must set this value to TOM minus all ME stolen memory if reclaim is disabled. If reclaim is enabled this value must be set to reclaim limit 1MB aligned since reclaim limit  1byte is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4GB.  Note: for 40bit addressing have to add a bit to this field"},
#else
{20, 31, 0x0000000000000000, "RW", "touud", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 19, 0x0000000000000000, "RO", "reserved_0", "Reserved should return 0s on read"},
#else
{1, 19, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lock_reserved", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: This bit will lock all writeable settings in this register including itself client definition."},
#else
{0, 0, 0x0000000000000000, "RW", "lock_reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo831[] = {{"TOUUD_LO_0_0_0_PCI", "", 0x000000A8, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields832[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{7, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "touud_hi", "This register contains bits 38  to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system. Configuration software must set this value to TOM minus all ME stolen memory if reclaim is disabled. If reclaim is enabled this value must be set to reclaim limit 1MB aligned since reclaim limit  1byte is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4GB.  Note: for 40bit addressing have to add a bit to this field"},
#else
{0, 6, 0x0000000000000000, "RW", "touud_hi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo832[] = {{"TOUUD_HI_0_0_0_PCI", "", 0x000000AC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields833[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RW", "bdsm", "This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size PCI Device 0 offset 52 bits 7:4 from TOLUD PCI Device 0 offset BC bits 31:20."},
#else
{20, 31, 0x0000000000000000, "RW", "bdsm", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 19, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{1, 19, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lock", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: This bit will lock all writeable settings in this register including itself."},
#else
{0, 0, 0x0000000000000000, "RW", "lock", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo833[] = {{"BDSM_0_0_0_PCI", "", 0x000000B0, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields834[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RW", "bgsm", "This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size PCI Device 0 offset 52 bits 11:8 from the Graphics Base of  Data Stolen Memory PCI Device 0 offset B0 bits 31:20."},
#else
{20, 31, 0x0000000000000000, "RW", "bgsm", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 19, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{1, 19, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lock", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: This bit will lock all writeable settings in this register including itself."},
#else
{0, 0, 0x0000000000000000, "RW", "lock", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo834[] = {{"BGSM_0_0_0_PCI", "", 0x000000B4, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields835[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000001, "RW", "tsegmb", "Base address of TSEG DRAM memory.  BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory BGSM.  SMM range starts at this base and ends at BGSM1.  Incoming Request Address [31:20] will be compared with TSEGMB[31:20] and BGSM[31:20] to determine if the request targets the SMM range.  The comparison check is as follows: Address[31:20]  TSEGMB[31:20]  Address[31:20]  BGSM[31:20]  Address[38:32]  0.  If the check passes the request targets the SMM range.  If the protection for the range is enabled then the request SAI is compared against allowed SAIs specified by BSMRRAC and BSMRWAC registers to determine if access is allowed."},
#else
{20, 31, 0x0000000000000001, "RW", "tsegmb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 19, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{1, 19, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lock", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: This bit will lock all writeable settings in this register including itself."},
#else
{0, 0, 0x0000000000000000, "RW", "lock", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo835[] = {{"TSEGMB_0_0_0_PCI", "", 0x000000B8, 3, 0x00000000FFFFFFFF, 0x0000000000100000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields836[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000001, "RW", "tolud", "Defines the top of lower usable DRAM which ends at the preceding byte.  Lower MMIO Address range starts at this address and continues up to the 4GB Address 0xFFFF_FFFF.  Bits 31:20 are compared with incoming request Address[31:20] to determine whether the request targets lower usable DRAM range or the lower MMIO range.  If Request Address[31:20]  TOLUD[31:20] and Request Address[38:32]  0 then the Request Address falls in the Lower MMIO Address range."},
#else
{20, 31, 0x0000000000000001, "RW", "tolud", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 19, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{1, 19, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lock", "N/A"},
#else
{0, 0, 0x0000000000000000, "RW", "lock", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo836[] = {{"TOLUD_0_0_0_PCI", "", 0x000000BC, 3, 0x00000000FFFFFFFF, 0x0000000000100000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields837[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "skpd", "1 DWORD of data storage."},
#else
{0, 31, 0x0000000000000000, "RW", "skpd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo837[] = {{"SKPD_0_0_0_PCI", "", 0x000000DC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields838[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{28, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000001, "RO", "capid_ver", "This field has the value 0001b to identify the first revision of the CAPID register definition."},
#else
{24, 27, 0x0000000000000001, "RO", "capid_ver", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x000000000000000C, "RO", "capidlen", "This field has the value 0Ch to indicate the structure length 12 bytes.  Are these the right values for us  Check with SCA  NOTE: merged these two registrers 0xE0 and 0xE2/CAPCTRL0"},
#else
{16, 23, 0x000000000000000C, "RO", "capidlen", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO", "next_cap", "This field is hardwired to 00h indicating the end of the capabilities linked list."},
#else
{8, 15, 0x0000000000000000, "RO", "next_cap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000009, "RO", "cap_id", "This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers."},
#else
{0, 7, 0x0000000000000009, "RO", "cap_id", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo838[] = {{"CAPID0_CAPCTRL0_0_0_0_PCI", "", 0x000000E0, 5, 0x00000000FFFFFFFF, 0x00000000010C0009}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields839[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "spare31_24", "Reserved for future capabilities."},
#else
{24, 31, 0x0000000000000000, "RW", "spare31_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW/Fuse", "vtdd", "0: Enable VTd  1: Disable VTd"},
#else
{23, 23, 0x0000000000000000, "RW/Fuse", "vtdd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW/Fuse", "fuse_spare22", "Fuse backed spare."},
#else
{22, 22, 0x0000000000000000, "RW/Fuse", "fuse_spare22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW/Fuse", "fuse_spare21", "Fuse backed spare."},
#else
{21, 21, 0x0000000000000000, "RW/Fuse", "fuse_spare21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW/Fuse", "fuse_spare20", "Fuse backed spare."},
#else
{20, 20, 0x0000000000000000, "RW/Fuse", "fuse_spare20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW/Fuse", "fuse_spare19", "Fuse backed spare."},
#else
{19, 19, 0x0000000000000000, "RW/Fuse", "fuse_spare19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW/Fuse", "fuse_spare18", "Fuse backed spare."},
#else
{18, 18, 0x0000000000000000, "RW/Fuse", "fuse_spare18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW/Fuse", "fuse_spare17", "Fuse backed spare."},
#else
{17, 17, 0x0000000000000000, "RW/Fuse", "fuse_spare17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW/Fuse", "fuse_spare16", "Fuse backed spare."},
#else
{16, 16, 0x0000000000000000, "RW/Fuse", "fuse_spare16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW/Fuse", "cdd", "0: DPTF Camarillo associated memory spaces are accessible.  1: DPTF Camarillo associated memory and IO spaces are disabled.  DEVEN_0_0_0_PCI field for DPTF can not be set."},
#else
{15, 15, 0x0000000000000000, "RW/Fuse", "cdd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW/Fuse", "fuse_spare14", "Fuse backed spare."},
#else
{14, 14, 0x0000000000000000, "RW/Fuse", "fuse_spare14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW/Fuse", "fuse_spare13", "Fuse backed spare."},
#else
{13, 13, 0x0000000000000000, "RW/Fuse", "fuse_spare13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW/Fuse", "fuse_spare12", "Fuse backed spare."},
#else
{12, 12, 0x0000000000000000, "RW/Fuse", "fuse_spare12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW/Fuse", "igd", "0: There is a graphics engine within this CPU. Internal Graphics Device Device 2 is enabled and all of its memory and I/O spaces are accessable. Configuration cycles to Device 2 will be completed within the CPU. All nonSMM memory and IO accesses to VGA will be handled based on Memory and IO enables of Device 2 and IO registers within Device 2 and VGA Enable of the PCI to PCI bridge control register in Devices 1 and 6 If PCI Express GFX attach is supported. A selected amount of Graphics Memory space is preallocated from the main memory based on Graphics Mode Select GMS in the GGC Register. Graphics Memory is preallocated above TSEG Memory.  1: There is no graphics engine within this CPU. Internal Graphics Device Device 2 and all of its memory and I/O functions are disabled. Configuration cycle targeted to Device 2 will be passed on to DMI. In addition all clocks to internal graphics logic are turned off. All nonSMM memory and IO accesses to VGA will be handled based on VGA Enable of the PCI to PCI bridge control register in Devices 1 and 6. DEVEN [4:3] Device 0 offset 54h have no meaning. Device 2 Functions 0 and 1 are disabled and hidden."},
#else
{11, 11, 0x0000000000000000, "RW/Fuse", "igd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "didoe", "Controls if there is an override of Dev2 GFX device ID. This functionality is not needed on BXT because Dev2 supports receiving the SetIDValue message for changing device ID. Hardwired to 1b0.   0b Disable ability to override DID  For production  1b Enable ability to override DID  For debug and samples only"},
#else
{10, 10, 0x0000000000000000, "RO", "didoe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RO", "cdid", "Controls the value of Dev2 GFX device ID. This functionality is not needed on BXT because Dev2 supports receiving the SetIDValue message for changing device ID. Hardwared to 2b00.  Identifier assigned to the core/primary PCI device.The corresponding two bit capability ID  programming is:  00: Desktop  01: Mobile  10: Server  11: Marketing Spare"},
#else
{8, 9, 0x0000000000000000, "RO", "cdid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "spare7_0", "Reserved for future capabilities"},
#else
{0, 7, 0x0000000000000000, "RW", "spare7_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo839[] = {{"CAPID0_A_0_0_0_PCI", "", 0x000000E4, 17, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields840[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/Fuse", "imgu_dis", "0: Imaging Unit associated memory spaces are accessible.  1: Imaging Unit associated memory and IO spaces are disabled.  DEVEN_0_0_0_PCI field for Iunit can not be set."},
#else
{31, 31, 0x0000000000000000, "RW/Fuse", "imgu_dis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/Fuse", "fuse_spare_30", "Fuse backed spare."},
#else
{30, 30, 0x0000000000000000, "RW/Fuse", "fuse_spare_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW/Fuse", "fuse_spare_29", "Fuse backed spares potentially to be used for PKGTYP encoding."},
#else
{29, 29, 0x0000000000000000, "RW/Fuse", "fuse_spare_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW/Fuse", "fuse_spare_28", "Fuse backed spares potentially to be used for PKGTYP encoding."},
#else
{28, 28, 0x0000000000000000, "RW/Fuse", "fuse_spare_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW/Fuse", "fuse_spare_27", "Fuse backed spares potentially to be used for PKGTYP encoding."},
#else
{27, 27, 0x0000000000000000, "RW/Fuse", "fuse_spare_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW/Fuse", "fuse_spare_26", "Fuse backed spares potentially to be used for PKGTYP encoding."},
#else
{26, 26, 0x0000000000000000, "RW/Fuse", "fuse_spare_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW/Fuse", "fuse_spare_25", "Fuse backed spares potentially to be used for PKGTYP encoding."},
#else
{25, 25, 0x0000000000000000, "RW/Fuse", "fuse_spare_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW/Fuse", "svmdis", "0: Enable SVM mode  1: Disable SVM mode"},
#else
{24, 24, 0x0000000000000000, "RW/Fuse", "svmdis", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 23, 0x0000000000000000, "RW", "spare23_0", "Reserved for future capabilities."},
#else
{0, 23, 0x0000000000000000, "RW", "spare23_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo840[] = {{"CAPID0_B_0_0_0_PCI", "", 0x000000E8, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields841[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RW/V", "reserved_0", "Reserved  These  bits  can  be  rewritten  from SETIDVALUE message 2nd DW data  byte 3  upper  nibble"},
#else
{28, 31, 0x0000000000000000, "RW/V", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW/V", "dot_portion_of_process_id", "DOT Portion of Process ID  These  bits  can  be  rewritten  from SETIDVALUE message 2nd DW data byte 3 lower  nibble"},
#else
{24, 27, 0x0000000000000000, "RW/V", "dot_portion_of_process_id", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW/V", "process_portion_of_process_id", "Process Portion of Process ID  These  bits  can  be  rewritten  from SETIDVALUE message 2nd DW data byte 0"},
#else
{16, 23, 0x0000000000000000, "RW/V", "process_portion_of_process_id", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW/V", "mid", "Manufacturing ID MID  These  bits  can  be  rewritten  from SETIDVALUE message 2nd DW data byte 1"},
#else
{8, 15, 0x0000000000000000, "RW/V", "mid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW/V", "msid", "Manufacturing Stepping ID MSID  These  bits  can  be  rewritten  from SETIDVALUE message 2nd DW data byte 2"},
#else
{0, 7, 0x0000000000000000, "RW/V", "msid", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo841[] = {{"MANUFACTURER_ID_0_0_0_PCI", "", 0x000000F8, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields842[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "spare_rw", "Spare RW bits for future"},
#else
{0, 31, 0x0000000000000000, "RW", "spare_rw", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo842[] = {{"DEBUP0_0_0_0_PCI", "", 0x000000F4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields843[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "spare_rw", "Spare RW bits for future"},
#else
{0, 31, 0x0000000000000000, "RW", "spare_rw", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo843[] = {{"DEBUP1_0_0_0_PCI", "", 0x000000FC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields844[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{1, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "c_clkgate_disable", "When set disables local clock gating in the Cunit"},
#else
{0, 0, 0x0000000000000000, "RW", "c_clkgate_disable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo844[] = {{"C_CR_LOCAL_CONTROL_MODE", "", 0x00004104, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields845[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "hae", "Hardware Autonomous Enable: If set then the IP may request a PG whenever it is idle.   Note: If this bit is set then bits[2:0] must be 000."},
#else
{5, 5, 0x0000000000000001, "RW", "hae", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{4, 4, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "se", "Sleep Enable: If clear then IP will never assert Sleep to the retention flops. If set then IP may assert Sleep during PGing. Note that some platforms may default this bit to 0 others to 1."},
#else
{3, 3, 0x0000000000000001, "RW", "se", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO", "d3he", "D3Hot Enable: If set then IP will PG when idle and the PMCSR[1:0] register is the IP11.  Hardwired to 1b0 since the Cunit does not support D0i3."},
#else
{2, 2, 0x0000000000000000, "RO", "d3he", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "i3e", "I3 Enable: if set then IP will PG when idle and the D0i3 register D0i3C[2]  1 is set.   Note: If bits[2:1] 11 then the IP would PG whenever either PMCSR  11 or the D0i3C.i3 bit is set.  Hardwired to 1b0 since the Cunit does not support D0i3."},
#else
{1, 1, 0x0000000000000000, "RO", "i3e", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "pmcre", "PMC Request Enable: If set then IP will PG when idle and the PMC requests power gating by asserting pmc_ip_sw_pg_req_b signal.  Hardwired to 1b0 since the Cunit does not support  SW controlled PGing."},
#else
{0, 0, 0x0000000000000000, "RO", "pmcre", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo845[] = {{"C_CR_PGCB_PWRGATE_PCE", "", 0x00004108, 7, 0x00000000FFFFFFFF, 0x0000000000000028}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields846[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{5, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "pgcb_clkgating_disable", "This will feed into the cfg_pgcb_clkgate_disabled input of PGCB clock gate component and when asserted, prevents the PGCB clock trunk from ever gating."},
#else
{4, 4, 0x0000000000000000, "RW", "pgcb_clkgating_disable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000002, "RW", "pg_timer", "Power Gate Hysterisis Timer This is the min time from which all internal Idle conditions have been observed to when PGCB actually starts the power gating sequence."},
#else
{0, 3, 0x0000000000000002, "RW", "pg_timer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo846[] = {{"C_CR_PGCB_PG_IDLE_TIMER", "", 0x0000410C, 3, 0x00000000FFFFFFFF, 0x0000000000000002}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields847[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{18, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{18, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "priclk_force_trunk", "Disable IOSFPri trunk gating"},
#else
{17, 17, 0x0000000000000000, "RW", "priclk_force_trunk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "sbclk_force_trunk", "Disable IOSFSB trunk gating"},
#else
{16, 16, 0x0000000000000000, "RW", "sbclk_force_trunk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 15, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{2, 15, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "priclkgating_disable", "Disable IOSFPri clk gating"},
#else
{1, 1, 0x0000000000000000, "RW", "priclkgating_disable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "sbclkgating_disable", "Disable IOSFSB clk gating"},
#else
{0, 0, 0x0000000000000000, "RW", "sbclkgating_disable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo847[] = {{"C_CR_PGCB_CLKGATE_DIS", "", 0x00004110, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields848[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{8, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000004, "RW", "priclk_idle_timer", "IOSFPri idle timer"},
#else
{4, 7, 0x0000000000000004, "RW", "priclk_idle_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000004, "RW", "sbclk_idle_timer", "IOSFSB idle timer"},
#else
{0, 3, 0x0000000000000004, "RW", "sbclk_idle_timer", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo848[] = {{"C_CR_PGCB_CG_IDLE_TIMER", "", 0x00004114, 3, 0x00000000FFFFFFFF, 0x0000000000000044}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields849[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{17, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "sai_vio_msg_enable", "Toggles sending of SAI violation messages on sideband"},
#else
{16, 16, 0x0000000000000000, "RW", "sai_vio_msg_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW/V", "vio_sai", "SAI bits that triggered the violation"},
#else
{8, 15, 0x0000000000000000, "RW/V", "vio_sai", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 7, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{2, 7, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/V", "vio_more_than_1", "More than one SAI violation detected"},
#else
{1, 1, 0x0000000000000000, "RW/V", "vio_more_than_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "vio_more_than_0", "First SAI violation detected"},
#else
{0, 0, 0x0000000000000000, "RW/V", "vio_more_than_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo849[] = {{"C_CR_SECURITY_STAT0", "", 0x00004118, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields850[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW/V", "vio_addr", "Address that triggered the violation"},
#else
{16, 31, 0x0000000000000000, "RW/V", "vio_addr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW/V", "vio_src_port", "Port that sent the violation"},
#else
{8, 15, 0x0000000000000000, "RW/V", "vio_src_port", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW/V", "vio_opc", "Opcode that triggered the violation"},
#else
{0, 7, 0x0000000000000000, "RW/V", "vio_opc", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo850[] = {{"C_CR_SECURITY_STAT1", "", 0x0000411C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields851[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040061210202, "RW", "sai", "N/A"},
#else
{0, 63, 0x0000040061210202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo851[] = {{"C_CR_BIOSWR_CP", "", 0x00004120, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040061210202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields852[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00632D0217, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000C00632D0217, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo852[] = {{"C_CR_BIOSWR_RAC", "", 0x00004128, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00632D0217}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields853[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00212C0212, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000C00212C0212, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo853[] = {{"C_CR_BIOSWR_WAC", "", 0x00004130, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00212C0212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields854[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040021200202, "RW", "sai", "N/A"},
#else
{0, 63, 0x0000040021200202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo854[] = {{"C_CR_P_U_CODERDWR_CP", "", 0x00004138, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040021200202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields855[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000400212C0202, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000400212C0202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo855[] = {{"C_CR_P_U_CODERDWR_RAC", "", 0x00004140, 1, 0xFFFFFFFFFFFFFFFF, 0x00000400212C0202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields856[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000400212C0202, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000400212C0202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo856[] = {{"C_CR_P_U_CODERDWR_WAC", "", 0x00004148, 1, 0xFFFFFFFFFFFFFFFF, 0x00000400212C0202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields857[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040021200202, "RW", "sai", "N/A"},
#else
{0, 63, 0x0000040021200202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo857[] = {{"C_CR_P_U_CODEWR_ALLRD_CP", "", 0x00004150, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040021200202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields858[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00632D0217, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000C00632D0217, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo858[] = {{"C_CR_P_U_CODEWR_ALLRD_RAC", "", 0x00004158, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00632D0217}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields859[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000400212C0202, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000400212C0202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo859[] = {{"C_CR_P_U_CODEWR_ALLRD_WAC", "", 0x00004160, 1, 0xFFFFFFFFFFFFFFFF, 0x00000400212C0202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields860[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040021200202, "RW", "sai", "N/A"},
#else
{0, 63, 0x0000040021200202, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo860[] = {{"C_CR_IA_UNTRUSTED_CP", "", 0x00004168, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040021200202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields861[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00632D0217, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000C00632D0217, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo861[] = {{"C_CR_IA_UNTRUSTED_RAC", "", 0x00004170, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00632D0217}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields862[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00632D0217, "RW", "sai", "N/A"},
#else
{0, 63, 0x00000C00632D0217, "RW", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo862[] = {{"C_CR_IA_UNTRUSTED_WAC", "", 0x00004178, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00632D0217}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields863[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000000000000000, "RO", "sai", "N/A"},
#else
{0, 63, 0x0000000000000000, "RO", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo863[] = {{"C_CR_SECURITY_CP_0_0_0_MCHBAR", "", 0x00006000, 1, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields864[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00612D0202, "RO", "sai", "N/A"},
#else
{0, 63, 0x00000C00612D0202, "RO", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo864[] = {{"C_CR_SECURITY_RAC_0_0_0_MCHBAR", "", 0x00006008, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00612D0202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields865[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00612D0202, "RO", "sai", "N/A"},
#else
{0, 63, 0x00000C00612D0202, "RO", "sai", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo865[] = {{"C_CR_SECURITY_WAC_0_0_0_MCHBAR", "", 0x00006010, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00612D0202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields866[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{40, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{40, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "defvtdbar_40_bit", "Reserved for future growth to 40bit addressing in uServer.  Will always be 0 in WLV/BXT"},
#else
{39, 39, 0x0000000000000000, "RO", "defvtdbar_40_bit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 38, 0x0000000000000000, "RW", "defvtdbar", "If DEFVTDBAR is enabled this field corresponds to bits 38:12 of the base address default IOMMU VTd configuration space.  BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space.  This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space.  System Software uses this base address to program the default VTd IOMMU register set.  If DEFVTDBAR is enabled and incoming Request Address[38:12] matches DEFVTDBAR[38:12] the request targets the Default VTd BAR."},
#else
{12, 38, 0x0000000000000000, "RW", "defvtdbar", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 11, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{2, 11, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lock", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: Locks the contents of the register including itself."},
#else
{1, 1, 0x0000000000000000, "RW", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/L", "defvtdbaren", "0: DEFVTDBAR is disabled and does not claim any memory  1: DEFVTDBAR memory mapped accesses are claimed and decoded appropriately  This bit will remain 0 if VTd capability is disabled."},
#else
{0, 0, 0x0000000000000000, "RW/L", "defvtdbaren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo866[] = {{"DEFVTDBAR_0_0_0_MCHBAR_C", "", 0x00006C80, 6, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields867[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 38, 0x0000000000000000, "RW", "gfxvtbar", "This field corresponds to bits 39 to 12 of the base address GFXVT configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the GFXVT register set. All the Bits in this register are locked in LT mode."},
#else
{12, 38, 0x0000000000000000, "RW", "gfxvtbar", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 11, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{2, 11, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lock", "This lock bit only impacts the Display copy of this register. In the Cunit all register protection is implemented with SAI policy groups. This bit is maintained in the Cunit for software observability. Diplay description: Locks the contents of the register including itself."},
#else
{1, 1, 0x0000000000000000, "RW", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/L", "gfxvtbaren", "0: GFXVTBAR is disabled and does not claim any memory  1: GFXVTBAR memory mapped accesses are claimed and decoded appropriately  This bit will remain 0 if VTd capability is disabled."},
#else
{0, 0, 0x0000000000000000, "RW/L", "gfxvtbaren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo867[] = {{"GFXVTDBAR_0_0_0_MCHBAR_C", "", 0x00006C88, 5, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields868[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/V", "data", "This field contains the low 32 bits of data associated with specific commands."},
#else
{0, 31, 0x0000000000000000, "RW/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo868[] = {{"P_CR_THERMAL_MAILBOX_DATA0_0_0_0_MCHBAR", "", 0x00007000, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields869[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/V", "data", "This field contains the low 32 bits of data associated with specific commands."},
#else
{0, 31, 0x0000000000000000, "RW/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo869[] = {{"P_CR_THERMAL_MAILBOX_DATA1_0_0_0_MCHBAR", "", 0x00007004, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields870[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/1S/V", "run_busy", "The run/busy control is used for managing the semaphore on the mailbox interface.  Typical usage involves the following flow:\r\n"
"              [list]\r\n"
"              [*] Software waits for the interface run/busy bit to clear.\r\n"
"              [*] Software writes the mailbox data registers as appropriate for this command.\r\n"
"              [*] Software writes a command encoding and sets the run/busy bit in the interface register.\r\n"
"              [*] Software waits for the interface run/busy bit to clear to indicate the command has been handled.\r\n"
"              [*] Software queries the completion code in the command field of the interface register to ensure it passed (0b indicates pass)\r\n"
"              [/list]\r\n"
" \r\n"
"              Bit encoding for the run/busy:\r\n"
"              [list]\r\n"
"              [*] 0 = The thermal mailbox is idle or the last request has been completed.  Software may initiate new requests.\r\n"
"              [*] 1 = The thermal mailbox is busy.  The thermal device is still handling a request.  Writes to thermal mailbox are not allowed at this time.\r\n"
"              [/list]\r\n"
"              "},
#else
{31, 31, 0x0000000000000000, "RW/1S/V", "run_busy", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 28, 0x0000000000000000, "RW/V", "addr_cntl", "This field is used as an additional modifier to the command encoding for incoming mailbox requests.  In thermal device mailbox responses, this field is always zero.  The applicability of this additional parameter field is handled on a case by case basis for the services supplied by this mailbox"},
#else
{8, 28, 0x0000000000000000, "RW/V", "addr_cntl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW/V", "command", "For incoming requests (where run/busy=1), this field represents the command opcode.  For responses (where run/busy=0), this field represents the response completion code.  A completion code of 0b indicates passing, all other completion codes indicate failure.  For detailed definition of services provided by this mailbox, please see the full mailbox specification."},
#else
{0, 7, 0x0000000000000000, "RW/V", "command", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo870[] = {{"P_CR_THERMAL_MAILBOX_INTERFACE_0_0_0_MCHBAR", "", 0x00007008, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields871[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/L", "lock", "Used to lock P_CR_INTR_LAT_0_0_1_PCI.INTPIN.  BIOS should set this lock bit before passing control to the OS"},
#else
{31, 31, 0x0000000000000000, "RW/L", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 30, 0x0000000000000000, "RO", "reserved", "Reserved"},
#else
{8, 30, 0x0000000000000000, "RO", "reserved", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "irq", "IRQ vector number for the thermal / power device.  This field controls the event vector issues to the IOAPIC.   It must be configured by BIOS for INTA support.  Recommended setting for Broxton is 24 (18h)"},
#else
{0, 7, 0x0000000000000000, "RW", "irq", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo871[] = {{"P_CR_THERMAL_DEVICE_IRQ_0_0_0_MCHBAR", "", 0x0000700C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields872[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "time_window", "Virtual Temperature thermal filter RC time constant.  Virtual temperature readings are run through an RC filter before they are fed into status and interrupt generation.  This filtering allows software smooth control of thermal responses to thermally significant events.  The bits of this field describe parameters for a mathematical equation for time window configuration.\r\n"
"              [p]This field is split into two sub-fields:[/p]\r\n"
"              [list]\r\n"
"              [*] x = bits[6:5]\r\n"
"              [*] y = bits[4:0]\r\n"
"              [/list]\r\n"
"              [p]Time window equation:[/p]\r\n"
"              [b]time_window = PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)[/b]"},
#else
{24, 30, 0x0000000000000000, "RW", "time_window", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "threshold2_temp", "Thermal interrupt threshold temperature in degrees Celsius.  Described in a signed, 2's complement format with the LSB representing 1'C resolution (S8.7.0).  E.g., a reading of 0x28 == 40'C.  This threshold is managed relative to the filtered temperature."},
#else
{16, 23, 0x0000000000000000, "RW", "threshold2_temp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "threshold1_temp", "Thermal interrupt threshold temperature in degrees Celsius.  Described in a signed, 2's complement format with the LSB representing 1'C resolution (S8.7.0).  E.g., a reading of 0x28 == 40'C.  This threshold is managed relative to the filtered temperature."},
#else
{8, 15, 0x0000000000000000, "RW", "threshold1_temp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "critical_thermal_int_enable", "Enable thermal interrupt generation when the processor has detected a critical thermal event that requires immediate servicing.  This event is intended to be an alert indicating thermal control failure and is an early warning of thermal runaway."},
#else
{2, 2, 0x0000000000000000, "RW", "critical_thermal_int_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "threshold2_int_enable", "When set, enables the generation of a thermal interrupt whenever the Thermal Threshold 2 Temperature is crossed.  Interrupts are generated when the threshold is crossed in either direction.  Interrupt destination is programmed in the TMBAR configuration space."},
#else
{1, 1, 0x0000000000000000, "RW", "threshold2_int_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "threshold1_int_enable", "When set, enables the generation of a thermal interrupt whenever the Thermal Threshold 1 Temperature is crossed.  Interrupts are generated when the threshold is crossed in either direction.  Interrupt destination is programmed in the TMBAR configuration space."},
#else
{0, 0, 0x0000000000000000, "RW", "threshold1_int_enable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo872[] = {{"P_CR_PKG_THERM_INTERRUPT_0_0_0_MCHBAR", "", 0x00007010, 6, 0x000000007FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields873[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", "Last resolved ratio for the image processing system. Units are 25MHz multiplied by the ratio. This value is updated dynamically whenever the processing system frequency changes."},
#else
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "max_ratio", "Maximum ratio for the image processing system. Units are 25MHz multiplied by the ratio."},
#else
{16, 23, 0x0000000000000000, "RO/V", "max_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "efficient_ratio", "Firmware-calculated efficient ratio for the image processing system. Units are 25MHz multiplied by the ratio."},
#else
{8, 15, 0x0000000000000000, "RO/V", "efficient_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "min_ratio", "Minimum ratio for the image processing system. Units are 25MHz multiplied by the ratio."},
#else
{0, 7, 0x0000000000000000, "RO/V", "min_ratio", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo873[] = {{"P_CR_PROCESSING_SYSTEM_FREQ_CAPABILITIES_0_0_0_MCHBAR", "", 0x00007014, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields874[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "temperature", "Virtual maximum SOC temperature in degrees Celsius. Caculated as a maximum of all on-die thermal sensor readings and filtered accoring to the time constant described in the PKG_THERM_INTERRUPT register.  Data format is signed, 2's complement with the LSB representing 1'C resolution (S8.7.0)."},
#else
{16, 23, 0x0000000000000000, "RO/V", "temperature", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW/0C/V", "critical_thermal_event_log", "Sticky log bit indicating that the processor has operated out of its thermal specification since the last time software cleared this bit. Set by hardware on a 0 to 1 transition of Critical Thermal Event Status."},
#else
{5, 5, 0x0000000000000000, "RW/0C/V", "critical_thermal_event_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "critical_thermal_event_status", "Status bit indicating that the processor is operating outside of its thermal specification. It is intended as an early warning of thermal runaway in the silicon and shutdown is recommended."},
#else
{4, 4, 0x0000000000000000, "RO/V", "critical_thermal_event_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW/0C/V", "threshold2_log", "Sticky log bit that indicates temperature has crossed the software programmable thermal threshold2 in either falling or rising directions."},
#else
{3, 3, 0x0000000000000000, "RW/0C/V", "threshold2_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO/V", "threshold2_status", "Indicates that the current filtered temperature (bits 23:16 of this register) is greater than or equal to the Threshold2 defined in the PKG_THERM_INTERRUPT configuration register."},
#else
{2, 2, 0x0000000000000000, "RO/V", "threshold2_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/0C/V", "threshold1_log", "Sticky log bit that indicates temperature has crossed the software programmable thermal threshold1 in either falling or rising directions."},
#else
{1, 1, 0x0000000000000000, "RW/0C/V", "threshold1_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "threshold1_status", "Indicates that the current filtered temperature (bits 23:16 of this register) is greater than or equal to the Threshold1 defined in the PKG_THERM_INTERRUPT configuration register."},
#else
{0, 0, 0x0000000000000000, "RO/V", "threshold1_status", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo874[] = {{"P_CR_PKG_THERM_STATUS_0_0_0_MCHBAR", "", 0x0000701C, 7, 0x0000000000FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields875[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", "Reserved"},
#else
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", "This field is updated after each read of Wide I/O DRAM MR4 Device Temperature Status. Update rate is configured by BIOS."},
#else
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo875[] = {{"P_CR_MEM_MR4_TEMPERATURE_DEV0_0_0_0_MCHBAR", "", 0x00007020, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields876[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo876[] = {{"P_CR_MEM_MR4_TEMPERATURE_DEV1_0_0_0_MCHBAR", "", 0x00007024, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields877[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo877[] = {{"P_CR_MEM_MR4_TEMPERATURE_DEV2_0_0_0_MCHBAR", "", 0x00007028, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields878[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/V", "caterr", "Asserted by HW on IERR or MCERR assertion."},
#else
{31, 31, 0x0000000000000000, "RW/V", "caterr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/V", "ierr", "Asserted by HW on IERR assertion."},
#else
{30, 30, 0x0000000000000000, "RW/V", "ierr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW/V", "mcerr", "Asserted by HW on MCERR assertion."},
#else
{29, 29, 0x0000000000000000, "RW/V", "mcerr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "reserved", "Undefined - reserved for future use."},
#else
{0, 7, 0x0000000000000000, "RW", "reserved", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo878[] = {{"P_CR_MCA_ERROR_SRC_0_0_0_MCHBAR", "", 0x0000702C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields879[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RO", "reserved_1", "RESERVED"},
#else
{26, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW/V", "ddr3l_refresh_rate", "[p]This field is to allow platform software to request refresh rate for DDR3L[/p]"},
#else
{25, 25, 0x0000000000000000, "RW/V", "ddr3l_refresh_rate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW/V", "throttle_level_enable", "[p]When set and DRAM_Type is DDR3L, SOC throttles memory traffic to level specified in THRT_LVL\r\n"
"                NOTE: This field is ignored if DRAM_Type is not DDR3L[/p]"},
#else
{24, 24, 0x0000000000000000, "RW/V", "throttle_level_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW/V", "throttle_level", "[p]Throttle level in %BW, in units of 1%.  Default = 0%. Input of 100 or higher is clipped to 100%, \r\n"
"              NOTE: this field is ignored if DRAM_type is not DDR3L[/p]"},
#else
{16, 23, 0x0000000000000000, "RW/V", "throttle_level", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 15, 0x0000000000000000, "RO", "reserved_0", "RESERVED"},
#else
{10, 15, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW/V", "mem_thrt_enable", "When set, memory traffic is throttled if memory MR4 value >= THERM_THRT_THRESHOLD, respectively.  Thermal throttling is achieved by applying memory bandwidth clips in the memory subsystem."},
#else
{9, 9, 0x0000000000000000, "RW/V", "mem_thrt_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW/V", "mem_thrt_cfg", "Configure memory throttling behavior.  Policies are defined as follows:\r\n"
"         [list]\r\n"
"         [*] 0 = Thermal throttling policy uses instanous MR4 status for THERM_THRT_THRESHOLD\r\n"
"         [*] 1 = Thermal throttling policy uses time filtered MR4 status for THERM_THRT_THRESHOLD.  Filtering time constant is configured in the DDR_THERM_INTERRUPT register.\r\n"
"         [/list]"},
#else
{8, 8, 0x0000000000000000, "RW/V", "mem_thrt_cfg", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW/V", "nm_therm_thrt_enable", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RW/V", "nm_therm_thrt_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW/V", "nm_therm_thrt_threshold", "Reserved"},
#else
{4, 6, 0x0000000000000000, "RW/V", "nm_therm_thrt_threshold", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW/V", "fm_therm_thrt_enable", "When set, throttling is activated if LPDDR memory MR4 value is greater than or equal to THERM_THRT_THRESHOLD.  For the standard LPDDR DRAM that is only capable up to Tcasemax of 85C this bit should be set to enable LPDDR throttling to keep DRAM within its Tcasemax spec."},
#else
{3, 3, 0x0000000000000000, "RW/V", "fm_therm_thrt_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW/V", "fm_therm_thrt_threshold", "Configurable threshold of LPDDR memory MR4 value greater than or equal to which thermal throttling is activated.  For the standard LPDDR DRAM that is only capable up to Tcasemax of 85C this field should be configured to avoid DRAM to exceed its Tcasemax spec.\r\n"
"             [list]\r\n"
"             [*] Memory MR4 >= Threshold = Enable thermal throttling\r\n"
"             [*] Memory MR4 < Threshold = Disable thermal throttling\r\n"
"             [/list]\r\n"
"             "},
#else
{0, 2, 0x0000000000000000, "RW/V", "fm_therm_thrt_threshold", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo879[] = {{"P_CR_DDR_THERM_THRT_CTRL_0_0_0_MCHBAR", "", 0x00007030, 11, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields880[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "time_window", "Virtual Temperature thermal filter RC time constant.  Virtual temperature readings are run through an RC filter before they are fed into status and interrupt generation.  This filtering allows software smooth control of thermal responses to thermally significant events.  The bits of this field describe parameters for a mathematical equation for time window configuration.\r\n"
"              [p]This field is split into two sub-fields:[/p]\r\n"
"              [list]\r\n"
"              [*] x = bits[6:5]\r\n"
"              [*] y = bits[4:0]\r\n"
"              [/list]\r\n"
"              [p]Time window equation:[/p]\r\n"
"              [b]time_window = PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)[/b]"},
#else
{24, 30, 0x0000000000000000, "RW", "time_window", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "near_mem_mr4_threshold2_int_enable", "Reserved"},
#else
{15, 15, 0x0000000000000000, "RW", "near_mem_mr4_threshold2_int_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 14, 0x0000000000000000, "RW", "near_mem_mr4_threshold2", "Reserved"},
#else
{12, 14, 0x0000000000000000, "RW", "near_mem_mr4_threshold2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "near_mem_mr4_threshold1_int_enable", "Reserved"},
#else
{11, 11, 0x0000000000000000, "RW", "near_mem_mr4_threshold1_int_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "near_mem_mr4_threshold1", "Reserved"},
#else
{8, 10, 0x0000000000000000, "RW", "near_mem_mr4_threshold1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "far_mem_mr4_threshold2_int_enable", "Enable thermal interrupt generation whenever the virtual maximum memory MR4 has crossed THRESHOLD2.  Interrupts are triggered when the filtered MR4 temperature crosses in both rising and falling directions."},
#else
{7, 7, 0x0000000000000000, "RW", "far_mem_mr4_threshold2_int_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 6, 0x0000000000000000, "RW", "far_mem_mr4_threshold2", "Configurable memory threshold2 value for memory thermal interrupt generation"},
#else
{4, 6, 0x0000000000000000, "RW", "far_mem_mr4_threshold2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "far_mem_mr4_threshold1_int_enable", "Enable thermal interrupt generation whenever the virtual maximum memory MR4 has crossed THRESHOLD1.  Interrupts are triggered when the filtered MR4 temperature crosses in both rising and falling directions."},
#else
{3, 3, 0x0000000000000000, "RW", "far_mem_mr4_threshold1_int_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "far_mem_mr4_threshold1", "Configurable memory threshold1 value for memory thermal interrupt generation"},
#else
{0, 2, 0x0000000000000000, "RW", "far_mem_mr4_threshold1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo880[] = {{"P_CR_DDR_THERM_INTERRUPT_0_0_0_MCHBAR", "", 0x00007034, 9, 0x000000007FFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields881[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{19, 21, 0x0000000000000000, "RO/V", "near_mem_mr4", "Reserved"},
#else
{19, 21, 0x0000000000000000, "RO/V", "near_mem_mr4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000000, "RO/V", "far_mem_mr4", "Virtual maximum memory MR4 reading.  Caculated as a maximum of all LPDDR memory MR4 readingsand filtered accoring to the time constant described in DDR_THERM_INTERRUPT register."},
#else
{16, 18, 0x0000000000000000, "RO/V", "far_mem_mr4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW/0C/V", "near_mem_mr4_threshold2_log", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RW/0C/V", "near_mem_mr4_threshold2_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "near_mem_mr4_threshold2_status", "Reserved"},
#else
{6, 6, 0x0000000000000000, "RO/V", "near_mem_mr4_threshold2_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW/0C/V", "near_mem_mr4_threshold1_log", "Reserved"},
#else
{5, 5, 0x0000000000000000, "RW/0C/V", "near_mem_mr4_threshold1_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "near_mem_mr4_threshold1_status", "Reserved"},
#else
{4, 4, 0x0000000000000000, "RO/V", "near_mem_mr4_threshold1_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW/0C/V", "far_mem_mr4_threshold2_log", "Indicates that the virtual maximum memory MR4 has crossed THRESHOLD2 since the last time this register was cleared.  The bit is set when the threshold is crossed in either direction.  Software may clear this bit."},
#else
{3, 3, 0x0000000000000000, "RW/0C/V", "far_mem_mr4_threshold2_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO/V", "far_mem_mr4_threshold2_status", "Status bit is set when the virtual maximum memory MR4 reading is greater than or equal to THRESHOLD2.  It is cleared when temperature is less than THRESHOLD2"},
#else
{2, 2, 0x0000000000000000, "RO/V", "far_mem_mr4_threshold2_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/0C/V", "far_mem_mr4_threshold1_log", "Indicates that the virtual maximum memory MR4 has crossed THRESHOLD1 since the last time this register was cleared.  The bit is set when the threshold is crossed in either direction.  Software may clear this bit."},
#else
{1, 1, 0x0000000000000000, "RW/0C/V", "far_mem_mr4_threshold1_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "far_mem_mr4_threshold1_status", "Status bit is set when the virtual maximum memory MR4 reading is greater than or equal to THRESHOLD1.  It is cleared when temperature is less than THRESHOLD1"},
#else
{0, 0, 0x0000000000000000, "RO/V", "far_mem_mr4_threshold1_status", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo881[] = {{"P_CR_DDR_THERM_STATUS_0_0_0_MCHBAR", "", 0x00007038, 10, 0x00000000003FFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields882[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "locked", "When set this entire register becomes readonly. This bit will typically be set by BIOS during boot."},
#else
{63, 63, 0x0000000000000000, "RW", "locked", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RSV", "reserved_1", "Reserved"},
#else
{24, 31, 0x0000000000000000, "RSV", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "limit1_time_window_x", "The time window for RAPL is expressed in a format called TAU.  TAU is specified in a mantissa+exponent format.  This format is common across all RAPL interfaces for TAU.\r\n"
"\r\n"
"      The format is specified with a 7 bit number that looks like: \r\n"
"         XXYYYYY   (2 bits of mantissa follwed by 5 exponent)\r\n"
"\r\n"
"      The time window corresponding to this config is calculated as:\r\n"
"         (1+ XXb / 4) * (2^YYYYYb)\r\n"
"\r\n"
"      The value that results from this math species the time window in units that are defined in PACKAGE_POWER_SKU_UNIT.TIME_UNIT MSR.  On every server product we have built, this value has been 976us, which we typically treat as 1ms.\r\n"
"      "},
#else
{22, 23, 0x0000000000000000, "RW", "limit1_time_window_x", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 21, 0x0000000000000000, "RW", "limit1_time_window_y", "The Tau Exponent.  See TIME_WINDOW_X for more information."},
#else
{17, 21, 0x0000000000000000, "RW", "limit1_time_window_y", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RSV", "reserved_0", "Reserved"},
#else
{16, 16, 0x0000000000000000, "RSV", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "limit1_enable", "Power Limit[0] enable bit for DDR domain."},
#else
{15, 15, 0x0000000000000000, "RW", "limit1_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 14, 0x0000000000000000, "RW", "limit1_power", "Power Limit[0] for DDR domain. UnitsWatts Format7.8 Resolution0.125W Range02047.875W."},
#else
{0, 14, 0x0000000000000000, "RW", "limit1_power", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo882[] = {{"P_CR_DDR_RAPL_LIMIT_0_0_0_MCHBAR", "", 0x00007040, 7, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields883[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "joules", "Total Joules of energy consumed by all DIMMs.  Units are proportional to Joules and are defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT."},
#else
{0, 31, 0x0000000000000000, "RO/V", "joules", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo883[] = {{"P_CR_DDR_ENERGY_STATUS_0_0_0_MCHBAR", "", 0x00007048, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields884[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x00000000000058F0, "RW", "duration", "Bandwidth throttle duration counter due to Memory RAPL.  Sum across all channels in PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT units. This data can serve as a proxy for the potential performance impacts of RAPL on memory accesses."},
#else
{0, 31, 0x00000000000058F0, "RW", "duration", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo884[] = {{"P_CR_DDR_RAPL_PERF_STATUS_0_0_0_MCHBAR", "", 0x0000704C, 1, 0x00000000FFFFFFFF, 0x00000000000058F0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields885[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "counts", "Time that any core in the IA domain is performance throttled below OS request and below the base frequency (P1) because of power limits (PL1 or PL2).  Counts in time units defined by PACKAGE_POWER_SKU_UNIT_MSR.TIME_UNIT"},
#else
{0, 31, 0x0000000000000000, "RW", "counts", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo885[] = {{"P_CR_PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR", "", 0x00007050, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields886[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{5, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RW", "priptp", "Performance priority Level for the IA Core (primary) power plane. A higher number implies a higher priority."},
#else
{0, 4, 0x0000000000000000, "RW", "priptp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo886[] = {{"P_CR_PRIMARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR", "", 0x00007054, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields887[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{5, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000010, "RW", "secptp", "Performance priority Level for the Graphics (secondary) power plane. A higher number implies a higher priority."},
#else
{0, 4, 0x0000000000000010, "RW", "secptp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo887[] = {{"P_CR_SECONDARY_PLANE_TURBO_PLCY_0_0_0_MCHBAR", "", 0x00007058, 2, 0x00000000FFFFFFFF, 0x0000000000000010}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields888[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "[p]Contains an accumulated value of the energy consumed in the primary power plane. To find the energy consumed in a given time window, sofwtare should subtract the two energy readings.\r\n"
"                 Software will have to take care of counter wrapping around when it overflows.[/p]\r\n"
"              [p]Units are proportional to Joules exact precsion is defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT[/p]"},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo888[] = {{"P_CR_PRIMARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR", "", 0x0000705C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields889[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "[p]Contains an accumulated value of the energy consumed in the secondary power plane. To find the energy consumed in a given time window, sofwtare should subtract the two energy readings. \r\n"
"                 Software will have to take care of counter wrapping around when it overflows.[/p]\r\n"
"              [p]Units are proportional to Joules exact precsion is defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT[/p]"},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo889[] = {{"P_CR_SECONDARY_PLANE_ENERGY_STATUS_0_0_0_MCHBAR", "", 0x00007060, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields890[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000003, "RW", "resistance_unit", "Used to define the units of resistance for control registers that describe parameters in ohms such as VR_CURRENT_CONFIG.  The actual unit value is calculated by 1mohm / 2^RESISTANCE_UNIT.  The default value of 3 corresponds to 0.125mohm."},
#else
{28, 31, 0x0000000000000003, "RW", "resistance_unit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000003, "RW", "current_unit", "Used to define the units of amps in control registers such as VR_CURRENT_CONFIG.  The actual unit value is calculated by 1A / 2^CURRENT_UNIT.  The default value of 3 corresponds to 0.125A."},
#else
{24, 27, 0x0000000000000003, "RW", "current_unit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RSV", "reserved_2", "Reserved"},
#else
{20, 23, 0x0000000000000000, "RSV", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x000000000000000A, "RW", "time_unit", "Used for to define the time units in registers such as PL1, PL2, PL3 and PL4.   The actual unit value is calculated by 1s / 2^TIME_UNIT.  The default value of 10 corresponds to 0.977ms."},
#else
{16, 19, 0x000000000000000A, "RW", "time_unit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 15, 0x0000000000000000, "RSV", "reserved_1", "Reserved"},
#else
{13, 15, 0x0000000000000000, "RSV", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 12, 0x000000000000000E, "RW", "energy_unit", "Used to define the units of energy reporting registers such as PACKAGE_ENERGY_STATUS.  The actual unit value is calculated by 1 J / 2^ENERGY_UNIT.  The default value of 14 corresponds to ~61uJ per bit."},
#else
{8, 12, 0x000000000000000E, "RW", "energy_unit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RSV", "reserved_0", "Reserved"},
#else
{4, 7, 0x0000000000000000, "RSV", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000008, "RW", "pwr_unit", "Used to define the units of power control registers such as PL1, PL2, PL3 and PL4.   The actual unit value is calculated by 1 W / 2^PWR_UNIT.  The default value of 8 corresponds to 3.9mW per bit."},
#else
{0, 3, 0x0000000000000008, "RW", "pwr_unit", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo890[] = {{"P_CR_PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR", "", 0x00007068, 8, 0x00000000FFFFFFFF, 0x00000000330A0E08}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields891[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "[p]Contains accumulated energy consumed by the entire CPU. This counter will wrap around and keep counting when the counter overflows.[/p]\r\n"
"              [p]Units are proportional to Joules exact precsion is defined by PACKAGE_POWER_SKU_UNIT_MSR.ENERGY_UNIT[/p]"},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo891[] = {{"P_CR_PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR", "", 0x0000706C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields892[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{17, 25, 0x0000000000000000, "RO/V", "rp_state_ratio_slice", "[p]Ratio of the current RP-state, in 16.6Mhz 1xclks. When the graphics engine is in RC6, this field is zeroed out.[/p]\r\n"
"              [p]For BXT the Unslice and Slice run at the same ratio.[/p]"},
#else
{17, 25, 0x0000000000000000, "RO/V", "rp_state_ratio_slice", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 16, 0x0000000000000000, "RO/V", "rp_state_ratio_unslice", "[p]Ratio of the current RP-state, in 16.6Mhz 1xclks. When the graphics engine is in RC6, this field is zeroed out.[/p]\r\n"
"              [p]For BXT the Unslice and Slice run at the same ratio.[/p]"},
#else
{8, 16, 0x0000000000000000, "RO/V", "rp_state_ratio_unslice", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "rp_state_voltage", "RP-State Voltage GT Target Voltage in U1.7 Volts"},
#else
{0, 7, 0x0000000000000000, "RO/V", "rp_state_voltage", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo892[] = {{"P_CR_GT_PERF_STATUS_0_0_0_MCHBAR", "", 0x00007070, 3, 0x0000000003FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields893[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RSV", "reserved_1", "Reserved"},
#else
{31, 31, 0x0000000000000000, "RSV", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW", "tj_max_tcc_offset", "This field allows platform software to configure the temperature at which thermal monitor engages to be lower than the manufacturing configured maximum constraint.  This field is programmed in 1'C units.  E.g., if the default silicon configured maximum temperature is 100'C and this field is configured to 10, then the silicon will engage thermal throttling algorithms at 90'C"},
#else
{24, 30, 0x0000000000000000, "RW", "tj_max_tcc_offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x000000000000005A, "RO/V", "ref_temp", "Tjmax a.k.a. Thermal Monitor activation temperature or Prochot Temperature.  This is the maximum junction temperature at which thermal throttling aka thermal monitor is activated.  This temperature is the maximum temperature at which the silicon is capable of operating at.  All IA core digital thermal sensor readings are reported as a relative nagative offset from this reference temperature, such that a readon of zero implies the cores are running at this temperature."},
#else
{16, 23, 0x000000000000005A, "RO/V", "ref_temp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "fan_temp_target_offset", "Fan Temperature Target Offset a.k.a. TControl indicates the relative offset from the the Thermal Monitor Trip Temperature at which fans should be engaged."},
#else
{8, 15, 0x0000000000000000, "RO/V", "fan_temp_target_offset", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RSV", "reserved_0", "Reserved"},
#else
{0, 7, 0x0000000000000000, "RSV", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo893[] = {{"P_CR_TEMPERATURE_TARGET_0_0_0_MCHBAR", "", 0x00007074, 5, 0x00000000FFFFFFFF, 0x00000000005A0000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields894[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "reserved0", "reserved"},
#else
{16, 31, 0x0000000000000000, "RW", "reserved0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO/V", "pcode_init_done7", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{15, 15, 0x0000000000000000, "RO/V", "pcode_init_done7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO/V", "pcode_init_done6", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{14, 14, 0x0000000000000000, "RO/V", "pcode_init_done6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RO/V", "pcode_init_done5", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{13, 13, 0x0000000000000000, "RO/V", "pcode_init_done5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO/V", "pcode_init_done4", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{12, 12, 0x0000000000000000, "RO/V", "pcode_init_done4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO/V", "pcode_init_done3", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{11, 11, 0x0000000000000000, "RO/V", "pcode_init_done3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO/V", "pcode_init_done2", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{10, 10, 0x0000000000000000, "RO/V", "pcode_init_done2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V", "pcode_init_done1", "Pcode sets this bit when it has completed this stage, BIOS must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{9, 9, 0x0000000000000000, "RO/V", "pcode_init_done1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO/V", "pcode_init_done", "Pcode has completed its actions in response to Stage0 BIOS Reset complete.  Between BIOS Stage0 complete and pcode Stage0 complete, pcode will apply all power savings configurations to PCS and will set up C_STATE_LATENCY control MSR settings for IRTL management."},
#else
{8, 8, 0x0000000000000000, "RO/V", "pcode_init_done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "rst_cpl7", "reset complete"},
#else
{7, 7, 0x0000000000000000, "RW", "rst_cpl7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "rst_cpl6", "BIOS sets this bit when it has completed this stage, Pcode must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{6, 6, 0x0000000000000000, "RW", "rst_cpl6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "rst_cpl5", "BIOS sets this bit when it has completed this stage, Pcode must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{5, 5, 0x0000000000000000, "RW", "rst_cpl5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "rst_cpl4", "BIOS sets this bit when it has completed this stage, Pcode must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{4, 4, 0x0000000000000000, "RW", "rst_cpl4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "rst_cpl3", "BIOS sets this bit when it has completed this stage, Pcode must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{3, 3, 0x0000000000000000, "RW", "rst_cpl3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "rst_cpl2", "BIOS sets this bit when it has completed this stage, Pcode must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{2, 2, 0x0000000000000000, "RW", "rst_cpl2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "rst_cpl1", "BIOS sets this bit when it has completed this stage, Pcode must wait for this bit to be set before proceeding to the next stage.  Stage validity is product-specific and this stage may not be applicable to this product."},
#else
{1, 1, 0x0000000000000000, "RW", "rst_cpl1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rst_cpl", "Set by BIOS to indicate that all power management configurations as part of reset are complete.  This must include Punit patch load done as well as all relevant Punit power management register and mailbox configurations done.  Once this bit is set, Punit will allow normal power management to start.  Before setting this bit, P-states and C-states support is disabled.  BIOS should wait before receiving the Pcode Stage0 reset complete before proceeding with any further steps."},
#else
{0, 0, 0x0000000000000000, "RW", "rst_cpl", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo894[] = {{"P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR", "", 0x00007078, 17, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields895[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/V", "data", "This field contains the data associated with specific commands."},
#else
{0, 31, 0x0000000000000000, "RW/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo895[] = {{"P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR", "", 0x00007080, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields896[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/1S/V", "run_busy", "SW may write to the two mailbox registers only when RUN_BUSY is clear(0). Setting RUN_BUSY to 1 will pend a Fast Path event to Pcode. After setting this bit SW will poll this bit until it is cleared.  PCODE will clear RUN_BUSY after updating the mailbox registers with the result and error code."},
#else
{31, 31, 0x0000000000000000, "RW/1S/V", "run_busy", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 28, 0x0000000000000000, "RW/V", "address", "This field is used to specify an additional parameter to extend the command when needed."},
#else
{8, 28, 0x0000000000000000, "RW/V", "address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW/V", "command", "This field contains the SW request command or the PCODE response code depending on the setting of RUN_BUSY."},
#else
{0, 7, 0x0000000000000000, "RW/V", "command", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo896[] = {{"P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR", "", 0x00007084, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields897[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_freq", "Last resolved ratio for the IA cores. Units are 100MHz multiplied by the ratio. This value is updated dynamically whenever the IA core frequency changes."},
#else
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "max_supported_freq", "Maximum ratio for the IA cores. Units are 100MHz multiplied by the ratio."},
#else
{16, 23, 0x0000000000000000, "RO/V", "max_supported_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "efficient_freq", "Firmware-calculated efficient ratio for the IA cores. Units are 100MHz multiplied by the ratio."},
#else
{8, 15, 0x0000000000000000, "RO/V", "efficient_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "min_supported_freq", "Minimum supported ratio for the IA cores. Units are 100MHz multiplied by the ratio."},
#else
{0, 7, 0x0000000000000000, "RO/V", "min_supported_freq", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo897[] = {{"P_CR_CORE_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR", "", 0x00007088, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields898[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_freq", "Last resolved ratio for the integrated graphics engine. Units are 50MHz multiplied by the ratio. This value is updated dynamically whenever the graphics engine frequency changes."},
#else
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "max_supported_freq", "Maximum supported ratio for the integrated graphics engine. Units are 50MHz multiplied by the ratio."},
#else
{16, 23, 0x0000000000000000, "RO/V", "max_supported_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "efficient_freq", "Firmware-calculated efficient ratio for the integrated graphics engine. Units are 50MHz multiplied by the ratio."},
#else
{8, 15, 0x0000000000000000, "RO/V", "efficient_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "min_supported_freq", "Minimum supported ratio for the integrated graphics engine. Units are 50MHz multiplied by the ratio."},
#else
{0, 7, 0x0000000000000000, "RO/V", "min_supported_freq", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo898[] = {{"P_CR_GRAPHICS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR", "", 0x0000708C, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields899[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", "Last resolved System Agent ratio, in units of 16.666MHz."},
#else
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "reserved_2", "Reserved"},
#else
{16, 23, 0x0000000000000000, "RO/V", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "reserved_1", "Reserved"},
#else
{8, 15, 0x0000000000000000, "RO/V", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "reserved_0", "Reserved"},
#else
{0, 7, 0x0000000000000000, "RO/V", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo899[] = {{"P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR", "", 0x00007090, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields900[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", "This field reports out the LPDDR memory frequency in integer multiple of 133.33MHz.  This register reflects what BIOS has programmed as the default LPDDR frequency in products that do not support run-time memory frequency control.  For products supporting run-time memory frequency control, this field describes the last resolved frequency."},
#else
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "reserved_2", "Reserved"},
#else
{16, 23, 0x0000000000000000, "RO/V", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "reserved_1", "Reserved"},
#else
{8, 15, 0x0000000000000000, "RO/V", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "reserved_0", "Reserved"},
#else
{0, 7, 0x0000000000000000, "RO/V", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo900[] = {{"P_CR_FAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR", "", 0x00007094, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields901[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", "This field reports out the Wide I/O near memory frequency in integer multiple of 133.33MHz.  This register reflects what BIOS has programmed as the default Wide I/O near memory frequency in products that do not support run-time memory frequency control.  For products supporting run-time memory frequency control, this field describes the last resolved frequency."},
#else
{24, 31, 0x0000000000000000, "RO/V", "last_resolved_ratio", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "reserved_2", "Reserved"},
#else
{16, 23, 0x0000000000000000, "RO/V", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "reserved_1", "Reserved"},
#else
{8, 15, 0x0000000000000000, "RO/V", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "reserved_0", "Reserved"},
#else
{0, 7, 0x0000000000000000, "RO/V", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo901[] = {{"P_CR_NEAR_MEMORY_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR", "", 0x00007098, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields902[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{55, 63, 0x0000000000000000, "RO", "reserved_3", "Reserved"},
#else
{55, 63, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 54, 0x0000000000000012, "RW", "pkg_max_win", "The maximal time window allowed to be programmed for RAPL PL1 and PL2 controls for the SKU.  Higher values will be clamped to this value.                [p]The bits of this field describe parameters for a mathematical equation for time window configuration.  This field is split into two sub-fields:[/p]\r\n"
"              [list]\r\n"
"              [*] x = bits[6:5]\r\n"
"              [*] y = bits[4:0]\r\n"
"              [/list]\r\n"
"              [p]Time window equation:[/p]\r\n"
"              [b]time_window = PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)[/b]"},
#else
{48, 54, 0x0000000000000012, "RW", "pkg_max_win", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "reserved_2", "Reserved"},
#else
{47, 47, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 46, 0x0000000000000240, "RW", "pkg_max_pwr", "The maximal package power setting allowed for the SKU. Higher values will be clamped to this value. The maximum setting is typical not guaranteed.  The default value for this field is determined by fuses.  The units for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT]."},
#else
{32, 46, 0x0000000000000240, "RW", "pkg_max_pwr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved"},
#else
{31, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 30, 0x0000000000000060, "RW", "pkg_min_pwr", "The minimal package power setting allowed for the SKU. Lower values may not be achievable by run-time RAPL PL1 and PL2 control algorithms."},
#else
{16, 30, 0x0000000000000060, "RW", "pkg_min_pwr", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{15, 15, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 14, 0x0000000000000118, "RW", "pkg_tdp", "The TDP package power setting allowed for the SKU. The TDP setting is typical not guaranteed.  The default value for this field is determined by fuses.  The units for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT]."},
#else
{0, 14, 0x0000000000000118, "RW", "pkg_tdp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo902[] = {{"P_CR_PACKAGE_POWER_SKU_0_0_0_MCHBAR", "", 0x000070A0, 8, 0xFFFFFFFFFFFFFFFF, 0x0012024000600118}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields903[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW/L", "pkg_pwr_lim_lock", "When set all settings in this register are locked and are treated as Read Only.  This lock control is persistent until the next reset.  This bit will typically set by BIOS during boot time or resume from Sx."},
#else
{63, 63, 0x0000000000000000, "RW/L", "pkg_pwr_lim_lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 62, 0x0000000000000000, "RSV", "reserved_1", "Reserved"},
#else
{56, 62, 0x0000000000000000, "RSV", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 55, 0x0000000000000000, "RW/L", "pkg_pwr_lim_2_time", "[p]Time window for Power Limit 1 (PL2).  This describes the control window of the power limit.  This time window is described in an RC time constant format, which means that if 1s is programmed, the power limit constraint really applies at more like 5s.  The maximal time window is bounded by PACKAGE_POWER_SKU_MSR.PKG_MAX_WIN. Thre is no constraint on the minimum programmable time window, however at very short time windows the control algorithms may not be effective.[/p]\r\n"
"              [p]The bits of this field describe parameters for a mathematical equation for time window configuration.  This field is split into two sub-fields:[/p]\r\n"
"              [list]\r\n"
"              [*] x = bits[6:5]\r\n"
"              [*] y = bits[4:0]\r\n"
"              [/list]\r\n"
"              [p]Time window equation:[/p]\r\n"
"              [b]time_window = PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)[/b]"},
#else
{49, 55, 0x0000000000000000, "RW/L", "pkg_pwr_lim_2_time", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW/L", "pkg_clmp_lim_2", "Clamp mode control for PL2.\r\n"
"              [list]\r\n"
"              [*] 0 = PL2 power control is prevented from forcing P-states below the base frequency / P1 for any domain in the SOC.\r\n"
"              [*] 1 = PL2 power control will take all actions necessary to meet the power target, even if that involves running at clock frequencies below the base frequency / P1 level.\r\n"
"              [/list]\r\n"
"              In order to ensure proper SOC cooling, it is generally recommended that the clamp mode is always enabled."},
#else
{48, 48, 0x0000000000000000, "RW/L", "pkg_clmp_lim_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RW/L", "pkg_pwr_lim_2_en", "Enable for Power Limit 2 (PL2).  Setting this bit activates the power limit and time window defined for PL2."},
#else
{47, 47, 0x0000000000000000, "RW/L", "pkg_pwr_lim_2_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 46, 0x0000000000000000, "RW/L", "pkg_pwr_lim_2", "Sets the average power usage limit of the package domain corresponding to the PL2 time window. The power units of this field are specified by the PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT.  This power limit must be configured by software before it will engage.  The PL2 limit is most commonly associated with long time windows (1s and longer), although there are no explicit constraints on what software configures."},
#else
{32, 46, 0x0000000000000000, "RW/L", "pkg_pwr_lim_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RSV", "reserved_0", "Reserved"},
#else
{24, 31, 0x0000000000000000, "RSV", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 23, 0x0000000000000000, "RW/L", "pkg_pwr_lim_1_time", "[p]Time window for Power Limit 1 (PL1).  This describes the control window of the power limit.  This time window is described in an RC time constant format, which means that if 1s is programmed, the power limit constraint really applies at more like 5s.  The maximal time window is bounded by PACKAGE_POWER_SKU_MSR.PKG_MAX_WIN. Thre is no constraint on the minimum programmable time window, however at very short time windows the control algorithms may not be effective.[/p]\r\n"
"              [p]The bits of this field describe parameters for a mathematical equation for time window configuration.  This field is split into two sub-fields:[/p]\r\n"
"              [list]\r\n"
"              [*] x = bits[6:5]\r\n"
"              [*] y = bits[4:0]\r\n"
"              [/list]\r\n"
"              [p]Time window equation:[/p]\r\n"
"              [b]time_window = PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)[/b]"},
#else
{17, 23, 0x0000000000000000, "RW/L", "pkg_pwr_lim_1_time", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW/L", "pkg_clmp_lim_1", "Clamp mode control for PL1.\r\n"
"              [list]\r\n"
"              [*] 0 = PL1 power control is prevented from forcing P-states below the base frequency / P1 for any domain in the SOC.\r\n"
"              [*] 1 = PL1 power control will take all actions necessary to meet the power target, even if that involves running at clock frequencies below the base frequency / P1 level.\r\n"
"              [/list]\r\n"
"              In order to ensure proper SOC cooling, it is generally recommended that the clamp mode is always enabled."},
#else
{16, 16, 0x0000000000000000, "RW/L", "pkg_clmp_lim_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW/L", "pkg_pwr_lim_1_en", "Enable for Power Limit 1 (PL1).  Setting this bit activates the power limit and time window defined for PL1."},
#else
{15, 15, 0x0000000000000000, "RW/L", "pkg_pwr_lim_1_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 14, 0x0000000000000000, "RW/L", "pkg_pwr_lim_1", "Sets the average power usage limit of the package domain corresponding to the PL1 time window. The power units of this field are specified by the PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT.  This power limit must be configured by software before it will engage.  The PL1 limit is most commonly associated with long time windows (1s and longer), although there are no explicit constraints on what software configures."},
#else
{0, 14, 0x0000000000000000, "RW/L", "pkg_pwr_lim_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo903[] = {{"P_CR_PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR", "", 0x000070A8, 11, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields904[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW/0C/V", "qos_log", "Logged indication that frequency was clamped below the software-defined quality-of-service floor. This bit is set by firmware, and is clearable by software."},
#else
{31, 31, 0x0000000000000000, "RW/0C/V", "qos_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW/0C/V", "max_efficiency_freq_log", "Logged indication that frequency was clamped below the firmware-calculated maximum efficiency frequency. This bit is set by firmware, and is clearable by software."},
#else
{30, 30, 0x0000000000000000, "RW/0C/V", "max_efficiency_freq_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW/0C/V", "mct_log", "Logged indication that frequency was clamped due to ratio change transition attenuation. This bit is set by firmware, and is clearable by software."},
#else
{29, 29, 0x0000000000000000, "RW/0C/V", "mct_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW/0C/V", "edp_log", "Logged indication that frequency was clamped due to the package-level Electrical Design Point constraint. This bit is set by firmware, and is clearable by software."},
#else
{28, 28, 0x0000000000000000, "RW/0C/V", "edp_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW/0C/V", "multi_core_turbo_log", "Logged indication that frequency was clamped due to effective multi-core turbo constraints. This bit is set by firmware, and is clearable by software."},
#else
{27, 27, 0x0000000000000000, "RW/0C/V", "multi_core_turbo_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW/0C/V", "vr_thermalert_log", "Logged indication that frequency was clamped due to a voltage regulator thermal excursion. This bit is set by firmware, and is clearable by software."},
#else
{26, 26, 0x0000000000000000, "RW/0C/V", "vr_thermalert_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW/0C/V", "ia_utilization_log", "Logged indication that frequency was clamped due to the autonomous utilization-based P-state control algorithm. This bit is set by firmware, and is clearable by software."},
#else
{25, 25, 0x0000000000000000, "RW/0C/V", "ia_utilization_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW/0C/V", "dev3_log", "Logged indication that frequency was clamped due to a Device 3 driver override. This bit is set by firmware, and is clearable by software."},
#else
{24, 24, 0x0000000000000000, "RW/0C/V", "dev3_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW/0C/V", "dev2_log", "Logged indication that frequency was clamped due to a Device 2 driver override. This bit is set by firmware, and is clearable by software."},
#else
{23, 23, 0x0000000000000000, "RW/0C/V", "dev2_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW/0C/V", "spare6_log", "Spare log bit. This bit is set by firmware, and is clearable by software."},
#else
{22, 22, 0x0000000000000000, "RW/0C/V", "spare6_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW/0C/V", "spare5_log", "Spare log bit. This bit is set by firmware, and is clearable by software."},
#else
{21, 21, 0x0000000000000000, "RW/0C/V", "spare5_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RW/0C/V", "spare4_log", "Spare log bit. This bit is set by firmware, and is clearable by software."},
#else
{20, 20, 0x0000000000000000, "RW/0C/V", "spare4_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW/0C/V", "pl2_log", "Logged indication that frequency was clamped due to a package-level PL2 excursion. This bit is set by firmware, and is clearable by software."},
#else
{19, 19, 0x0000000000000000, "RW/0C/V", "pl2_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW/0C/V", "pl1_log", "Logged indication that frequency was clamped due to a package-level PL1 excursion. This bit is set by firmware, and is clearable by software."},
#else
{18, 18, 0x0000000000000000, "RW/0C/V", "pl1_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW/0C/V", "thermal_log", "Logged indication that frequency was clamped due to a thermal excursion. This bit is set by firmware, and is clearable by software."},
#else
{17, 17, 0x0000000000000000, "RW/0C/V", "thermal_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW/0C/V", "prochot_log", "Logged indication that frequency was clamped due to PROCHOT assertion. This bit is set by firmware, and is clearable by software."},
#else
{16, 16, 0x0000000000000000, "RW/0C/V", "prochot_log", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO/V", "qos_status", "Frequency is limited below the operating system or driver Quality-of-Service floor."},
#else
{15, 15, 0x0000000000000000, "RO/V", "qos_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO/V", "max_efficiency_freq_status", "Frequency is limited below the maximum efficiency frequency."},
#else
{14, 14, 0x0000000000000000, "RO/V", "max_efficiency_freq_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RO/V", "mct_status", "Frequency is limited due to ratio change transition attenuation (MCT, prevents frequent ratio changes due to core C-state entry/exit)."},
#else
{13, 13, 0x0000000000000000, "RO/V", "mct_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO/V", "edp_status", "Frequency is limited due to a package-level EDP constraint."},
#else
{12, 12, 0x0000000000000000, "RO/V", "edp_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO/V", "multi_core_turbo_status", "Frequency is limited due to effective multi-core turbo constraints."},
#else
{11, 11, 0x0000000000000000, "RO/V", "multi_core_turbo_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO/V", "vr_thermalert_status", "Frequency is limited due to a VR thermal excursion."},
#else
{10, 10, 0x0000000000000000, "RO/V", "vr_thermalert_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO/V", "ia_utilization_status", "Frequency is limited due to autonomous utilization-based P-state control."},
#else
{9, 9, 0x0000000000000000, "RO/V", "ia_utilization_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO/V", "dev3_status", "Frequency is limited due to Dev3 driver override."},
#else
{8, 8, 0x0000000000000000, "RO/V", "dev3_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO/V", "dev2_status", "Frequency is limited due to Dev2 driver override."},
#else
{7, 7, 0x0000000000000000, "RO/V", "dev2_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO/V", "spare6_status", "Spare status bit."},
#else
{6, 6, 0x0000000000000000, "RO/V", "spare6_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO/V", "spare5_status", "Spare status bit."},
#else
{5, 5, 0x0000000000000000, "RO/V", "spare5_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO/V", "spare4_status", "Spare status bit."},
#else
{4, 4, 0x0000000000000000, "RO/V", "spare4_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO/V", "pl2_status", "Frequency is limited due to a package-level PL2 excursion."},
#else
{3, 3, 0x0000000000000000, "RO/V", "pl2_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO/V", "pl1_status", "Frequency is limited due to a package-level PL1 excursion."},
#else
{2, 2, 0x0000000000000000, "RO/V", "pl1_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO/V", "thermal_status", "Frequency is limited due to thermal excursion."},
#else
{1, 1, 0x0000000000000000, "RO/V", "thermal_status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO/V", "prochot_status", "Frequency is limited due to external PROCHOT assertion."},
#else
{0, 0, 0x0000000000000000, "RO/V", "prochot_status", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo904[] = {{"P_CR_IA_PERF_LIMIT_REASONS_0_0_0_MCHBAR", "", 0x000070B0, 32, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields905[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "This counter measures time that any core is active in the C0 state.  This counter counts at the crystal clock frequency divided by 16."},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo905[] = {{"P_CR_TELEM_IA_C0_RESIDENCY_0_0_0_MCHBAR", "", 0x000070C0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields906[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "This counter measures time that graphics is active in the C0 state.  This counter counts at the crystal clock frequency divided by 16."},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo906[] = {{"P_CR_TELEM_GT_C0_RESIDENCY_0_0_0_MCHBAR", "", 0x000070C4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields907[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "This counter measures time that I-unit processing system is active in the C0 state.  This counter counts at the crystal clock frequency divided by 16."},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo907[] = {{"P_CR_TELEM_IUNIT_C0_RESIDENCY_0_0_0_MCHBAR", "", 0x000070C8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields908[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "Residency data"},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo908[] = {{"P_CR_TELEM_IA_FREQ_ACCUMULATOR_0_0_0_MCHBAR", "", 0x000070CC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields909[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "This counter integrates the current clock ratio of the domain at the same rate as the corresponding C0 residency counter"},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo909[] = {{"P_CR_TELEM_GT_FREQ_ACCUMULATOR_0_0_0_MCHBAR", "", 0x000070D0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields910[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "This counter integrates the current clock ratio of the domain at the same rate as the corresponding C0 residency counter"},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo910[] = {{"P_CR_TELEM_IUNIT_FREQ_ACCUMULATOR_0_0_0_MCHBAR", "", 0x000070D4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields911[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000000000000000, "RO/V", "data", "This counter measures the total time spent with near memory active, as measured by any rank being in the active or active idle state.  The inverse of this counter indicates the total time spent with all near memory in the self-refresh state.  This counter counts at the crystal clock frequency divided by 16."},
#else
{0, 63, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo911[] = {{"P_CR_TELEM_NEAR_MEMORY_ACTIVE_0_0_0_MCHBAR", "", 0x000070E0, 1, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields912[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000000000000000, "RO/V", "data", "This counter measures the total time spent with memory active, as measured by any rank being in the active or active idle state.  The inverse of this counter indicates the total time spent with all memory in the self-refresh state.  This counter counts at the crystal clock frequency divided by 16."},
#else
{0, 63, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo912[] = {{"P_CR_TELEM_FAR_MEMORY_ACTIVE_0_0_0_MCHBAR", "", 0x000070E8, 1, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields913[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RW", "rsvd", "reserved"},
#else
{26, 31, 0x0000000000000000, "RW", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 25, 0x0000000000000000, "RW", "gbe_ports", "Snapshot of the number of GBE lanes for power meter."},
#else
{24, 25, 0x0000000000000000, "RW", "gbe_ports", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "pcie_lanes", "Snapshot of the number of PCIE lanes for power meter."},
#else
{16, 23, 0x0000000000000000, "RW", "pcie_lanes", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "sata_lanes", "Snapshot of the number of SATA lanes for power meter."},
#else
{8, 15, 0x0000000000000000, "RW", "sata_lanes", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "usb3_lanes", "Snapshot of the number of USB3 lanes for power meter."},
#else
{4, 7, 0x0000000000000000, "RW", "usb3_lanes", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000000, "RW", "usb2_lanes", "Snapshot of the number of USB2 lanes for power meter."},
#else
{0, 3, 0x0000000000000000, "RW", "usb2_lanes", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo913[] = {{"P_CR_SOUTH_IO_PORT_STATUS3_0_0_0_MCHBAR", "", 0x0000711C, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields914[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RO/V", "sa_temperature", "System agent domain max temperature in degrees C.  Reported in a signed, 2's complement format with the LSB representing 1'C resolution (S8.7.0).  Raw, unfiltered"},
#else
{24, 31, 0x0000000000000000, "RO/V", "sa_temperature", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO/V", "isp_temperature", "Camera domain max temperature in degrees C.  Reported in a signed, 2's complement format with the LSB representing 1'C resolution (S8.7.0).  Raw, unfiltered"},
#else
{16, 23, 0x0000000000000000, "RO/V", "isp_temperature", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RO/V", "gt_temperature", "Graphics domain max temperature in degrees C.  Reported in a signed, 2's complement format with the LSB representing 1'C resolution (S8.7.0).  Raw, unfiltered"},
#else
{8, 15, 0x0000000000000000, "RO/V", "gt_temperature", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO/V", "ia_temperature", "Virtual max temperature of all IA cores in degrees C.  Reported in a signed, 2's complement format with the LSB representing 1'C resolution (S8.7.0).  Raw, unfiltered"},
#else
{0, 7, 0x0000000000000000, "RO/V", "ia_temperature", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo914[] = {{"P_CR_PACKAGE_TEMPERATURES_0_0_0_MCHBAR", "", 0x000070F4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields915[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "enable", "When set, it enables run-time thermal limit control to the THERMAL_LIMIT_TEMP described in this register."},
#else
{8, 8, 0x0000000000000000, "RW", "enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "thermal_limit_temp", "Maximum SOC temperature allowed.  Described in a signed, 2's complement format with the least significant bit representing 1'C resolution (S8.7.0).  If the setting is higher than the processor's factory configured maximum temperature as described in the TEMPERATURE_TARGET MSR, this field is ignored.  This field may be updated at any time."},
#else
{0, 7, 0x0000000000000000, "RW", "thermal_limit_temp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo915[] = {{"P_CR_THERMAL_LIMIT_CONTROL_0_0_0_MCHBAR", "", 0x00007104, 2, 0x00000000000001FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields916[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "num_nm_ch", "Reserved"},
#else
{30, 31, 0x0000000000000000, "RW", "num_nm_ch", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RW", "wio_freq", "Reserved"},
#else
{24, 29, 0x0000000000000000, "RW", "wio_freq", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 23, 0x0000000000000000, "RW", "lp4_freq_high", "This field indicates maximum LPDDR4 frequency that SOC supports, in integer multiple of 133.33MHz.  A value of zero indicates LPDDR4 is not supported."},
#else
{18, 23, 0x0000000000000000, "RW", "lp4_freq_high", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 17, 0x0000000000000000, "RW", "lp4_freq_low", "This field indicates maximum LPDDR4 frequency supported at the minimum voltage level, in integer multiple of 133.33MHz.  If this frequency is the same as 'Max' frequency, it indicates there is no voltage scaling.  A value of zero indicates LPDDR4 is not supported."},
#else
{12, 17, 0x0000000000000000, "RW", "lp4_freq_low", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000000, "RW", "lp3_freq_high", "This field indicates maximum LPDDR3 frequency that SOC supports, in integer multiple of 133.33MHz.  A value of zero indicates LPDDR3 is not supported."},
#else
{6, 11, 0x0000000000000000, "RW", "lp3_freq_high", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "lp3_freq_low", "This field indicates maximum LPDDR3 frequency supported at the minimum voltage level, in integer multiple of 133.33MHz.  If this frequency is the same as 'Max' frequency, it indicates there is no voltage scaling.  A value of zero indicates LPDDR3 is not supported."},
#else
{0, 5, 0x0000000000000000, "RW", "lp3_freq_low", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo916[] = {{"P_CR_MEMSS_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR", "", 0x00007108, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields917[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "run_busy", "[p]This bit indicates that the BIOS request is pending for P-unit firmware processing.  BIOS sets this bit together with command details defined in the lower bits of this register.  Firmware may only clear this bit after the BIOS request has been observed and completed.[p]\r\n"
"              [list]\r\n"
"              [*] 0 = The MC BIOS reset mailbox is idle or the last request has been completed.  Software may initiate new requests.\r\n"
"              [*] 1 = The MC BIOS reset mailbox is busy. It is still handling a request.  Writes to the mailbox are not allowed at this time.\r\n"
"              [/list]"},
#else
{31, 31, 0x0000000000000000, "RW", "run_busy", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 30, 0x0000000000000000, "RW", "reserved_2", "reserved"},
#else
{27, 30, 0x0000000000000000, "RW", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "dram_type", "BIOS programs DRAM type filed:\r\n"
"              [list]\r\n"
"              [*] 001b = LPDDR3 \r\n"
"              [*] 010b = LPDDR4\r\n"
"              [*] 100b = DDR3L\r\n"
"              [*] else = reserved\r\n"
"              [/list]"},
#else
{24, 26, 0x0000000000000000, "RW", "dram_type", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RW", "reserved_1", "reserved"},
#else
{20, 23, 0x0000000000000000, "RW", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RW", "mem_init_done", "BIOS programs this bit after memory subsystem is fully configured, including security locking configuration completed"},
#else
{19, 19, 0x0000000000000000, "RW", "mem_init_done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "cpgc_mode_complete", "BIOS programs this bit after the memory train/init flow is complete.  This initiates P-unit firmware execution of memory and D-unit clock configuration settings for normal operation"},
#else
{18, 18, 0x0000000000000000, "RW", "cpgc_mode_complete", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "dunit_reset_complete", "Punit programs this bit after memory subsystem IPs are powered and corresponding reset flows are complete.  At this point, those blocks are ready for executing the memory training flow, including intialization to support CPGC mode.  BIOS can talk to Dunit after this."},
#else
{17, 17, 0x0000000000000000, "RW", "dunit_reset_complete", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "phy_config_complete", "BIOS programs this bit indicating PHY initial configuration is complete and all DDR PHY PLLs are locked. Upon observation of this flag, P-unit firmware will initiate the power-up sequence of memory subsystem related IPs"},
#else
{16, 16, 0x0000000000000000, "RW", "phy_config_complete", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW", "fm_ch3_active", "BIOS writes this value to indicate a DDR memory channel has DRAM devices active to allow the channel to have active memory traffic.  Note, by default, a channel is not active and BIOS needs to explicitly program a value of 1 to indicate that the channel is active. If a channel is fused off on a particular SOC, BIOS input is ignored:\r\n"
"              [list]\r\n"
"              [*] 0 = channel not active\r\n"
"              [*] 1 = channel active\r\n"
"              [/list]"},
#else
{15, 15, 0x0000000000000000, "RW", "fm_ch3_active", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RW", "fm_ch2_active", "BIOS writes this value to indicate a DDR memory channel has DRAM devices active to allow the channel to have active memory traffic.  Note, by default, a channel is not active and BIOS needs to explicitly program a value of 1 to indicate that the channel is active. If a channel is fused off on a particular SOC, BIOS input is ignored:\r\n"
"              [list]\r\n"
"              [*] 0 = channel not active\r\n"
"              [*] 1 = channel active\r\n"
"              [/list]"},
#else
{14, 14, 0x0000000000000000, "RW", "fm_ch2_active", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "fm_ch1_active", "BIOS writes this value to indicate a DDR memory channel has DRAM devices active to allow the channel to have active memory traffic.  Note, by default, a channel is not active and BIOS needs to explicitly program a value of 1 to indicate that the channel is active. If a channel is fused off on a particular SOC, BIOS input is ignored:\r\n"
"              [list]\r\n"
"              [*] 0 = channel not active\r\n"
"              [*] 1 = channel active\r\n"
"              [/list]"},
#else
{13, 13, 0x0000000000000000, "RW", "fm_ch1_active", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "fm_ch0_active", "BIOS writes this value to indicate a DDR memory channel has DRAM devices active to allow the channel to have active memory traffic.  Note, by default, a channel is not active and BIOS needs to explicitly program a value of 1 to indicate that the channel is active. If a channel is fused off on a particular SOC, BIOS input is ignored:\r\n"
"              [list]\r\n"
"              [*] 0 = channel not active\r\n"
"              [*] 1 = channel active\r\n"
"              [/list]"},
#else
{12, 12, 0x0000000000000000, "RW", "fm_ch0_active", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RW", "wio_only", "Reserved"},
#else
{11, 11, 0x0000000000000000, "RW", "wio_only", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "reserved_0", "reserved"},
#else
{10, 10, 0x0000000000000000, "RW", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "req_type_special", "reserved"},
#else
{9, 9, 0x0000000000000000, "RW", "req_type_special", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 8, 0x0000000000000000, "RW", "req_type", "This field is used to configure reset hints to the P-unit firmware.  Encodings include:\r\n"
"              [list]\r\n"
"              [*] 1xxb = Memory is in self-refresh, manual self-refresh exit is required\r\n"
"              [*] 0xxb = Memory is not in self-refresh or DRAM contents do not need to be preserved.\r\n"
"              [/list]"},
#else
{6, 8, 0x0000000000000000, "RW", "req_type", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "req_data", "[p]BIOS programs this field to request DDR frequency in integer\r\n"
"              multiple of 133.33MHz.  BIOS reads MEMSS_FREQUENCY_CAPABILITIES register(s) to\r\n"
"              discover maximum SOC supported capabilities.  And BIOS is expected to request\r\n"
"              only legal DDR frequencies that are equal or lower than the maximum SOC\r\n"
"              supported capabilities.[/p]"},
#else
{0, 5, 0x0000000000000000, "RW", "req_data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo917[] = {{"P_CR_MC_BIOS_REQ_0_0_0_MCHBAR", "", 0x00007114, 17, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields918[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{25, 31, 0x0000000000000000, "RW", "reserved_2", "reserved"},
#else
{25, 31, 0x0000000000000000, "RW", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "ddr_config_limitation", "Describe the DDR configuration limitation of this particular SOC:\r\n"
"             [list]\r\n"
"             [*] 0 = no DDR configuration limitation\r\n"
"             [*] 1 = DDR configuration is limited to1ch x 64-bit DDR3L, or 2ch x32 LPDDR3 or LPDDR4\r\n"
"             [/list]"},
#else
{24, 24, 0x0000000000000000, "RW", "ddr_config_limitation", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 23, 0x0000000000000000, "RW", "ddr4_freq_high", "This field indicates maximum DDR4 frequency that SOC supports, in integer multiple of 133.33MHz. A value of zero indicates DDR4 is not supported"},
#else
{18, 23, 0x0000000000000000, "RW", "ddr4_freq_high", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 17, 0x0000000000000000, "RW", "ddr4_freq_low", "This field indicates maximum DDR4 frequency supported at the minimum voltage level, in integer multiple of 133.33MHz. If this frequency is the same as Max frequency, it indicates there is no voltage scaling. A value of zero indicates DDR4 is not supported "},
#else
{12, 17, 0x0000000000000000, "RW", "ddr4_freq_low", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 11, 0x0000000000000000, "RW", "ddr3l_freq_high", "This field indicates maximum DDR3L frequency that SOC supports, in integer multiple of 133.33MHz.  A value of zero indicates DDR3L is not supported."},
#else
{6, 11, 0x0000000000000000, "RW", "ddr3l_freq_high", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RW", "ddr3l_freq_low", "This field indicates maximum DDR3L frequency supported at the minimum voltage level, in integer multiple of 133.33MHz.  If this frequency is the same as Max frequency, it indicates there is no voltage scaling.  A value of zero indicates LPDDR4 is not supported."},
#else
{0, 5, 0x0000000000000000, "RW", "ddr3l_freq_low", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo918[] = {{"P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR", "", 0x00007118, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields919[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "data", "Accumulated cycles GT has been in RC0."},
#else
{0, 31, 0x0000000000000000, "RO/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo919[] = {{"P_CR_PP1_C0_CORE_CLOCK_0_0_0_MCHBAR", "", 0x00007160, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields920[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "core3_exists", "Indication of core physical presence"},
#else
{3, 3, 0x0000000000000000, "RW", "core3_exists", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "core2_exists", "Indication of core physical presence"},
#else
{2, 2, 0x0000000000000000, "RW", "core2_exists", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "core1_exists", "Indication of core physical presence"},
#else
{1, 1, 0x0000000000000000, "RW", "core1_exists", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "core0_exists", "Indication of core physical presence"},
#else
{0, 0, 0x0000000000000000, "RW", "core0_exists", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo920[] = {{"P_CR_CORE_EXISTS_VECTOR_0_0_0_MCHBAR", "", 0x00007164, 4, 0x000000000000000F, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields921[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "core3_disable_mask", "core3 disable mask"},
#else
{3, 3, 0x0000000000000000, "RW", "core3_disable_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "core2_disable_mask", "core2 disable mask"},
#else
{2, 2, 0x0000000000000000, "RW", "core2_disable_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "core1_disable_mask", "core1 disable mask"},
#else
{1, 1, 0x0000000000000000, "RW", "core1_disable_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "core0_disable_mask", "core0 disable mask"},
#else
{0, 0, 0x0000000000000000, "RW", "core0_disable_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo921[] = {{"P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR", "", 0x00007168, 4, 0x000000000000000F, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields922[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW/L", "lock", "Write a 1b to lock this register until next reset.  Once locked, no further updates may be written to any bits in the register."},
#else
{63, 63, 0x0000000000000000, "RW/L", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RW/L", "pl4_enable", "[list]\r\n"
"              [*]0 = disabled\r\n"
"              [*]1 = enabled\r\n"
"              [/list]"},
#else
{47, 47, 0x0000000000000000, "RW/L", "pl4_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 46, 0x0000000000000000, "RW/L", "pmax", "Power Limit 'PL4' or Pmax power limit in the units as described PACAKGE_POWER_SKU_UNIT MSR.  The SOC guarantees it will never exceed this power limit even for very short time windows."},
#else
{32, 46, 0x0000000000000000, "RW/L", "pmax", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 30, 0x0000000000000000, "RW/L", "duty_cycle", "Power limit excursion duty cycle control for PL3, describing what percentage of time it is allowed for the SOC to exceed the programmed PL3 power limit.  0% implies excursions are not supported ever and 100% implies excursions are always allowed (effectively disabling the feature).  Units are in percentage(%).  E.g., to allow for 20% excursion time and 80% PL3 power limit clamp time, program a value of 14h.  Values greater than 100 (64h) are clipped to 100%."},
#else
{24, 30, 0x0000000000000000, "RW/L", "duty_cycle", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 23, 0x0000000000000000, "RW/L", "time_window", "Duration over which duty cycle control will be maintained.  The bits of this field describe parameters for a mathematical equation for time window configuration.   This time window is strictly adhered to, if the window described is 40ms, then silicon guarantees no excursions to the programmed duty cycle within a rolling 40ms window.  [p]This field is split into two sub-fields:[/p]\r\n"
"              [list]\r\n"
"              [*] x = bits[6:5]\r\n"
"              [*] y = bits[4:0]\r\n"
"              [/list]\r\n"
"              [p]Time window equation:[/p]\r\n"
"              [b]time_window = PACKAGE_POWER_SKU_UNIT.TIME_UNIT * ((1+x/4)^y)[/b]"},
#else
{17, 23, 0x0000000000000000, "RW/L", "time_window", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RW/L", "pl3_enable", "[list]\r\n"
"              [*]0 = disabled\r\n"
"              [*]1 = enabled\r\n"
"              [/list]"},
#else
{15, 15, 0x0000000000000000, "RW/L", "pl3_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 14, 0x0000000000000000, "RW/L", "power_limit", "Power Limit 3 (PL3) or PAppMax power level.  Any SOC power measurement observed above this level is considered as an excursion against the PL3 power limit and duty cycle / time window budget.  Units of this power limit are defined by PACKAGE_POWER_SKU_UNIT_MSR.PWR_UNIT."},
#else
{0, 14, 0x0000000000000000, "RW/L", "power_limit", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo922[] = {{"P_CR_PL3_CONTROL_0_0_0_MCHBAR", "", 0x000071F0, 7, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields923[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "superqueue_active_residency", "Graphics Superqueue active residency counter.  Counts in crystal reference clocks divided by 16."},
#else
{0, 31, 0x0000000000000000, "RO/V", "superqueue_active_residency", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo923[] = {{"P_CR_PP1_ANY_THREAD_ACTIVITY_0_0_0_MCHBAR", "", 0x00007244, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields924[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo924[] = {{"P_CR_MEM_MR4_TEMPERATURE_DEV3_0_0_0_MCHBAR", "", 0x00007248, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields925[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved"},
#else
{6, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{3, 5, 0x0000000000000000, "RW", "mr4_rank_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", "This field is updated each read of LPDDR DRAM MR4 Device Temperature Status per rank. Update rate is configured by BIOS."},
#else
{0, 2, 0x0000000000000000, "RW", "mr4_rank_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo925[] = {{"P_CR_MEM_MR4_TEMPERATURE_DEV4_0_0_0_MCHBAR", "", 0x0000724C, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields926[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{45, 63, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{45, 63, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "PSMI_Mode_Enabled", "Set/cleared by PSMI handler. When set, causes MLMC to stop swapping. Overrides Disable_Swaps."},
#else
{44, 44, 0x0000000000000000, "RW", "PSMI_Mode_Enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "Thermal_Throttling_Enabled", "Set/cleared by Pcode. When set, causes MLMC to stop swapping. Dynamic."},
#else
{43, 43, 0x0000000000000000, "RW", "Thermal_Throttling_Enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 42, 0x0000000000000004, "RW", "PMI_Max_FM_Rd_Ret_Credits", "Specifies how many read return credits to give to each far memory D-Unit."},
#else
{40, 42, 0x0000000000000004, "RW", "PMI_Max_FM_Rd_Ret_Credits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 39, 0x0000000000000004, "RW", "PMI_Max_NM_Rd_Ret_Credits", "Specifies how many read return credits to give to each near memory D-Unit."},
#else
{37, 39, 0x0000000000000004, "RW", "PMI_Max_NM_Rd_Ret_Credits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 36, 0x0000000000000002, "RW", "PMI_Max_Bunit_Wr_Credits", "Specifies how many write request credits to give to B-Unit."},
#else
{34, 36, 0x0000000000000002, "RW", "PMI_Max_Bunit_Wr_Credits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 33, 0x0000000000000002, "RW", "PMI_Max_Bunit_Rd_Credits", "Specifies how many read request credits to give to B-Unit."},
#else
{31, 33, 0x0000000000000002, "RW", "PMI_Max_Bunit_Rd_Credits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 30, 0x000000000000000F, "RW", "MLM_Controller_Enable", "4bit vector to identify active MLMCs: \r\n"
"             [list]\r\n"
"             [*]0: inactive \r\n"
"             [*]1: active\r\n"
"             [/list]"},
#else
{27, 30, 0x000000000000000F, "RW", "MLM_Controller_Enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 26, 0x0000000000000000, "RW", "CR_2LM_Mode", " [list]\r\n"
"               [*]0: exclusive 2LMDDR \r\n"
"               [*]1: inclusive 2LMDDR \r\n"
"               [*]2: inclusive 2LMSXP \r\n"
"               [*]3: Reserved\r\n"
"               [/list]"},
#else
{25, 26, 0x0000000000000000, "RW", "CR_2LM_Mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000001, "RW", "CR_1LM_Mode", "[list]\r\n"
"              [*]0: 2LM \r\n"
"              [*]1: 1LM mode bypass MLM core logic\r\n"
"              [/list]"},
#else
{24, 24, 0x0000000000000001, "RW", "CR_1LM_Mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 23, 0x0000000000000000, "RW", "TQ_rsvd_non_VC0", "TBD"},
#else
{17, 23, 0x0000000000000000, "RW", "TQ_rsvd_non_VC0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 16, 0x0000000000000000, "RW", "Astore_rsvd_non_VC0", "TBD"},
#else
{10, 16, 0x0000000000000000, "RW", "Astore_rsvd_non_VC0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 9, 0x0000000000000004, "RW", "Astore_Low_WM", "Watermark for when Astore starts to evict old translations."},
#else
{3, 9, 0x0000000000000004, "RW", "Astore_Low_WM", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000001, "RW", "NM_Size_MB", "Near memory size in GB: \r\n"
"              [list]\r\n"
"              [*]1: 1GB \r\n"
"              [*]2: 2GB\r\n"
"              [/list]"},
#else
{1, 2, 0x0000000000000001, "RW", "NM_Size_MB", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "Num_NM_Channels", "\r\n"
"              [list]\r\n"
"              [*]0: 4Ch \r\n"
"              [*]1: 8Ch\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000001, "RW", "Num_NM_Channels", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo926[] = {{"MLM_CR_CONFIG", "", 0x00004F00, 15, 0xFFFFFFFFFFFFFFFF, 0x0000048979000023}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields927[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{26, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{26, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 25, 0x0000000000000010, "RW", "Swap_Inter_Swap_Delay", "Interswap delay in MLM clocks."},
#else
{16, 25, 0x0000000000000010, "RW", "Swap_Inter_Swap_Delay", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000011, "RW", "Swap_Inter_Sector_Delay", "Intersector delay in MLM clocks."},
#else
{8, 15, 0x0000000000000011, "RW", "Swap_Inter_Sector_Delay", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000004, "RW", "Swap_Num_Outstanding_CL_requests", "Max outstanding FM swap CL requests."},
#else
{4, 7, 0x0000000000000004, "RW", "Swap_Num_Outstanding_CL_requests", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 3, 0x0000000000000002, "RW", "Policy", "First Miss2 currently our only supported policy."},
#else
{0, 3, 0x0000000000000002, "RW", "Policy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo927[] = {{"MLM_CR_SWAP_PARAMS", "", 0x00004F08, 5, 0x00000000FFFFFFFF, 0x0000000000101142}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields928[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{11, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits - FIXME  - jlunderd - the lower 3 bits of this field have been used in the RTL and must be renamed. reserved_0[2] --> forcepgpok_sai_check_def, reserved_0[1] --> sbep_cgctrl_clkgaten_b, reserved_0[0] --> sbep_cgctrl_clkgate_def"},
#else
{11, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW", "Adjust_Sleep_idle_count", "Change idle count for entering SRAM sleep from 1 us to"},
#else
{10, 10, 0x0000000000000000, "RW", "Adjust_Sleep_idle_count", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "Disable_WL_Sleep", "Disable large SRAM WL sleep mode."},
#else
{9, 9, 0x0000000000000000, "RW", "Disable_WL_Sleep", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "Disable_BL_Float", "Disable large SRAM BL floating."},
#else
{8, 8, 0x0000000000000000, "RW", "Disable_BL_Float", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RWV", "MLM_SDT_EXPOSE_RUNBUSY", "Polled by SDT Expose clients to determine expose completion."},
#else
{7, 7, 0x0000000000000000, "RWV", "MLM_SDT_EXPOSE_RUNBUSY", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 6, 0x0000000000000000, "RW", "MLM_SDT_EXPOSE_TARGET", "[list]\r\n"
"              [*]00: Expose SDT in MLMC 0 \r\n"
"              [*]01: Expose SDT in MLMC 1 \r\n"
"              [*]10: Expose SDT in MLMC 2 \r\n"
"              [*]11: Expose SDT in MLMC 3\r\n"
"              [/list]"},
#else
{5, 6, 0x0000000000000000, "RW", "MLM_SDT_EXPOSE_TARGET", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "Disable_Porous_Swap", "Disable porous swapping."},
#else
{4, 4, 0x0000000000000000, "RW", "Disable_Porous_Swap", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "Disable_Pinning", "Disable pinning."},
#else
{3, 3, 0x0000000000000000, "RW", "Disable_Pinning", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "Disable_TC", "Disable ondie tag cache."},
#else
{2, 2, 0x0000000000000000, "RW", "Disable_TC", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "Disable_ODTS", "Disable ondie tag store."},
#else
{1, 1, 0x0000000000000000, "RW", "Disable_ODTS", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "Disable_Swaps", "Disable swapping. Static overrides all other swapping enables."},
#else
{0, 0, 0x0000000000000000, "RW", "Disable_Swaps", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo928[] = {{"MLM_CR_DEFEATURES", "", 0x00004F0C, 11, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields929[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enabled", "Enable pinning region 0."},
#else
{31, 31, 0x0000000000000000, "RW", "enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", "Read only 0"},
#else
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "Pinned_way", "Pinned region 0 pinned way."},
#else
{24, 27, 0x0000000000000000, "RW", "Pinned_way", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", "Read only 0"},
#else
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "Size", "Pinned region 0 -- size of pinned region, 1MB granularity."},
#else
{16, 21, 0x0000000000000000, "RW", "Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "Base", "Pinning region 0 -- base address of pinned PPA, 1MB granularity."},
#else
{0, 15, 0x0000000000000000, "RW", "Base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo929[] = {{"MLM_CR_PINNING_REGION0", "", 0x00004F10, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields930[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enabled", "Enable pinning region 1."},
#else
{31, 31, 0x0000000000000000, "RW", "enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", "Read only 0"},
#else
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "Pinned_way", "Pinned region 1 pinned way."},
#else
{24, 27, 0x0000000000000000, "RW", "Pinned_way", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", "Read only 0"},
#else
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "Size", "Pinned region 1 -- size of pinned region, 1MB granularity."},
#else
{16, 21, 0x0000000000000000, "RW", "Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "Base", "Pinning region 1: Base address of pinned PPA, 1MB granularity."},
#else
{0, 15, 0x0000000000000000, "RW", "Base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo930[] = {{"MLM_CR_PINNING_REGION1", "", 0x00004F14, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields931[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enabled", "Enable pinning region 2."},
#else
{31, 31, 0x0000000000000000, "RW", "enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", "Read only 0"},
#else
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "Pinned_way", "Pinned region 2 pinned way."},
#else
{24, 27, 0x0000000000000000, "RW", "Pinned_way", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", "Read only 0"},
#else
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "Size", "Pinned region 2: Size of pinned region, 1MB granularity."},
#else
{16, 21, 0x0000000000000000, "RW", "Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "Base", "Pinning region 2: Base address of pinned PPA, 1MB granularity."},
#else
{0, 15, 0x0000000000000000, "RW", "Base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo931[] = {{"MLM_CR_PINNING_REGION2", "", 0x00004F18, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields932[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enabled", "Enable pinning region 2"},
#else
{31, 31, 0x0000000000000000, "RW", "enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", "Read only 0"},
#else
{28, 30, 0x0000000000000000, "RW", "RESERVED_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RW", "Pinned_way", "Pinned region 2 pinned way."},
#else
{24, 27, 0x0000000000000000, "RW", "Pinned_way", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", "Read only 0"},
#else
{22, 23, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "Size", "Pinned region 2: Size of pinned region, 1MB granularity."},
#else
{16, 21, 0x0000000000000000, "RW", "Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "Base", "Pinning region 2: Base address of pinned PPA, 1MB granularity."},
#else
{0, 15, 0x0000000000000000, "RW", "Base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo932[] = {{"MLM_CR_PINNING_REGION3", "", 0x00004F1C, 6, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields933[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{10, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{10, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 9, 0x0000000000000004, "RW", "Max_Pinned_Ways", "Maximum number of pinned ways per set."},
#else
{5, 9, 0x0000000000000004, "RW", "Max_Pinned_Ways", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000004, "RW", "Min_Unpinned_Ways", "Minimum number of unpinned ways per set"},
#else
{0, 4, 0x0000000000000004, "RW", "Min_Unpinned_Ways", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo933[] = {{"MLM_CR_PINNING", "", 0x00004F20, 3, 0x00000000FFFFFFFF, 0x0000000000000084}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields934[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{2, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RWV", "SDT_Init_Done", "Flag set by MLMC when SDT initialization is complete."},
#else
{1, 1, 0x0000000000000000, "RWV", "SDT_Init_Done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "Execute_SDT_Init", "Flag for Pcode/BIOS to set when MLMC should perform SDT initialization."},
#else
{0, 0, 0x0000000000000000, "RW", "Execute_SDT_Init", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo934[] = {{"MLM_CR_MISC", "", 0x00004F24, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields935[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{52, 63, 0x0000000000000000, "RWV", "MLM3_DED_SET_ADDRESS", "SET address in DED : For the case of both SRAM have DED the set of small SRAM will be reported."},
#else
{52, 63, 0x0000000000000000, "RWV", "MLM3_DED_SET_ADDRESS", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RWV", "MLM3_DED_SET_VALID", "[list]\r\n"
"              [*]0: set address is not valid  \r\n"
"              [*]1: SET address in DED is valid\r\n"
"              [/list]"},
#else
{51, 51, 0x0000000000000000, "RWV", "MLM3_DED_SET_VALID", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RWV", "MLM3_DED_overflow", "There are DEDs more than 1."},
#else
{50, 50, 0x0000000000000000, "RWV", "MLM3_DED_overflow", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RWV", "MLM3_LARGE_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the large SRAM\r\n"
"              [/list]"},
#else
{49, 49, 0x0000000000000000, "RWV", "MLM3_LARGE_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RWV", "MLM3_SMALL_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the small SRAM\r\n"
"              [/list]"},
#else
{48, 48, 0x0000000000000000, "RWV", "MLM3_SMALL_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 47, 0x0000000000000000, "RWV", "MLM2_DED_SET_ADDRESS", "SET address in DED: For the case in which both SRAMs have DED, the set of small SRAM will be reported."},
#else
{36, 47, 0x0000000000000000, "RWV", "MLM2_DED_SET_ADDRESS", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RWV", "MLM2_DED_SET_VALID", "[list]\r\n"
"              [*]0: set address is not valid  \r\n"
"              [*]1: SET address in DED is valid\r\n"
"              [/list]"},
#else
{35, 35, 0x0000000000000000, "RWV", "MLM2_DED_SET_VALID", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RWV", "MLM2_DED_overflow", "There are DEDs more than 1."},
#else
{34, 34, 0x0000000000000000, "RWV", "MLM2_DED_overflow", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RWV", "MLM2_LARGE_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the large SRAM\r\n"
"              [/list]"},
#else
{33, 33, 0x0000000000000000, "RWV", "MLM2_LARGE_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RWV", "MLM2_SMALL_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the small SRAM\r\n"
"              [/list]"},
#else
{32, 32, 0x0000000000000000, "RWV", "MLM2_SMALL_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 31, 0x0000000000000000, "RWV", "MLM1_DED_SET_ADDRESS", "SET address in DED: For the case in which both SRAMs have DED, the set of small SRAM will be reported."},
#else
{20, 31, 0x0000000000000000, "RWV", "MLM1_DED_SET_ADDRESS", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RWV", "MLM1_DED_SET_VALID", "[list]\r\n"
"              [*]0: set address is not valid\r\n"
"              [*]1: SET address in DED is valid\r\n"
"              [/list]"},
#else
{19, 19, 0x0000000000000000, "RWV", "MLM1_DED_SET_VALID", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RWV", "MLM1_DED_overflow", "There are DEDs more than 1."},
#else
{18, 18, 0x0000000000000000, "RWV", "MLM1_DED_overflow", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RWV", "MLM1_LARGE_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the large SRAM\r\n"
"              [/list]"},
#else
{17, 17, 0x0000000000000000, "RWV", "MLM1_LARGE_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RWV", "MLM1_SMALL_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the small SRAM\r\n"
"              [/list]"},
#else
{16, 16, 0x0000000000000000, "RWV", "MLM1_SMALL_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 15, 0x0000000000000000, "RWV", "MLM0_DED_SET_ADDRESS", "SET address in DED: For the case in which both SRAMs have DED, the set of small SRAM will be reported."},
#else
{4, 15, 0x0000000000000000, "RWV", "MLM0_DED_SET_ADDRESS", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RWV", "MLM0_DED_SET_VALID", "[list]\r\n"
"              [*]0: set address is not valid\r\n"
"              [*]1: SET address in DED is valid\r\n"
"              [/list]"},
#else
{3, 3, 0x0000000000000000, "RWV", "MLM0_DED_SET_VALID", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RWV", "MLM0_DED_overflow", "There are DEDs more than 1."},
#else
{2, 2, 0x0000000000000000, "RWV", "MLM0_DED_overflow", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RWV", "MLM0_LARGE_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the large SRAM\r\n"
"              [/list]"},
#else
{1, 1, 0x0000000000000000, "RWV", "MLM0_LARGE_SRAM_DED", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RWV", "MLM0_SMALL_SRAM_DED", "[list]\r\n"
"              [*]0: no double bit errors in the large SRAM  \r\n"
"              [*]1: DED happens in the small SRAM\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RWV", "MLM0_SMALL_SRAM_DED", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo935[] = {{"MLM_CR_ARRAY_ECC_STATUS", "", 0x00004F28, 20, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields936[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{46, 63, 0x0000000000000000, "RWV", "RESERVED_0", "Reserved bits"},
#else
{46, 63, 0x0000000000000000, "RWV", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "ROV", "MLMC_core_empty", "1 if la astore is empty -- all rd/wt were done."},
#else
{45, 45, 0x0000000000000000, "ROV", "MLMC_core_empty", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "ROV", "MLMC_core_quiet", "1 if all TC/TM/LA/DA are quiet --  all functional units in mlmc are quiet."},
#else
{44, 44, 0x0000000000000000, "ROV", "MLMC_core_quiet", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "ROV", "MLMC_adapters_quiet", "1 if all responders are ready for entering clock_gating."},
#else
{43, 43, 0x0000000000000000, "ROV", "MLMC_adapters_quiet", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RWV", "FM_PMI_Idle_Status", "1 if all far memory PMIs are in idle state."},
#else
{42, 42, 0x0000000000000000, "RWV", "FM_PMI_Idle_Status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RWV", "NM_PMI_Idle_Status", "1 if all near memory PMIs are in idle state."},
#else
{41, 41, 0x0000000000000000, "RWV", "NM_PMI_Idle_Status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RWV", "Bunit_PMI_Idle_Status", "1 if all B-Unit PMIs are in idle state."},
#else
{40, 40, 0x0000000000000000, "RWV", "Bunit_PMI_Idle_Status", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 39, 0x0000000000000000, "RWV", "FM_Access_Count", "Total number of FM accesses readswrites across all MLMCs."},
#else
{16, 39, 0x0000000000000000, "RWV", "FM_Access_Count", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RWV", "Swap_Count", "Total swap count across all 4 MLMCs."},
#else
{0, 15, 0x0000000000000000, "RWV", "Swap_Count", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo936[] = {{"MLM_CR_STATUS", "", 0x00004F30, 9, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields937[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010212, "RW", "RESERVED_0", "Reserved bits"},
#else
{0, 63, 0x00000C0061010212, "RW", "RESERVED_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo937[] = {{"MLM_CR_SAI_RAC", "", 0x00004F38, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields938[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010212, "RW", "RESERVED_0", "Reserved bits"},
#else
{0, 63, 0x00000C0061010212, "RW", "RESERVED_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo938[] = {{"MLM_CR_SAI_WAC", "", 0x00004F40, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields939[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "RESERVED_0", "Reserved bits"},
#else
{0, 63, 0x00000C0061010202, "RW", "RESERVED_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo939[] = {{"MLM_CR_SAI_CP", "", 0x00004F48, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields940[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{29, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{29, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "Disable_pgcbclk_trunk_gating", "This will prevent PGCB clockreq from going down. pgcb clock stays alive but ipclk clkreq can turn off."},
#else
{28, 28, 0x0000000000000000, "RW", "Disable_pgcbclk_trunk_gating", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "Enable_clkreq2ccp", "This is for disabling the clock req from CDC to the CCP.ie trunk clock. This will not affect local clock gating."},
#else
{27, 27, 0x0000000000000000, "RW", "Enable_clkreq2ccp", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "Sleep_Enable", "If set, then IP may assert Sleep during PG ing."},
#else
{26, 26, 0x0000000000000000, "RW", "Sleep_Enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "Astore_Always_Flush", "Enables immediate flushing of Astore entries."},
#else
{25, 25, 0x0000000000000000, "RW", "Astore_Always_Flush", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000001, "RW", "Powergate_Leave_TC_ON", "If set, causes TC to remain turned on during AutoPG."},
#else
{24, 24, 0x0000000000000001, "RW", "Powergate_Leave_TC_ON", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 23, 0x0000000000000002, "RW", "PGCB_Powergate_Timer", "Number of SB clocks 100MHz till PGCB powergates MLMC."},
#else
{13, 23, 0x0000000000000002, "RW", "PGCB_Powergate_Timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 12, 0x0000000000000002, "RW", "PGCB_Clockgate_hyst_timer", "Number of SB clocks 100MHz till PGCB clockgates MLMC."},
#else
{9, 12, 0x0000000000000002, "RW", "PGCB_Clockgate_hyst_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "PGCB_HW_Autonomous_Enable", "Enable of PGCB HW_AutoPG -- always 0 since POR is P-Unit control."},
#else
{8, 8, 0x0000000000000000, "RW", "PGCB_HW_Autonomous_Enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "PMC_Request_Enable", "If set, then IP will PG when idle and the PMC requests power gating."},
#else
{7, 7, 0x0000000000000001, "RW", "PMC_Request_Enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RW", "PGCB_CGREQ_DISABLE", "This will disable internal clock gating in cdc. This in turn will also disable IP to CCP clock req."},
#else
{6, 6, 0x0000000000000000, "RW", "PGCB_CGREQ_DISABLE", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 5, 0x0000000000000004, "RW", "PMI_ISM_Idle_Timer", "Number of MLMC clocks of idleness before requesting PMI to go idle."},
#else
{2, 5, 0x0000000000000004, "RW", "PMI_ISM_Idle_Timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "PMI_ISM_Force_Wakeup", "If set, forces all requestor ISMs to wake up and stop requesting clock/power gating."},
#else
{1, 1, 0x0000000000000000, "RW", "PMI_ISM_Force_Wakeup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "PMI_ISM_Idle_Disable", "If set, prevents all PMI ISMs from entering idle state."},
#else
{0, 0, 0x0000000000000000, "RW", "PMI_ISM_Idle_Disable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo940[] = {{"MLM_CR_POWER_MGMT", "", 0x00004F50, 14, 0x00000000FFFFFFFF, 0x0000000001004490}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields941[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{30, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "Mem_Init_Done", "Flag for BIOS to set when FM configuration fields are set."},
#else
{29, 29, 0x0000000000000000, "RW", "Mem_Init_Done", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 28, 0x0000000000000004, "RW", "FM_Chan_E_Size", "Far memory channel East size in 256MB multiples."},
#else
{23, 28, 0x0000000000000004, "RW", "FM_Chan_E_Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 22, 0x0000000000000004, "RW", "FM_Chan_W_Size", "Far memory channel West size in 256MB multiples"},
#else
{17, 22, 0x0000000000000004, "RW", "FM_Chan_W_Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 16, 0x0000000000000004, "RW", "FM_Chan_N_Size", "Far memory channel North size in 256MB multiples"},
#else
{11, 16, 0x0000000000000004, "RW", "FM_Chan_N_Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 10, 0x0000000000000004, "RW", "FM_Chan_S_Size", "Far memory channel South size in 256MB multiples"},
#else
{5, 10, 0x0000000000000004, "RW", "FM_Chan_S_Size", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 4, 0x0000000000000009, "RW", "FM_Active_Dunits", "Active far memory Dunits. One bit for S N W E Dunits."},
#else
{1, 4, 0x0000000000000009, "RW", "FM_Active_Dunits", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "FM_No_LPDDR_Present", "Near memory only configuration, i.e. only WIO2 populated -- debugonly only."},
#else
{0, 0, 0x0000000000000000, "RW", "FM_No_LPDDR_Present", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo941[] = {{"MLM_CR_FM_CONFIG", "", 0x00004F54, 8, 0x00000000FFFFFFFF, 0x0000000002082092}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields942[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{13, 31, 0x0000000000000000, "RW", "RESERVED_0", "Reserved bits"},
#else
{13, 31, 0x0000000000000000, "RW", "RESERVED_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "FMArb_Staggered_Intlv", "[list]\r\n"
"              [*]1: FMArb performs staggered interleave \r\n"
"              [*]0: FMArb does flat interleave\r\n"
"              [/list]"},
#else
{12, 12, 0x0000000000000000, "RW", "FMArb_Staggered_Intlv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x000000000000000D, "RW", "NM_Intlv_Xor_Bit2", "NM interleave XOR bit 2 should be higher than XOR bit 1 if enabled"},
#else
{8, 11, 0x000000000000000D, "RW", "NM_Intlv_Xor_Bit2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "NM_Intlv_Xor_Bit2_Enable", "Optional. Do not use with 1K and 2K interleave."},
#else
{7, 7, 0x0000000000000000, "RW", "NM_Intlv_Xor_Bit2_Enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 6, 0x000000000000000A, "RW", "NM_Intlv_Xor_Bit1", "This should be higher than bit 6, if enabled."},
#else
{3, 6, 0x000000000000000A, "RW", "NM_Intlv_Xor_Bit1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "NM_Intlv_Xor_Bit1_Enable", "Optional. Do not use with 1K and 2K interleave."},
#else
{2, 2, 0x0000000000000000, "RW", "NM_Intlv_Xor_Bit1_Enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "NM_Intlv_Bit", "[list]\r\n"
"              [*]0: bit 10 interleave \r\n"
"              [*]1: bit 11 interleave \r\n"
"              [*]2: bit 6 interleave\r\n"
"              [/list]"},
#else
{0, 1, 0x0000000000000000, "RW", "NM_Intlv_Bit", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo942[] = {{"MLM_CR_NM_INTERLEAVE", "", 0x00004F58, 7, 0x00000000FFFFFFFF, 0x0000000000000D50}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields943[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "vc0b_c", "VC0B completion grant count to T-Unit."},
#else
{24, 29, 0x0000000000000001, "RW", "vc0b_c", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "vc0b_p", "VC0B posted transaction grant count to T-Unit.  This is only for MSIs."},
#else
{16, 21, 0x0000000000000001, "RW", "vc0b_p", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "vc0a_c", "VC0A completion grant count to T-Unit."},
#else
{8, 13, 0x0000000000000001, "RW", "vc0a_c", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "vc0a_p", "VC0A posted to T-Unit MSIs."},
#else
{0, 5, 0x0000000000000001, "RW", "vc0a_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo943[] = {{"A_CR_UPARB_GCNT_DEV_A2T_MCHBAR", "", 0x00006400, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields944[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid0_tgt", "Target arbiter grant count for the channel ID 0 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid0_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid0_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 0."},
#else
{16, 21, 0x0000000000000001, "RW", "chid0_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid0_np", "Grant count for non-posted transactions on channel ID 0."},
#else
{8, 13, 0x0000000000000001, "RW", "chid0_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0_p", "Grant count for posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo944[] = {{"A_CR_UPARB_GCNT_A2B_0_MCHBAR", "", 0x00006404, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields945[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid1_tgt", "Target arbiter grant count for the channel ID 1 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid1_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid1_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 1."},
#else
{16, 21, 0x0000000000000001, "RW", "chid1_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1_np", "Grant count for non-posted transactions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid1_p", "Grant count for posted transactions on channel ID 1."},
#else
{0, 5, 0x0000000000000001, "RW", "chid1_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo945[] = {{"A_CR_UPARB_GCNT_A2B_1_MCHBAR", "", 0x00006408, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields946[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid2_tgt", "Target arbiter grant count for the channel ID 2 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid2_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid2_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 2."},
#else
{16, 21, 0x0000000000000000, "RO", "chid2_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid2_np", "Grant count for non-posted transactions on channel ID 2."},
#else
{8, 13, 0x0000000000000001, "RW", "chid2_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RO", "chid2_p", "Grant count for posted transactions on channel ID 2."},
#else
{0, 5, 0x0000000000000000, "RO", "chid2_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo946[] = {{"A_CR_UPARB_GCNT_A2B_2_MCHBAR", "", 0x0000640C, 4, 0x000000003FFFFFFF, 0x0000000001000100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields947[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid3_tgt", "Target arbiter grant count for the channel ID 3 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid3_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid3_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 3."},
#else
{16, 21, 0x0000000000000001, "RW", "chid3_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid3_np", "Grant count for non-posted transactions on channel ID 3."},
#else
{8, 13, 0x0000000000000001, "RW", "chid3_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid3_p", "Grant count for posted transactions on channel ID 3."},
#else
{0, 5, 0x0000000000000001, "RW", "chid3_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo947[] = {{"A_CR_UPARB_GCNT_A2B_3_MCHBAR", "", 0x00006410, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields948[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid4_tgt", "Target arbiter grant count for the channel ID 4 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid4_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid4_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 4."},
#else
{16, 21, 0x0000000000000000, "RO", "chid4_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid4_np", "Grant count for non-posted transactions on channel ID 4."},
#else
{8, 13, 0x0000000000000001, "RW", "chid4_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RO", "chid4_p", "Grant count for posted transactions on channel ID 4."},
#else
{0, 5, 0x0000000000000000, "RO", "chid4_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo948[] = {{"A_CR_UPARB_GCNT_A2B_4_MCHBAR", "", 0x00006414, 4, 0x000000003FFFFFFF, 0x0000000001000100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields949[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid5_tgt", "Target arbiter grant count for the channel ID 5 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid5_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid5_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 5."},
#else
{16, 21, 0x0000000000000000, "RO", "chid5_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid5_np", "Grant count for non-posted transactions on channel ID 5."},
#else
{8, 13, 0x0000000000000001, "RW", "chid5_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid5_p", "Grant count for posted transactions on channel ID 5."},
#else
{0, 5, 0x0000000000000001, "RW", "chid5_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo949[] = {{"A_CR_UPARB_GCNT_A2B_5_MCHBAR", "", 0x00006418, 4, 0x000000003FFFFFFF, 0x0000000001000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields950[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid6_tgt", "Target arbiter grant count for the channel ID 6 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid6_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid6_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 6."},
#else
{16, 21, 0x0000000000000000, "RO", "chid6_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid6_np", "Grant count for non-posted transactions on channel ID 6."},
#else
{8, 13, 0x0000000000000001, "RW", "chid6_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid6_p", "Grant count for posted transactions on channel ID 6."},
#else
{0, 5, 0x0000000000000001, "RW", "chid6_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo950[] = {{"A_CR_UPARB_GCNT_A2B_6_MCHBAR", "", 0x0000641C, 4, 0x000000003FFFFFFF, 0x0000000001000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields951[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid7_tgt", "Target arbiter grant count for the channel ID 7 class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid7_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid7_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 7."},
#else
{16, 21, 0x0000000000000000, "RO", "chid7_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid7_np", "Grant count for non-posted transactions on channel ID 7."},
#else
{8, 13, 0x0000000000000001, "RW", "chid7_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid7_p", "Grant count for posted transactions on channel ID 7."},
#else
{0, 5, 0x0000000000000001, "RW", "chid7_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo951[] = {{"A_CR_UPARB_GCNT_A2B_7_MCHBAR", "", 0x00006420, 4, 0x000000003FFFFFFF, 0x0000000001000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields952[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid0_tgt", "Target arbiter grant count for the channel ID 0 a2t class arbiter."},
#else
{24, 29, 0x0000000000000001, "RW", "chid0_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid0_mmu_np", "Grant count for IOMMU non-posted transactions on channel ID 0."},
#else
{16, 21, 0x0000000000000000, "RO", "chid0_mmu_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid0_np", "Grant count for non-posted transactions on channel ID 0."},
#else
{8, 13, 0x0000000000000001, "RW", "chid0_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0_p", "Grant count for posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo952[] = {{"A_CR_UPARB_GCNT_A2T_0_MCHBAR", "", 0x00006424, 4, 0x000000003FFFFFFF, 0x0000000001000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields953[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RO", "chid0_tgt", "Target arbiter grant count for the channel ID 0 p2p class arbiter."},
#else
{24, 29, 0x0000000000000001, "RO", "chid0_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RO", "chid0_c", "Grant count for completions on channel ID 0."},
#else
{16, 21, 0x0000000000000001, "RO", "chid0_c", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RO", "chid0_n", "Grant count for non-posted transactions on channel ID 0."},
#else
{8, 13, 0x0000000000000001, "RO", "chid0_n", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RO", "chid0_p", "Grant count for posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RO", "chid0_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo953[] = {{"A_CR_UPARB_GCNT_P2P_0_MCHBAR", "", 0x00006428, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields954[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RO", "chid1_tgt", "Target arbiter grant count for the channel ID 1 p2p class arbiter."},
#else
{24, 29, 0x0000000000000001, "RO", "chid1_tgt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RO", "chid1_c", "Grant count for completions on channel ID 1."},
#else
{16, 21, 0x0000000000000001, "RO", "chid1_c", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RO", "chid1_n", "Grant count for non-posted transactions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RO", "chid1_n", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RO", "chid1_p", "Grant count for posted transactions on channel ID 1"},
#else
{0, 5, 0x0000000000000001, "RO", "chid1_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo954[] = {{"A_CR_UPARB_GCNT_P2P_1_MCHBAR", "", 0x0000642C, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields955[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid3", "Grant count for posted transactions on channel ID 3."},
#else
{24, 29, 0x0000000000000001, "RW", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid2", "Grant count for posted transactions on channel ID 2."},
#else
{16, 21, 0x0000000000000000, "RO", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1", "Grant count for posted transactions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0", "Grant count for posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo955[] = {{"A_CR_CRDARB_PRIV_GCNT_DEV_P_0_MCHBAR", "", 0x00006430, 4, 0x000000003FFFFFFF, 0x0000000001000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields956[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid7", "Grant count for posted transactions on channel ID 7."},
#else
{24, 29, 0x0000000000000001, "RW", "chid7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid6", "Grant count for posted transactions on channel ID 6."},
#else
{16, 21, 0x0000000000000001, "RW", "chid6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid5", "Grant count for posted transactions on channel ID 5."},
#else
{8, 13, 0x0000000000000001, "RW", "chid5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RO", "chid4", "Grant count for posted transactions on channel ID 4."},
#else
{0, 5, 0x0000000000000000, "RO", "chid4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo956[] = {{"A_CR_CRDARB_PRIV_GCNT_DEV_P_1_MCHBAR", "", 0x00006434, 4, 0x000000003FFFFFFF, 0x0000000001010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields957[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid3", "Grant count for non-posted transactions on channel ID 3."},
#else
{24, 29, 0x0000000000000001, "RW", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid2", "Grant count for non-posted transactions on channel ID 2."},
#else
{16, 21, 0x0000000000000001, "RW", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1", "Grant count for non-posted transactions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0", "Grant count for non-posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo957[] = {{"A_CR_CRDARB_PRIV_GCNT_DEV_N_0_MCHBAR", "", 0x00006438, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields958[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid7", "Grant count for non-posted transactions on channel ID 7."},
#else
{24, 29, 0x0000000000000001, "RW", "chid7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "chid6", "Grant count for non-posted transactions on channel ID 6."},
#else
{16, 21, 0x0000000000000004, "RW", "chid6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid5", "Grant count for non-posted transactions on channel ID 5."},
#else
{8, 13, 0x0000000000000001, "RW", "chid5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "chid4", "Grant count for non-posted transactions on channel ID 4."},
#else
{0, 5, 0x0000000000000004, "RW", "chid4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo958[] = {{"A_CR_CRDARB_PRIV_GCNT_DEV_N_1_MCHBAR", "", 0x0000643C, 4, 0x000000003FFFFFFF, 0x0000000001040104}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields959[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RO", "chid3", "Grant count for completions on channel ID 3."},
#else
{24, 29, 0x0000000000000000, "RO", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid2", "Grant count for completions on channel ID 2."},
#else
{16, 21, 0x0000000000000000, "RO", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1", "Grant count for completions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0", "Grant count for completions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo959[] = {{"A_CR_CRDARB_PRIV_GCNT_DEV_C_0_MCHBAR", "", 0x00006440, 4, 0x000000003FFFFFFF, 0x0000000000000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields960[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid3", "Grant count for posted transactions on channel ID 3."},
#else
{24, 29, 0x0000000000000001, "RW", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid2", "Grant count for posted transactions on channel ID 2."},
#else
{16, 21, 0x0000000000000000, "RO", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1", "Grant count for posted transactions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0", "Grant count for posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo960[] = {{"A_CR_CRDARB_SHRD_GCNT_DEV_P_0_MCHBAR", "", 0x00006444, 4, 0x000000003FFFFFFF, 0x0000000001000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields961[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid7", "Grant count for posted transactions on channel ID 7."},
#else
{24, 29, 0x0000000000000001, "RW", "chid7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid6", "Grant count for posted transactions on channel ID 6."},
#else
{16, 21, 0x0000000000000001, "RW", "chid6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid5", "Grant count for posted transactions on channel ID 5."},
#else
{8, 13, 0x0000000000000001, "RW", "chid5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000000, "RO", "chid4", "Grant count for posted transactions on channel ID 4."},
#else
{0, 5, 0x0000000000000000, "RO", "chid4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo961[] = {{"A_CR_CRDARB_SHRD_GCNT_DEV_P_1_MCHBAR", "", 0x00006448, 4, 0x000000003FFFFFFF, 0x0000000001010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields962[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid3", "Grant count for non-posted transactions on channel ID 3."},
#else
{24, 29, 0x0000000000000001, "RW", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "chid2", "Grant count for non-posted transactions on channel ID 2."},
#else
{16, 21, 0x0000000000000001, "RW", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1", "Grant count for non-posted transactions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0", "Grant count for non-posted transactions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo962[] = {{"A_CR_CRDARB_SHRD_GCNT_DEV_N_0_MCHBAR", "", 0x0000644C, 4, 0x000000003FFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields963[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000001, "RW", "chid7", "Grant count for non-posted transactions on channel ID 7."},
#else
{24, 29, 0x0000000000000001, "RW", "chid7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "chid6", "Grant count for non-posted transactions on channel ID 6."},
#else
{16, 21, 0x0000000000000004, "RW", "chid6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid5", "Grant count for non-posted transactions on channel ID 5."},
#else
{8, 13, 0x0000000000000001, "RW", "chid5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "chid4", "Grant count for non-posted transactions on channel ID 4."},
#else
{0, 5, 0x0000000000000004, "RW", "chid4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo963[] = {{"A_CR_CRDARB_SHRD_GCNT_DEV_N_1_MCHBAR", "", 0x00006450, 4, 0x000000003FFFFFFF, 0x0000000001040104}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields964[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000000, "RO", "chid3", "Grant count for completions on channel ID 3."},
#else
{24, 29, 0x0000000000000000, "RO", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RO", "chid2", "Grant count for completions on channel ID 2."},
#else
{16, 21, 0x0000000000000000, "RO", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "chid1", "Grant count for completions on channel ID 1."},
#else
{8, 13, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "chid0", "Grant count for completions on channel ID 0."},
#else
{0, 5, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo964[] = {{"A_CR_CRDARB_SHRD_GCNT_DEV_C_0_MCHBAR", "", 0x00006454, 4, 0x000000003FFFFFFF, 0x0000000000000101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields965[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "c", "All Completions."},
#else
{16, 21, 0x0000000000000001, "RW", "c", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "np", "All non-posted."},
#else
{8, 13, 0x0000000000000001, "RW", "np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "p", "All posted."},
#else
{0, 5, 0x0000000000000001, "RW", "p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo965[] = {{"A_CR_CRDARB_PRIV_GCNT_CLS_MCHBAR", "", 0x00006458, 3, 0x00000000003FFFFF, 0x0000000000010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields966[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "c", "All Completions"},
#else
{16, 21, 0x0000000000000001, "RW", "c", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "np", "All Non Posteds"},
#else
{8, 13, 0x0000000000000001, "RW", "np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "p", "All Posteds"},
#else
{0, 5, 0x0000000000000001, "RW", "p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo966[] = {{"A_CR_CRDARB_SHRD_GCNT_CLS_MCHBAR", "", 0x0000645C, 3, 0x00000000003FFFFF, 0x0000000000010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields967[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000FF, "RW", "chid3", "Gazelle queue limit for Upstream NP on channel ID 3."},
#else
{24, 31, 0x00000000000000FF, "RW", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000FF, "RW", "chid2", "Gazelle queue limit for Upstream NP on channel ID 2."},
#else
{16, 23, 0x00000000000000FF, "RW", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000FF, "RW", "chid1", "Gazelle queue limit for Upstream NP on channel ID 1."},
#else
{8, 15, 0x00000000000000FF, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000FF, "RW", "chid0", "Gazelle queue limit for Upstream NP on channel ID 0."},
#else
{0, 7, 0x00000000000000FF, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo967[] = {{"A_CR_GZLQ_LIMIT_CH0_3_MCHBAR", "", 0x00006460, 4, 0x00000000FFFFFFFF, 0x00000000FFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields968[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000FF, "RW", "chid7", "Gazelle queue limit for Upstream NP on channel ID 7."},
#else
{24, 31, 0x00000000000000FF, "RW", "chid7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x00000000000000FF, "RW", "chid6", "Gazelle queue limit for Upstream NP on channel ID 6."},
#else
{16, 23, 0x00000000000000FF, "RW", "chid6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000FF, "RW", "chid5", "Gazelle queue limit for Upstream NP on channel ID 5."},
#else
{8, 15, 0x00000000000000FF, "RW", "chid5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x00000000000000FF, "RW", "chid4", "Gazelle queue limit for Upstream NP on channel ID 4."},
#else
{0, 7, 0x00000000000000FF, "RW", "chid4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo968[] = {{"A_CR_GZLQ_LIMIT_CH4_7_MCHBAR", "", 0x00006464, 4, 0x00000000FFFFFFFF, 0x00000000FFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields969[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "class_cnt", "IOMMU arbiter class grant count."},
#else
{16, 21, 0x0000000000000001, "RW", "class_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "dev_np", "IOMMU arbiter device grant count for NP."},
#else
{8, 13, 0x0000000000000001, "RW", "dev_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "dev_p", "IOMMU arbiter device grant count for p."},
#else
{0, 5, 0x0000000000000001, "RW", "dev_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo969[] = {{"A_CR_IOMMUARB_GCNT_VC0a_0_0_0_MCHBAR", "", 0x00006468, 3, 0x00000000003FFFFF, 0x0000000000010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields970[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "class_cnt", "IOMMU arbiter class grant count."},
#else
{16, 21, 0x0000000000000001, "RW", "class_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "dev_np", "IOMMU arbiter device grant count for NP."},
#else
{8, 13, 0x0000000000000001, "RW", "dev_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "dev_p", "IOMMU arbiter device grant count for p."},
#else
{0, 5, 0x0000000000000001, "RW", "dev_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo970[] = {{"A_CR_IOMMUARB_GCNT_VC0b_0_0_0_MCHBAR", "", 0x0000646C, 3, 0x00000000003FFFFF, 0x0000000000010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields971[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000001, "RW", "class_cnt", "IOMMU arbiter class grant count."},
#else
{16, 21, 0x0000000000000001, "RW", "class_cnt", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000001, "RW", "dev_np", "IOMMU arbiter device grant count for NP."},
#else
{8, 13, 0x0000000000000001, "RW", "dev_np", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000001, "RW", "dev_p", "IOMMU arbiter device grant count for p."},
#else
{0, 5, 0x0000000000000001, "RW", "dev_p", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo971[] = {{"A_CR_IOMMUARB_GCNT_VC1b_0_0_0_MCHBAR", "", 0x00006470, 3, 0x00000000003FFFFF, 0x0000000000010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields972[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000004, "RW", "chid3", "Gazelle queue limit for Upstream NP on channel ID 3."},
#else
{24, 31, 0x0000000000000004, "RW", "chid3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000004, "RW", "chid2", "Gazelle queue limit for Upstream NP on channel ID 2."},
#else
{16, 23, 0x0000000000000004, "RW", "chid2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000001, "RW", "chid1", "Gazelle queue limit for Upstream NP on Channel ID 1."},
#else
{8, 15, 0x0000000000000001, "RW", "chid1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000001, "RW", "chid0", "Gazelle queue limit for Upstream NP on Channel ID 0."},
#else
{0, 7, 0x0000000000000001, "RW", "chid0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo972[] = {{"A_CR_GZLQ_RSVD_CH0_3_MCHBAR", "", 0x00006474, 4, 0x00000000FFFFFFFF, 0x0000000004040101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields973[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000001, "RW", "chid7", "Gazelle queue limit for Upstream NP on channel ID 7."},
#else
{24, 31, 0x0000000000000001, "RW", "chid7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000001, "RW", "chid6", "Gazellequeue limit for Upstream NP on channel ID 6."},
#else
{16, 23, 0x0000000000000001, "RW", "chid6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000001, "RW", "chid5", "Gazelle queue limit for Upstream NP on channel ID 5."},
#else
{8, 15, 0x0000000000000001, "RW", "chid5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000001, "RW", "chid4", "Gazelle queue limit for Upstream NP on channel ID 4."},
#else
{0, 7, 0x0000000000000001, "RW", "chid4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo973[] = {{"A_CR_GZLQ_RSVD_CH4_7_MCHBAR", "", 0x00006478, 4, 0x00000000FFFFFFFF, 0x0000000001010101}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields974[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "spare_rw", "Spare RW 32 bits in BIOSWR policy group."},
#else
{0, 31, 0x0000000000000000, "RW", "spare_rw", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo974[] = {{"A_CR_SPARE_BIOS_MCHBAR", "", 0x0000647C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields975[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000004, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000004, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000004, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x0000000000000004, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x000000000000000C, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x000000000000000C, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo975[] = {{"A_CR_UPCMD_CRDTMAX_CH0_0_0_0_MCHBAR", "", 0x00006490, 3, 0x00000000007FFFFF, 0x000000000004040C}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields976[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000004, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000004, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000004, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x0000000000000004, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000004, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x0000000000000004, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo976[] = {{"A_CR_UPCMD_CRDTMAX_CH1_0_0_0_MCHBAR", "", 0x00006494, 3, 0x00000000007FFFFF, 0x0000000000040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields977[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000000, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x000000000000007F, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x000000000000007F, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x0000000000000000, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo977[] = {{"A_CR_UPCMD_CRDTMAX_CH2_0_0_0_MCHBAR", "", 0x00006498, 3, 0x00000000007FFFFF, 0x0000000000007F00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields978[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000000, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x000000000000007F, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x000000000000007F, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x000000000000007F, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x000000000000007F, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo978[] = {{"A_CR_UPCMD_CRDTMAX_CH3_0_0_0_MCHBAR", "", 0x0000649C, 3, 0x00000000007FFFFF, 0x0000000000007F7F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields979[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000000, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000004, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x0000000000000004, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x0000000000000000, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo979[] = {{"A_CR_UPCMD_CRDTMAX_CH4_0_0_0_MCHBAR", "", 0x000064A0, 3, 0x00000000007FFFFF, 0x0000000000000400}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields980[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000000, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000004, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x0000000000000004, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000004, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x0000000000000004, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo980[] = {{"A_CR_UPCMD_CRDTMAX_CH5_0_0_0_MCHBAR", "", 0x000064A4, 3, 0x00000000007FFFFF, 0x0000000000000404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields981[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000000, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000004, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x0000000000000004, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000004, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x0000000000000004, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo981[] = {{"A_CR_UPCMD_CRDTMAX_CH6_0_0_0_MCHBAR", "", 0x000064A8, 3, 0x00000000007FFFFF, 0x0000000000000404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields982[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 22, 0x0000000000000000, "RW", "cmp_max", "Max Cmp credits sent to PSF0 for Chid."},
#else
{16, 22, 0x0000000000000000, "RW", "cmp_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 14, 0x0000000000000004, "RW", "np_max", "Max non-posted credits sent to PSF0 for Chid."},
#else
{8, 14, 0x0000000000000004, "RW", "np_max", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x000000000000000C, "RW", "p_max", "Max posted credits sent to PSF0 for Chid."},
#else
{0, 6, 0x000000000000000C, "RW", "p_max", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo982[] = {{"A_CR_UPCMD_CRDTMAX_CH7_0_0_0_MCHBAR", "", 0x000064AC, 3, 0x00000000007FFFFF, 0x000000000000040C}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields983[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "IMR Enable: Enables access checking for the MOT region.  Note: this does not enable MOT itself merely enables access control checks for transactions that attempt to access the MOT buffer."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO", "tr_en", "Asset Classification (AC)[0]: Trace Enable: Enables snooping of transactions to the IMR region by tracing agents such as MOT.  Reserved and set to 0 for the MOT region, since otherwise this would enable recursive"},
#else
{30, 30, 0x0000000000000000, "RO", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 28, 0x0000000000000000, "RW", "mot_out_base", "Specifies bits 38:24 of the start address of the MOT memory region.  Region size must be a strict poweroftwo at least 16MB and naturally aligned to the size.  These bits are compared with the result of the MOT_OUT_MASK[28:14] applied to bits 38:24 of the incoming address to determine if an access falls within the MOT region."},
#else
{14, 28, 0x0000000000000000, "RW", "mot_out_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo983[] = {{"A_CR_MOT_OUT_BASE_0_0_0_MCHBAR", "", 0x000064C0, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields984[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Asset Classification AC[2]: GT Implicit WB Enable: Enables implicit writebacks to protected region from GT caching agent. When set to 1 enables implicit writeback data HITM data from GT to be returned to the requester.  When set to 0 inhibits HITM data from GT from being returned to the requester.  HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Asset Classification AC[1]: IA Implicit WB Enable: Enables implicit writebacks to protected region from IA caching agent.  When set to 1 enables implicit writeback data HITM data from IA cores to be returned to the requester.  When set to 0 inhibits HITM data from IA cores from being returned to the requester.  HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 28, 0x0000000000000000, "RW", "mot_out_mask", "Specifies the size of the MOT region.  If Request Address [38:24] ANDed with MOT_OUT_MASK[28:14] matches the MOT_OUT_BASE[28:14] then the request falls within the MOT_OUT region"},
#else
{14, 28, 0x0000000000000000, "RW", "mot_out_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo984[] = {{"A_CR_MOT_OUT_MASK_0_0_0_MCHBAR", "", 0x000064C4, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields985[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040001000202, "RW", "p_u_codewr_allrd_cp", "Bit vector used to determine which agents are allowed access to the Aunit P_U_CODEWR_ALLRD based on the value from the agents 6 bit SAI field. This register is selfreferential the access policy provided applies to access to the control register itself."},
#else
{0, 63, 0x0000040001000202, "RW", "p_u_codewr_allrd_cp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo985[] = {{"A_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR", "", 0x000064E0, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040001000202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields986[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "p_u_codewr_allrd_rac", "Bit vector used to determine which agents are allowed Rd access to the Aunit P_U_CODEWR_ALLRD based on the value from the agents 6 bit SAI field."},
#else
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "p_u_codewr_allrd_rac", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo986[] = {{"A_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR", "", 0x000064E8, 1, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields987[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040001000202, "RW", "p_u_codewr_allrd_wac", "Bit vector used to determine which agents are allowed Wr access to the Aunit P_U_CODEWR_ALLRD based on the value from the agents 6 bit SAI field."},
#else
{0, 63, 0x0000040001000202, "RW", "p_u_codewr_allrd_wac", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo987[] = {{"A_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR", "", 0x000064F0, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040001000202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields988[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040061010202, "RW", "bioswr_cp", "Bit vector used to determine which agents are allowed access to the A-Unit BIOSWR Registers based on the value from the agents 6 bit SAI field. This register is selfreferential the access policy provided applies to access to the control register itself."},
#else
{0, 63, 0x0000040061010202, "RW", "bioswr_cp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo988[] = {{"A_CR_BIOSWR_CP_0_0_0_MCHBAR", "", 0x000064C8, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields989[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x80000C0063010217, "RW", "bioswr_rac", "Bit vector used to determine which agents are allowed Rd access to the A-Unit BIOSWR Register based on the value from the agents 6 bit SAI field."},
#else
{0, 63, 0x80000C0063010217, "RW", "bioswr_rac", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo989[] = {{"A_CR_BIOSWR_RAC_0_0_0_MCHBAR", "", 0x000064D0, 1, 0xFFFFFFFFFFFFFFFF, 0x80000C0063010217}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields990[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061000212, "RW", "bioswr_wac", "Bit vector used to determine which agents are allowed Wr access to the A-Unit BIOSWR registers based on the value from the agents 6 bit SAI field."},
#else
{0, 63, 0x00000C0061000212, "RW", "bioswr_wac", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo990[] = {{"A_CR_BIOSWR_WAC_0_0_0_MCHBAR", "", 0x000064D8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061000212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields991[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imrglobal_bm_cp", "Bit vector used to determine which agents are allowed access to the A-Unit IMRGLOBAL_BM Registers based on the value from the agents 6 bit SAI field. This register is selfreferential the access policy provided applies to access to the control register itself."},
#else
{0, 63, 0x00000C0061010202, "RW", "imrglobal_bm_cp", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo991[] = {{"A_CR_IMRGLOBAL_BM_CP_0_0_0_MCHBAR", "", 0x00006510, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields992[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "imrglobal_bm_rac", "Bit vector used to determine which agents are allowed Rd access to the A-Unit IMRGLOBAL_BM Register based on the value from the agents 6 bit SAI field."},
#else
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "imrglobal_bm_rac", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo992[] = {{"A_CR_IMRGLOBAL_BM_RAC_0_0_0_MCHBAR", "", 0x00006518, 1, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields993[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imrglobal_bm_wac", "Bit vector used to determine which agents are allowed Wr access to the A-Unit IMRGLOBAL_BM registers based on the value from the agents 6 bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imrglobal_bm_wac", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo993[] = {{"A_CR_IMRGLOBAL_BM_WAC_0_0_0_MCHBAR", "", 0x00006520, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields994[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "chid_y_cnt_uptxn", "Count upstream txn on all VCs where CHID_Y[i]=1."},
#else
{16, 23, 0x0000000000000000, "RW", "chid_y_cnt_uptxn", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "chid_x_cnt_uptxn", "Count upstream txn on all VCs where CHID_X[i]=1."},
#else
{0, 7, 0x0000000000000000, "RW", "chid_x_cnt_uptxn", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo994[] = {{"A_CR_CHAP_SLCT1_MCHBAR", "", 0x00006500, 2, 0x0000000000FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields995[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RW", "chid_y_cnt_dntxn", "Count downstream txn on all VCs where CHID_Y[i]=1."},
#else
{16, 23, 0x0000000000000000, "RW", "chid_y_cnt_dntxn", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "chid_x_cnt_dntxn", "Count downstream txn on all VCs where CHID_X[i]=1."},
#else
{0, 7, 0x0000000000000000, "RW", "chid_x_cnt_dntxn", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo995[] = {{"A_CR_CHAP_SLCT2_MCHBAR", "", 0x00006504, 2, 0x0000000000FFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields996[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000001, "RW", "q_occupancy_y", "Count occupancy/residency of certain Q in A-Unit\r\n"
"          [list]\r\n"
"	  [*]00: UpCmd  \r\n"
"	  [*]01: UpData\r\n"
"	  [*]10: GzlQ  \r\n"
"	  [*]11: DnCmd/Data\r\n"
"	  [/list]"},
#else
{2, 3, 0x0000000000000001, "RW", "q_occupancy_y", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "q_occupancy_x", "Count occupancy/residency of certain Q in A-Unit\r\n"
"	  [list]\r\n"
"	  [*]00: UpCmd\r\n"
"	  [*]01: UpData\r\n"
"	  [*]10: GzlQ\r\n"
"	  [*]11: DnCmd/Data\r\n"
"	  [/list]"},
#else
{0, 1, 0x0000000000000000, "RW", "q_occupancy_x", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo996[] = {{"A_CR_CHAP_SLCT3_MCHBAR", "", 0x00006508, 2, 0x000000000000000F, 0x0000000000000004}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields997[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "undefined31", "reserved for future use"},
#else
{31, 31, 0x0000000000000000, "RO", "undefined31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO", "undefined30", "reserved for future use"},
#else
{30, 30, 0x0000000000000000, "RO", "undefined30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "undefined29", "reserved for future use"},
#else
{29, 29, 0x0000000000000000, "RO", "undefined29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RO", "undefined28", "reserved for future use"},
#else
{28, 28, 0x0000000000000000, "RO", "undefined28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "undefined27", "reserved for future use"},
#else
{27, 27, 0x0000000000000000, "RO", "undefined27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RO", "undefined26", "reserved for future use"},
#else
{26, 26, 0x0000000000000000, "RO", "undefined26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RO", "undefined25", "reserved for future use"},
#else
{25, 25, 0x0000000000000000, "RO", "undefined25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RO", "undefined24", "reserved for future use"},
#else
{24, 24, 0x0000000000000000, "RO", "undefined24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "undefined23", "reserved for future use"},
#else
{23, 23, 0x0000000000000000, "RO", "undefined23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "undefined22", "reserved for future use"},
#else
{22, 22, 0x0000000000000000, "RO", "undefined22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RO", "undefined21", "reserved for future use"},
#else
{21, 21, 0x0000000000000000, "RO", "undefined21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "undefined20", "reserved for future use"},
#else
{20, 20, 0x0000000000000000, "RO", "undefined20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "undefined19", "reserved for future use"},
#else
{19, 19, 0x0000000000000000, "RO", "undefined19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "undefined18", "reserved for future use"},
#else
{18, 18, 0x0000000000000000, "RO", "undefined18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RO", "undefined17", "reserved for future use"},
#else
{17, 17, 0x0000000000000000, "RO", "undefined17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RO", "undefined16", "reserved for future use"},
#else
{16, 16, 0x0000000000000000, "RO", "undefined16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "undefined15", "reserved for future use"},
#else
{15, 15, 0x0000000000000000, "RO", "undefined15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "undefined14", "reserved for future use"},
#else
{14, 14, 0x0000000000000000, "RO", "undefined14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RO", "undefined13", "reserved for future use"},
#else
{13, 13, 0x0000000000000000, "RO", "undefined13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RO", "undefined12", "reserved for future use"},
#else
{12, 12, 0x0000000000000000, "RO", "undefined12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "undefined11", "reserved for future use"},
#else
{11, 11, 0x0000000000000000, "RO", "undefined11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RW/1C", "msi_rsvd_set", "An MSI was received with reserved bits set"},
#else
{10, 10, 0x0000000000000000, "RW/1C", "msi_rsvd_set", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW/1C", "gpa_overflow", "A transaction was received with a guest physical address that was too large"},
#else
{9, 9, 0x0000000000000000, "RW/1C", "gpa_overflow", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW/1C", "illegal_msi", "A malformed/illegal MSI was received in the upstream direction"},
#else
{8, 8, 0x0000000000000000, "RW/1C", "illegal_msi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW/1C", "at_translated_illegal_device", "A device that is not support to set the AT bit set it to an illegal value"},
#else
{7, 7, 0x0000000000000000, "RW/1C", "at_translated_illegal_device", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "undefined5", "reserved for future use"},
#else
{6, 6, 0x0000000000000000, "RO", "undefined5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW/1C", "bad_sai_cmpl", "An incorrect/illegal sai was received with an upstream completion transaction."},
#else
{5, 5, 0x0000000000000000, "RW/1C", "bad_sai_cmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW/1C", "received_lk_cmpl", "Received a CmplLck completion from iosf."},
#else
{4, 4, 0x0000000000000000, "RW/1C", "received_lk_cmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW/1C", "bad_sai_nonposted", "An incorrect/illegal sai was received with an upstream non-posted transaction."},
#else
{3, 3, 0x0000000000000000, "RW/1C", "bad_sai_nonposted", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW/1C", "illegal_nonposted_opcode", "Illegal/Unsupported non-posted opcode received from iosf."},
#else
{2, 2, 0x0000000000000000, "RW/1C", "illegal_nonposted_opcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/1C", "bad_sai_posted", "An incorrect/illegal sai was received with an upstream posted transaction."},
#else
{1, 1, 0x0000000000000000, "RW/1C", "bad_sai_posted", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/1C", "illegal_posted_opcode", "Illegal/Unsupported posted opcode received from iosf."},
#else
{0, 0, 0x0000000000000000, "RW/1C", "illegal_posted_opcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo997[] = {{"A_CR_UNCERRSTS_0_0_0_MCHBAR", "", 0x00006588, 32, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields998[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000001, "RO", "undefined31", "reserved for future use"},
#else
{31, 31, 0x0000000000000001, "RO", "undefined31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000001, "RO", "undefined30", "reserved for future use"},
#else
{30, 30, 0x0000000000000001, "RO", "undefined30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RO", "undefined29", "reserved for future use"},
#else
{29, 29, 0x0000000000000001, "RO", "undefined29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000001, "RO", "undefined28", "reserved for future use"},
#else
{28, 28, 0x0000000000000001, "RO", "undefined28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000001, "RO", "undefined27", "reserved for future use"},
#else
{27, 27, 0x0000000000000001, "RO", "undefined27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000001, "RO", "undefined26", "reserved for future use"},
#else
{26, 26, 0x0000000000000001, "RO", "undefined26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000001, "RO", "undefined25", "reserved for future use"},
#else
{25, 25, 0x0000000000000001, "RO", "undefined25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000001, "RO", "undefined24", "reserved for future use"},
#else
{24, 24, 0x0000000000000001, "RO", "undefined24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000001, "RO", "undefined23", "reserved for future use"},
#else
{23, 23, 0x0000000000000001, "RO", "undefined23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000001, "RO", "undefined22", "reserved for future use"},
#else
{22, 22, 0x0000000000000001, "RO", "undefined22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000001, "RO", "undefined21", "reserved for future use"},
#else
{21, 21, 0x0000000000000001, "RO", "undefined21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000001, "RO", "undefined20", "reserved for future use"},
#else
{20, 20, 0x0000000000000001, "RO", "undefined20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000001, "RO", "undefined19", "reserved for future use"},
#else
{19, 19, 0x0000000000000001, "RO", "undefined19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000001, "RO", "undefined18", "reserved for future use"},
#else
{18, 18, 0x0000000000000001, "RO", "undefined18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000001, "RO", "undefined17", "reserved for future use"},
#else
{17, 17, 0x0000000000000001, "RO", "undefined17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000001, "RO", "undefined16", "reserved for future use"},
#else
{16, 16, 0x0000000000000001, "RO", "undefined16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000001, "RO", "undefined15", "reserved for future use"},
#else
{15, 15, 0x0000000000000001, "RO", "undefined15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000001, "RO", "undefined14", "reserved for future use"},
#else
{14, 14, 0x0000000000000001, "RO", "undefined14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000001, "RO", "undefined13", "reserved for future use"},
#else
{13, 13, 0x0000000000000001, "RO", "undefined13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000001, "RO", "undefined12", "reserved for future use"},
#else
{12, 12, 0x0000000000000001, "RO", "undefined12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000001, "RO", "undefined11", "reserved for future use"},
#else
{11, 11, 0x0000000000000001, "RO", "undefined11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000001, "RW", "msi_rsvd_set", "An MSI was received with reserved bits set"},
#else
{10, 10, 0x0000000000000001, "RW", "msi_rsvd_set", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000001, "RW", "gpa_overflow", "A transaction was received with a guest physical address that was too large"},
#else
{9, 9, 0x0000000000000001, "RW", "gpa_overflow", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "illegal_msi", "A malformed/illegal MSI was received in the upstream direction"},
#else
{8, 8, 0x0000000000000001, "RW", "illegal_msi", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000001, "RW", "at_translated_illegal_device", "A device that is not support to set the AT bit set it to an illegal value"},
#else
{7, 7, 0x0000000000000001, "RW", "at_translated_illegal_device", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000001, "RO", "undefined5", "reserved for future use"},
#else
{6, 6, 0x0000000000000001, "RO", "undefined5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "bad_sai_cmpl", "An incorrect/illegal sai was received with an upstream completion transaction."},
#else
{5, 5, 0x0000000000000001, "RW", "bad_sai_cmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "received_lk_cmpl", "Received a CmplLck completion from iosf."},
#else
{4, 4, 0x0000000000000001, "RW", "received_lk_cmpl", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "bad_sai_nonposted", "An incorrect/illegal sai was received with an upstream non-posted transaction."},
#else
{3, 3, 0x0000000000000001, "RW", "bad_sai_nonposted", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "illegal_nonposted_opcode", "Illegal/Unsupported non-posted opcode received from iosf."},
#else
{2, 2, 0x0000000000000001, "RW", "illegal_nonposted_opcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "bad_sai_posted", "An incorrect/illegal sai was received with an upstream posted transaction."},
#else
{1, 1, 0x0000000000000001, "RW", "bad_sai_posted", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "illegal_posted_opcode", "Illegal/Unsupported posted opcode received from iosf."},
#else
{0, 0, 0x0000000000000001, "RW", "illegal_posted_opcode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo998[] = {{"A_CR_UNCERRMSK_0_0_0_MCHBAR", "", 0x0000658C, 32, 0x00000000FFFFFFFF, 0x00000000FFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields999[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "lock", "Intended usage is for BIOS to set the LOCK when it updates the CR.  A-Unit implements only storage for this bit.  No hardware exists to implement hardware locking.  \r\n"
"	  [p]NOTE:  B-Unit copy of this bit is used by ucode to protect WRMSR to the B-Unit's CR.  Ucode has no access to the A-Unit's copy of the CR.[/p]"},
#else
{63, 63, 0x0000000000000000, "RW", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 51, 0x0000000000000000, "RW", "ch_hash_mask", "When both PMI channels in a slice are enabled, this field specifies the Channel Hash Mask to be applied on Addr[19:6] postremap DRAM address of the request to compute which PMI channel a request must be routed to.  Relevant only when HVM mode is disabled and only for requests that do not fall under the MOT region.  B-Unit will override the programmed value to include the Channel Selector bit See SLICEHASH.INTERLEAVE_MODE field.  Note that HVM mode and MOT regions have special hash requirements and hence they do not use the CH_HASH_MASK."},
#else
{38, 51, 0x0000000000000000, "RW", "ch_hash_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 37, 0x0000000000000003, "RW", "sym_slice1_channel_enabled", "Specifies which channel is enabled for Slice 1, This is for those cases where Channel 0 or 1 could be disabled for Slice 1\r\n"
"                        If both bits are set then channel select will be based on the Channel Select logic"},
#else
{36, 37, 0x0000000000000003, "RW", "sym_slice1_channel_enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 35, 0x0000000000000003, "RW", "sym_slice0_channel_enabled", "Specifies which channel is enabled for Slice 0, This is for those cases where Channel 0 or 1 could be disabled for Slice 0\r\n"
"                        If both bits are set then channel select will be based on the Channel Select logic"},
#else
{34, 35, 0x0000000000000003, "RW", "sym_slice0_channel_enabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "ch_1_disabled", "Channel 1 in both slices are disabled no memory address mapped to ch 1. All requests sent to channel 0."},
#else
{32, 32, 0x0000000000000000, "RW", "ch_1_disabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enable_pmi_dual_data_mode", "When set to 1, Single Command Interface and Dual Data Interface for Reads and Writes"},
#else
{31, 31, 0x0000000000000000, "RW", "enable_pmi_dual_data_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 19, 0x0000000000000000, "RW", "slice_hash_mask", "When both slices are enabled this field specifies the Slice Hash Mask to be applied on Addr[19:6] physical address of the request to compute which slice a request must be routed to.  Relevant only when HVM mode is disabled and only for physical addresses that do not fall under the Asymmetric Memory Region and the MOT region.  B-Unit will override the programmed value to include the Slice Selector bit See INTERLEAVE_MODE field.  Note that HVM mode nonaddress IDI requests asymmetric memory region and MOT regions have special hash requirements and hence they do not use the SLICE_HASH_MASK."},
#else
{6, 19, 0x0000000000000000, "RW", "slice_hash_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "slice_0_mem_disabled", "Slice 0 is disabled for memory accesses; no memory address mapped to Slice 0 and all memory requests sent to Slice 1.  In BXT, this bit is RO with the value of 0."},
#else
{4, 4, 0x0000000000000000, "RW", "slice_0_mem_disabled", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "interleave_mode", "Default interleave mode that specifies how the Slice Selector and Channel Selector bits are to be determined.  Relevant only when HVM mode is disabled and only for system memory addresses that do not fall under the MOT region or the Asymmetric memory region in the System Address Map.  Legal encodings are 0x0 0x1 and 0x2.  An encoding of 0x3 is treated as if it was 0x2.   When both slices and all four PMI channels are enabled:\r\n"
"	  [list]\r\n"
"	  [*]0h: Default Slice Selector is Addr[10] and Default Channel Selector is Addr[11]  \r\n"
"	  [*]1h: Default Slice Selector is Addr[11] and Default Channel Selector is Addr[12]  \r\n"
"	  [*]2h: Default Slice Selector is Addr[12] and Default Channel Selector is Addr[13]\r\n"
"          [/list]\r\n"
"	  [p]When both slices are enabled but only one channel in each slice enabled:[/p]\r\n"
"          [list]\r\n"
"	  [*]0h: Default Slice Selector is Addr[10]  \r\n"
"	  [*]1h: Default Slice Selector is Addr[11]  \r\n"
"	  [*]2h: Default Slice Selector is Addr[12]  \r\n"
"	  [/list]\r\n"
"	  [p]When only SLICE0 is enabled and both channels on that slice are enabled:[/p]\r\n"
"          [list]\r\n"
"	  [*]0h: Default Channel Selector is Addr[10]  \r\n"
"	  [*]1h: Default Channel Selector is Addr[11]  \r\n"
"	  [*]2h: Default Channel Selector is Addr[12]  \r\n"
"	  [/list]\r\n"
"	  [p]When SLICE0 and only one channel in that slice is enabled this field is not relevant.  B-Unit overrides the setting of the SLICE_HASH_MASK to always include the Slice Selector bit.  Similarly, B-Unit overrides the setting of the CH_HASH_MASK to always include the Channel Selector bit.[/p]"},
#else
{2, 3, 0x0000000000000000, "RW", "interleave_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "hvm_mode", "\r\n"
"	  [list]\r\n"
"	  [*]0: HVM mode is disabled.\r\n"
"	  [*]1: HVM mode is enabled.\r\n"
"          [/list]\r\n"
"	  [p]When HVM mode is enabled, Slice Hash and Channel Hash is done as follows:[/p]\r\n"
"	  [p]Both slices and all four PMI channels enabled:[/p]  \r\n"
"	  [list]\r\n"
"	  [*]Slice Hash is Request Physical Addr[29]\r\n"
"	  [*]Channel Hash is PostRemap Addr[30]\r\n"
"	  [/list]\r\n"
"	  [p]Both slices enabled but only one PMI channel in each slice enabled:[/p]\r\n"
"	  [list]\r\n"
"	  [*]Slice Hash is Request Physical Addr[29]\r\n"
"          [/list]\r\n"
"	  [p]Only one SLICE0 enabled but both PMI channels in SLICE0 enabled:[/p]\r\n"
"	  [list]\r\n"
"	  [*]Channel Hash is PostRemap Addr[29]\r\n"
"          [/list]\r\n"
"	  [p]When HVM_MODE is enabled TOLUD must be set at 2GB.[/p]"},
#else
{1, 1, 0x0000000000000000, "RW", "hvm_mode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "slice_1_disabled", "Slice 1 is disabled; no memory address mapped to Slice 1.  All request sent to Slice 0."},
#else
{0, 0, 0x0000000000000000, "RW", "slice_1_disabled", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo999[] = {{"A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR", "", 0x000065C0, 11, 0xFFFFFFFFFFFFFFFF, 0x0000003C00000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1000[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{32, 47, 0x0000000000000000, "RW", "mirror_limit", "Mirror Limit: specifies b38:b23 of HPA indicating the end of mirror packet buffer region"},
#else
{32, 47, 0x0000000000000000, "RW", "mirror_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "mirror_base", "Mirror Base: specifies b38:b23 of HPA indicating the start of mirror packet buffer region"},
#else
{0, 15, 0x0000000000000000, "RW", "mirror_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1000[] = {{"A_CR_MIRROR_RANGE_0_0_0_MCHBAR", "", 0x000065C8, 2, 0x0000FFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1001[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "slice0_asym_enable", "Setting this bit to 0 disables asymmetric memory region 0; setting it to 1 enables the region."},
#else
{31, 31, 0x0000000000000000, "RW", "slice0_asym_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "slice0_asym_channel_select", "Specifies which Channel in ASYM Slice 0 request is sent"},
#else
{30, 30, 0x0000000000000000, "RW", "slice0_asym_channel_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 29, 0x0000000000000000, "RW", "slice0_asym_limit", "Specifies bits [38:31] of the highest address of asymmetric memory region 0 (in slice 0); all the lower bits of the region's highest address are equal to 1."},
#else
{19, 29, 0x0000000000000000, "RW", "slice0_asym_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RW", "slice0_asym_base", "Specifies bits [38:31] of the base address of asymmetric memory region 0 (in slice 0); all the lower bits of the region's base address are equal to 0."},
#else
{4, 14, 0x0000000000000000, "RW", "slice0_asym_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1001[] = {{"A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR", "", 0x000065D0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1002[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "slice1_asym_enable", "Setting this bit to 0 disables asymmetric memory region 1; setting it to 1 enables the region."},
#else
{31, 31, 0x0000000000000000, "RW", "slice1_asym_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "slice1_asym_channel_select", "Specifies Channel for ASYM Region Slice 1"},
#else
{30, 30, 0x0000000000000000, "RW", "slice1_asym_channel_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 29, 0x0000000000000000, "RW", "slice1_asym_limit", "Specifies bits [38:31] of the highest address of asymmetric memory region 1 (in slice 1); all the lower bits of the region's highest address are equal to 1."},
#else
{19, 29, 0x0000000000000000, "RW", "slice1_asym_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RW", "slice1_asym_base", "Specifies bits [38:31] of the base address of asymmetric memory region 1 (in slice 1); all the lower bits of the region's base address are equal to 0."},
#else
{4, 14, 0x0000000000000000, "RW", "slice1_asym_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1002[] = {{"A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR", "", 0x000065D4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1003[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "asym_2way_interleave_enable", "Setting this bit to 0 disables Interleave Asymmetric memory region 1, setting it to 1 enables the region."},
#else
{31, 31, 0x0000000000000000, "RW", "asym_2way_interleave_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 27, 0x0000000000000000, "RW", "asym_2way_limit", "Specifies bits [38:28] of the highest address of Interleave Asymmetric Region, all the lower bits of the region's highest address are equal to 1."},
#else
{17, 27, 0x0000000000000000, "RW", "asym_2way_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RW", "asym_2way_base", "Specifies bits [38:28] of the base address of Interleave Asymmetric Region; all the lower bits of the region's base address are equal to 0."},
#else
{4, 14, 0x0000000000000000, "RW", "asym_2way_base", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "asym_2way_intlv_mode", "\r\n"
"               Going with 2 bits here.\r\n"
"               2'b00 : Asymmetric memory Split between Channel 0 of Slice 0 and Slice 1\r\n"
"               2'b01 : Asymmetric memory split between Channel 1 of Slice 0 and Slice 1\r\n"
"               2'b10 : Asymmetric memory split between Channel 0 and Channel 1 of Slice 0\r\n"
"               2'b11 : Asymmetric memory split between Channel 0 and Channel 1 of Slice 1\r\n"
"      "},
#else
{0, 1, 0x0000000000000000, "RW", "asym_2way_intlv_mode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1003[] = {{"A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR", "", 0x000065D8, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1004[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x000000000000C5C5, "RO", "did", "The upper 8-bits of this field can be overridden by the SetID IOSF-SB Message."},
#else
{16, 31, 0x000000000000C5C5, "RO", "did", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000008086, "RO", "vid", "Indicates Intel"},
#else
{0, 15, 0x0000000000008086, "RO", "vid", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1004[] = {{"PCIID", "", 0x00000000, 2, 0x00000000FFFFFFFF, 0x00000000C5C58086}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1005[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{11, 15, 0x0000000000000000, "RO", "rsvd", "Reserved"},
#else
{11, 15, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "intd", "P2SB does not issue any interrupts on its own behalf"},
#else
{10, 10, 0x0000000000000000, "RO", "intd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "fb2be", "Not applicable"},
#else
{9, 9, 0x0000000000000000, "RO", "fb2be", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RO", "se", "P2SB does not issue SERR# on its own behalf."},
#else
{8, 8, 0x0000000000000000, "RO", "se", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "rsvd_1", "Reserved"},
#else
{7, 7, 0x0000000000000000, "RO", "rsvd_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "per", "No support for parity error detection."},
#else
{6, 6, 0x0000000000000000, "RO", "per", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RO", "vga", "Not applicable."},
#else
{5, 5, 0x0000000000000000, "RO", "vga", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO", "mwie", "Not applicable."},
#else
{4, 4, 0x0000000000000000, "RO", "mwie", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "sce", "Not applicable."},
#else
{3, 3, 0x0000000000000000, "RO", "sce", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RO", "bme", "Bus mastering cannot be disabled as this device acts as a proxy for non-PCI devices."},
#else
{2, 2, 0x0000000000000001, "RO", "bme", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "mse", "Will control the P2SB acceptance of PCI MMIO BARs only. Other legacy regions are unaffected by this bit."},
#else
{1, 1, 0x0000000000000000, "RW", "mse", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "iose", "Legacy regions are unaffected by this bit."},
#else
{0, 0, 0x0000000000000000, "RW", "iose", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1005[] = {{"PCICMD", "", 0x00000004, 12, 0x000000000000FFFF, 0x0000000000000004}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1006[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RO", "rsvd", "Reserved"},
#else
{0, 15, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1006[] = {{"PCISTS", "", 0x00000006, 1, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1007[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO", "rid", "Indicates the part revision. This will reset to 0 but will overridden by the SetID IOSFSB message during the power-up sequence"},
#else
{0, 7, 0x0000000000000000, "RO", "rid", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1007[] = {{"PCIRID", "", 0x00000008, 1, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1008[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000005, "RO", "bcc", "Indicates a memory controller device class."},
#else
{16, 23, 0x0000000000000005, "RO", "bcc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000080, "RO", "scc", "Indicates an unspecified other memory controller."},
#else
{8, 15, 0x0000000000000080, "RO", "scc", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO", "pi", "No programming interface."},
#else
{0, 7, 0x0000000000000000, "RO", "pi", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1008[] = {{"PCICC", "", 0x00000009, 3, 0x0000000000FFFFFF, 0x0000000000058000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1009[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO", "rsvd", "Reserved"},
#else
{0, 7, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1009[] = {{"PCIMLT", "", 0x0000000D, 1, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1010[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "mfd", "Indicates that this is part of a multi-function device."},
#else
{7, 7, 0x0000000000000000, "RO", "mfd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 6, 0x0000000000000000, "RO", "htype", "Indicates a generic device header."},
#else
{0, 6, 0x0000000000000000, "RO", "htype", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1010[] = {{"PCIHTYPE", "", 0x0000000E, 2, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1011[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "rba", "Lower DWORD of the base address for the sideband register access BAR."},
#else
{24, 31, 0x0000000000000000, "RW", "rba", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 23, 0x0000000000000000, "RO", "hw202rb16mb", "Hardwired to 0 to request a BAR of 16MB"},
#else
{4, 23, 0x0000000000000000, "RO", "hw202rb16mb", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "pref", "Indicates this is not prefetchable."},
#else
{3, 3, 0x0000000000000000, "RO", "pref", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000002, "RO", "atype", "Indicates that this can be placed anywhere in 64b space."},
#else
{1, 2, 0x0000000000000002, "RO", "atype", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "stype", "Indicates memory space"},
#else
{0, 0, 0x0000000000000000, "RO", "stype", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1011[] = {{"SBREG_BAR", "", 0x00000010, 5, 0x00000000FFFFFFFF, 0x0000000000000004}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1012[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "rbah", "Upper DWORD of the base address for the sideband register access BAR."},
#else
{0, 31, 0x0000000000000000, "RW", "rbah", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1012[] = {{"SBREG_BARH", "", 0x00000014, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1013[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW/O", "ssid", "Written by BIOS. Not used by hardware."},
#else
{16, 31, 0x0000000000000000, "RW/O", "ssid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW/O", "ssvid", "Written by BIOS. Not used by hardware."},
#else
{0, 15, 0x0000000000000000, "RW/O", "ssvid", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1013[] = {{"PCIHSS", "", 0x0000002C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1014[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "bus", "N/A"},
#else
{8, 15, 0x0000000000000000, "RW", "bus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x000000000000001F, "RW", "dev", "N/A"},
#else
{3, 7, 0x000000000000001F, "RW", "dev", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "func", "N/A"},
#else
{0, 2, 0x0000000000000000, "RW", "func", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1014[] = {{"VBDF", "", 0x00000050, 3, 0x000000000000FFFF, 0x00000000000000F8}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1015[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "bus", "N/A"},
#else
{8, 15, 0x0000000000000000, "RW", "bus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x000000000000001F, "RW", "dev", "N/A"},
#else
{3, 7, 0x000000000000001F, "RW", "dev", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "func", "N/A"},
#else
{0, 2, 0x0000000000000000, "RW", "func", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1015[] = {{"EBDF", "", 0x00000052, 3, 0x000000000000FFFF, 0x00000000000000F8}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1016[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "rsvd", "N/A"},
#else
{16, 31, 0x0000000000000000, "RW", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x00000000000000D2, "RW", "rprid", "Specifies the  IOSF-SB destination ID for sending Reserved Page Register cycles (e.g. Port 80h).  By default this will load to the ID of the LPC or eSPI device depending on which has been strapped active in the system."},
#else
{8, 15, 0x00000000000000D2, "RW", "rprid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 7, 0x0000000000000000, "RW", "rsvd_1", "N/A"},
#else
{1, 7, 0x0000000000000000, "RW", "rsvd_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rse", "When set, all IO writes to the RTC will be also sent to the PMC.  This allows cases where the battery backed storage is in an external PMIC."},
#else
{0, 0, 0x0000000000000000, "RW", "rse", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1016[] = {{"RCFG", "", 0x00000054, 4, 0x00000000FFFFFFFF, 0x000000000000D200}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1017[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "ae", "When set, the P2SB will decode the High Performance Timer memory address range selected by bits 1:0 below."},
#else
{7, 7, 0x0000000000000000, "RW", "ae", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 6, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{2, 6, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "as", "This 2-bit field selects 1 of 4 possible memory address ranges for the High Performance Timer functionality. The encodings are:\r\n"
"00 : FED0_0000h - FED0_03FFFh\r\n"
"01 : FED0_1000h - FED0_13FFFh\r\n"
"10 : FED0_2000h - FED0_23FFFh\r\n"
"11 : FED0_3000h - FED0_33FFFh"},
#else
{0, 1, 0x0000000000000000, "RW", "as", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1017[] = {{"HPTC", "", 0x00000060, 3, 0x00000000000000FF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1018[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{9, 15, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{9, 15, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "ae", "When set, the P2SB will decode the IOxAPIC memory address range selected by bits 7:0 below."},
#else
{8, 8, 0x0000000000000000, "RW", "ae", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "asel", "These bits define address bits 19:12 for the IOxAPIC range. The default value of 00h enables compatibility with prior products as an initial value. This value must not be changed unless the IOxAPIC Enable bit is cleared."},
#else
{0, 7, 0x0000000000000000, "RW", "asel", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1018[] = {{"IOAC", "", 0x00000064, 3, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1019[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "bus", "N/A"},
#else
{8, 15, 0x0000000000000000, "RW", "bus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x000000000000001F, "RW", "dev", "N/A"},
#else
{3, 7, 0x000000000000001F, "RW", "dev", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "func", "N/A"},
#else
{0, 2, 0x0000000000000000, "RW", "func", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1019[] = {{"IBDF", "", 0x0000006C, 3, 0x000000000000FFFF, 0x00000000000000F8}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1020[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "bus", "N/A"},
#else
{8, 15, 0x0000000000000000, "RW", "bus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x000000000000001F, "RW", "dev", "N/A"},
#else
{3, 7, 0x000000000000001F, "RW", "dev", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "func", "N/A"},
#else
{0, 2, 0x0000000000000000, "RW", "func", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1020[] = {{"HBDF", "", 0x00000070, 3, 0x000000000000FFFF, 0x00000000000000F8}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1021[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted0", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 31-0."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1021[] = {{"SBREGPOSTED0", "", 0x00000080, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1022[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted1", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 63-32."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1022[] = {{"SBREGPOSTED1", "", 0x00000084, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1023[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted2", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 95-64."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted2", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1023[] = {{"SBREGPOSTED2", "", 0x00000088, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1024[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted3", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 127-96."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1024[] = {{"SBREGPOSTED3", "", 0x0000008C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1025[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted4", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 159-128."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1025[] = {{"SBREGPOSTED4", "", 0x00000090, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1026[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted5", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 191-160."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted5", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1026[] = {{"SBREGPOSTED5", "", 0x00000094, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1027[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted6", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 223-192."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted6", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1027[] = {{"SBREGPOSTED6", "", 0x00000098, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1028[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "sbregposted7", "One hot masks for setting SBREG to posted posted for IOSF-SB endpoint IDs 255-224."},
#else
{0, 31, 0x0000000000000000, "RW", "sbregposted7", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1028[] = {{"SBREGPOSTED7", "", 0x0000009C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1029[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{19, 31, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{19, 31, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 18, 0x0000000000000006, "RW", "dtblk", "This register contains the Target BLK field that will be used when sending RAVDM messages to the CPU Complex North Display."},
#else
{16, 18, 0x0000000000000006, "RW", "dtblk", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "bus", "The bus number of the Display in the CPU Complex."},
#else
{8, 15, 0x0000000000000000, "RW", "bus", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x0000000000000002, "RW", "dev", "The bus number of the Display in the CPU Complex."},
#else
{3, 7, 0x0000000000000002, "RW", "dev", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RW", "func", "The function number of the Display in the CPU Complex"},
#else
{0, 2, 0x0000000000000000, "RW", "func", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1029[] = {{"DISPBDF", "", 0x000000A0, 5, 0x00000000FFFFFFFF, 0x0000000000060010}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1030[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "modbase", "This specifies the upper 8b for the 16b address that will be used for sending RAVDM access that target the Modulator Control range of the ICC (FFF00h - FFFFFh)."},
#else
{8, 15, 0x0000000000000000, "RW", "modbase", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "bufbase", "This specifies the upper 8b for the 16b address that will be used for sending RAVDM access that target the Buffer range of the ICC (FFE00h - FFEFFh)."},
#else
{0, 7, 0x0000000000000000, "RW", "bufbase", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1030[] = {{"ICCOS", "", 0x000000A4, 2, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1031[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask0", "One hot masks for disabling IOSF-SB endpoint IDs 31-0."},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1031[] = {{"EPMASK0", "", 0x000000B0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1032[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask1", "One hot masks for disabling IOSF-SB endpoint IDs 63-32."},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1032[] = {{"EPMASK1", "", 0x000000B4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1033[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask2", "One hot masks for disabling IOSF-SB endpoint IDs 95-64"},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask2", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1033[] = {{"EPMASK2", "", 0x000000B8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1034[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask3", "One hot masks for disabling IOSF-SB endpoint IDs 127-96"},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask3", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1034[] = {{"EPMASK3", "", 0x000000BC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1035[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask4", "One hot masks for disabling IOSF-SB endpoint IDs 128-159"},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask4", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1035[] = {{"EPMASK4", "", 0x000000C0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1036[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask5", "One hot masks for disabling IOSF-SB endpoint IDs 191-160"},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask5", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1036[] = {{"EPMASK5", "", 0x000000C4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1037[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask6", "One hot masks for disabling IOSF-SB endpoint IDs 223-192"},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask6", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1037[] = {{"EPMASK6", "", 0x000000C8, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1038[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/L", "epmask7", "One hot masks for disabling IOSF-SB endpoint IDs 255-224"},
#else
{0, 31, 0x0000000000000000, "RW/L", "epmask7", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1038[] = {{"EPMASK7", "", 0x000000CC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1039[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x0000000000000000, "RW", "destid", "The content of this register field is sent in the IOSF Sideband Message Register Access dest field.\r\n"
"See the IOSF Sideband C-spec chapter for Destination ID assignments."},
#else
{24, 31, 0x0000000000000000, "RW", "destid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 23, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{20, 23, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 19, 0x0000000000000000, "RW", "rs", "Destination IOSF-SB Root Space.\r\n"
"*Note: This register may only be written during manufacturing test.  P2SB will only accept writes to this register from transactions with a SAI equal to the SBI_RS_ACCESS_SAI parameter.  This should be assigned to the SAI used by the functional test module (typically TAM) that will perform this register write on IOSF-P."},
#else
{16, 19, 0x0000000000000000, "RW", "rs", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "offset", "Register address offset.  The content of this register field is sent in the IOSF Sideband Message Register Access address(15:0) field."},
#else
{0, 15, 0x0000000000000000, "RW", "offset", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1039[] = {{"SBIADDR", "", 0x000000D0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1040[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/V", "data", "The content of this register field is sent on the IOSF sideband Message Register Access data(31:0) field."},
#else
{0, 31, 0x0000000000000000, "RW/V", "data", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1040[] = {{"SBIDATA", "", 0x000000D4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1041[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "opcode", "This is the Opcode sent in the IOSF sideband message."},
#else
{8, 15, 0x0000000000000000, "RW", "opcode", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RW", "posted", "When set to 1, the message will be send as a posted message instead of non-posted.  This should only be used if the receiver is known to support posted operations for the specified operation."},
#else
{7, 7, 0x0000000000000000, "RW", "posted", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 6, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{3, 6, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 2, 0x0000000000000000, "RO/V", "response", "00 - Successful\r\n"
"01 - Unsuccessful / Not Supported \r\n"
"10 - Powered Down\r\n"
"11 - Multi-cast Mixed\r\n"
"\r\n"
"This register reflects the response status for the previously completed transaction.  The value of this register is only meaningful if SBISTAT.INITRDY is zero."},
#else
{1, 2, 0x0000000000000000, "RO/V", "response", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/1S", "initrdy", "0:  The IOSF sideband interface is ready for a new transaction\r\n"
"1:  The IOSF sideband interface is busy with the previous transaction. \r\n"
"A write to set this register bit to 1 will trigger an IOSF sideband message on the private IOSF sideband interface. The message will be formed based on the values programmed in the Sideband Message Interface Register Access registers. \r\n"
"Software needs to ensure that the interface is not busy (SBISTAT.INITRDY is clear) before writing to this register."},
#else
{0, 0, 0x0000000000000000, "RW/1S", "initrdy", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1041[] = {{"SBISTAT", "", 0x000000D8, 5, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1042[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "fbe", "The content of this field is sent in the IOSF Sideband Register Access FBE field."},
#else
{12, 15, 0x0000000000000000, "RW", "fbe", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{11, 11, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 10, 0x0000000000000000, "RW", "bar", "The contents of this field are sent in the IOSF Sideband Register Access BAR field.  This should be zero performing a Memory Mapped operation to a PCI compliant device."},
#else
{8, 10, 0x0000000000000000, "RW", "bar", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "fid", "The contents of this field are sent in the IOSF Sideband Register access FID field.\r\n"
"This field should generally remain at zero unless specifically required by a particular application."},
#else
{0, 7, 0x0000000000000000, "RW", "fid", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1042[] = {{"SBIRID", "", 0x000000DA, 4, 0x000000000000FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1043[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW/V", "addr", "The content of this register field is sent on the IOSF sideband Message Register Access address(48:32) field.\r\n"
"This must be set to all 0 if 16b addressing is desired."},
#else
{0, 31, 0x0000000000000000, "RW/V", "addr", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1043[] = {{"SBIEXTADDR", "", 0x000000DC, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1044[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{18, 31, 0x0000000000000000, "RW", "rsvd", "N/A"},
#else
{18, 31, 0x0000000000000000, "RW", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW/O", "masklock", "Locks the value of the EPMASK[0-7] registers.  Once this value is written to a one it may only be cleared by a reset."},
#else
{17, 17, 0x0000000000000000, "RW/O", "masklock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "pgcbcge", "When asserted the P2SB can de-assert the clock request to disable the PGCB clock dynamically when it reaches the power down idle state."},
#else
{16, 16, 0x0000000000000000, "RW", "pgcbcge", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 15, 0x0000000000000000, "RW", "rsvd_1", "Hardware will not allocate these bits for any purpose in the future so that BIOS can always write to the HIDE field with this byte enabled without having to remember any other field values since it will not be possible to do a read-modify-write when the device is hidden."},
#else
{9, 15, 0x0000000000000000, "RW", "rsvd_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "hide", "When this bit is set, the P2SB will return 1s on any PCI Configuration Read on IOSF-P.  All other transactions including PCI Configuration Writes are unaffected by this.  This does not affect reads performed on the IOSF-SB interface."},
#else
{8, 8, 0x0000000000000000, "RW", "hide", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 7, 0x0000000000000000, "RW", "rsvd_2", "N/A"},
#else
{3, 7, 0x0000000000000000, "RW", "rsvd_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000007, "RW", "maxw", "This controls the max number of outstanding writes on IOSF-SB initiated by MMIO writes to the SBREG_BAR.\r\n"
"Once the number of SBREG_BAR writes issued but not completed on IOSF-SB is equal to this value no new requests will be forwarded until completions are received.  \r\n"
"A value of zero will have the same behavior as the value of one (single write outstanding)."},
#else
{0, 2, 0x0000000000000007, "RW", "maxw", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1044[] = {{"P2SBC", "", 0x000000E0, 7, 0x00000000FFFFFFFF, 0x0000000000000007}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1045[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{6, 7, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "hae", "When set, the P2SB will automatically engage power gating when it has reached its idle condition."},
#else
{5, 5, 0x0000000000000000, "RW", "hae", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 4, 0x0000000000000000, "RO", "rsvd_1", "N/A"},
#else
{3, 4, 0x0000000000000000, "RO", "rsvd_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RO", "d3he", "No support for D3 Hot power gating."},
#else
{2, 2, 0x0000000000000000, "RO", "d3he", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RO", "i3e", "No support for S0i3 power gating."},
#else
{1, 1, 0x0000000000000000, "RO", "i3e", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "pmcpg_en", "When set to 1, the P2SB will engage power gating if it is idle and the pmc_p2sb_sw_pg_req_b signal is asserted."},
#else
{0, 0, 0x0000000000000001, "RW", "pmcpg_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1045[] = {{"PCE", "", 0x000000E4, 6, 0x00000000000000FF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1046[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000000, "RW", "rsvd", "N/A"},
#else
{12, 15, 0x0000000000000000, "RW", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000001, "RW", "tirstup", "Value representing the number of delay clocks required between the deassertion of pgcb_force_prim_rst_b and the next state in the FSM (varies).\r\n"
"               00:  1 clock \r\n"
"               01:  2 clocks (default)\r\n"
"               10:  8 clocks \r\n"
"               11:  256 clocks\r\n"
"              "},
#else
{10, 11, 0x0000000000000001, "RW", "tirstup", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000001, "RW", "tdeisolate", "Value representing the minimum number of delay clocks required between the deassertion of pgcb_isol_en_b until the restore flow begins.\r\n"
"               00:  1 clock \r\n"
"               01:  2 clocks (default)\r\n"
"               10:  8 clocks \r\n"
"               11:  256 clocks\r\n"
"              "},
#else
{8, 9, 0x0000000000000001, "RW", "tdeisolate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000001, "RW", "tslpinactv", "Value representing the minimum number of delay clocks required between the deassertion of pgcb_sleep to the deassertion of either pgcb_ip_*_lock_req_b from state retention or pgcb_isol_en_b from a non-retention state.\r\n"
"00:  1 clock \r\n"
"01:  2 clocks (default)\r\n"
"10:  8 clocks \r\n"
"11:  256 clocks\r\n"
""},
#else
{6, 7, 0x0000000000000001, "RW", "tslpinactv", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 5, 0x0000000000000001, "RW", "tresetact", "Value representing the minimum number of delay clocks required between the assertion of pgcb_force_prim_rst_b (and pgcb_force_rst_b) to either the assertion of pgcb_pmc_pg_req_b for state retention or pgcb_sleep for non-retention.\r\n"
"00:  1 clock \r\n"
"01:  2 clocks (default)\r\n"
"10:  8 clocks \r\n"
"11:  256 clocks\r\n"
""},
#else
{4, 5, 0x0000000000000001, "RW", "tresetact", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000001, "RW", "tisolate", "alue representing the minimum number of pgcb_clk cyles required between the assertion of pgcb_isol_en_b to the assertion of pgcb_force_prim_rst_b and pgcb_force_rst_b.\r\n"
"00:  1 clock \r\n"
"01:  2 clocks (default)\r\n"
"10:  8 clocks \r\n"
"11:  256 clocks\r\n"
""},
#else
{2, 3, 0x0000000000000001, "RW", "tisolate", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000001, "RW", "tsleepact", "Value representing the minimum number of pgcb_clk cyles required between the assertion of pgcb_sleep (and the deassertion of pgcb_isol_latchen) to the assertion of pgcb_isol_en_b.\r\n"
"00:  1 clock \r\n"
"01:  2 clocks (default)\r\n"
"10:  8 clocks \r\n"
"11:  256 clocks\r\n"
""},
#else
{0, 1, 0x0000000000000001, "RW", "tsleepact", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1046[] = {{"PGCBT", "", 0x000000E6, 7, 0x000000000000FFFF, 0x0000000000000555}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1047[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000003, "RW", "ckreqho", "Defines the amount of idle time required between locking for power gate preparation and deassertion of the prim_clkreq signal.  This field defines the exponent such that the actual delay = 2^ CKREQHO."},
#else
{12, 15, 0x0000000000000003, "RW", "ckreqho", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000003, "RW", "lockho", "Defines the amount of idle time required between local clock gating and locking for power gate preparation (if power gating is enabled).  This field defines the exponent such that the actual delay = 2^ LOCKHO."},
#else
{8, 11, 0x0000000000000003, "RW", "lockho", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000003, "RW", "cgateho", "Defines the amount of idle time required before local clock gating will be engaged (if enabled).  This field defines the exponent such that the actual delay = 2^ CGATEHO."},
#else
{4, 7, 0x0000000000000003, "RW", "cgateho", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rsvd", "N/A"},
#else
{2, 3, 0x0000000000000000, "RW", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ckreqd", "N/A"},
#else
{1, 1, 0x0000000000000000, "RW", "ckreqd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cgd", "When set to 1, the local clock gating for the IOSF-P clock domain within the P2SB will be disabled."},
#else
{0, 0, 0x0000000000000000, "RW", "cgd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1047[] = {{"PDOMAIN", "", 0x000000E8, 6, 0x000000000000FFFF, 0x0000000000003330}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1048[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{12, 15, 0x0000000000000003, "RW", "ckreqho", "Defines the amount of idle time required between locking for power gate preparation and deassertion of the prim_clkreq signal.  This field defines the exponent such that the actual delay = 2^ SCKREQHO."},
#else
{12, 15, 0x0000000000000003, "RW", "ckreqho", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 11, 0x0000000000000003, "RW", "lockho", "Defines the amount of idle time required between local clock gating and locking for power gate preparation (if power gating is enabled).  This field defines the exponent such that the actual delay = 2^ PLOCKHO."},
#else
{8, 11, 0x0000000000000003, "RW", "lockho", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000003, "RW", "cgateho", "Defines the amount of idle time required before local clock gating will be engaged (if enabled).  This field defines the exponent such that the actual delay = 2^ CGATEHO."},
#else
{4, 7, 0x0000000000000003, "RW", "cgateho", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "rsvd", "N/A"},
#else
{2, 3, 0x0000000000000000, "RW", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "ckreqd", "N/A"},
#else
{1, 1, 0x0000000000000000, "RW", "ckreqd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "cgd", "When set to 1, the local clock gating for the IOSF-P clock domain within the P2SB will be disabled."},
#else
{0, 0, 0x0000000000000000, "RW", "cgd", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1048[] = {{"SDOMAIN", "", 0x000000EA, 6, 0x000000000000FFFF, 0x0000000000003330}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1049[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x0000000000000000, "RO", "rsvd", "N/A"},
#else
{28, 31, 0x0000000000000000, "RO", "rsvd", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 27, 0x0000000000000000, "RO", "dot", "Indicates the dot process"},
#else
{24, 27, 0x0000000000000000, "RO", "dot", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x0000000000000000, "RO", "msid", "This field is incremented for each stepping of the part.\r\n"
"\r\n"
"Note that this field can be used by software to differentiate steppings when the Stepping Revision ID may not change."},
#else
{16, 23, 0x0000000000000000, "RO", "msid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x000000000000000F, "RO", "mid", "0Fh = Intel"},
#else
{8, 15, 0x000000000000000F, "RO", "mid", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RO", "proc", "Indicates the process.  The dot portion of the process is reflected in bits (27:24)"},
#else
{0, 7, 0x0000000000000000, "RO", "proc", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1049[] = {{"MANID", "", 0x000000F8, 5, 0x00000000FFFFFFFF, 0x0000000000000F00}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1050[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{4, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{4, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "send_boot_vector_to_dram", "When set,IA accesses to 0xFFFF_0000 to 0XFFFF_FFFF will be sent to memory, regardless of the Host IO Boundary setting in TOLUD."},
#else
{3, 3, 0x0000000000000000, "RW", "send_boot_vector_to_dram", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "absegindram", "When this bit is set, reads and writes targeting A or Bsegments are routed to DRAM. Asegment corresponds to the memory range 0xA_0000 to 0xA_FFFF. Bsegment corresponds to the memory ranges 0xB_0000 to 0xB_7FFF and 0xB_8000 to 0xB_FFFF."},
#else
{2, 2, 0x0000000000000001, "RW", "absegindram", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "read_fseg_from_dram", "When this bit is set, reads targeting Fsegment are routed to DRAM. Fsegment corresponds to the memory range 0xF_0000 to 0xF_FFFF."},
#else
{1, 1, 0x0000000000000001, "RW", "read_fseg_from_dram", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "read_eseg_from_dram", "When this bit is set, reads targeting Esegment are routed to DRAM. Esegment corresponds to the memory range 0xE_0000 to 0xE_FFFF."},
#else
{0, 0, 0x0000000000000001, "RW", "read_eseg_from_dram", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1050[] = {{"B_CR_BMISC_0_0_0_MCHBAR", "", 0x00006800, 5, 0x00000000FFFFFFFF, 0x0000000000000007}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1051[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000000000000000, "RO", "sec_sai_pol", "Bit vector used to determine which agents are allowed access to the BIARAC, BIAWAC and BIACP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x0000000000000000, "RO", "sec_sai_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1051[] = {{"B_CR_SECURITY_CP_0_0_0_MCHBAR", "", 0x00006808, 1, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1052[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RO", "sec_sai_pol", "Bit vector used to determine which agents are allowed read access to the B-Unit Security Group Configuration registers based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x00000C0061010202, "RO", "sec_sai_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1052[] = {{"B_CR_SECURITY_RAC_0_0_0_MCHBAR", "", 0x00006810, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1053[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RO", "sec_sai_pol", "Bit vector used to determine which agents are allowed write access to the B-Unit Security Group Configuration registers, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x00000C0061010202, "RO", "sec_sai_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1053[] = {{"B_CR_SECURITY_WAC_0_0_0_MCHBAR", "", 0x00006818, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1054[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "mem_access_count", "Counts the number of PMI transactions that the B-Unit has sent to any PMI channel. Counts both reads and writes. Counter is not saturating and will roll over to zero. It is up to the consumer of the counter to handle roll over cases."},
#else
{0, 31, 0x0000000000000000, "RO/V", "mem_access_count", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1054[] = {{"B_CR_MEM_ACCESS_COUNT_SLICE0", "", 0x00006868, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1055[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO/V", "mem_access_count", "Counts the number of PMI transactions that the B-Unit has sent to any PMI channel. Counts both reads and writes. Counter is not saturating and will roll over to zero. It is up to the consumer of the counter to handle roll over cases."},
#else
{0, 31, 0x0000000000000000, "RO/V", "mem_access_count", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1055[] = {{"B_CR_MEM_ACCESS_COUNT_SLICE1", "", 0x0000686C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1056[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr0_base", "Specifies bits 38:10 of the start address of IMR0 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR0MASK[28:0] applied to bits 38:10 of the incoming address, to determine if an access falls within the IMR0 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr0_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1056[] = {{"B_CR_BIMR0BASE_0_0_0_MCHBAR", "", 0x00006870, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1057[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables return to the requester of implicit writeback HITM data from GT. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr0_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR0BASE[28:0] value. A match indicates that the incoming address falls within the IMR0 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr0_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1057[] = {{"B_CR_BIMR0MASK_0_0_0_MCHBAR", "", 0x00006874, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1058[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr0_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR0RAC, BIMR0WAC and BIMR0CP registers based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr0_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1058[] = {{"B_CR_BIMR0CP_0_0_0_MCHBAR", "", 0x00006878, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1059[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr0_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr0_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr0_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr0_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr0_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr0_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr0_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr0_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr0_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr0_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr0_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr0_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr0_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr0_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr0_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr0_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr0_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr0_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr0_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr0_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr0_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr0_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr0_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr0_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr0_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr0_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr0_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr0_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr0_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr0_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr0_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr0_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr0_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr0_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr0_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr0_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr0_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr0_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr0_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr0_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr0_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr0_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr0_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr0_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr0_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr0_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr0_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr0_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr0_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr0_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr0_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr0_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr0_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr0_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr0_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr0_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr0_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr0_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr0_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr0_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr0_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr0_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr0_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr0_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr0_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr0_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr0_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr0_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr0_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr0_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr0_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr0_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr0_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr0_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr0_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr0_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr0_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr0_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr0_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr0_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr0_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr0_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr0_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr0_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr0_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr0_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr0_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr0_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr0_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr0_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr0_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr0_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr0_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr0_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr0_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr0_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr0_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr0_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr0_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr0_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr0_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr0_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr0_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr0_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr0_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr0_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr0_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr0_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr0_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr0_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr0_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr0_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr0_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr0_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr0_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr0_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr0_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr0_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr0_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr0_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr0_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr0_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr0_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr0_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr0_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr0_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr0_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr0_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1059[] = {{"B_CR_BIMR0RAC_0_0_0_MCHBAR", "", 0x00006880, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1060[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr0_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr0_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr0_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr0_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr0_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr0_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr0_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr0_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr0_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr0_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr0_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr0_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr0_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr0_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr0_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr0_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr0_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr0_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr0_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr0_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr0_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr0_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr0_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr0_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr0_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr0_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr0_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr0_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr0_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr0_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr0_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr0_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr0_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr0_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr0_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr0_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr0_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr0_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr0_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr0_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr0_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr0_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr0_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr0_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr0_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr0_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr0_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr0_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr0_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr0_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr0_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr0_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr0_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr0_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr0_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr0_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr0_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr0_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr0_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr0_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr0_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr0_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr0_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr0_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr0_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr0_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr0_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr0_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr0_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr0_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr0_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr0_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr0_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr0_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr0_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr0_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr0_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr0_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr0_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr0_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr0_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr0_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr0_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr0_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr0_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr0_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr0_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr0_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr0_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr0_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr0_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr0_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr0_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr0_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr0_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr0_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr0_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr0_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr0_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr0_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr0_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr0_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr0_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr0_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr0_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr0_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr0_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr0_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr0_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr0_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr0_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr0_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr0_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr0_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr0_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr0_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr0_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr0_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr0_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr0_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr0_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr0_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr0_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr0_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr0_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr0_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr0_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR0 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr0_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1060[] = {{"B_CR_BIMR0WAC_0_0_0_MCHBAR", "", 0x00006888, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1061[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Asset Classification AC[0]: Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr1_base", "Specifies bits 38:10 of the start address of IMR1 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR1MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR1 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr1_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1061[] = {{"B_CR_BIMR1BASE_0_0_0_MCHBAR", "", 0x00006890, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1062[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Asset Classification AC[2]: Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables return to the requester of implicit writeback HITM data from GT. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr1_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR1BASE[28:0] value. A match indicates that the incoming address falls within the IMR1 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr1_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1062[] = {{"B_CR_BIMR1MASK_0_0_0_MCHBAR", "", 0x00006894, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1063[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr1_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR1RAC, BIMR1WAC and BIMR1CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr1_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1063[] = {{"B_CR_BIMR1CP_0_0_0_MCHBAR", "", 0x00006898, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1064[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr1_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr1_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr1_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr1_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr1_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr1_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr1_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr1_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr1_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr1_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr1_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr1_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr1_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr1_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr1_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr1_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr1_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr1_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr1_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr1_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr1_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr1_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr1_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr1_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr1_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr1_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr1_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr1_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr1_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr1_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr1_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr1_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr1_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr1_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr1_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr1_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr1_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr1_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr1_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr1_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr1_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr1_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr1_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr1_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr1_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr1_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr1_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr1_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr1_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr1_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr1_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr1_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr1_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr1_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr1_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr1_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr1_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr1_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr1_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr1_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr1_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr1_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr1_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr1_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr1_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr1_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr1_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr1_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr1_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr1_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr1_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr1_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr1_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr1_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr1_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr1_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr1_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr1_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr1_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr1_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr1_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr1_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr1_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr1_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr1_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr1_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr1_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr1_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr1_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr1_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr1_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr1_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr1_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr1_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr1_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr1_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr1_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr1_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr1_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr1_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr1_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr1_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr1_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr1_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr1_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr1_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr1_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr1_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr1_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr1_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr1_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr1_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr1_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr1_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr1_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr1_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr1_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr1_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr1_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr1_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr1_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr1_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr1_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr1_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr1_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr1_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr1_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr1_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1064[] = {{"B_CR_BIMR1RAC_0_0_0_MCHBAR", "", 0x000068A0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1065[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr1_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr1_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr1_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr1_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr1_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr1_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr1_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr1_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr1_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr1_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr1_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr1_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr1_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr1_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr1_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr1_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr1_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr1_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr1_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr1_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr1_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr1_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr1_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr1_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr1_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr1_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr1_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr1_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr1_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr1_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr1_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr1_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr1_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr1_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr1_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr1_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr1_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr1_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr1_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr1_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr1_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr1_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr1_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr1_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr1_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr1_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr1_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr1_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr1_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr1_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr1_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr1_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr1_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr1_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr1_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr1_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr1_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr1_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr1_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr1_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr1_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr1_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr1_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr1_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr1_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr1_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr1_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr1_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr1_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr1_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr1_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr1_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr1_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr1_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr1_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr1_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr1_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr1_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr1_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr1_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr1_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr1_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr1_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr1_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr1_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr1_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr1_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr1_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr1_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr1_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr1_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr1_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr1_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr1_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr1_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr1_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr1_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr1_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr1_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr1_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr1_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr1_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr1_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr1_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr1_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr1_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr1_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr1_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr1_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr1_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr1_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr1_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr1_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr1_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr1_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr1_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr1_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr1_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr1_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr1_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr1_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr1_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr1_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr1_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr1_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr1_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr1_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR1 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr1_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1065[] = {{"B_CR_BIMR1WAC_0_0_0_MCHBAR", "", 0x000068A8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1066[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr2_base", "Specifies bits 38:10 of the start address of IMR2 region. IMR region size must be a strict power of two, at least 1KB and naturally aligned to the size.  These bits are compared with the result of the IMR2MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR2 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr2_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1066[] = {{"B_CR_BIMR2BASE_0_0_0_MCHBAR", "", 0x000068B0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1067[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester.  When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr2_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR2BASE[28:0] value. A match indicates that the incoming address falls within the IMR2 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr2_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1067[] = {{"B_CR_BIMR2MASK_0_0_0_MCHBAR", "", 0x000068B4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1068[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr2_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR2RAC, BIMR2WAC and BIMR2CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr2_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1068[] = {{"B_CR_BIMR2CP_0_0_0_MCHBAR", "", 0x000068B8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1069[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr2_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr2_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr2_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr2_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr2_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr2_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr2_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr2_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr2_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr2_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr2_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr2_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr2_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr2_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr2_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr2_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr2_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr2_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr2_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr2_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr2_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr2_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr2_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr2_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr2_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr2_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr2_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr2_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr2_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr2_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr2_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr2_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr2_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr2_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr2_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr2_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr2_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr2_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr2_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr2_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr2_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr2_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr2_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr2_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr2_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr2_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr2_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr2_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr2_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr2_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr2_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr2_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr2_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr2_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr2_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr2_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr2_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr2_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr2_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr2_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr2_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr2_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr2_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr2_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr2_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr2_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr2_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr2_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr2_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr2_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr2_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr2_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr2_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr2_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr2_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr2_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr2_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr2_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr2_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr2_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr2_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr2_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr2_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr2_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr2_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr2_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr2_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr2_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr2_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr2_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr2_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr2_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr2_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr2_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr2_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr2_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr2_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr2_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr2_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr2_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr2_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr2_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr2_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr2_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr2_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr2_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr2_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr2_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr2_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr2_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr2_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr2_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr2_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr2_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr2_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr2_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr2_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr2_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr2_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr2_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr2_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr2_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr2_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr2_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr2_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr2_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr2_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr2_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1069[] = {{"B_CR_BIMR2RAC_0_0_0_MCHBAR", "", 0x000068C0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1070[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr2_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr2_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr2_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr2_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr2_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr2_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr2_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr2_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr2_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr2_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr2_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr2_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr2_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr2_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr2_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr2_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr2_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr2_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr2_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr2_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr2_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr2_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr2_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr2_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr2_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr2_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr2_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr2_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr2_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr2_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr2_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr2_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr2_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr2_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr2_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr2_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr2_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr2_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr2_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr2_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr2_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr2_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr2_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr2_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr2_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr2_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr2_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr2_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr2_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr2_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr2_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr2_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr2_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr2_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr2_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr2_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr2_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr2_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr2_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr2_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr2_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr2_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr2_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr2_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr2_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr2_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr2_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr2_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr2_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr2_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr2_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr2_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr2_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr2_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr2_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr2_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr2_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr2_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr2_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr2_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr2_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr2_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr2_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr2_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr2_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr2_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr2_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr2_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr2_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr2_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr2_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr2_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr2_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr2_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr2_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr2_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr2_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr2_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr2_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr2_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr2_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr2_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr2_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr2_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr2_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr2_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr2_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr2_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr2_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr2_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr2_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr2_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr2_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr2_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr2_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr2_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr2_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr2_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr2_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr2_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr2_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr2_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr2_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr2_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr2_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr2_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr2_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR2 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr2_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1070[] = {{"B_CR_BIMR2WAC_0_0_0_MCHBAR", "", 0x000068C8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1071[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr3_base", "Specifies bits 38:10 of the start address of IMR3 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR3MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR3 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr3_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1071[] = {{"B_CR_BIMR3BASE_0_0_0_MCHBAR", "", 0x000068D0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1072[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester.  When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester.  When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr3_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR3BASE[28:0] value. A match indicates that the incoming address falls within the IMR3 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr3_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1072[] = {{"B_CR_BIMR3MASK_0_0_0_MCHBAR", "", 0x000068D4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1073[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr3_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR3RAC, BIMR3WAC and BIMR3CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr3_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1073[] = {{"B_CR_BIMR3CP_0_0_0_MCHBAR", "", 0x000068D8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1074[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr3_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr3_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr3_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr3_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr3_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr3_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr3_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr3_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr3_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr3_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr3_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr3_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr3_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr3_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr3_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr3_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr3_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr3_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr3_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr3_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr3_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr3_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr3_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr3_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr3_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr3_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr3_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr3_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr3_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr3_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr3_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr3_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr3_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr3_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr3_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr3_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr3_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr3_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr3_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr3_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr3_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr3_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr3_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr3_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr3_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr3_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr3_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr3_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr3_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr3_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr3_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr3_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr3_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr3_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr3_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr3_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr3_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr3_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr3_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr3_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr3_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr3_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr3_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr3_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr3_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr3_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr3_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr3_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr3_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr3_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr3_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr3_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr3_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr3_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr3_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr3_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr3_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr3_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr3_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr3_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr3_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr3_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr3_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr3_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr3_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr3_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr3_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr3_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr3_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr3_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr3_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr3_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr3_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr3_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr3_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr3_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr3_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr3_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr3_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr3_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr3_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr3_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr3_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr3_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr3_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr3_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr3_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr3_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr3_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr3_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr3_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr3_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr3_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr3_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr3_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr3_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr3_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr3_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr3_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr3_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr3_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr3_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr3_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr3_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr3_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr3_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr3_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr3_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1074[] = {{"B_CR_BIMR3RAC_0_0_0_MCHBAR", "", 0x000068E0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1075[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr3_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr3_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr3_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr3_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr3_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr3_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr3_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr3_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr3_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr3_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr3_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr3_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr3_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr3_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr3_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr3_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr3_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr3_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr3_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr3_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr3_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr3_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr3_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr3_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr3_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr3_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr3_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr3_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr3_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr3_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr3_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr3_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr3_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr3_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr3_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr3_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr3_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr3_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr3_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr3_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr3_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr3_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr3_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr3_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr3_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr3_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr3_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr3_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr3_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr3_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr3_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr3_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr3_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr3_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr3_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr3_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr3_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr3_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr3_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr3_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr3_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr3_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr3_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr3_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr3_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr3_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr3_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr3_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr3_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr3_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr3_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr3_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr3_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr3_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr3_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr3_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr3_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr3_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr3_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr3_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr3_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr3_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr3_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr3_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr3_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr3_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr3_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr3_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr3_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr3_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr3_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr3_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr3_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr3_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr3_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr3_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr3_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr3_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr3_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr3_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr3_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr3_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr3_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr3_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr3_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr3_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr3_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr3_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr3_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr3_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr3_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr3_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr3_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr3_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr3_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr3_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr3_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr3_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr3_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr3_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr3_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr3_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr3_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr3_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr3_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr3_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr3_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR3 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr3_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1075[] = {{"B_CR_BIMR3WAC_0_0_0_MCHBAR", "", 0x000068E8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1076[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr4_base", "Specifies bits 38:10 of the start address of IMR4 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR4MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR4 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr4_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1076[] = {{"B_CR_BIMR4BASE_0_0_0_MCHBAR", "", 0x000068F0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1077[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr4_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR4BASE[28:0] value. A match indicates that the incoming address falls within the IMR4 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr4_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1077[] = {{"B_CR_BIMR4MASK_0_0_0_MCHBAR", "", 0x000068F4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1078[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr4_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR4RAC, BIMR4WAC and BIMR4CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr4_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1078[] = {{"B_CR_BIMR4CP_0_0_0_MCHBAR", "", 0x000068F8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1079[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr4_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr4_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr4_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr4_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr4_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr4_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr4_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr4_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr4_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr4_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr4_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr4_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr4_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr4_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr4_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr4_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr4_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr4_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr4_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr4_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr4_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr4_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr4_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr4_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr4_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr4_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr4_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr4_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr4_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr4_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr4_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr4_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr4_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr4_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr4_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr4_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr4_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr4_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr4_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr4_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr4_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr4_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr4_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr4_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr4_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr4_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr4_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr4_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr4_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr4_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr4_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr4_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr4_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr4_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr4_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr4_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr4_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr4_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr4_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr4_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr4_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr4_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr4_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr4_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr4_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr4_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr4_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr4_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr4_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr4_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr4_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr4_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr4_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr4_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr4_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr4_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr4_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr4_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr4_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr4_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr4_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr4_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr4_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr4_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr4_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr4_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr4_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr4_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr4_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr4_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr4_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr4_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr4_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr4_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr4_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr4_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr4_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr4_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr4_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr4_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr4_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr4_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr4_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr4_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr4_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr4_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr4_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr4_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr4_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr4_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr4_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr4_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr4_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr4_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr4_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr4_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr4_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr4_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr4_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr4_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr4_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr4_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr4_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr4_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr4_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr4_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr4_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr4_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1079[] = {{"B_CR_BIMR4RAC_0_0_0_MCHBAR", "", 0x00006900, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1080[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr4_write_pol_63", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr4_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr4_write_pol_62", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr4_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr4_write_pol_61", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr4_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr4_write_pol_60", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr4_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr4_write_pol_59", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr4_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr4_write_pol_58", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr4_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr4_write_pol_57", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr4_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr4_write_pol_56", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr4_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr4_write_pol_55", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr4_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr4_write_pol_54", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr4_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr4_write_pol_53", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr4_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr4_write_pol_52", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr4_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr4_write_pol_51", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr4_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr4_write_pol_50", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr4_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr4_write_pol_49", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr4_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr4_write_pol_48", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr4_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr4_write_pol_47", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr4_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr4_write_pol_46", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr4_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr4_write_pol_45", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr4_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr4_write_pol_44", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr4_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr4_write_pol_43", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr4_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr4_write_pol_42", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr4_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr4_write_pol_41", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr4_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr4_write_pol_40", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr4_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr4_write_pol_39", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr4_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr4_write_pol_38", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr4_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr4_write_pol_37", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr4_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr4_write_pol_36", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr4_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr4_write_pol_35", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr4_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr4_write_pol_34", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr4_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr4_write_pol_33", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr4_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr4_write_pol_32", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr4_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr4_write_pol_31", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr4_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr4_write_pol_30", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr4_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr4_write_pol_29", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr4_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr4_write_pol_28", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr4_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr4_write_pol_27", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr4_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr4_write_pol_26", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr4_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr4_write_pol_25", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr4_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr4_write_pol_24", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr4_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr4_write_pol_23", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr4_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr4_write_pol_22", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr4_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr4_write_pol_21", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr4_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr4_write_pol_20", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr4_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr4_write_pol_19", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr4_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr4_write_pol_18", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr4_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr4_write_pol_17", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr4_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr4_write_pol_16", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr4_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr4_write_pol_15", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr4_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr4_write_pol_14", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr4_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr4_write_pol_13", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr4_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr4_write_pol_12", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr4_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr4_write_pol_11", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr4_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr4_write_pol_10", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr4_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr4_write_pol_9", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr4_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr4_write_pol_8", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr4_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr4_write_pol_7", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr4_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr4_write_pol_6", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr4_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr4_write_pol_5", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr4_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr4_write_pol_4", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr4_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr4_write_pol_3", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr4_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr4_write_pol_2", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr4_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr4_write_pol_1", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr4_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr4_write_pol_0", "B-Unit IMR4 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR4 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr4_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1080[] = {{"B_CR_BIMR4WAC_0_0_0_MCHBAR", "", 0x00006908, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1081[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr5_base", "Specifies bits 38:10 of the start address of IMR5 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR5MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR5 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr5_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1081[] = {{"B_CR_BIMR5BASE_0_0_0_MCHBAR", "", 0x00006910, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1082[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr5_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR5BASE[28:0] value. A match indicates that the incoming address falls within the IMR5 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr5_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1082[] = {{"B_CR_BIMR5MASK_0_0_0_MCHBAR", "", 0x00006914, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1083[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr5_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR5RAC, BIMR5WAC and BIMR5CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr5_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1083[] = {{"B_CR_BIMR5CP_0_0_0_MCHBAR", "", 0x00006918, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1084[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr5_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr5_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr5_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr5_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr5_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr5_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr5_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr5_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr5_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr5_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr5_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr5_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr5_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr5_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr5_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr5_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr5_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr5_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr5_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr5_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr5_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr5_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr5_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr5_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr5_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr5_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr5_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr5_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr5_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr5_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr5_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr5_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr5_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr5_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr5_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr5_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr5_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr5_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr5_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr5_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr5_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr5_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr5_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr5_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr5_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr5_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr5_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr5_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr5_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr5_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr5_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr5_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr5_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr5_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr5_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr5_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr5_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr5_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr5_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr5_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr5_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr5_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr5_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr5_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr5_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr5_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr5_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr5_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr5_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr5_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr5_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr5_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr5_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr5_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr5_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr5_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr5_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr5_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr5_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr5_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr5_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr5_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr5_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr5_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr5_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr5_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr5_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr5_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr5_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr5_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr5_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr5_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr5_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr5_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr5_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr5_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr5_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr5_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr5_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr5_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr5_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr5_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr5_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr5_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr5_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr5_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr5_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr5_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr5_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr5_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr5_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr5_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr5_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr5_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr5_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr5_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr5_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr5_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr5_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr5_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr5_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr5_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr5_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr5_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr5_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr5_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr5_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr5_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1084[] = {{"B_CR_BIMR5RAC_0_0_0_MCHBAR", "", 0x00006920, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1085[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr5_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr5_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr5_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr5_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr5_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr5_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr5_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr5_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr5_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr5_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr5_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr5_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr5_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr5_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr5_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr5_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr5_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr5_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr5_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr5_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr5_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr5_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr5_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr5_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr5_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr5_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr5_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr5_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr5_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr5_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr5_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr5_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr5_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr5_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr5_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr5_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr5_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr5_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr5_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr5_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr5_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr5_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr5_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr5_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr5_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr5_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr5_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr5_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr5_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr5_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr5_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr5_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr5_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr5_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr5_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr5_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr5_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr5_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr5_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr5_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr5_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr5_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr5_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr5_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr5_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr5_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr5_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr5_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr5_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr5_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr5_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr5_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr5_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr5_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr5_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr5_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr5_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr5_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr5_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr5_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr5_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr5_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr5_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr5_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr5_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr5_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr5_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr5_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr5_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr5_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr5_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr5_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr5_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr5_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr5_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr5_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr5_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr5_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr5_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr5_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr5_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr5_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr5_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr5_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr5_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr5_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr5_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr5_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr5_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr5_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr5_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr5_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr5_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr5_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr5_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr5_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr5_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr5_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr5_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr5_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr5_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr5_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr5_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr5_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr5_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr5_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr5_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR5 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr5_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1085[] = {{"B_CR_BIMR5WAC_0_0_0_MCHBAR", "", 0x00006928, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1086[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr6_base", "Specifies bits 38:10 of the start address of IMR6 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR6MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR6 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr6_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1086[] = {{"B_CR_BIMR6BASE_0_0_0_MCHBAR", "", 0x00006930, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1087[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr6_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR6BASE[28:0] value. A match indicates that the incoming address falls within the IMR6 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr6_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1087[] = {{"B_CR_BIMR6MASK_0_0_0_MCHBAR", "", 0x00006934, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1088[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr6_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR6RAC, BIMR6WAC, BIMR6CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr6_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1088[] = {{"B_CR_BIMR6CP_0_0_0_MCHBAR", "", 0x00006938, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1089[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr6_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr6_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr6_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr6_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr6_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr6_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr6_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr6_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr6_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr6_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr6_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr6_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr6_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr6_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr6_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr6_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr6_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr6_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr6_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr6_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr6_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr6_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr6_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr6_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr6_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr6_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr6_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr6_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr6_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr6_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr6_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr6_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr6_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr6_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr6_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr6_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr6_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr6_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr6_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr6_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr6_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr6_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr6_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr6_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr6_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr6_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr6_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr6_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr6_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr6_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr6_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr6_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr6_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr6_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr6_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr6_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr6_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr6_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr6_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr6_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr6_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr6_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr6_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr6_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr6_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr6_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr6_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr6_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr6_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr6_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr6_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr6_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr6_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr6_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr6_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr6_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr6_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr6_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr6_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr6_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr6_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr6_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr6_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr6_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr6_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr6_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr6_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr6_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr6_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr6_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr6_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr6_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr6_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr6_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr6_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr6_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr6_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr6_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr6_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr6_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr6_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr6_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr6_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr6_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr6_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr6_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr6_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr6_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr6_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr6_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr6_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr6_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr6_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr6_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr6_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr6_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr6_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr6_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr6_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr6_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr6_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr6_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr6_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr6_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr6_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr6_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr6_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr6_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1089[] = {{"B_CR_BIMR6RAC_0_0_0_MCHBAR", "", 0x00006940, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1090[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr6_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr6_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr6_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr6_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr6_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr6_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr6_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr6_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr6_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr6_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr6_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr6_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr6_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr6_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr6_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr6_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr6_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr6_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr6_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr6_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr6_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr6_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr6_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr6_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr6_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr6_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr6_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr6_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr6_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr6_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr6_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr6_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr6_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr6_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr6_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr6_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr6_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr6_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr6_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr6_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr6_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr6_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr6_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr6_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr6_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr6_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr6_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr6_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr6_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr6_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr6_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr6_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr6_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr6_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr6_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr6_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr6_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr6_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr6_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr6_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr6_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr6_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr6_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr6_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr6_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr6_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr6_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr6_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr6_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr6_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr6_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr6_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr6_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr6_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr6_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr6_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr6_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr6_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr6_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr6_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr6_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr6_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr6_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr6_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr6_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr6_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr6_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr6_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr6_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr6_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr6_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr6_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr6_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr6_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr6_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr6_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr6_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr6_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr6_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr6_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr6_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr6_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr6_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr6_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr6_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr6_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr6_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr6_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr6_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr6_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr6_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr6_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr6_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr6_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr6_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr6_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr6_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr6_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr6_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr6_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr6_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr6_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr6_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr6_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr6_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr6_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr6_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR6 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr6_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1090[] = {{"B_CR_BIMR6WAC_0_0_0_MCHBAR", "", 0x00006948, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1091[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr7_base", "Specifies bits 38:10 of the start address of IMR7 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR7MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR7 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr7_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1091[] = {{"B_CR_BIMR7BASE_0_0_0_MCHBAR", "", 0x00006950, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1092[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr7_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR7BASE[28:0] value. A match indicates that the incoming address falls within the IMR7 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr7_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1092[] = {{"B_CR_BIMR7MASK_0_0_0_MCHBAR", "", 0x00006954, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1093[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr7_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR7RAC, BIMR7WAC and BIMR7CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr7_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1093[] = {{"B_CR_BIMR7CP_0_0_0_MCHBAR", "", 0x00006958, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1094[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr7_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr7_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr7_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr7_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr7_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr7_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr7_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr7_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr7_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr7_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr7_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr7_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr7_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr7_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr7_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr7_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr7_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr7_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr7_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr7_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr7_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr7_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr7_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr7_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr7_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr7_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr7_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr7_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr7_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr7_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr7_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr7_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr7_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr7_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr7_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr7_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr7_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr7_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr7_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr7_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr7_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr7_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr7_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr7_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr7_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr7_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr7_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr7_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr7_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr7_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr7_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr7_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr7_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr7_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr7_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr7_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr7_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr7_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr7_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr7_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr7_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr7_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr7_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr7_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr7_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr7_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr7_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr7_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr7_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr7_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr7_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr7_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr7_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr7_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr7_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr7_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr7_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr7_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr7_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr7_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr7_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr7_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr7_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr7_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr7_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr7_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr7_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr7_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr7_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr7_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr7_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr7_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr7_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr7_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr7_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr7_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr7_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr7_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr7_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr7_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr7_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr7_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr7_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr7_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr7_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr7_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr7_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr7_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr7_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr7_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr7_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr7_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr7_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr7_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr7_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr7_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr7_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr7_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr7_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr7_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr7_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr7_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr7_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr7_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr7_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr7_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr7_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr7_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1094[] = {{"B_CR_BIMR7RAC_0_0_0_MCHBAR", "", 0x00006960, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1095[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr7_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr7_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr7_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr7_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr7_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr7_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr7_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr7_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr7_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr7_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr7_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr7_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr7_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr7_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr7_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr7_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr7_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr7_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr7_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr7_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr7_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr7_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr7_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr7_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr7_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr7_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr7_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr7_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr7_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr7_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr7_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr7_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr7_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr7_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr7_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr7_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr7_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr7_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr7_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr7_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr7_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr7_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr7_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr7_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr7_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr7_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr7_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr7_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr7_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr7_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr7_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr7_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr7_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr7_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr7_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr7_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr7_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr7_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr7_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr7_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr7_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr7_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr7_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr7_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr7_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr7_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr7_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr7_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr7_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr7_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr7_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr7_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr7_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr7_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr7_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr7_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr7_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr7_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr7_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr7_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr7_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr7_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr7_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr7_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr7_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr7_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr7_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr7_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr7_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr7_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr7_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr7_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr7_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr7_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr7_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr7_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr7_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr7_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr7_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr7_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr7_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr7_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr7_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr7_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr7_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr7_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr7_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr7_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr7_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr7_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr7_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr7_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr7_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr7_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr7_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr7_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr7_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr7_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr7_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr7_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr7_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr7_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr7_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr7_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr7_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr7_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr7_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR7 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr7_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1095[] = {{"B_CR_BIMR7WAC_0_0_0_MCHBAR", "", 0x00006968, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1096[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr8_base", "Specifies bits 38:10 of the start address of IMR8 region. IMR region size must be a strict power of two at least 1KB and naturally aligned to the size. These bits are compared with the result of the IMR8MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR8 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr8_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1096[] = {{"B_CR_BIMR8BASE_0_0_0_MCHBAR", "", 0x00006970, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1097[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester.  When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr8_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR8BASE[28:0] value.  A match indicates that the incoming address falls within the IMR8 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr8_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1097[] = {{"B_CR_BIMR8MASK_0_0_0_MCHBAR", "", 0x00006974, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1098[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr8_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR8RAC, BIMR8WAC and BIMR8CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr8_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1098[] = {{"B_CR_BIMR8CP_0_0_0_MCHBAR", "", 0x00006978, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1099[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr8_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr8_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr8_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr8_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr8_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr8_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr8_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr8_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr8_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr8_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr8_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr8_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr8_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr8_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr8_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr8_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr8_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr8_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr8_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr8_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr8_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr8_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr8_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr8_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr8_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr8_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr8_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr8_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr8_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr8_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr8_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr8_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr8_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr8_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr8_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr8_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr8_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr8_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr8_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr8_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr8_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr8_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr8_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr8_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr8_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr8_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr8_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr8_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr8_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr8_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr8_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr8_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr8_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr8_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr8_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr8_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr8_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr8_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr8_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr8_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr8_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr8_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr8_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr8_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr8_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr8_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr8_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr8_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr8_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr8_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr8_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr8_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr8_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr8_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr8_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr8_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr8_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr8_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr8_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr8_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr8_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr8_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr8_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr8_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr8_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr8_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr8_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr8_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr8_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr8_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr8_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr8_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr8_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr8_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr8_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr8_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr8_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr8_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr8_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr8_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr8_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr8_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr8_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr8_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr8_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr8_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr8_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr8_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr8_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr8_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr8_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr8_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr8_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr8_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr8_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr8_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr8_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr8_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr8_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr8_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr8_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr8_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr8_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr8_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr8_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr8_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr8_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr8_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1099[] = {{"B_CR_BIMR8RAC_0_0_0_MCHBAR", "", 0x00006980, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1100[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr8_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr8_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr8_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr8_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr8_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr8_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr8_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr8_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr8_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr8_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr8_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr8_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr8_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr8_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr8_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr8_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr8_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr8_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr8_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr8_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr8_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr8_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr8_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr8_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr8_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr8_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr8_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr8_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr8_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr8_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr8_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr8_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr8_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr8_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr8_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr8_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr8_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr8_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr8_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr8_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr8_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr8_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr8_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr8_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr8_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr8_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr8_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr8_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr8_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr8_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr8_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr8_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr8_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr8_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr8_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr8_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr8_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr8_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr8_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr8_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr8_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr8_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr8_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr8_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr8_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr8_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr8_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr8_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr8_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr8_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr8_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr8_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr8_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr8_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr8_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr8_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr8_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr8_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr8_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr8_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr8_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr8_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr8_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr8_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr8_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr8_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr8_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr8_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr8_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr8_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr8_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr8_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr8_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr8_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr8_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr8_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr8_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr8_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr8_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr8_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr8_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr8_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr8_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr8_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr8_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr8_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr8_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr8_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr8_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr8_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr8_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr8_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr8_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr8_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr8_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr8_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr8_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr8_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr8_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr8_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr8_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr8_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr8_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr8_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr8_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr8_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr8_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR8 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr8_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1100[] = {{"B_CR_BIMR8WAC_0_0_0_MCHBAR", "", 0x00006988, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1101[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr9_base", "Specifies bits 38:10 of the start address of IMR9 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR9MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR9 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr9_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1101[] = {{"B_CR_BIMR9BASE_0_0_0_MCHBAR", "", 0x00006990, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1102[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester.  When set to 0, inhibits HITM data from GT from being returned to the requester.  HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr9_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR9BASE[28:0] value. A match indicates that the incoming address falls within the IMR9 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr9_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1102[] = {{"B_CR_BIMR9MASK_0_0_0_MCHBAR", "", 0x00006994, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1103[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr9_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR9RAC, BIMR9WAC, BIMR9CP registers based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr9_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1103[] = {{"B_CR_BIMR9CP_0_0_0_MCHBAR", "", 0x00006998, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1104[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr9_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr9_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr9_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr9_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr9_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr9_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr9_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr9_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr9_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr9_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr9_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr9_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr9_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr9_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr9_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr9_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr9_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr9_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr9_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr9_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr9_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr9_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr9_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr9_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr9_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr9_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr9_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr9_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr9_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr9_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr9_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr9_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr9_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr9_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr9_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr9_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr9_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr9_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr9_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr9_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr9_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr9_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr9_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr9_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr9_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr9_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr9_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr9_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr9_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr9_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr9_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr9_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr9_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr9_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr9_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr9_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr9_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr9_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr9_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr9_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr9_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr9_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr9_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr9_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr9_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr9_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr9_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr9_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr9_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr9_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr9_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr9_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr9_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr9_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr9_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr9_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr9_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr9_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr9_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr9_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr9_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr9_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr9_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr9_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr9_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr9_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr9_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr9_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr9_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr9_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr9_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr9_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr9_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr9_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr9_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr9_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr9_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr9_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr9_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr9_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr9_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr9_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr9_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr9_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr9_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr9_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr9_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr9_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr9_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr9_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr9_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr9_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr9_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr9_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr9_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr9_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr9_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr9_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr9_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr9_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr9_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr9_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr9_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr9_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr9_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr9_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr9_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr9_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1104[] = {{"B_CR_BIMR9RAC_0_0_0_MCHBAR", "", 0x000069A0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1105[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr9_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr9_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr9_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr9_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr9_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr9_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr9_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr9_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr9_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr9_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr9_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr9_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr9_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr9_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr9_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr9_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr9_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr9_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr9_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr9_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr9_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr9_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr9_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr9_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr9_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr9_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr9_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr9_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr9_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr9_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr9_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr9_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr9_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr9_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr9_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr9_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr9_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr9_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr9_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr9_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr9_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr9_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr9_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr9_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr9_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr9_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr9_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr9_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr9_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr9_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr9_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr9_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr9_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr9_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr9_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr9_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr9_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr9_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr9_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr9_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr9_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr9_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr9_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr9_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr9_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr9_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr9_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr9_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr9_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr9_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr9_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr9_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr9_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr9_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr9_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr9_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr9_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr9_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr9_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr9_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr9_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr9_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr9_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr9_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr9_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr9_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr9_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr9_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr9_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr9_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr9_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr9_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr9_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr9_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr9_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr9_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr9_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr9_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr9_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr9_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr9_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr9_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr9_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr9_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr9_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr9_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr9_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr9_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr9_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr9_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr9_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr9_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr9_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr9_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr9_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr9_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr9_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr9_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr9_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr9_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr9_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr9_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr9_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr9_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr9_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr9_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr9_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR9 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr9_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1105[] = {{"B_CR_BIMR9WAC_0_0_0_MCHBAR", "", 0x000069A8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1106[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr10_base", "Specifies bits 38:10 of the start address of IMR10 region.  IMR region size must be a strict power of two at least 1KB and naturally aligned to the size.  These bits are compared with the result of the IMR10MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR10 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr10_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1106[] = {{"B_CR_BIMR10BASE_0_0_0_MCHBAR", "", 0x000069B0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1107[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent.  When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester.  When set to 0, inhibits HITM data from IA cores from being returned to the requester.  HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr10_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR10BASE[28:0] value.  A match indicates that the incoming address falls within the IMR10 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr10_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1107[] = {{"B_CR_BIMR10MASK_0_0_0_MCHBAR", "", 0x000069B4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1108[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr10_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR10RAC, BIMR10WAC and BIMR10CP, registers based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr10_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1108[] = {{"B_CR_BIMR10CP_0_0_0_MCHBAR", "", 0x000069B8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1109[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr10_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr10_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr10_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr10_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr10_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr10_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr10_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr10_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr10_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr10_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr10_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr10_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr10_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr10_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr10_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr10_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr10_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr10_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr10_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr10_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr10_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr10_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr10_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr10_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr10_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr10_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr10_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr10_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr10_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr10_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr10_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr10_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr10_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr10_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr10_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr10_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr10_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr10_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr10_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr10_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr10_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr10_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr10_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr10_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr10_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr10_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr10_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr10_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr10_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr10_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr10_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr10_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr10_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr10_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr10_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr10_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr10_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr10_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr10_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr10_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr10_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr10_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr10_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr10_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr10_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr10_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr10_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr10_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr10_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr10_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr10_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr10_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr10_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr10_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr10_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr10_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr10_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr10_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr10_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr10_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr10_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr10_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr10_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr10_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr10_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr10_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr10_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr10_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr10_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr10_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr10_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr10_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr10_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr10_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr10_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr10_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr10_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr10_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr10_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr10_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr10_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr10_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr10_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr10_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr10_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr10_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr10_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr10_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr10_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr10_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr10_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr10_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr10_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr10_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr10_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr10_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr10_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr10_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr10_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr10_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr10_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr10_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr10_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr10_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr10_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr10_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr10_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr10_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1109[] = {{"B_CR_BIMR10RAC_0_0_0_MCHBAR", "", 0x000069C0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1110[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr10_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr10_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr10_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr10_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr10_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr10_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr10_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr10_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr10_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr10_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr10_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr10_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr10_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr10_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr10_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr10_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr10_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr10_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr10_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr10_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr10_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr10_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr10_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr10_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr10_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr10_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr10_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr10_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr10_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr10_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr10_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr10_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr10_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr10_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr10_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr10_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr10_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr10_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr10_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr10_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr10_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr10_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr10_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr10_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr10_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr10_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr10_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr10_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr10_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr10_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr10_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr10_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr10_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr10_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr10_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr10_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr10_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr10_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr10_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr10_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr10_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr10_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr10_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr10_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr10_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr10_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr10_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr10_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr10_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr10_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr10_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr10_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr10_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr10_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr10_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr10_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr10_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr10_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr10_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr10_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr10_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr10_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr10_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr10_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr10_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr10_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr10_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr10_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr10_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr10_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr10_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr10_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr10_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr10_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr10_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr10_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr10_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr10_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr10_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr10_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr10_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr10_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr10_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr10_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr10_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr10_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr10_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr10_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr10_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr10_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr10_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr10_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr10_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr10_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr10_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr10_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr10_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr10_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr10_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr10_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr10_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr10_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr10_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr10_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr10_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr10_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr10_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR10 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr10_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1110[] = {{"B_CR_BIMR10WAC_0_0_0_MCHBAR", "", 0x000069C8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1111[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr11_base", "Specifies bits 38:10 of the start address of IMR11 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR11MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR11 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr11_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1111[] = {{"B_CR_BIMR11BASE_0_0_0_MCHBAR", "", 0x000069D0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1112[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester.  HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr11_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR11BASE[28:0] value.  A match indicates that the incoming address falls within the IMR11 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr11_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1112[] = {{"B_CR_BIMR11MASK_0_0_0_MCHBAR", "", 0x000069D4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1113[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr11_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR11RAC, BIMR11WAC and BIMR11CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr11_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1113[] = {{"B_CR_BIMR11CP_0_0_0_MCHBAR", "", 0x000069D8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1114[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr11_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr11_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr11_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr11_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr11_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr11_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr11_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr11_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr11_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr11_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr11_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr11_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr11_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr11_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr11_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr11_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr11_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr11_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr11_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr11_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr11_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr11_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr11_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr11_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr11_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr11_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr11_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr11_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr11_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr11_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr11_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr11_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr11_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr11_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr11_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr11_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr11_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr11_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr11_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr11_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr11_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr11_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr11_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr11_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr11_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr11_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr11_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr11_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr11_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr11_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr11_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr11_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr11_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr11_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr11_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr11_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr11_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr11_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr11_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr11_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr11_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr11_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr11_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr11_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr11_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr11_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr11_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr11_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr11_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr11_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr11_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr11_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr11_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr11_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr11_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr11_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr11_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr11_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr11_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr11_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr11_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr11_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr11_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr11_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr11_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr11_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr11_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr11_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr11_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr11_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr11_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr11_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr11_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr11_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr11_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr11_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr11_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr11_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr11_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr11_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr11_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr11_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr11_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr11_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr11_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr11_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr11_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr11_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr11_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr11_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr11_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr11_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr11_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr11_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr11_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr11_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr11_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr11_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr11_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr11_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr11_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr11_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr11_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr11_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr11_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr11_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr11_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr11_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1114[] = {{"B_CR_BIMR11RAC_0_0_0_MCHBAR", "", 0x000069E0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1115[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr11_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr11_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr11_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr11_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr11_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr11_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr11_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr11_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr11_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr11_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr11_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr11_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr11_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr11_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr11_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr11_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr11_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr11_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr11_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr11_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr11_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr11_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr11_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr11_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr11_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr11_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr11_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr11_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr11_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr11_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr11_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr11_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr11_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr11_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr11_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr11_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr11_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr11_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr11_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr11_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr11_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr11_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr11_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr11_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr11_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr11_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr11_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr11_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr11_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr11_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr11_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr11_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr11_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr11_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr11_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr11_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr11_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr11_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr11_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr11_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr11_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr11_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr11_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr11_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr11_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr11_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr11_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr11_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr11_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr11_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr11_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr11_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr11_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr11_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr11_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr11_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr11_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr11_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr11_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr11_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr11_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr11_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr11_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr11_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr11_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr11_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr11_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr11_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr11_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr11_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr11_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr11_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr11_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr11_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr11_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr11_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr11_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr11_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr11_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr11_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr11_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr11_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr11_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr11_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr11_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr11_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr11_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr11_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr11_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr11_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr11_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr11_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr11_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr11_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr11_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr11_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr11_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr11_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr11_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr11_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr11_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr11_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr11_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr11_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr11_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr11_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr11_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR11 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr11_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1115[] = {{"B_CR_BIMR11WAC_0_0_0_MCHBAR", "", 0x000069E8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1116[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr12_base", "Specifies bits 38:10 of the start address of IMR12 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR12MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR12 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr12_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1116[] = {{"B_CR_BIMR12BASE_0_0_0_MCHBAR", "", 0x000069F0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1117[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr12_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR12BASE[28:0] value. A match indicates that the incoming address falls within the IMR12 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr12_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1117[] = {{"B_CR_BIMR12MASK_0_0_0_MCHBAR", "", 0x000069F4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1118[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr12_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR12RAC, BIMR12WAC and BIMR12CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr12_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1118[] = {{"B_CR_BIMR12CP_0_0_0_MCHBAR", "", 0x000069F8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1119[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr12_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr12_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr12_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr12_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr12_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr12_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr12_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr12_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr12_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr12_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr12_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr12_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr12_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr12_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr12_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr12_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr12_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr12_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr12_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr12_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr12_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr12_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr12_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr12_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr12_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr12_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr12_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr12_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr12_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr12_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr12_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr12_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr12_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr12_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr12_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr12_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr12_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr12_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr12_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr12_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr12_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr12_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr12_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr12_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr12_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr12_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr12_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr12_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr12_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr12_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr12_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr12_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr12_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr12_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr12_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr12_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr12_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr12_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr12_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr12_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr12_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr12_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr12_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr12_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr12_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr12_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr12_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr12_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr12_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr12_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr12_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr12_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr12_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr12_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr12_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr12_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr12_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr12_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr12_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr12_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr12_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr12_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr12_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr12_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr12_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr12_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr12_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr12_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr12_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr12_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr12_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr12_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr12_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr12_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr12_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr12_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr12_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr12_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr12_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr12_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr12_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr12_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr12_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr12_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr12_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr12_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr12_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr12_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr12_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr12_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr12_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr12_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr12_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr12_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr12_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr12_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr12_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr12_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr12_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr12_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr12_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr12_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr12_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr12_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr12_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr12_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr12_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr12_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1119[] = {{"B_CR_BIMR12RAC_0_0_0_MCHBAR", "", 0x00006A00, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1120[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr12_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr12_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr12_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr12_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr12_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr12_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr12_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr12_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr12_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr12_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr12_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr12_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr12_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr12_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr12_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr12_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr12_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr12_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr12_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr12_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr12_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr12_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr12_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr12_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr12_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr12_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr12_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr12_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr12_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr12_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr12_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr12_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr12_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr12_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr12_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr12_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr12_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr12_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr12_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr12_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr12_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr12_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr12_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr12_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr12_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr12_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr12_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr12_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr12_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr12_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr12_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr12_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr12_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr12_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr12_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr12_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr12_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr12_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr12_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr12_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr12_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr12_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr12_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr12_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr12_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr12_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr12_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr12_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr12_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr12_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr12_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr12_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr12_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr12_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr12_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr12_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr12_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr12_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr12_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr12_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr12_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr12_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr12_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr12_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr12_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr12_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr12_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr12_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr12_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr12_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr12_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr12_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr12_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr12_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr12_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr12_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr12_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr12_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr12_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr12_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr12_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr12_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr12_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr12_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr12_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr12_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr12_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr12_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr12_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr12_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr12_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr12_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr12_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr12_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr12_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr12_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr12_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr12_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr12_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr12_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr12_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr12_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr12_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr12_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr12_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr12_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr12_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR12 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr12_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1120[] = {{"B_CR_BIMR12WAC_0_0_0_MCHBAR", "", 0x00006A08, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1121[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr13_base", "Specifies bits 38:10 of the start address of IMR13 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR13MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR13 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr13_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1121[] = {{"B_CR_BIMR13BASE_0_0_0_MCHBAR", "", 0x00006A10, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1122[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent.  When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester.  When set to 0, inhibits HITM data from IA cores from being returned to the requester.  HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr13_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR13BASE[28:0] value. A match indicates that the incoming address falls within the IMR13 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr13_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1122[] = {{"B_CR_BIMR13MASK_0_0_0_MCHBAR", "", 0x00006A14, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1123[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr13_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR13RAC, BIMR13WAC and BIMR13CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr13_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1123[] = {{"B_CR_BIMR13CP_0_0_0_MCHBAR", "", 0x00006A18, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1124[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr13_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr13_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr13_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr13_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr13_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr13_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr13_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr13_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr13_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr13_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr13_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr13_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr13_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr13_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr13_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr13_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr13_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr13_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr13_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr13_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr13_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr13_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr13_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr13_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr13_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr13_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr13_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr13_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr13_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr13_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr13_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr13_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr13_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr13_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr13_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr13_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr13_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr13_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr13_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr13_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr13_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr13_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr13_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr13_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr13_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr13_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr13_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr13_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr13_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr13_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr13_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr13_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr13_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr13_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr13_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr13_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr13_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr13_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr13_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr13_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr13_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr13_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr13_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr13_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr13_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr13_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr13_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr13_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr13_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr13_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr13_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr13_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr13_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr13_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr13_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr13_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr13_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr13_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr13_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr13_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr13_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr13_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr13_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr13_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr13_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr13_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr13_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr13_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr13_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr13_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr13_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr13_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr13_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr13_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr13_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr13_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr13_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr13_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr13_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr13_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr13_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr13_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr13_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr13_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr13_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr13_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr13_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr13_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr13_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr13_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr13_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr13_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr13_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr13_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr13_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr13_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr13_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr13_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr13_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr13_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr13_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr13_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr13_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr13_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr13_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr13_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr13_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr13_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1124[] = {{"B_CR_BIMR13RAC_0_0_0_MCHBAR", "", 0x00006A20, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1125[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr13_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr13_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr13_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr13_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr13_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr13_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr13_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr13_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr13_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr13_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr13_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr13_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr13_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr13_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr13_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr13_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr13_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr13_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr13_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr13_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr13_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr13_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr13_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr13_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr13_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr13_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr13_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr13_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr13_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr13_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr13_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr13_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr13_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr13_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr13_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr13_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr13_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr13_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr13_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr13_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr13_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr13_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr13_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr13_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr13_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr13_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr13_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr13_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr13_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr13_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr13_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr13_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr13_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr13_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr13_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr13_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr13_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr13_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr13_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr13_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr13_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr13_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr13_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr13_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr13_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr13_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr13_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr13_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr13_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr13_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr13_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr13_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr13_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr13_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr13_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr13_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr13_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr13_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr13_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr13_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr13_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr13_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr13_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr13_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr13_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr13_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr13_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr13_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr13_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr13_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr13_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr13_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr13_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr13_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr13_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr13_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr13_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr13_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr13_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr13_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr13_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr13_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr13_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr13_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr13_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr13_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr13_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr13_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr13_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr13_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr13_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr13_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr13_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr13_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr13_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr13_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr13_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr13_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr13_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr13_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr13_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr13_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr13_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr13_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr13_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr13_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr13_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR13 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr13_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1125[] = {{"B_CR_BIMR13WAC_0_0_0_MCHBAR", "", 0x00006A28, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1126[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr14_base", "Specifies bits 38:10 of the start address of IMR14 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR14MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR14 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr14_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1126[] = {{"B_CR_BIMR14BASE_0_0_0_MCHBAR", "", 0x00006A30, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1127[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester.  When set to 0, inhibits HITM data from GT from being returned to the requester.  HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr14_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR14BASE[28:0] value. A match indicates that the incoming address falls within the IMR14 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr14_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1127[] = {{"B_CR_BIMR14MASK_0_0_0_MCHBAR", "", 0x00006A34, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1128[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr14_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR14RAC, BIMR14WAC and BIMR14CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr14_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1128[] = {{"B_CR_BIMR14CP_0_0_0_MCHBAR", "", 0x00006A38, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1129[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr14_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr14_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr14_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr14_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr14_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr14_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr14_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr14_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr14_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr14_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr14_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr14_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr14_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr14_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr14_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr14_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr14_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr14_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr14_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr14_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr14_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr14_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr14_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr14_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr14_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr14_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr14_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr14_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr14_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr14_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr14_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr14_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr14_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr14_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr14_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr14_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr14_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr14_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr14_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr14_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr14_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr14_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr14_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr14_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr14_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr14_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr14_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr14_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr14_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr14_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr14_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr14_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr14_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr14_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr14_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr14_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr14_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr14_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr14_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr14_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr14_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr14_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr14_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr14_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr14_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr14_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr14_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr14_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr14_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr14_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr14_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr14_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr14_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr14_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr14_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr14_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr14_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr14_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr14_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr14_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr14_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr14_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr14_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr14_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr14_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr14_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr14_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr14_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr14_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr14_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr14_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr14_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr14_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr14_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr14_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr14_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr14_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr14_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr14_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr14_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr14_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr14_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr14_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr14_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr14_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr14_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr14_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr14_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr14_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr14_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr14_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr14_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr14_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr14_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr14_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr14_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr14_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr14_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr14_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr14_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr14_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr14_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr14_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr14_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr14_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr14_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr14_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr14_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1129[] = {{"B_CR_BIMR14RAC_0_0_0_MCHBAR", "", 0x00006A40, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1130[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr14_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr14_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr14_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr14_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr14_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr14_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr14_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr14_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr14_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr14_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr14_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr14_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr14_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr14_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr14_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr14_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr14_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr14_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr14_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr14_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr14_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr14_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr14_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr14_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr14_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr14_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr14_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr14_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr14_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr14_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr14_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr14_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr14_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr14_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr14_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr14_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr14_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr14_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr14_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr14_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr14_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr14_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr14_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr14_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr14_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr14_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr14_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr14_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr14_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr14_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr14_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr14_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr14_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr14_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr14_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr14_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr14_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr14_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr14_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr14_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr14_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr14_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr14_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr14_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr14_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr14_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr14_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr14_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr14_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr14_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr14_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr14_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr14_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr14_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr14_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr14_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr14_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr14_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr14_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr14_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr14_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr14_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr14_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr14_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr14_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr14_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr14_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr14_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr14_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr14_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr14_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr14_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr14_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr14_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr14_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr14_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr14_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr14_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr14_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr14_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr14_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr14_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr14_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr14_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr14_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr14_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr14_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr14_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr14_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr14_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr14_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr14_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr14_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr14_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr14_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr14_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr14_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr14_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr14_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr14_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr14_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr14_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr14_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr14_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr14_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr14_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr14_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR14 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr14_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1130[] = {{"B_CR_BIMR14WAC_0_0_0_MCHBAR", "", 0x00006A48, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1131[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr15_base", "Specifies bits 38:10 of the start address of IMR15 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR15MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR15 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr15_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1131[] = {{"B_CR_BIMR15BASE_0_0_0_MCHBAR", "", 0x00006A50, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1132[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr15_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR15BASE[28:0] value. A match indicates that the incoming address falls within the IMR15 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr15_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1132[] = {{"B_CR_BIMR15MASK_0_0_0_MCHBAR", "", 0x00006A54, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1133[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr15_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR15RAC, BIMR15WAC and BIMR15CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr15_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1133[] = {{"B_CR_BIMR15CP_0_0_0_MCHBAR", "", 0x00006A58, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1134[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr15_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr15_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr15_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr15_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr15_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr15_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr15_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr15_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr15_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr15_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr15_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr15_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr15_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr15_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr15_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr15_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr15_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr15_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr15_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr15_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr15_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr15_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr15_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr15_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr15_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr15_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr15_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr15_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr15_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr15_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr15_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr15_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr15_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr15_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr15_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr15_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr15_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr15_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr15_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr15_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr15_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr15_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr15_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr15_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr15_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr15_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr15_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr15_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr15_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr15_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr15_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr15_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr15_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr15_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr15_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr15_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr15_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr15_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr15_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr15_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr15_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr15_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr15_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr15_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr15_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr15_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr15_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr15_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr15_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr15_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr15_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr15_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr15_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr15_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr15_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr15_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr15_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr15_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr15_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr15_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr15_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr15_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr15_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr15_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr15_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr15_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr15_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr15_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr15_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr15_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr15_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr15_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr15_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr15_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr15_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr15_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr15_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr15_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr15_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr15_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr15_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr15_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr15_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr15_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr15_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr15_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr15_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr15_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr15_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr15_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr15_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr15_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr15_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr15_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr15_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr15_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr15_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr15_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr15_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr15_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr15_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr15_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr15_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr15_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr15_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr15_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr15_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr15_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1134[] = {{"B_CR_BIMR15RAC_0_0_0_MCHBAR", "", 0x00006A60, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1135[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr15_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr15_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr15_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr15_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr15_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr15_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr15_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr15_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr15_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr15_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr15_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr15_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr15_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr15_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr15_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr15_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr15_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr15_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr15_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr15_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr15_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr15_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr15_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr15_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr15_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr15_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr15_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr15_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr15_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr15_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr15_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr15_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr15_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr15_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr15_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr15_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr15_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr15_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr15_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr15_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr15_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr15_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr15_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr15_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr15_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr15_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr15_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr15_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr15_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr15_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr15_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr15_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr15_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr15_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr15_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr15_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr15_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr15_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr15_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr15_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr15_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr15_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr15_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr15_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr15_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr15_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr15_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr15_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr15_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr15_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr15_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr15_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr15_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr15_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr15_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr15_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr15_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr15_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr15_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr15_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr15_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr15_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr15_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr15_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr15_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr15_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr15_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr15_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr15_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr15_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr15_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr15_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr15_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr15_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr15_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr15_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr15_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr15_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr15_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr15_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr15_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr15_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr15_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr15_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr15_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr15_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr15_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr15_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr15_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr15_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr15_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr15_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr15_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr15_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr15_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr15_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr15_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr15_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr15_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr15_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr15_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr15_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr15_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr15_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr15_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr15_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr15_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR15 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr15_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1135[] = {{"B_CR_BIMR15WAC_0_0_0_MCHBAR", "", 0x00006A68, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1136[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr16_base", "Specifies bits 38:10 of the start address of IMR16 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR16MASK[28:0] applied to bits 38:10 of the incoming address, to determine if an access falls within the IMR16 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr16_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1136[] = {{"B_CR_BIMR16BASE_0_0_0_MCHBAR", "", 0x00006A70, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1137[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester.  HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr16_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR16BASE[28:0] value.  A match indicates that the incoming address falls within the IMR16 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr16_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1137[] = {{"B_CR_BIMR16MASK_0_0_0_MCHBAR", "", 0x00006A74, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1138[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr16_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR16RAC, BIMR16WAC and BIMR16CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr16_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1138[] = {{"B_CR_BIMR16CP_0_0_0_MCHBAR", "", 0x00006A78, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1139[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr16_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr16_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr16_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr16_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr16_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr16_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr16_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr16_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr16_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr16_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr16_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr16_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr16_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr16_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr16_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr16_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr16_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr16_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr16_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr16_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr16_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr16_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr16_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr16_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr16_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr16_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr16_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr16_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr16_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr16_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr16_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr16_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr16_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr16_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr16_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr16_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr16_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr16_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr16_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr16_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr16_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr16_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr16_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr16_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr16_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr16_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr16_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr16_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr16_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr16_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr16_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr16_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr16_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr16_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr16_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr16_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr16_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr16_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr16_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr16_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr16_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr16_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr16_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr16_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr16_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr16_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr16_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr16_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr16_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr16_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr16_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr16_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr16_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr16_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr16_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr16_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr16_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr16_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr16_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr16_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr16_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr16_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr16_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr16_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr16_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr16_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr16_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr16_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr16_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr16_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr16_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr16_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr16_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr16_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr16_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr16_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr16_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr16_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr16_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr16_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr16_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr16_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr16_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr16_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr16_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr16_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr16_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr16_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr16_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr16_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr16_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr16_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr16_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr16_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr16_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr16_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr16_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr16_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr16_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr16_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr16_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr16_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr16_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr16_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr16_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr16_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr16_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr16_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1139[] = {{"B_CR_BIMR16RAC_0_0_0_MCHBAR", "", 0x00006A80, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1140[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr16_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr16_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr16_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr16_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr16_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr16_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr16_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr16_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr16_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr16_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr16_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr16_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr16_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr16_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr16_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr16_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr16_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr16_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr16_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr16_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr16_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr16_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr16_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr16_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr16_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr16_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr16_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr16_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr16_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr16_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr16_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr16_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr16_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr16_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr16_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr16_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr16_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr16_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr16_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr16_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr16_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr16_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr16_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr16_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr16_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr16_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr16_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr16_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr16_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr16_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr16_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr16_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr16_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr16_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr16_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr16_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr16_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr16_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr16_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr16_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr16_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr16_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr16_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr16_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr16_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr16_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr16_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr16_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr16_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr16_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr16_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr16_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr16_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr16_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr16_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr16_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr16_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr16_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr16_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr16_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr16_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr16_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr16_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr16_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr16_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr16_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr16_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr16_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr16_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr16_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr16_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr16_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr16_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr16_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr16_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr16_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr16_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr16_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr16_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr16_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr16_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr16_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr16_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr16_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr16_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr16_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr16_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr16_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr16_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr16_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr16_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr16_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr16_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr16_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr16_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr16_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr16_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr16_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr16_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr16_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr16_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr16_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr16_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr16_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr16_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr16_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr16_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR16 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr16_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1140[] = {{"B_CR_BIMR16WAC_0_0_0_MCHBAR", "", 0x00006A88, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1141[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr17_base", "Specifies bits 38:10 of the start address of IMR17 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR17MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR17 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr17_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1141[] = {{"B_CR_BIMR17BASE_0_0_0_MCHBAR", "", 0x00006A90, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1142[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent.  When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester.  When set to 0, inhibits HITM data from IA cores from being returned to the requester.  HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr17_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR17BASE[28:0] value. A match indicates that the incoming address falls within the IMR17 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr17_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1142[] = {{"B_CR_BIMR17MASK_0_0_0_MCHBAR", "", 0x00006A94, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1143[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr17_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR17RAC, BIMR17WAC and  BIMR17CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr17_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1143[] = {{"B_CR_BIMR17CP_0_0_0_MCHBAR", "", 0x00006A98, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1144[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr17_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr17_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr17_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr17_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr17_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr17_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr17_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr17_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr17_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr17_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr17_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr17_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr17_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr17_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr17_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr17_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr17_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr17_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr17_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr17_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr17_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr17_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr17_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr17_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr17_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr17_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr17_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr17_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr17_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr17_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr17_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr17_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr17_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr17_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr17_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr17_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr17_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr17_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr17_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr17_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr17_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr17_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr17_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr17_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr17_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr17_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr17_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr17_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr17_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr17_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr17_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr17_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr17_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr17_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr17_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr17_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr17_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr17_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr17_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr17_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr17_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr17_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr17_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr17_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr17_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr17_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr17_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr17_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr17_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr17_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr17_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr17_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr17_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr17_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr17_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr17_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr17_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr17_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr17_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr17_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr17_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr17_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr17_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr17_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr17_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr17_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr17_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr17_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr17_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr17_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr17_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr17_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr17_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr17_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr17_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr17_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr17_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr17_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr17_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr17_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr17_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr17_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr17_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr17_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr17_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr17_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr17_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr17_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr17_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr17_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr17_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr17_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr17_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr17_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr17_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr17_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr17_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr17_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr17_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr17_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr17_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr17_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr17_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr17_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr17_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr17_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr17_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr17_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1144[] = {{"B_CR_BIMR17RAC_0_0_0_MCHBAR", "", 0x00006AA0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1145[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr17_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr17_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr17_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr17_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr17_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr17_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr17_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr17_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr17_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr17_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr17_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr17_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr17_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr17_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr17_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr17_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr17_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr17_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr17_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr17_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr17_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr17_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr17_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr17_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr17_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr17_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr17_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr17_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr17_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr17_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr17_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr17_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr17_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr17_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr17_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr17_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr17_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr17_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr17_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr17_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr17_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr17_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr17_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr17_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr17_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr17_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr17_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr17_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr17_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr17_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr17_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr17_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr17_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr17_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr17_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr17_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr17_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr17_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr17_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr17_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr17_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr17_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr17_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr17_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr17_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr17_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr17_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr17_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr17_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr17_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr17_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr17_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr17_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr17_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr17_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr17_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr17_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr17_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr17_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr17_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr17_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr17_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr17_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr17_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr17_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr17_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr17_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr17_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr17_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr17_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr17_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr17_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr17_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr17_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr17_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr17_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr17_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr17_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr17_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr17_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr17_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr17_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr17_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr17_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr17_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr17_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr17_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr17_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr17_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr17_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr17_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr17_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr17_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr17_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr17_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr17_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr17_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr17_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr17_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr17_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr17_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr17_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr17_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr17_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr17_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr17_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr17_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR17 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr17_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1145[] = {{"B_CR_BIMR17WAC_0_0_0_MCHBAR", "", 0x00006AA8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1146[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr18_base", "Specifies bits 38:10 of the start address of IMR18 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR18MASK[28:0] applied to bits 38:10 of the incoming address, to determine if an access falls within the IMR18 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr18_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1146[] = {{"B_CR_BIMR18BASE_0_0_0_MCHBAR", "", 0x00006AB0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1147[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester.  When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr18_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR18BASE[28:0] value. A match indicates that the incoming address falls within the IMR18 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr18_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1147[] = {{"B_CR_BIMR18MASK_0_0_0_MCHBAR", "", 0x00006AB4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1148[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr18_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR18RAC, BIMR18WAC and BIMR18CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr18_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1148[] = {{"B_CR_BIMR18CP_0_0_0_MCHBAR", "", 0x00006AB8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1149[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr18_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr18_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr18_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr18_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr18_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr18_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr18_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr18_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr18_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr18_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr18_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr18_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr18_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr18_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr18_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr18_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr18_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr18_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr18_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr18_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr18_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr18_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr18_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr18_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr18_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr18_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr18_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr18_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr18_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr18_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr18_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr18_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr18_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr18_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr18_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr18_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr18_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr18_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr18_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr18_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr18_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr18_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr18_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr18_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr18_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr18_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr18_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr18_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr18_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr18_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr18_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr18_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr18_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr18_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr18_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr18_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr18_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr18_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr18_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr18_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr18_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr18_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr18_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr18_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr18_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr18_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr18_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr18_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr18_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr18_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr18_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr18_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr18_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr18_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr18_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr18_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr18_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr18_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr18_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr18_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr18_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr18_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr18_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr18_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr18_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr18_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr18_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr18_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr18_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr18_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr18_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr18_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr18_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr18_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr18_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr18_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr18_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr18_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr18_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr18_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr18_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr18_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr18_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr18_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr18_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr18_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr18_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr18_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr18_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr18_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr18_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr18_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr18_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr18_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr18_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr18_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr18_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr18_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr18_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr18_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr18_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr18_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr18_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr18_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr18_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr18_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr18_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr18_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1149[] = {{"B_CR_BIMR18RAC_0_0_0_MCHBAR", "", 0x00006AC0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1150[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr18_write_pol_63", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr18_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr18_write_pol_62", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr18_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr18_write_pol_61", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr18_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr18_write_pol_60", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr18_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr18_write_pol_59", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr18_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr18_write_pol_58", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr18_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr18_write_pol_57", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr18_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr18_write_pol_56", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr18_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr18_write_pol_55", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr18_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr18_write_pol_54", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr18_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr18_write_pol_53", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr18_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr18_write_pol_52", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr18_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr18_write_pol_51", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr18_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr18_write_pol_50", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr18_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr18_write_pol_49", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr18_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr18_write_pol_48", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr18_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr18_write_pol_47", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr18_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr18_write_pol_46", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr18_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr18_write_pol_45", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr18_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr18_write_pol_44", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr18_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr18_write_pol_43", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr18_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr18_write_pol_42", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr18_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr18_write_pol_41", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr18_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr18_write_pol_40", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr18_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr18_write_pol_39", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr18_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr18_write_pol_38", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr18_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr18_write_pol_37", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr18_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr18_write_pol_36", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr18_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr18_write_pol_35", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr18_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr18_write_pol_34", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr18_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr18_write_pol_33", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr18_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr18_write_pol_32", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr18_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr18_write_pol_31", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr18_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr18_write_pol_30", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr18_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr18_write_pol_29", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr18_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr18_write_pol_28", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr18_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr18_write_pol_27", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr18_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr18_write_pol_26", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr18_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr18_write_pol_25", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr18_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr18_write_pol_24", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr18_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr18_write_pol_23", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr18_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr18_write_pol_22", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr18_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr18_write_pol_21", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr18_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr18_write_pol_20", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr18_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr18_write_pol_19", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr18_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr18_write_pol_18", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr18_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr18_write_pol_17", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr18_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr18_write_pol_16", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr18_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr18_write_pol_15", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr18_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr18_write_pol_14", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr18_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr18_write_pol_13", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr18_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr18_write_pol_12", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr18_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr18_write_pol_11", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr18_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr18_write_pol_10", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr18_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr18_write_pol_9", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr18_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr18_write_pol_8", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr18_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr18_write_pol_7", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr18_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr18_write_pol_6", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr18_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr18_write_pol_5", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr18_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr18_write_pol_4", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr18_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr18_write_pol_3", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr18_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr18_write_pol_2", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr18_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr18_write_pol_1", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr18_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr18_write_pol_0", "B-Unit IMR18 Write Access Policy: Bit vector used to determine which agents are allowed write access to the IMR18 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr18_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1150[] = {{"B_CR_BIMR18WAC_0_0_0_MCHBAR", "", 0x00006AC8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1151[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the IMR region."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents."},
#else
{30, 30, 0x0000000000000000, "RW", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr19_base", "Specifies bits 38:10 of the start address of IMR19 region. IMR region size must be a strict power of two, at least 1KB, and naturally aligned to the size. These bits are compared with the result of the IMR19MASK[28:0] applied to bits 38:10 of the incoming address to determine if an access falls within the IMR19 defined region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr19_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1151[] = {{"B_CR_BIMR19BASE_0_0_0_MCHBAR", "", 0x00006AD0, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1152[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 28, 0x0000000000000000, "RW", "imr19_mask", "These bits are ANDed with bits 38:10 of the incoming address to determine if the combined result matches the IMR19BASE[28:0] value. A match indicates that the incoming address falls within the IMR19 region."},
#else
{0, 28, 0x0000000000000000, "RW", "imr19_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1152[] = {{"B_CR_BIMR19MASK_0_0_0_MCHBAR", "", 0x00006AD4, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1153[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "imr19_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BIMR19RAC, BIMR19WAC, BIMR19CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "imr19_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1153[] = {{"B_CR_BIMR19CP_0_0_0_MCHBAR", "", 0x00006AD8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1154[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr19_read_pol_63", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr19_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr19_read_pol_62", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr19_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr19_read_pol_61", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr19_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr19_read_pol_60", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr19_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr19_read_pol_59", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr19_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr19_read_pol_58", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr19_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr19_read_pol_57", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr19_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr19_read_pol_56", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr19_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr19_read_pol_55", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr19_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr19_read_pol_54", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr19_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr19_read_pol_53", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr19_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr19_read_pol_52", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr19_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr19_read_pol_51", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr19_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr19_read_pol_50", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr19_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr19_read_pol_49", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr19_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr19_read_pol_48", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr19_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr19_read_pol_47", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr19_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr19_read_pol_46", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr19_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr19_read_pol_45", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr19_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr19_read_pol_44", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr19_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr19_read_pol_43", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr19_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr19_read_pol_42", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr19_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr19_read_pol_41", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr19_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr19_read_pol_40", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr19_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr19_read_pol_39", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr19_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr19_read_pol_38", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr19_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr19_read_pol_37", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr19_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr19_read_pol_36", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr19_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr19_read_pol_35", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr19_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr19_read_pol_34", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr19_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr19_read_pol_33", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr19_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr19_read_pol_32", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr19_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr19_read_pol_31", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr19_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr19_read_pol_30", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr19_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr19_read_pol_29", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr19_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr19_read_pol_28", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr19_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr19_read_pol_27", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr19_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr19_read_pol_26", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr19_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr19_read_pol_25", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr19_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr19_read_pol_24", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr19_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr19_read_pol_23", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr19_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr19_read_pol_22", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr19_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr19_read_pol_21", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr19_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr19_read_pol_20", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr19_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr19_read_pol_19", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr19_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr19_read_pol_18", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr19_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr19_read_pol_17", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr19_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr19_read_pol_16", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr19_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr19_read_pol_15", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr19_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr19_read_pol_14", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr19_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr19_read_pol_13", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr19_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr19_read_pol_12", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr19_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr19_read_pol_11", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr19_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr19_read_pol_10", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr19_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr19_read_pol_9", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr19_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr19_read_pol_8", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr19_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr19_read_pol_7", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr19_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr19_read_pol_6", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr19_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr19_read_pol_5", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr19_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr19_read_pol_4", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr19_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr19_read_pol_3", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr19_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr19_read_pol_2", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr19_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr19_read_pol_1", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr19_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr19_read_pol_0", "Bit vector used to determine which agents are allowed read access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr19_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1154[] = {{"B_CR_BIMR19RAC_0_0_0_MCHBAR", "", 0x00006AE0, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1155[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "imr19_write_pol_63", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "imr19_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "imr19_write_pol_62", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "imr19_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "imr19_write_pol_61", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "imr19_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "imr19_write_pol_60", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "imr19_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "imr19_write_pol_59", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "imr19_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "imr19_write_pol_58", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "imr19_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "imr19_write_pol_57", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "imr19_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "imr19_write_pol_56", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "imr19_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "imr19_write_pol_55", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "imr19_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "imr19_write_pol_54", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "imr19_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "imr19_write_pol_53", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "imr19_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "imr19_write_pol_52", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "imr19_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "imr19_write_pol_51", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "imr19_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "imr19_write_pol_50", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "imr19_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "imr19_write_pol_49", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "imr19_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "imr19_write_pol_48", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "imr19_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "imr19_write_pol_47", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "imr19_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "imr19_write_pol_46", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "imr19_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "imr19_write_pol_45", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "imr19_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "imr19_write_pol_44", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "imr19_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "imr19_write_pol_43", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "imr19_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "imr19_write_pol_42", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "imr19_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "imr19_write_pol_41", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "imr19_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "imr19_write_pol_40", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "imr19_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "imr19_write_pol_39", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "imr19_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "imr19_write_pol_38", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "imr19_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "imr19_write_pol_37", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "imr19_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "imr19_write_pol_36", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "imr19_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "imr19_write_pol_35", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "imr19_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "imr19_write_pol_34", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "imr19_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "imr19_write_pol_33", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "imr19_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "imr19_write_pol_32", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "imr19_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "imr19_write_pol_31", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "imr19_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "imr19_write_pol_30", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000000, "RW", "imr19_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RW", "imr19_write_pol_29", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000000, "RW", "imr19_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "imr19_write_pol_28", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "imr19_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "imr19_write_pol_27", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "imr19_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "imr19_write_pol_26", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "imr19_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "imr19_write_pol_25", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "imr19_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "imr19_write_pol_24", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "imr19_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "imr19_write_pol_23", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "imr19_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "imr19_write_pol_22", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "imr19_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "imr19_write_pol_21", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "imr19_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "imr19_write_pol_20", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "imr19_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "imr19_write_pol_19", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "imr19_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "imr19_write_pol_18", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "imr19_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "imr19_write_pol_17", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "imr19_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000000, "RW", "imr19_write_pol_16", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000000, "RW", "imr19_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "imr19_write_pol_15", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "imr19_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "imr19_write_pol_14", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "imr19_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "imr19_write_pol_13", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "imr19_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "imr19_write_pol_12", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "imr19_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "imr19_write_pol_11", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "imr19_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "imr19_write_pol_10", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "imr19_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "imr19_write_pol_9", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "imr19_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "imr19_write_pol_8", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "imr19_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "imr19_write_pol_7", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "imr19_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "imr19_write_pol_6", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "imr19_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "imr19_write_pol_5", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "imr19_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "imr19_write_pol_4", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "imr19_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "imr19_write_pol_3", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "imr19_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "imr19_write_pol_2", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "imr19_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "imr19_write_pol_1", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "imr19_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "imr19_write_pol_0", "Bit vector used to determine which agents are allowed write access to the IMR19 region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "imr19_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1155[] = {{"B_CR_BIMR19WAC_0_0_0_MCHBAR", "", 0x00006AE8, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1156[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "imr_en", "Enables access checking for the MOT region. Note: this does not enable MOT itself, but merely enables access control checks for transactions that attempt to access the MOT buffer."},
#else
{31, 31, 0x0000000000000000, "RW", "imr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RO", "tr_en", "Enables snooping of transactions to the IMR region by tracing agents such as MOT. Reserved and set to 0 for the MOT region, since otherwise this would enable recursive tracing and corrupt MOT buffer."},
#else
{30, 30, 0x0000000000000000, "RO", "tr_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 28, 0x0000000000000000, "RW", "mot_out_base", "Specifies bits 38:24 of the start address of the MOT memory region. Region size must be a strict power of two, at least 16MB, and naturally aligned to the size. These bits are compared with the result of the MOT_OUT_MASK[28:14] applied to bits 38:24 of the incoming address to determine if an access falls within the MOT region."},
#else
{14, 28, 0x0000000000000000, "RW", "mot_out_base", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 13, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 13, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1156[] = {{"B_CR_MOT_OUT_BASE_0_0_0_MCHBAR", "", 0x00006AF0, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1157[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{30, 30, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{29, 29, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 28, 0x0000000000000000, "RW", "mot_out_mask", "Specifies the size of the MOT region. If Request Address [38:24] ANDed with MOT_OUT_MASK[28:14] matches the MOT_OUT_BASE[28:14] then the request falls within the MOT_OUT region."},
#else
{14, 28, 0x0000000000000000, "RW", "mot_out_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 13, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 13, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1157[] = {{"B_CR_MOT_OUT_MASK_0_0_0_MCHBAR", "", 0x00006AF4, 5, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1158[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "mot_buf_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BMOT_BUF_RAC, BMOT_BUF_WAC and BMOT_BUF_CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "mot_buf_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1158[] = {{"B_CR_BMOT_BUF_CP_0_0_0_MCHBAR", "", 0x00006AF8, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1159[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "mot_buf_read_pol_63", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "mot_buf_read_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "mot_buf_read_pol_62", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "mot_buf_read_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "mot_buf_read_pol_61", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "mot_buf_read_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "mot_buf_read_pol_60", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "mot_buf_read_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "mot_buf_read_pol_59", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "mot_buf_read_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "mot_buf_read_pol_58", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "mot_buf_read_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "mot_buf_read_pol_57", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "mot_buf_read_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "mot_buf_read_pol_56", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "mot_buf_read_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "mot_buf_read_pol_55", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "mot_buf_read_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "mot_buf_read_pol_54", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "mot_buf_read_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "mot_buf_read_pol_53", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "mot_buf_read_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "mot_buf_read_pol_52", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "mot_buf_read_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "mot_buf_read_pol_51", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "mot_buf_read_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "mot_buf_read_pol_50", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "mot_buf_read_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "mot_buf_read_pol_49", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "mot_buf_read_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "mot_buf_read_pol_48", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "mot_buf_read_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "mot_buf_read_pol_47", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "mot_buf_read_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "mot_buf_read_pol_46", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "mot_buf_read_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "mot_buf_read_pol_45", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "mot_buf_read_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "mot_buf_read_pol_44", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "mot_buf_read_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "mot_buf_read_pol_43", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "mot_buf_read_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "mot_buf_read_pol_42", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "mot_buf_read_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "mot_buf_read_pol_41", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "mot_buf_read_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "mot_buf_read_pol_40", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "mot_buf_read_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "mot_buf_read_pol_39", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "mot_buf_read_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "mot_buf_read_pol_38", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "mot_buf_read_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "mot_buf_read_pol_37", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "mot_buf_read_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "mot_buf_read_pol_36", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "mot_buf_read_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "mot_buf_read_pol_35", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "mot_buf_read_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "mot_buf_read_pol_34", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "mot_buf_read_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "mot_buf_read_pol_33", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "mot_buf_read_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "mot_buf_read_pol_32", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "mot_buf_read_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "mot_buf_read_pol_31", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "mot_buf_read_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000001, "RW", "mot_buf_read_pol_30", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000001, "RW", "mot_buf_read_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RW", "mot_buf_read_pol_29", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000001, "RW", "mot_buf_read_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "mot_buf_read_pol_28", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "mot_buf_read_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "mot_buf_read_pol_27", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "mot_buf_read_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "mot_buf_read_pol_26", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "mot_buf_read_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "mot_buf_read_pol_25", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "mot_buf_read_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "mot_buf_read_pol_24", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "mot_buf_read_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "mot_buf_read_pol_23", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "mot_buf_read_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "mot_buf_read_pol_22", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "mot_buf_read_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "mot_buf_read_pol_21", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "mot_buf_read_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "mot_buf_read_pol_20", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "mot_buf_read_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "mot_buf_read_pol_19", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "mot_buf_read_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "mot_buf_read_pol_18", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "mot_buf_read_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "mot_buf_read_pol_17", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "mot_buf_read_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000001, "RW", "mot_buf_read_pol_16", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000001, "RW", "mot_buf_read_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "mot_buf_read_pol_15", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "mot_buf_read_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "mot_buf_read_pol_14", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "mot_buf_read_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "mot_buf_read_pol_13", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "mot_buf_read_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "mot_buf_read_pol_12", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "mot_buf_read_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "mot_buf_read_pol_11", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "mot_buf_read_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "mot_buf_read_pol_10", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "mot_buf_read_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "mot_buf_read_pol_9", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "mot_buf_read_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "mot_buf_read_pol_8", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "mot_buf_read_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "mot_buf_read_pol_7", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "mot_buf_read_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "mot_buf_read_pol_6", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "mot_buf_read_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "mot_buf_read_pol_5", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "mot_buf_read_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "mot_buf_read_pol_4", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000001, "RW", "mot_buf_read_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "mot_buf_read_pol_3", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "mot_buf_read_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "mot_buf_read_pol_2", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000001, "RW", "mot_buf_read_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "mot_buf_read_pol_1", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000001, "RW", "mot_buf_read_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "mot_buf_read_pol_0", "Bit vector used to determine which agents are allowed read access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000001, "RW", "mot_buf_read_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1159[] = {{"B_CR_BMOT_BUF_RAC_0_0_0_MCHBAR", "", 0x00006B00, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000060010017}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1160[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "mot_buf_write_pol_63", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "mot_buf_write_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "mot_buf_write_pol_62", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "mot_buf_write_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "mot_buf_write_pol_61", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "mot_buf_write_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "mot_buf_write_pol_60", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "mot_buf_write_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "mot_buf_write_pol_59", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "mot_buf_write_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "mot_buf_write_pol_58", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "mot_buf_write_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "mot_buf_write_pol_57", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "mot_buf_write_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "mot_buf_write_pol_56", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "mot_buf_write_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "mot_buf_write_pol_55", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "mot_buf_write_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "mot_buf_write_pol_54", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "mot_buf_write_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "mot_buf_write_pol_53", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "mot_buf_write_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "mot_buf_write_pol_52", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "mot_buf_write_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "mot_buf_write_pol_51", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "mot_buf_write_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "mot_buf_write_pol_50", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "mot_buf_write_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "mot_buf_write_pol_49", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "mot_buf_write_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "mot_buf_write_pol_48", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "mot_buf_write_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "mot_buf_write_pol_47", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "mot_buf_write_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "mot_buf_write_pol_46", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "mot_buf_write_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "mot_buf_write_pol_45", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "mot_buf_write_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000000, "RW", "mot_buf_write_pol_44", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000000, "RW", "mot_buf_write_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "mot_buf_write_pol_43", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "mot_buf_write_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "mot_buf_write_pol_42", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "mot_buf_write_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "mot_buf_write_pol_41", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "mot_buf_write_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "mot_buf_write_pol_40", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "mot_buf_write_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "mot_buf_write_pol_39", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "mot_buf_write_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "mot_buf_write_pol_38", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "mot_buf_write_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "mot_buf_write_pol_37", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "mot_buf_write_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "mot_buf_write_pol_36", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "mot_buf_write_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "mot_buf_write_pol_35", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "mot_buf_write_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "mot_buf_write_pol_34", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "mot_buf_write_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "mot_buf_write_pol_33", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "mot_buf_write_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "mot_buf_write_pol_32", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "mot_buf_write_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "mot_buf_write_pol_31", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "mot_buf_write_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000001, "RW", "mot_buf_write_pol_30", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000001, "RW", "mot_buf_write_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RW", "mot_buf_write_pol_29", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000001, "RW", "mot_buf_write_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "mot_buf_write_pol_28", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "mot_buf_write_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "mot_buf_write_pol_27", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "mot_buf_write_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "mot_buf_write_pol_26", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "mot_buf_write_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "mot_buf_write_pol_25", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "mot_buf_write_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "mot_buf_write_pol_24", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "mot_buf_write_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "mot_buf_write_pol_23", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "mot_buf_write_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "mot_buf_write_pol_22", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "mot_buf_write_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "mot_buf_write_pol_21", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "mot_buf_write_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "mot_buf_write_pol_20", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "mot_buf_write_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "mot_buf_write_pol_19", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "mot_buf_write_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "mot_buf_write_pol_18", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "mot_buf_write_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "mot_buf_write_pol_17", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "mot_buf_write_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000001, "RW", "mot_buf_write_pol_16", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000001, "RW", "mot_buf_write_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "mot_buf_write_pol_15", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "mot_buf_write_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "mot_buf_write_pol_14", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "mot_buf_write_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "mot_buf_write_pol_13", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "mot_buf_write_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "mot_buf_write_pol_12", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "mot_buf_write_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "mot_buf_write_pol_11", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "mot_buf_write_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "mot_buf_write_pol_10", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "mot_buf_write_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "mot_buf_write_pol_9", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "mot_buf_write_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "mot_buf_write_pol_8", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000000, "RW", "mot_buf_write_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "mot_buf_write_pol_7", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "mot_buf_write_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "mot_buf_write_pol_6", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "mot_buf_write_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "mot_buf_write_pol_5", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "mot_buf_write_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "mot_buf_write_pol_4", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "mot_buf_write_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "mot_buf_write_pol_3", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "mot_buf_write_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "mot_buf_write_pol_2", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "mot_buf_write_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "mot_buf_write_pol_1", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "mot_buf_write_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "mot_buf_write_pol_0", "Bit vector used to determine which agents are allowed write access to the MOT region, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "mot_buf_write_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1160[] = {{"B_CR_BMOT_BUF_WAC_0_0_0_MCHBAR", "", 0x00006B08, 64, 0xFFFFFFFFFFFFFFFF, 0x0000000060010000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1161[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "bm_ctrl_pol", "Bit vector used to determine which agents are allowed write access to BIMRGLOBAL_BM_WAC, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x00000C0061010202, "RW", "bm_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1161[] = {{"B_CR_BIMRGLOBAL_BM_CP_0_0_0_MCHBAR", "", 0x00006B10, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1162[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "bm_read_pol", "Bit vector used to determine which agents are allowed read access to all IMRxBASE and IMRxMASK registers, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "bm_read_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1162[] = {{"B_CR_BIMRGLOBAL_BM_RAC_0_0_0_MCHBAR", "", 0x00006B18, 1, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1163[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "bm_write_pol", "Bit vector used to determine which agents are allowed write access to all IMRxBASE and IMRxMASK registers, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x00000C0061010202, "RW", "bm_write_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1163[] = {{"B_CR_BIMRGLOBAL_BM_WAC_0_0_0_MCHBAR", "", 0x00006B20, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1164[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "gsm_ctrl_pol", "Bit vector used to determine which agents are allowed access to the BGSMRAC, BGSMWAC and BGSMCP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "gsm_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1164[] = {{"B_CR_BGSMCP_0_0_0_MCHBAR", "", 0x00006B28, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1165[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "gsm_sai_pol_63", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "gsm_sai_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "gsm_sai_pol_62", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "gsm_sai_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "gsm_sai_pol_61", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "gsm_sai_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "gsm_sai_pol_60", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "gsm_sai_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "gsm_sai_pol_59", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "gsm_sai_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "gsm_sai_pol_58", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "gsm_sai_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "gsm_sai_pol_57", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "gsm_sai_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "gsm_sai_pol_56", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "gsm_sai_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "gsm_sai_pol_55", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "gsm_sai_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "gsm_sai_pol_54", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "gsm_sai_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "gsm_sai_pol_53", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "gsm_sai_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "gsm_sai_pol_52", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "gsm_sai_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "gsm_sai_pol_51", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "gsm_sai_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "gsm_sai_pol_50", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "gsm_sai_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "gsm_sai_pol_49", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "gsm_sai_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "gsm_sai_pol_48", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "gsm_sai_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "gsm_sai_pol_47", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "gsm_sai_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "gsm_sai_pol_46", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "gsm_sai_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "gsm_sai_pol_45", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "gsm_sai_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000001, "RW", "gsm_sai_pol_44", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000001, "RW", "gsm_sai_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "gsm_sai_pol_43", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "gsm_sai_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "gsm_sai_pol_42", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "gsm_sai_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "gsm_sai_pol_41", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "gsm_sai_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "gsm_sai_pol_40", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "gsm_sai_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "gsm_sai_pol_39", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "gsm_sai_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "gsm_sai_pol_38", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "gsm_sai_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "gsm_sai_pol_37", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "gsm_sai_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "gsm_sai_pol_36", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "gsm_sai_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "gsm_sai_pol_35", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "gsm_sai_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "gsm_sai_pol_34", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "gsm_sai_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "gsm_sai_pol_33", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "gsm_sai_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "gsm_sai_pol_32", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "gsm_sai_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "gsm_sai_pol_31", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "gsm_sai_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000001, "RW", "gsm_sai_pol_30", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000001, "RW", "gsm_sai_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RW", "gsm_sai_pol_29", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000001, "RW", "gsm_sai_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "gsm_sai_pol_28", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "gsm_sai_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "gsm_sai_pol_27", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "gsm_sai_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "gsm_sai_pol_26", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "gsm_sai_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "gsm_sai_pol_25", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "gsm_sai_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "gsm_sai_pol_24", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "gsm_sai_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "gsm_sai_pol_23", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "gsm_sai_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "gsm_sai_pol_22", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "gsm_sai_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "gsm_sai_pol_21", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "gsm_sai_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "gsm_sai_pol_20", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "gsm_sai_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "gsm_sai_pol_19", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "gsm_sai_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "gsm_sai_pol_18", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "gsm_sai_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "gsm_sai_pol_17", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "gsm_sai_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000001, "RW", "gsm_sai_pol_16", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000001, "RW", "gsm_sai_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "gsm_sai_pol_15", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "gsm_sai_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "gsm_sai_pol_14", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "gsm_sai_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "gsm_sai_pol_13", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "gsm_sai_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "gsm_sai_pol_12", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "gsm_sai_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "gsm_sai_pol_11", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "gsm_sai_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "gsm_sai_pol_10", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "gsm_sai_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "gsm_sai_pol_9", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "gsm_sai_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "gsm_sai_pol_8", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000001, "RW", "gsm_sai_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "gsm_sai_pol_7", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "gsm_sai_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "gsm_sai_pol_6", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "gsm_sai_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "gsm_sai_pol_5", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "gsm_sai_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "gsm_sai_pol_4", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "gsm_sai_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "gsm_sai_pol_3", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "gsm_sai_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "gsm_sai_pol_2", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "gsm_sai_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "gsm_sai_pol_1", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "gsm_sai_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "gsm_sai_pol_0", "Bit vector used to determine which agents are allowed read access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "gsm_sai_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1165[] = {{"B_CR_BGSMRAC_0_0_0_MCHBAR", "", 0x00006B30, 64, 0xFFFFFFFFFFFFFFFF, 0x0000100060010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1166[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{63, 63, 0x0000000000000000, "RW", "gsm_sai_pol_63", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{63, 63, 0x0000000000000000, "RW", "gsm_sai_pol_63", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{62, 62, 0x0000000000000000, "RO", "gsm_sai_pol_62", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{62, 62, 0x0000000000000000, "RO", "gsm_sai_pol_62", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{61, 61, 0x0000000000000000, "RO", "gsm_sai_pol_61", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{61, 61, 0x0000000000000000, "RO", "gsm_sai_pol_61", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{60, 60, 0x0000000000000000, "RO", "gsm_sai_pol_60", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{60, 60, 0x0000000000000000, "RO", "gsm_sai_pol_60", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{59, 59, 0x0000000000000000, "RO", "gsm_sai_pol_59", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{59, 59, 0x0000000000000000, "RO", "gsm_sai_pol_59", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{58, 58, 0x0000000000000000, "RO", "gsm_sai_pol_58", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{58, 58, 0x0000000000000000, "RO", "gsm_sai_pol_58", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{57, 57, 0x0000000000000000, "RO", "gsm_sai_pol_57", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{57, 57, 0x0000000000000000, "RO", "gsm_sai_pol_57", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{56, 56, 0x0000000000000000, "RW", "gsm_sai_pol_56", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{56, 56, 0x0000000000000000, "RW", "gsm_sai_pol_56", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{55, 55, 0x0000000000000000, "RW", "gsm_sai_pol_55", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{55, 55, 0x0000000000000000, "RW", "gsm_sai_pol_55", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{54, 54, 0x0000000000000000, "RW", "gsm_sai_pol_54", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{54, 54, 0x0000000000000000, "RW", "gsm_sai_pol_54", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{53, 53, 0x0000000000000000, "RO", "gsm_sai_pol_53", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{53, 53, 0x0000000000000000, "RO", "gsm_sai_pol_53", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{52, 52, 0x0000000000000000, "RO", "gsm_sai_pol_52", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{52, 52, 0x0000000000000000, "RO", "gsm_sai_pol_52", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{51, 51, 0x0000000000000000, "RO", "gsm_sai_pol_51", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{51, 51, 0x0000000000000000, "RO", "gsm_sai_pol_51", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{50, 50, 0x0000000000000000, "RW", "gsm_sai_pol_50", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{50, 50, 0x0000000000000000, "RW", "gsm_sai_pol_50", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{49, 49, 0x0000000000000000, "RW", "gsm_sai_pol_49", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{49, 49, 0x0000000000000000, "RW", "gsm_sai_pol_49", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{48, 48, 0x0000000000000000, "RW", "gsm_sai_pol_48", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{48, 48, 0x0000000000000000, "RW", "gsm_sai_pol_48", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{47, 47, 0x0000000000000000, "RO", "gsm_sai_pol_47", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{47, 47, 0x0000000000000000, "RO", "gsm_sai_pol_47", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{46, 46, 0x0000000000000000, "RO", "gsm_sai_pol_46", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{46, 46, 0x0000000000000000, "RO", "gsm_sai_pol_46", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{45, 45, 0x0000000000000000, "RO", "gsm_sai_pol_45", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{45, 45, 0x0000000000000000, "RO", "gsm_sai_pol_45", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{44, 44, 0x0000000000000001, "RW", "gsm_sai_pol_44", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{44, 44, 0x0000000000000001, "RW", "gsm_sai_pol_44", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{43, 43, 0x0000000000000000, "RW", "gsm_sai_pol_43", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{43, 43, 0x0000000000000000, "RW", "gsm_sai_pol_43", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{42, 42, 0x0000000000000000, "RW", "gsm_sai_pol_42", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{42, 42, 0x0000000000000000, "RW", "gsm_sai_pol_42", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{41, 41, 0x0000000000000000, "RW", "gsm_sai_pol_41", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{41, 41, 0x0000000000000000, "RW", "gsm_sai_pol_41", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{40, 40, 0x0000000000000000, "RW", "gsm_sai_pol_40", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{40, 40, 0x0000000000000000, "RW", "gsm_sai_pol_40", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "gsm_sai_pol_39", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{39, 39, 0x0000000000000000, "RO", "gsm_sai_pol_39", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{38, 38, 0x0000000000000000, "RW", "gsm_sai_pol_38", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{38, 38, 0x0000000000000000, "RW", "gsm_sai_pol_38", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{37, 37, 0x0000000000000000, "RO", "gsm_sai_pol_37", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{37, 37, 0x0000000000000000, "RO", "gsm_sai_pol_37", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{36, 36, 0x0000000000000000, "RW", "gsm_sai_pol_36", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{36, 36, 0x0000000000000000, "RW", "gsm_sai_pol_36", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{35, 35, 0x0000000000000000, "RO", "gsm_sai_pol_35", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{35, 35, 0x0000000000000000, "RO", "gsm_sai_pol_35", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{34, 34, 0x0000000000000000, "RW", "gsm_sai_pol_34", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{34, 34, 0x0000000000000000, "RW", "gsm_sai_pol_34", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{33, 33, 0x0000000000000000, "RW", "gsm_sai_pol_33", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{33, 33, 0x0000000000000000, "RW", "gsm_sai_pol_33", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{32, 32, 0x0000000000000000, "RW", "gsm_sai_pol_32", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{32, 32, 0x0000000000000000, "RW", "gsm_sai_pol_32", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RO", "gsm_sai_pol_31", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{31, 31, 0x0000000000000000, "RO", "gsm_sai_pol_31", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000001, "RW", "gsm_sai_pol_30", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{30, 30, 0x0000000000000001, "RW", "gsm_sai_pol_30", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{29, 29, 0x0000000000000001, "RW", "gsm_sai_pol_29", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{29, 29, 0x0000000000000001, "RW", "gsm_sai_pol_29", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{28, 28, 0x0000000000000000, "RW", "gsm_sai_pol_28", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{28, 28, 0x0000000000000000, "RW", "gsm_sai_pol_28", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RW", "gsm_sai_pol_27", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{27, 27, 0x0000000000000000, "RW", "gsm_sai_pol_27", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW", "gsm_sai_pol_26", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{26, 26, 0x0000000000000000, "RW", "gsm_sai_pol_26", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "gsm_sai_pol_25", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{25, 25, 0x0000000000000000, "RW", "gsm_sai_pol_25", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "gsm_sai_pol_24", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{24, 24, 0x0000000000000000, "RW", "gsm_sai_pol_24", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RO", "gsm_sai_pol_23", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{23, 23, 0x0000000000000000, "RO", "gsm_sai_pol_23", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RO", "gsm_sai_pol_22", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{22, 22, 0x0000000000000000, "RO", "gsm_sai_pol_22", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{21, 21, 0x0000000000000000, "RW", "gsm_sai_pol_21", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{21, 21, 0x0000000000000000, "RW", "gsm_sai_pol_21", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000000, "RO", "gsm_sai_pol_20", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{20, 20, 0x0000000000000000, "RO", "gsm_sai_pol_20", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 19, 0x0000000000000000, "RO", "gsm_sai_pol_19", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{19, 19, 0x0000000000000000, "RO", "gsm_sai_pol_19", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RO", "gsm_sai_pol_18", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{18, 18, 0x0000000000000000, "RO", "gsm_sai_pol_18", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 17, 0x0000000000000000, "RW", "gsm_sai_pol_17", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{17, 17, 0x0000000000000000, "RW", "gsm_sai_pol_17", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000001, "RW", "gsm_sai_pol_16", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{16, 16, 0x0000000000000001, "RW", "gsm_sai_pol_16", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{15, 15, 0x0000000000000000, "RO", "gsm_sai_pol_15", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{15, 15, 0x0000000000000000, "RO", "gsm_sai_pol_15", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 14, 0x0000000000000000, "RO", "gsm_sai_pol_14", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{14, 14, 0x0000000000000000, "RO", "gsm_sai_pol_14", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 13, 0x0000000000000000, "RW", "gsm_sai_pol_13", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{13, 13, 0x0000000000000000, "RW", "gsm_sai_pol_13", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 12, 0x0000000000000000, "RW", "gsm_sai_pol_12", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{12, 12, 0x0000000000000000, "RW", "gsm_sai_pol_12", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{11, 11, 0x0000000000000000, "RO", "gsm_sai_pol_11", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{11, 11, 0x0000000000000000, "RO", "gsm_sai_pol_11", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 10, 0x0000000000000000, "RO", "gsm_sai_pol_10", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{10, 10, 0x0000000000000000, "RO", "gsm_sai_pol_10", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RO", "gsm_sai_pol_9", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{9, 9, 0x0000000000000000, "RO", "gsm_sai_pol_9", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "gsm_sai_pol_8", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{8, 8, 0x0000000000000001, "RW", "gsm_sai_pol_8", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{7, 7, 0x0000000000000000, "RO", "gsm_sai_pol_7", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{7, 7, 0x0000000000000000, "RO", "gsm_sai_pol_7", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 6, 0x0000000000000000, "RO", "gsm_sai_pol_6", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{6, 6, 0x0000000000000000, "RO", "gsm_sai_pol_6", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "gsm_sai_pol_5", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{5, 5, 0x0000000000000000, "RW", "gsm_sai_pol_5", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "gsm_sai_pol_4", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{4, 4, 0x0000000000000000, "RW", "gsm_sai_pol_4", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "gsm_sai_pol_3", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{3, 3, 0x0000000000000000, "RW", "gsm_sai_pol_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "gsm_sai_pol_2", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{2, 2, 0x0000000000000000, "RW", "gsm_sai_pol_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "gsm_sai_pol_1", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{1, 1, 0x0000000000000000, "RW", "gsm_sai_pol_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "gsm_sai_pol_0", "Bit vector used to determine which agents are allowed write access to the memory range from BGSM to TOLUD1, based on each agent's 6bit encoded SAI value."},
#else
{0, 0, 0x0000000000000000, "RW", "gsm_sai_pol_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1166[] = {{"B_CR_BGSMWAC_0_0_0_MCHBAR", "", 0x00006B38, 64, 0xFFFFFFFFFFFFFFFF, 0x0000100060010100}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1167[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "ctrl_pol", "Bit vector used to determine which agents are allowed write access to TPM_AC register, based on each agent's 6-bit encoded SAI value."},
#else
{0, 63, 0x00000C0061010202, "RW", "ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1167[] = {{"B_CR_TPM_CP_0_0_0_MCHBAR", "", 0x00006B40, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1168[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "ac_pol", "Bit vector used to determine which agents are allowed read/write access to TPM_SELECTOR, based on each agent's 6-bit encoded SAI value."},
#else
{0, 63, 0x00000C0061010202, "RW", "ac_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1168[] = {{"B_CR_TPM_AC_0_0_0_MCHBAR", "", 0x00006B48, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1169[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{5, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "rs0_en", "PII transactions from RS0 that hit the Graphics and Data Stolen Memory range will be allowed access only when both of the following conditions are met: a) Request SAI is in the legal permitted list as specified in the RAC/WAC policy registers and b) GSM_RS0_EN bit is set to 1. PII RS0 transactions targeting DRAM that do not hit any enabled IMR or special protected regions will always be allowed access."},
#else
{4, 4, 0x0000000000000001, "RW", "rs0_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester depending on the setting of the IA_IWB_EN bit."},
#else
{3, 3, 0x0000000000000001, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{2, 2, 0x0000000000000000, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "trace_en", "Enables snooping of transactions to the Graphics Stolen Memory region by tracing agents."},
#else
{1, 1, 0x0000000000000000, "RW", "trace_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "range_check_en", "Enables SAI checking for the memory range from BGSM to TOLUD-1"},
#else
{0, 0, 0x0000000000000001, "RW", "range_check_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1169[] = {{"B_CR_BGSM_CTRL_0_0_0_MCHBAR", "", 0x00006B50, 6, 0x00000000FFFFFFFF, 0x0000000000000019}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1170[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{5, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RO", "rs0_en", "No PII transaction is allowed access to SMM region.  As such RS0 asset classification bit does not apply and hence provisioned as a readonly bit and set to 0."},
#else
{4, 4, 0x0000000000000000, "RO", "rs0_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{3, 3, 0x0000000000000000, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent.  When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester.  When set to 0, inhibits HITM data from IA cores from being returned to the requester.  HITM data from GT may be returned to the requester depending on the setting of the GT_IWB_EN bit."},
#else
{2, 2, 0x0000000000000001, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "trace_en", "Enables snooping of transactions to the SMM region by tracing agents."},
#else
{1, 1, 0x0000000000000001, "RW", "trace_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "range_check_en", "Enables SAI checking for the SMM memory range: TSEGMB to BGSM."},
#else
{0, 0, 0x0000000000000001, "RW", "range_check_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1170[] = {{"B_CR_BSMR_CTRL_0_0_0_MCHBAR", "", 0x00006B54, 6, 0x00000000FFFFFFFF, 0x0000000000000007}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1171[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{5, 31, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{5, 31, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "rs0_en", "PII transactions from RS0 that hit VTd PMR high and low memory ranges will be allowed access only when both of the following conditions are met: a) Request SAI is in the legal permitted list as specified in the RAC/WAC policy registers and b) VTDPMR_RS0_EN bit is set to 1. PII RS0 transactions targeting DRAM that do not hit any enabled IMR or special protected regions will always be allowed access."},
#else
{4, 4, 0x0000000000000001, "RW", "rs0_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000001, "RW", "gt_iwb_en", "Enables implicit writebacks to protected region from GT caching agent. When set to 1, enables implicit writeback data HITM data from GT to be returned to the requester. When set to 0, inhibits HITM data from GT from being returned to the requester. HITM data from IA cores may be returned to the requester, depending on the setting of the IA_IWB_EN bit."},
#else
{3, 3, 0x0000000000000001, "RW", "gt_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "ia_iwb_en", "Enables implicit writebacks to protected region from IA caching agent. When set to 1, enables implicit writeback data HITM data from IA cores to be returned to the requester. When set to 0, inhibits HITM data from IA cores from being returned to the requester. HITM data from GT may be returned to the requester, depending on the setting of the GT_IWB_EN bit."},
#else
{2, 2, 0x0000000000000001, "RW", "ia_iwb_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "trace_en", "Enables snooping of transactions to the Default VTd PHM and PLM regions by tracing agents."},
#else
{1, 1, 0x0000000000000000, "RW", "trace_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 0, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1171[] = {{"B_CR_BDEFVTDPMR_CTRL_0_0_0_MCHBAR", "", 0x00006B58, 6, 0x00000000FFFFFFFF, 0x000000000000001C}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1172[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "upper_no_snoop_bound", "These bits are compared with bits 35:20 of the incoming address to determine the upper 1MB aligned value of the nonsnoop range when EnableNoSnoop is set."},
#else
{16, 31, 0x0000000000000000, "RW", "upper_no_snoop_bound", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "lower_no_snoop_bound", "These bits are compared with bits 35:20 of the incoming address to determine the lower 1MB aligned value of the protected range when EnableNoSnoop is set."},
#else
{0, 15, 0x0000000000000000, "RW", "lower_no_snoop_bound", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1172[] = {{"B_CR_BNOCACHE_0_0_0_MCHBAR", "", 0x00006B5C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1173[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{1, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_no_snoop", "When set, B-Unit compares bits 35:20 incoming addresses to Upper and Lower NoSnoop Bounds to see if the transaction should be prevented from issuing a processor snoop operation."},
#else
{0, 0, 0x0000000000000000, "RW", "enable_no_snoop", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1173[] = {{"B_CR_BNOCACHECTL_0_0_0_MCHBAR", "", 0x00006B60, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1174[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{28, 31, 0x000000000000000E, "RW", "flush_timer_period", "Specifies the duration of the periodic MOT flush timer.  Duration is 2^N cycles of a 19.2 MHz clock, where N is the value specified in the field."},
#else
{28, 31, 0x000000000000000E, "RW", "flush_timer_period", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 27, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{27, 27, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW/V", "sticky_trigger_1_match", "1 indicates Trigger 1 match. Cleared by powergood or explicit SW write."},
#else
{26, 26, 0x0000000000000000, "RW/V", "sticky_trigger_1_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW/V", "sticky_trigger_0_match", "1 indicates Trigger 0 match. Cleared by powergood or explicit SW write."},
#else
{25, 25, 0x0000000000000000, "RW/V", "sticky_trigger_0_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW/V", "sticky_filter_1_match", "1 indicates Filter 1 match. Cleared by powergood or explicit SW write."},
#else
{24, 24, 0x0000000000000000, "RW/V", "sticky_filter_1_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{23, 23, 0x0000000000000000, "RW/V", "sticky_filter_0_match", "1 indicates Filter 0 match. Cleared by powergood or explicit SW write."},
#else
{23, 23, 0x0000000000000000, "RW/V", "sticky_filter_0_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 22, 0x0000000000000000, "RW/V", "mot_storage_active", "Current status of MOT storage to memory. Used to save/restore trigger state across power states."},
#else
{22, 22, 0x0000000000000000, "RW/V", "mot_storage_active", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000000, "RW", "mot_trace_storage_stop_source", "A bit field allowing multiple triggers to result in a trace storage stop. Storage stop is the logical OR of trigger sources selected. Note that selecting the same trigger to start and stop trace storage results in start trace storage only. \r\n"
"              [list]\r\n"
"              [*]Bit position 5: External Trigger in 1 \r\n"
"              [*]Bit position 4: External Trigger in 0\r\n"
"              [*]Bit position 3: MOT Trigger  1 \r\n"
"              [*]Bit position 2: MOT Trigger 0 \r\n"
"              [*]Bit position 1: MOT Filter 1 match \r\n"
"              [*]Bit position 0: MOT Filter 0 match\r\n"
"              [/list]"},
#else
{16, 21, 0x0000000000000000, "RW", "mot_trace_storage_stop_source", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 15, 0x0000000000000000, "RW", "mot_trace_storage_start_source", "A bit field allowing multiple triggers to result in a trace storage start.  Storage stop is the logical OR of trigger sources selected. Note that selecting the same trigger to start and stop trace storage results in start trace storage only. For bit positions, see description for MOT_TRACE_STORAGE_STOP_SOURCE field."},
#else
{10, 15, 0x0000000000000000, "RW", "mot_trace_storage_start_source", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{9, 9, 0x0000000000000000, "RW", "enable_external_trigger_in_1", "[list]\r\n"
"              [*]1 to enable external trigger 1 to MOT from rdu_mid  \r\n"
"              [*]0 to disable external trigger 1 to MOT from rdu_mid\r\n"
"              [/list]"},
#else
{9, 9, 0x0000000000000000, "RW", "enable_external_trigger_in_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000000, "RW", "enable_external_trigger_in_0", "[list]\r\n"
"              [*]1 to enable external trigger 0 to MOT from rdu_mid  \r\n"
"              [*]0 to disable external trigger 0 to MOT from rdu_mid\r\n"
"              [/list]"},
#else
{8, 8, 0x0000000000000000, "RW", "enable_external_trigger_in_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RW", "trigger_out_source", "Select source of trigger sent to rdu_mid. \r\n"
"              [list]\r\n"
"              [*]00b: Filter 0 \r\n"
"              [*]01b: Filter 1 \r\n"
"              [*]10b: Trigger 0 \r\n"
"              [*]11b: Trigger 1\r\n"
"              [/list]"},
#else
{6, 7, 0x0000000000000000, "RW", "trigger_out_source", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000000, "RW", "enable_external_trigger_out_0", "[list]\r\n"
"              [*]1: enable external trigger out to from MOT to rdu_mid\r\n"
"              [*]0: disable external trigger out to from MOT to rdu_mid\r\n"
"              [/list]"},
#else
{5, 5, 0x0000000000000000, "RW", "enable_external_trigger_out_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000000, "RW", "enable_mot_trigger_1", "[list]\r\n"
"              [*]1: enable MOT trigger 1 \r\n"
"              [*]0: disable MOT trigger 1 \r\n"
"              [/list]"},
#else
{4, 4, 0x0000000000000000, "RW", "enable_mot_trigger_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "enable_mot_trigger_0", "[list]\r\n"
"              [*]1: enable MOT trigger 0 \r\n"
"              [*]0: disable MOT trigger 0 \r\n"
"              [/list]"},
#else
{3, 3, 0x0000000000000000, "RW", "enable_mot_trigger_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "enable_mot_filter_1", "[list]\r\n"
"              [*]1: enable MOT filter 1 \r\n"
"              [*]0: disable MOT filter 1 \r\n"
"              [/list]"},
#else
{2, 2, 0x0000000000000000, "RW", "enable_mot_filter_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "enable_mot_filter_0", "[list]\r\n"
"              [*]1: enable MOT filter 0 \r\n"
"              [*]0: disable MOT filter 0 \r\n"
"              [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "enable_mot_filter_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_mot", "[list]\r\n"
"              [*]1: enable MOT \r\n"
"              [*]0: disable MOT \r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "enable_mot", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1174[] = {{"B_CR_MOT_TRIG_TRACE_CTRL_0_0_0_MCHBAR", "", 0x00006B7C, 18, 0x00000000FFFFFFFF, 0x00000000E0000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1175[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 38, 0x0000000000000000, "RW/V", "mot_memory_pointer", "The current pointer into MOT slice 0 region. Cache line granularity bits [38:6]."},
#else
{6, 38, 0x0000000000000000, "RW/V", "mot_memory_pointer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 5, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{2, 5, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "near_or_far_memory", "Pin MOT slice 0 to near1 or far0 memory. This logic is implemented in the 2LM. Thus, this register bit is shadowed in its entirety in the 2LM. Unused by MOT."},
#else
{1, 1, 0x0000000000000001, "RW", "near_or_far_memory", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "mot_buffer_wrap", "Indication that the MOT slice 0 buffer has wrapped since the last clear of this write cleared by power good or explicit SW write."},
#else
{0, 0, 0x0000000000000000, "RW/V", "mot_buffer_wrap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1175[] = {{"B_CR_MOT_SLICE_0_MEM_PTR_0_0_0_MCHBAR", "", 0x00006B80, 5, 0xFFFFFFFFFFFFFFFF, 0x0000000000000002}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1176[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 38, 0x0000000000000000, "RW/V", "mot_memory_pointer", "The current pointer into MOT slice 1 region. Cache line granularity bits [38:6]."},
#else
{6, 38, 0x0000000000000000, "RW/V", "mot_memory_pointer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 5, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{2, 5, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000001, "RW", "near_or_far_memory", "Pin MOT slice 1 to near1 or far0 memory. This logic is implemented in the 2LM. Thus, this register is shadowed in its entirety in the 2LM."},
#else
{1, 1, 0x0000000000000001, "RW", "near_or_far_memory", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "mot_buffer_wrap", "Indication that the MOT slice 1 buffer has wrapped since the last clear of this write cleared by power good or explicit SW write."},
#else
{0, 0, 0x0000000000000000, "RW/V", "mot_buffer_wrap", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1176[] = {{"B_CR_MOT_SLICE_1_MEM_PTR_0_0_0_MCHBAR", "", 0x00006B88, 5, 0xFFFFFFFFFFFFFFFF, 0x0000000000000002}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1177[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{27, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW/V", "first_pkt_captured", "Indicates that MOT has captured the first data packet after tracing started."},
#else
{26, 26, 0x0000000000000000, "RW/V", "first_pkt_captured", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 25, 0x0000000000000000, "RW/V", "record_id", "The current MOT unique record ID number."},
#else
{0, 25, 0x0000000000000000, "RW/V", "record_id", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1177[] = {{"B_CR_MOT_SLICE_0_RECORD_ID_0_0_0_MCHBAR", "", 0x00006B90, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1178[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{27, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{27, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 26, 0x0000000000000000, "RW/V", "first_pkt_captured", "Indicates that MOT has captured the first data packet after tracing started."},
#else
{26, 26, 0x0000000000000000, "RW/V", "first_pkt_captured", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 25, 0x0000000000000000, "RW/V", "record_id", "The current MOT unique record ID number."},
#else
{0, 25, 0x0000000000000000, "RW/V", "record_id", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1178[] = {{"B_CR_MOT_SLICE_1_RECORD_ID_0_0_0_MCHBAR", "", 0x00006B94, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1179[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x0000000000000000, "RW", "mot_0_filter_match_address", "Access address to match. Match results in trace of access. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x0000000000000000, "RW", "mot_0_filter_match_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1179[] = {{"B_CR_MOT_FILTER_MATCH0_0_0_0_MCHBAR", "", 0x00006BA0, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1180[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_0_filter_mask_address", "Access address bits to mask. A value of 1 ignores the corresponding address bit. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_0_filter_mask_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1180[] = {{"B_CR_MOT_FILTER_MASK0_0_0_0_MCHBAR", "", 0x00006BA8, 3, 0xFFFFFFFFFFFFFFFF, 0x0000007FFFFFFFE0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1181[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x0000000000000000, "RW", "mot_1_filter_match_address", "Access address to match. Match results in trace of access. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x0000000000000000, "RW", "mot_1_filter_match_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1181[] = {{"B_CR_MOT_FILTER_MATCH1_0_0_0_MCHBAR", "", 0x00006BB0, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1182[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_1_filter_mask_address", "Access address bits to mask. A value of 1 ignores the corresponding address bit. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_1_filter_mask_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1182[] = {{"B_CR_MOT_FILTER_MASK1_0_0_0_MCHBAR", "", 0x00006BB8, 3, 0xFFFFFFFFFFFFFFFF, 0x0000007FFFFFFFE0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1183[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{35, 63, 0x0000000000000000, "RO", "reserved_0", "N/A"},
#else
{35, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 34, 0x0000000000000000, "RW", "ia_core_match", "Match if transaction originated from one of up to 16 IA cores (one bit per logical processor)."},
#else
{19, 34, 0x0000000000000000, "RW", "ia_core_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "gt_match", "[list]\r\n"
"              [*]1: match \r\n"
"              [*]0: ignore\r\n"
"              [/list]"},
#else
{18, 18, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 17, 0x0000000000000000, "RW", "vc_match", "Match if transaction originated from one of up to 16 virtual channel cores (one bit per VC)."},
#else
{2, 17, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", "[list]\r\n"
"              [*]1: filter inversion \r\n"
"              [*]0: match criteria\r\n"
"              [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", "[list]\r\n"
"              [*]1: match writes \r\n"
"              [*]0: match reads\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1183[] = {{"B_CR_MOT_FILTER_MISC0_0_0_0_MCHBAR", "", 0x00006BC0, 6, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1184[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{35, 63, 0x0000000000000000, "RO", "reserved_0", "N/A"},
#else
{35, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 34, 0x0000000000000000, "RW", "ia_core_match", "Match if transaction originated from one of up to 16 IA cores (one bit per logical processor)."},
#else
{19, 34, 0x0000000000000000, "RW", "ia_core_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "gt_match", "[list]\r\n"
"              [*]1: match \r\n"
"              [*]0: ignore\r\n"
"              [/list]"},
#else
{18, 18, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 17, 0x0000000000000000, "RW", "vc_match", "Match if transaction originated from one of up to 16 virtual channel cores (one bit per VC)."},
#else
{2, 17, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", "[list]\r\n"
"              [*]1: filter inversion \r\n"
"              [*]0: match criteria\r\n"
"              [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", "[list]\r\n"
"              [*]1: match writes \r\n"
"              [*]0: match reads\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1184[] = {{"B_CR_MOT_FILTER_MISC1_0_0_0_MCHBAR", "", 0x00006BC8, 6, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1185[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x0000000000000000, "RW", "mot_0_trigger_match_address", "Access address to match. Match results in trace of access. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x0000000000000000, "RW", "mot_0_trigger_match_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1185[] = {{"B_CR_MOT_TRIGGER_MATCH0_0_0_0_MCHBAR", "", 0x00006BD0, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1186[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_0_trigger_mask_address", "Access address bits to mask. A value of 1 ignores the corresponding address bit. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_0_trigger_mask_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1186[] = {{"B_CR_MOT_TRIGGER_MASK0_0_0_0_MCHBAR", "", 0x00006BD8, 3, 0xFFFFFFFFFFFFFFFF, 0x0000007FFFFFFFE0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1187[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x0000000000000000, "RW", "mot_1_trigger_match_address", "Access address to match. Match results in trace of access. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x0000000000000000, "RW", "mot_1_trigger_match_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1187[] = {{"B_CR_MOT_TRIGGER_MATCH1_0_0_0_MCHBAR", "", 0x00006BE0, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1188[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_1_trigger_mask_address", "Access address bits to mask. A value of 1 ignores the corresponding address bit. Half cache line granularity bits 38:5 to support legacy devices."},
#else
{5, 38, 0x00000003FFFFFFFF, "RW", "mot_1_trigger_mask_address", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 4, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{0, 4, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1188[] = {{"B_CR_MOT_TRIGGER_MASK1_0_0_0_MCHBAR", "", 0x00006BE8, 3, 0xFFFFFFFFFFFFFFFF, 0x0000007FFFFFFFE0}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1189[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{35, 63, 0x0000000000000000, "RO", "reserved_0", "N/A"},
#else
{35, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 34, 0x0000000000000000, "RW", "ia_core_match", "Match if transaction originated from one of up to 16 IA cores (one bit per logical processor)."},
#else
{19, 34, 0x0000000000000000, "RW", "ia_core_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "gt_match", "[list]\r\n"
"              [*]1: match \r\n"
"              [*]0: ignore\r\n"
"              [/list]"},
#else
{18, 18, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 17, 0x0000000000000000, "RW", "vc_match", "Match if transaction originated from one of up to 16 virtual channel cores (one bit per VC)."},
#else
{2, 17, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", "[list]\r\n"
"              [*]1: filter inversion \r\n"
"              [*]0: match criteria\r\n"
"              [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", "[list]\r\n"
"              [*]1: match writes \r\n"
"              [*]0: match reads\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1189[] = {{"B_CR_MOT_TRIGGER_MISC0_0_0_0_MCHBAR", "", 0x00006BF0, 6, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1190[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{35, 63, 0x0000000000000000, "RO", "reserved_0", "N/A"},
#else
{35, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 34, 0x0000000000000000, "RW", "ia_core_match", "Match if transaction originated from one of up to 16 IA cores (one bit per logical processor)."},
#else
{19, 34, 0x0000000000000000, "RW", "ia_core_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{18, 18, 0x0000000000000000, "RW", "gt_match", "[list]\r\n"
"              [*]1: match \r\n"
"              [*]0: ignore\r\n"
"              [/list]"},
#else
{18, 18, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 17, 0x0000000000000000, "RW", "vc_match", "Match if transaction originated from one of up to 16 virtual channel cores (one bit per VC)."},
#else
{2, 17, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", "[list]\r\n"
"              [*]1: filter inversion \r\n"
"              [*]0: match criteria\r\n"
"              [/list]"},
#else
{1, 1, 0x0000000000000000, "RW", "addr_match_polarity", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", "[list]\r\n"
"              [*]1: match writes \r\n"
"              [*]0: match reads\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW", "access_type_match_read_or_write", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1190[] = {{"B_CR_MOT_TRIGGER_MISC1_0_0_0_MCHBAR", "", 0x00006BF8, 6, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1191[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{2, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW/V", "psmi_sync1", "Set by PSMI microcode. Once set, cleared by HW after creation of first MOT record in Slice1."},
#else
{1, 1, 0x0000000000000000, "RW/V", "psmi_sync1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/V", "psmi_sync0", "Set by PSMI microcode. Once set, cleared by HW after creation of first MOT record in Slice0."},
#else
{0, 0, 0x0000000000000000, "RW/V", "psmi_sync0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1191[] = {{"B_CR_MOT_PSMI_SYNC_0_0_0_MCHBAR", "", 0x00006C00, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1192[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{2, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{2, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 1, 0x0000000000000000, "RW", "tpm_selector", "[list]\r\n"
"              [*]0h: fTPM enabled. Target of TPM accesses is the CSE.\r\n"
"              [*]1h: SPI TPM enabled. Target of TPM accesses is SPI.\r\n"
"              [*]2h: LPC TPM enabled. Target of TPM accesses is LPC.  \r\n"
"              [*]3h: All TPMs disabled. Target of TPM accesses is the PSF Error Handler.\r\n"
"              [/list]"},
#else
{0, 1, 0x0000000000000000, "RW", "tpm_selector", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1192[] = {{"B_CR_TPM_SELECTOR_0_0_0_MCHBAR", "", 0x00006C24, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1193[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{40, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{40, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{39, 39, 0x0000000000000000, "RO", "defvtdbar_40_bit", "Reserved for future growth to 40bit addressing in uServer. Will always be 0 in WLV/BXT."},
#else
{39, 39, 0x0000000000000000, "RO", "defvtdbar_40_bit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 38, 0x0000000000000000, "RW", "defvtdbar", "If DEFVTDBAR is enabled, this field corresponds to bits 38:12 of the base address default IOMMU VTd configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the default VTd IOMMU register set. If DEFVTDBAR is enabled and incoming Request Address[38:12] matches DEFVTDBAR[38:12] the request targets the Default VTd BAR."},
#else
{12, 38, 0x0000000000000000, "RW", "defvtdbar", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 11, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{2, 11, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lock", "Locks the contents of the register including itself. Unused by the B-Unit, and does not implement the intended lock functionality. B-Unit includes this bit to support shadow copies of the register that rely on this lock bit."},
#else
{1, 1, 0x0000000000000000, "RW", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/L", "defvtdbaren", "[list]\r\n"
"              [*]0: DEFVTDBAR is disabled and does not claim any memory\r\n"
"              [*]1: DEFVTDBAR memory mapped accesses are claimed and decoded appropriately. This bit will remain 0 if VTd capability is disabled.\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW/L", "defvtdbaren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1193[] = {{"B_CR_DEFVTDBAR_0_0_0_MCHBAR", "", 0x00006C80, 6, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1194[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 38, 0x0000000000000000, "RW", "gfxvtbar", "This field corresponds to bits 38 to 12 of the base address GFXVT configuration space. BIOS will program this register, resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the GFXVT register set. If GFXVTBAR is enabled and incoming Request Address[38:12] matches GFXVTBAR[38:12] the request targets the Gfx VTd BAR."},
#else
{12, 38, 0x0000000000000000, "RW", "gfxvtbar", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 11, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{2, 11, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lock", "Locks the contents of the register, including itself. Unused by the B-Unit, and does not implement the intended lock functionality. B-Unit includes this bit to support shadow copies of the register that rely on this lock bit."},
#else
{1, 1, 0x0000000000000000, "RW", "lock", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW/L", "gfxvtbaren", "[list]\r\n"
"              [*]0: GFXVTBAR is disabled and does not claim any memory\r\n"
"              [*]1: GFXVTBAR memory mapped accesses are claimed and decoded appropriately. This bit will remain 0 if VTd capability is disabled.\r\n"
"              [/list]"},
#else
{0, 0, 0x0000000000000000, "RW/L", "gfxvtbaren", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1194[] = {{"B_CR_GFXVTDBAR_0_0_0_MCHBAR", "", 0x00006C88, 5, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1195[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RW", "idi_length_match", "Enables length matching for IDI requests for Lites Group 0. Each bit, when set to 1, enables match for that length for an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only 64B for all other opcodes. \r\n"
"	  [list]\r\n"
"	    [*]Bit 31:64B                  \r\n"
"	    [*]Bit 30:16B                  \r\n"
"	    [*]Bit 29:15B                  \r\n"
"	    [*]Bit 28:14B                  \r\n"
"	    [*]Bit 27:13B                  \r\n"
"	    [*]Bit 26:12B                  \r\n"
"	    [*]Bit 25:11B                  \r\n"
"	    [*]Bit 24:10B                  \r\n"
"	    [*]Bit 23:9B                  \r\n"
"	    [*]Bit 22:8B                  \r\n"
"	    [*]Bit 21:7B                  \r\n"
"	    [*]Bit 20:6B                  \r\n"
"	    [*]Bit 19:5B                  \r\n"
"	    [*]Bit 18:4B                  \r\n"
"	    [*]Bit 17:3B                  \r\n"
"	    [*]Bit 16:2B                  \r\n"
"	    [*]Bit 15:1B                  \r\n"
"	    [*]Bit 14:0B\r\n"
"	  [/list]"},
#else
{14, 31, 0x0000000000000000, "RW", "idi_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "pii_length_match", "Enables length matching for PII requests for Lites Group 0. Each bit, when set to 1, enables length match for the PII request.\r\n"
"             [list]\r\n"
"             [*]Bit 13:64B                   \r\n"
"             [*]Bit 12:32B\r\n"
"             [/list]"},
#else
{12, 13, 0x0000000000000000, "RW", "pii_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{10, 11, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "slice_match", "[list]\r\n"
"              [*]00: All mask/match hits are suppressed \r\n"
"              [*]01: Mask/Match hits enabled only for Slice0 \r\n"
"              [*]10: Mask/match hits enabled only for Slice1 \r\n"
"              [*]11: Mask/Match hits enabled for both Slices\r\n"
"              [/list]"},
#else
{8, 9, 0x0000000000000000, "RW", "slice_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "dword_select", "Selects the dword within the 512bit data field that is compared for data mask/matches for Lites Group 0."},
#else
{4, 7, 0x0000000000000000, "RW", "dword_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "enable_data_match", "When set, this field enables data matching on Lites Group 0."},
#else
{3, 3, 0x0000000000000000, "RW", "enable_data_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "altu2creqview", "When set, address match/mask, opcode match and agent match registers are used to generate matches for the U2C request observation point. When clear, Badmit observation point matches are reported on the U2C request observation point."},
#else
{2, 2, 0x0000000000000000, "RW", "altu2creqview", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", "When set, inverts the polarity of the address match/mask logic, i.e., reports a match for addresses that are not in the specified range."},
#else
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_group", "Enables all match filters for Lites Group 0. The following are the observation points that contain match filters:  Badmit logic within each slice after a transaction is successfully admitted into the B-Unit, U2C request launch, PMI datain for each PMI channel for read data, PMI dataout for each PMI channel for writes, data write from requesters to BRAM in each slice, and read data return on the live bypass and nonlive bypass paths in each slice. To report a match at an observation point, all match criteria for that point must be satisfied."},
#else
{0, 0, 0x0000000000000000, "RW", "enable_group", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1195[] = {{"B_CR_LITES0_CTL_0_0_0_MCHBAR", "", 0x00006C90, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1196[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "opcode_match", "Bit vector that enables a match on the opcode for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation points, Badmit in both slices  and the U2C request interface, use this same opcode match register. Each bit, when set, enables a match on the corresponding opcode, and, when clear, will suppress a match on the corresponding opcode. To match on any opcode, set all bits to 1.\r\n"
"      [list] \r\n"
"      [*]Bit 31: C2U_Req_CRd  \r\n"
"      [*]Bit 30: C2U_Req_DRd  \r\n"
"      [*]Bit 29: C2U_Req_DRdPTE  \r\n"
"      [*]Bit 28: C2U_Req_SetMonitor  \r\n"
"      [*]Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet  \r\n"
"      [*]Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet \r\n"
"      [*]Bit 25: C2U_Req_UcRdF  \r\n"
"      [*]Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode  \r\n"
"      [*]Bit 23: C2U_Req_IntA,U2C_Req_SnpData  \r\n"
"      [*]Bit 22: C2U_Req_Lock  \r\n"
"      [*]Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet  \r\n"
"      [*]Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet  \r\n"
"      [*]Bit 19: C2U_Req_ItoM  \r\n"
"      [*]Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv  \r\n"
"      [*]Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq  \r\n"
"      [*]Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq  \r\n"
"      [*]Bit 15: C2U_Req_CLFlush  \r\n"
"      [*]Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI  \r\n"
"      [*]Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI  \r\n"
"      [*]Bit 12: C2U_Req_WiL  \r\n"
"      [*]Bit 11: C2U_Req_WCiL  \r\n"
"      [*]Bit 10: C2U_Req_WCilF  \r\n"
"      [*]Bit 9: C2U_Req_PortOut  \r\n"
"      [*]Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite  \r\n"
"      [*]Bit 7: C2U_Req_IntLog  \r\n"
"      [*]Bit 6: C2U_Req_IntPhy  \r\n"
"      [*]Bit 5: C2U_Req_EOI,U2C_Req_VLW  \r\n"
"      [*]Bit 4: C2U_Req_ItoMWr  \r\n"
"      [*]Bit 3: A2B_Req_SnoopedRead  \r\n"
"      [*]Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI  \r\n"
"      [*]Bit 1: A2B_Req_SnoopedWrite  \r\n"
"      [*]Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI\r\n"
"      [/list]"},
#else
{0, 31, 0x0000000000000000, "RW", "opcode_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1196[] = {{"B_CR_LITES0_OPCODE_MATCH_0_0_0_MCHBAR", "", 0x00006C94, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1197[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_match", "This field is used to match IDI transactions from GT for Lites Group0. When set, enables a match for a transaction originating from GT. When clear, suppresses a match for a transaction from GT."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 30, 0x0000000000000000, "RW", "vc_match", "This field is used to match VC Channel ID for PII transactions for Lites Group0. Each bit, when set, enables a match for a transaction originating from that VC. When clear, suppresses a match for a transaction from that VC.\r\n"
"       [list]      \r\n"
"       [*]Bit 30: VC14   \r\n"
"       [*]Bit 29: VC13   \r\n"
"       [*]Bit 28: VC12   \r\n"
"       [*]Bit 27: VC11   \r\n"
"       [*]Bit 26: VC10   \r\n"
"       [*]Bit 25: VC9   \r\n"
"       [*]Bit 24: VC8   \r\n"
"       [*]Bit 23: VC7   \r\n"
"       [*]Bit 22: VC6   \r\n"
"       [*]Bit 21: VC5   \r\n"
"       [*]Bit 20: VC4   \r\n"
"       [*]Bit 19: VC3   \r\n"
"       [*]Bit 18: VC2   \r\n"
"       [*]Bit 17: VC1   \r\n"
"       [*]Bit 16: VC0\r\n"
"       [/list]"},
#else
{16, 30, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", "This field is used to match Logical Processor Core ID for CPU IDI transactions for Lites Group 0. Each bit, when set, enables a match for a transaction originating from that core. When clear, suppresses a match for a transaction from that core. \r\n"
"               [list]\r\n"
"               [*]Bit 15: CPU7 Core1   \r\n"
"               [*]Bit 14: CPU7 Core0   \r\n"
"               [*]Bit 13: CPU6 Core1  \r\n"
"               [*]Bit 12: CPU6 Core0   \r\n"
"               [*]Bit 11: CPU5 Core1   \r\n"
"               [*]Bit 10: CPU5 Core0   \r\n"
"               [*]Bit 9: CPU4 Core1   \r\n"
"               [*]Bit 8: CPU4 Core0   \r\n"
"               [*]Bit 7: CPU3 Core1   \r\n"
"               [*]Bit 6: CPU3 Core0   \r\n"
"               [*]Bit 5: CPU2 Core1   \r\n"
"               [*]Bit 4: CPU2 Core0   \r\n"
"               [*]Bit 3: CPU1 Core1   \r\n"
"               [*]Bit 2: CPU1 Core0   \r\n"
"               [*]Bit 1: CPU0 Core1   \r\n"
"               [*]Bit 0: CPU0 Core0\r\n"
"               [/list]"},
#else
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1197[] = {{"B_CR_LITES0_AGENT_MATCH_0_0_0_MCHBAR", "", 0x00006C98, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1198[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "intdata_mask", "This mask is for generating Lites Group 0 U2C request alternative view match.  Only bits [7:0] of this field are used; bits [15:8] are ignored.  If a mask bit in this register is 0, then the corresponding bit in the INTDATA_MATCH field is ignored. If the mask bit is 1, then the corresponding bit in the INTDATA_MATCH[7:0] field must match its corresponding u2c request IntData[15:8] bit for a match."},
#else
{16, 31, 0x0000000000000000, "RW", "intdata_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "intdata_match", "U2C Request IntData[15:8] value is compared with bits [7:0] of this field to generate a match for the U2C request address match.  Bits [15:8] of this field are ignored.  Note that matching based on the IntData[7:0] bits is not supported."},
#else
{0, 15, 0x0000000000000000, "RW", "intdata_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1198[] = {{"B_CR_LITES0_U2CINTDATA_MATCH_0_0_0_MCHBAR", "", 0x00006C9C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1199[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_match", "Address value to match for Lites."},
#else
{3, 38, 0x0000000000000000, "RW", "address_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1199[] = {{"B_CR_LITES0_ADDR_MATCH_0_0_0_MCHBAR", "", 0x00006CA0, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1200[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_mask", "Address mask value used for comparing request address during filter operation for Lites. If the mask bit in this register is 0, then the corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the ADDR_MATCH register must match the corresponding request address bit for a match."},
#else
{3, 38, 0x0000000000000000, "RW", "address_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1200[] = {{"B_CR_LITES0_ADDR_MASK_0_0_0_MCHBAR", "", 0x00006CA8, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1201[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_match", "Data value to match for Lites."},
#else
{0, 31, 0x0000000000000000, "RW", "data_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1201[] = {{"B_CR_LITES0_DATA_MATCH_0_0_0_MCHBAR", "", 0x00006CB0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1202[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_mask", "Data mask value used for comparing data during filter operations for Lites. If the mask bit in this register is 0, then the corresponding bit in the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the DATA_MATCH register must match the corresponding bit of the request data for a match."},
#else
{0, 31, 0x0000000000000000, "RW", "data_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1202[] = {{"B_CR_LITES0_DATA_MASK_0_0_0_MCHBAR", "", 0x00006CB4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1203[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RW", "idi_length_match", "Enables length matching for IDI requests for Lites Group 1. Each bit, when set to 1, enables match for that length for an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only 64B for all other opcodes. \r\n"
"	  [list]\r\n"
"	    [*]Bit 31:64B                  \r\n"
"	    [*]Bit 30:16B                  \r\n"
"	    [*]Bit 29:15B                  \r\n"
"	    [*]Bit 28:14B                  \r\n"
"	    [*]Bit 27:13B                  \r\n"
"	    [*]Bit 26:12B                  \r\n"
"	    [*]Bit 25:11B                  \r\n"
"	    [*]Bit 24:10B                  \r\n"
"	    [*]Bit 23:9B                  \r\n"
"	    [*]Bit 22:8B                  \r\n"
"	    [*]Bit 21:7B                  \r\n"
"	    [*]Bit 20:6B                  \r\n"
"	    [*]Bit 19:5B                  \r\n"
"	    [*]Bit 18:4B                  \r\n"
"	    [*]Bit 17:3B                  \r\n"
"	    [*]Bit 16:2B                  \r\n"
"	    [*]Bit 15:1B                  \r\n"
"	    [*]Bit 14:0B\r\n"
"	  [/list]"},
#else
{14, 31, 0x0000000000000000, "RW", "idi_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "pii_length_match", "Enables length matching for PII requests for Lites Group 1. Each bit, when set to 1, enables length match for the PII request.\r\n"
"        [list]                  \r\n"
"        [*]Bit 13:64B                   \r\n"
"        [*]Bit 12:32B\r\n"
"        [/list]"},
#else
{12, 13, 0x0000000000000000, "RW", "pii_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{10, 11, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "slice_match", "\r\n"
"         [list]\r\n"
"         [*]00: All mask/match hits are suppressed \r\n"
"         [*]01: mask/match hits enabled only for Slice0 \r\n"
"         [*]10: mask/match hits enabled only for Slice1 \r\n"
"         [*]11: mask/match hits enabled for both Slices\r\n"
"         [/list]"},
#else
{8, 9, 0x0000000000000000, "RW", "slice_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "dword_select", "Selects the dword within the 512bit data field that is compared for data mask/matches for Lites Group 1."},
#else
{4, 7, 0x0000000000000000, "RW", "dword_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "enable_data_match", "When set, this field enables data matching on Lites Group 1."},
#else
{3, 3, 0x0000000000000000, "RW", "enable_data_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "altu2creqview", "When set, address match/mask opcode match and agent match registers are used to generate matches for the U2C request observation point. When clear, Badmit observation point matches are reported on the U2C request observation point."},
#else
{2, 2, 0x0000000000000000, "RW", "altu2creqview", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", "When set, inverts the polarity of the address match/mask logic, i.e., reports a match for addresses that are not in the specified range."},
#else
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_group", "Enables all match filters for Lites Group 1. The following are the observation points that contain match filters:  Badmit logic within each slice after a transaction is successfully admitted into the B-Unit, U2C request launch, PMI datain for each PMI channel for read data, PMI dataout for each PMI channel for writes, data write from requesters to BRAM in each slice, and read data return on the live bypass and nonlive bypass paths in each slice. To report a match at an observation point, all match criteria for that point must be satisfied."},
#else
{0, 0, 0x0000000000000000, "RW", "enable_group", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1203[] = {{"B_CR_LITES1_CTL_0_0_0_MCHBAR", "", 0x00006CC0, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1204[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "opcode_match", "Bit vector that enables a match on the opcode for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation points -- Badmit in both slices, and the U2C request interface -- use this same opcode match register. Each bit, when set, enables a match on the corresponding opcode, and when clear will suppress a match on the corresponding opcode. To match on any opcode, set all bits to 1.\r\n"
"              [list] \r\n"
"              [*]Bit 31: C2U_Req_CRd  \r\n"
"              [*]Bit 30: C2U_Req_DRd  \r\n"
"              [*]Bit 29: C2U_Req_DRdPTE  \r\n"
"              [*]Bit 28: C2U_Req_SetMonitor  \r\n"
"              [*]Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet  \r\n"
"              [*]Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet \r\n"
"              [*]Bit 25: C2U_Req_UcRdF  \r\n"
"              [*]Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode  \r\n"
"              [*]Bit 23: C2U_Req_IntA,U2C_Req_SnpData  \r\n"
"              [*]Bit 22: C2U_Req_Lock  \r\n"
"              [*]Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet  \r\n"
"              [*]Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet  \r\n"
"              [*]Bit 19: C2U_Req_ItoM  \r\n"
"              [*]Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv  \r\n"
"              [*]Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq  \r\n"
"              [*]Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq  \r\n"
"              [*]Bit 15: C2U_Req_CLFlush  \r\n"
"              [*]Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI  \r\n"
"              [*]Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI  \r\n"
"              [*]Bit 12: C2U_Req_WiL  \r\n"
"              [*]Bit 11: C2U_Req_WCiL  \r\n"
"              [*]Bit 10: C2U_Req_WCilF  \r\n"
"              [*]Bit 9: C2U_Req_PortOut  \r\n"
"              [*]Bit 8: C2U_Req_IntPriUp,U2C_Req_LTWrite  \r\n"
"              [*]Bit 7: C2U_Req_IntLog  \r\n"
"              [*]Bit 6: C2U_Req_IntPhy  \r\n"
"              [*]Bit 5: C2U_Req_EOI,U2C_Req_VLW  \r\n"
"              [*]Bit 4: C2U_Req_ItoMWr  \r\n"
"              [*]Bit 3: A2B_Req_SnoopedRead  \r\n"
"              [*]Bit 2: A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI  \r\n"
"              [*]Bit 1: A2B_Req_SnoopedWrite  \r\n"
"              [*]Bit 0: A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI\r\n"
"              [/list]"},
#else
{0, 31, 0x0000000000000000, "RW", "opcode_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1204[] = {{"B_CR_LITES1_OPCODE_MATCH_0_0_0_MCHBAR", "", 0x00006CC4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1205[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_match", "This field is used to match IDI transactions from GT for Lites Group1. When set, enables a match for a transaction originating from GT. When clear, suppresses a match for a transaction from GT."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 30, 0x0000000000000000, "RW", "vc_match", "This field is used to match VC Channel ID for PII transactions for Lites Group1. Each bit, when set, enables a match for a transaction originating from that VC. When clear, each bit suppresses a match for a transaction from that VC.   \r\n"
"             [list]\r\n"
"             [*]Bit 30: VC14   \r\n"
"             [*]Bit 29: VC13   \r\n"
"             [*]Bit 28: VC12   \r\n"
"             [*]Bit 27: VC11   \r\n"
"             [*]Bit 26: VC10   \r\n"
"             [*]Bit 25: VC9   \r\n"
"             [*]Bit 24: VC8   \r\n"
"             [*]Bit 23: VC7   \r\n"
"             [*]Bit 22: VC6   \r\n"
"             [*]Bit 21: VC5   \r\n"
"             [*]Bit 20: VC4   \r\n"
"             [*]Bit 19: VC3   \r\n"
"             [*]Bit 18: VC2   \r\n"
"             [*]Bit 17: VC1   \r\n"
"             [*]Bit 16: VC0\r\n"
"             [/list]"},
#else
{16, 30, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", "This field is used to match Logical Processor Core ID for CPU IDI transactions, for Lites Group 1. Each bit, when set, enables a match for a transaction originating from that core. When clear, each bit suppresses a match for a transaction from that core.   \r\n"
"              [list]\r\n"
"              [*]Bit 15: CPU7 Core1   \r\n"
"              [*]Bit 14: CPU7 Core0   \r\n"
"              [*]Bit 13: CPU6 Core1   \r\n"
"              [*]Bit 12: CPU6 Core0   \r\n"
"              [*]Bit 11: CPU5 Core1   \r\n"
"              [*]Bit 10: CPU5 Core0   \r\n"
"              [*]Bit 9:  CPU4 Core1   \r\n"
"              [*]Bit 8:  CPU4 Core0   \r\n"
"              [*]Bit 7:  CPU3 Core1   \r\n"
"              [*]Bit 6:  CPU3 Core0   \r\n"
"              [*]Bit 5:  CPU2 Core1   \r\n"
"              [*]Bit 4:  CPU2 Core0   \r\n"
"              [*]Bit 3:  CPU1 Core1   \r\n"
"              [*]Bit 2:  CPU1 Core0   \r\n"
"              [*]Bit 1:  CPU0 Core1   \r\n"
"              [*]Bit 0:  CPU0 Core0\r\n"
"              [/list]"},
#else
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1205[] = {{"B_CR_LITES1_AGENT_MATCH_0_0_0_MCHBAR", "", 0x00006CC8, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1206[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "intdata_mask", "This mask is for generating Lites Group 1 U2C request alternative view match.  Only bits [7:0] of this field are used; bits [15:8] are ignored.  If a mask bit in this register is 0, then the corresponding bit in the INTDATA_MATCH field is ignored. If the mask bit is 1, then the corresponding bit in the INTDATA_MATCH[7:0] field must match its corresponding u2c request IntData[15:8] bit for a match."},
#else
{16, 31, 0x0000000000000000, "RW", "intdata_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "intdata_match", "U2C Request IntData[15:8] value is compared with bits [7:0] of this field to generate a match for the U2C request address match.  Bits [15:8] of this field are ignored.  Note that matching based on the IntData[7:0] bits is not supported."},
#else
{0, 15, 0x0000000000000000, "RW", "intdata_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1206[] = {{"B_CR_LITES1_U2CINTDATA_MATCH_0_0_0_MCHBAR", "", 0x00006CCC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1207[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_match", "Address value to match for Lites"},
#else
{3, 38, 0x0000000000000000, "RW", "address_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1207[] = {{"B_CR_LITES1_ADDR_MATCH_0_0_0_MCHBAR", "", 0x00006CD0, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1208[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_mask", "Address mask value used for comparing request address during filter operation for Lites. If the mask bit in this register is 0, then the corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the ADDR_MATCH register must match the corresponding request address bit for a match."},
#else
{3, 38, 0x0000000000000000, "RW", "address_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1208[] = {{"B_CR_LITES1_ADDR_MASK_0_0_0_MCHBAR", "", 0x00006CD8, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1209[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_match", "Data value to match for Lites."},
#else
{0, 31, 0x0000000000000000, "RW", "data_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1209[] = {{"B_CR_LITES1_DATA_MATCH_0_0_0_MCHBAR", "", 0x00006CE0, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1210[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_mask", "Data mask value used for comparing data during filter operations for Lites. If the mask bit in this register is 0, then the corresponding bit in the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the DATA_MATCH register must match the corresponding bit of the request data for a match."},
#else
{0, 31, 0x0000000000000000, "RW", "data_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1210[] = {{"B_CR_LITES1_DATA_MASK_0_0_0_MCHBAR", "", 0x00006CE4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1211[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RW", "idi_length_match", "Enables length matching for IDI requests for Lites Group 2. Each bit, when set to 1, enables match for that length for an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only 64B for all other opcodes. \r\n"
"	  [list]\r\n"
"	    [*]Bit 31:64B                  \r\n"
"	    [*]Bit 30:16B                  \r\n"
"	    [*]Bit 29:15B                  \r\n"
"	    [*]Bit 28:14B                  \r\n"
"	    [*]Bit 27:13B                  \r\n"
"	    [*]Bit 26:12B                  \r\n"
"	    [*]Bit 25:11B                  \r\n"
"	    [*]Bit 24:10B                  \r\n"
"	    [*]Bit 23:9B                  \r\n"
"	    [*]Bit 22:8B                  \r\n"
"	    [*]Bit 21:7B                  \r\n"
"	    [*]Bit 20:6B                  \r\n"
"	    [*]Bit 19:5B                  \r\n"
"	    [*]Bit 18:4B                  \r\n"
"	    [*]Bit 17:3B                  \r\n"
"	    [*]Bit 16:2B                  \r\n"
"	    [*]Bit 15:1B                  \r\n"
"	    [*]Bit 14:0B\r\n"
"	  [/list]"},
#else
{14, 31, 0x0000000000000000, "RW", "idi_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "pii_length_match", "Enables length matching for PII requests for Lites Group 2. Each bit, when set to 1, enables  length match for the PII request.\r\n"
"        [list]\r\n"
"        [*]Bit 13:64B                  \r\n"
"        [*]Bit 12:32B\r\n"
"        [/list]"},
#else
{12, 13, 0x0000000000000000, "RW", "pii_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{10, 11, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "slice_match", "[list]\r\n"
"              [*]00: All mask/match hits are suppressed \r\n"
"              [*]01: Mask/Match hits enabled only for Slice0 \r\n"
"              [*]10: Mask/match hits enabled only for Slice1 \r\n"
"              [*]11: Mask/Match hits enabled for both Slices\r\n"
"              [/list]"},
#else
{8, 9, 0x0000000000000000, "RW", "slice_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "dword_select", "Selects the dword within the 512bit data field that is compared for data mask/matches for Lites Group 2."},
#else
{4, 7, 0x0000000000000000, "RW", "dword_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "enable_data_match", "When set, this field enables data matching on Lites Group 2."},
#else
{3, 3, 0x0000000000000000, "RW", "enable_data_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "altu2creqview", "When set, address match/mask opcode match and agent match registers are used to generate matches for the U2C request observation point. When clear, Badmit observation point matches are reported on the U2C request observation point."},
#else
{2, 2, 0x0000000000000000, "RW", "altu2creqview", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", "When set, inverts the polarity of the address match/mask logic, i.e., reports a match for addresses that are not in the specified range."},
#else
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_group", "Enables all match filters for Lites Group 2. The following are the observation points that contain match filters: Badmit logic within each slice after a transaction is successfully admitted into the B-Unit, U2C request launch PMI datain for each PMI channel read data, PMI dataout for each PMI channel write data, agent data write to BRAM in each slice, read data return on the live bypass and nonlive bypass paths in each slice. To report a match at an observation point all match criteria for that point must be satisfied."},
#else
{0, 0, 0x0000000000000000, "RW", "enable_group", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1211[] = {{"B_CR_LITES2_CTL_0_0_0_MCHBAR", "", 0x00006CF0, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1212[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "opcode_match", "Bit vector that enables a match on the opcode for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation points -- Badmit in both slices, and the U2C request interface -- use this same opcode match register. Each bit, when set, enables a match on the corresponding opcode and when clear will suppress a match on the corresponding opcode. To match on any opcode, set all bits to 1.  \r\n"
"              [list]\r\n"
"              [*]Bit 31: C2U_Req_CRd  \r\n"
"              [*]Bit 30: C2U_Req_DRd  \r\n"
"              [*]Bit 29: C2U_Req_DRdPTE  \r\n"
"              [*]Bit 28: C2U_Req_SetMonitor  \r\n"
"              [*]Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet  \r\n"
"              [*]Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet  \r\n"
"              [*]Bit 25: C2U_Req_UcRdF  \r\n"
"              [*]Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode  \r\n"
"              [*]Bit 23: C2U_Req_IntA,U2C_Req_SnpData  \r\n"
"              [*]Bit 22: C2U_Req_Lock  \r\n"
"              [*]Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet  \r\n"
"              [*]Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet  \r\n"
"              [*]Bit 19: C2U_Req_ItoM  \r\n"
"              [*]Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv  \r\n"
"              [*]Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq  \r\n"
"              [*]Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq  \r\n"
"              [*]Bit 15: C2U_Req_CLFlush  \r\n"
"              [*]Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI  \r\n"
"              [*]Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI  \r\n"
"              [*]Bit 12: C2U_Req_WiL  \r\n"
"              [*]Bit 11: C2U_Req_WCiL  \r\n"
"              [*]Bit 10: C2U_Req_WCilF  \r\n"
"              [*]Bit 9:  C2U_Req_PortOut  \r\n"
"              [*]Bit 8:  C2U_Req_IntPriUp,U2C_Req_LTWrite  \r\n"
"              [*]Bit 7:  C2U_Req_IntLog  \r\n"
"              [*]Bit 6:  C2U_Req_IntPhy  \r\n"
"              [*]Bit 5:  C2U_Req_EOI,U2C_Req_VLW  \r\n"
"              [*]Bit 4:  C2U_Req_ItoMWr  \r\n"
"              [*]Bit 3:  A2B_Req_SnoopedRead  \r\n"
"              [*]Bit 2:  A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI  \r\n"
"              [*]Bit 1:  A2B_Req_SnoopedWrite  \r\n"
"              [*]Bit 0:  A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI\r\n"
"              [*][/list]"},
#else
{0, 31, 0x0000000000000000, "RW", "opcode_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1212[] = {{"B_CR_LITES2_OPCODE_MATCH_0_0_0_MCHBAR", "", 0x00006CF4, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1213[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_match", "This field is used to match IDI ransactions from GT for Lites Group2. When set, enables a match for a transaction originating from GT. When clear, suppresses a match for a transaction from GT."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 30, 0x0000000000000000, "RW", "vc_match", "This field is used to match VC Channel ID, for PII transactions for Lites Group2. Each bit, when set, enables a match for a transaction originating from that VC. When clear, suppresses a match for a transaction from that VC. \r\n"
"             [list]\r\n"
"             [*]Bit 30: VC14   \r\n"
"             [*]Bit 29: VC13   \r\n"
"             [*]Bit 28: VC12   \r\n"
"             [*]Bit 27: VC11   \r\n"
"             [*]Bit 26: VC10   \r\n"
"             [*]Bit 25: VC9   \r\n"
"             [*]Bit 24: VC8   \r\n"
"             [*]Bit 23: VC7   \r\n"
"             [*]Bit 22: VC6   \r\n"
"             [*]Bit 21: VC5   \r\n"
"             [*]Bit 20: VC4   \r\n"
"             [*]Bit 19: VC3   \r\n"
"             [*]Bit 18: VC2   \r\n"
"             [*]Bit 17: VC1   \r\n"
"             [*]Bit 16: VC0\r\n"
"             [/list]"},
#else
{16, 30, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", "This field is used to match Logical Processor Core ID for CPU IDI transactions for Lites Group 2. Each bit, when set, enables a match for a transaction originating from that core. When clear, suppresses a match for a transaction from that core. \r\n"
"              [list]\r\n"
"              [*]Bit 15: CPU7 Core1   \r\n"
"              [*]Bit 14: CPU7 Core0   \r\n"
"              [*]Bit 13: CPU6 Core1   \r\n"
"              [*]Bit 12: CPU6 Core0   \r\n"
"              [*]Bit 11: CPU5 Core1   \r\n"
"              [*]Bit 10: CPU5 Core0   \r\n"
"              [*]Bit 9:  CPU4 Core1   \r\n"
"              [*]Bit 8:  CPU4 Core0   \r\n"
"              [*]Bit 7:  CPU3 Core1   \r\n"
"              [*]Bit 6:  CPU3 Core0   \r\n"
"              [*]Bit 5:  CPU2 Core1   \r\n"
"              [*]Bit 4:  CPU2 Core0   \r\n"
"              [*]Bit 3:  CPU1 Core1   \r\n"
"              [*]Bit 2:  CPU1 Core0  \r\n"
"              [*]Bit 1:  CPU0 Core1   \r\n"
"              [*]Bit 0:  CPU0 Core0\r\n"
"              [/list]"},
#else
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1213[] = {{"B_CR_LITES2_AGENT_MATCH_0_0_0_MCHBAR", "", 0x00006CF8, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1214[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "intdata_mask", "This mask is for generating Lites Group 2 U2C request alternative view match.  Only bits [7:0] of this field are used; bits [15:8] are ignored.  If a mask bit in this register is 0, then the corresponding bit in the INTDATA_MATCH field is ignored. If the mask bit is 1, then the corresponding bit in the INTDATA_MATCH[7:0] field must match its corresponding u2c request IntData[15:8] bit for a match."},
#else
{16, 31, 0x0000000000000000, "RW", "intdata_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "intdata_match", "U2C Request IntData[15:8] value is compared with bits [7:0] of this field to generate a match for the U2C request address match.  Bits [15:8] of this field are ignored.  Note that matching based on the IntData[7:0] bits is not supported."},
#else
{0, 15, 0x0000000000000000, "RW", "intdata_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1214[] = {{"B_CR_LITES2_U2CINTDATA_MATCH_0_0_0_MCHBAR", "", 0x00006CFC, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1215[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_match", "Address value to match for Lites."},
#else
{3, 38, 0x0000000000000000, "RW", "address_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1215[] = {{"B_CR_LITES2_ADDR_MATCH_0_0_0_MCHBAR", "", 0x00006D00, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1216[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_mask", "Address mask value used for comparing request address during filter operation for Lites. If the mask bit in this register is 0, then the corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the ADDR_MATCH register must match the corresponding request address bit for a match."},
#else
{3, 38, 0x0000000000000000, "RW", "address_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1216[] = {{"B_CR_LITES2_ADDR_MASK_0_0_0_MCHBAR", "", 0x00006D08, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1217[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_match", "Data value to match for Lites"},
#else
{0, 31, 0x0000000000000000, "RW", "data_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1217[] = {{"B_CR_LITES2_DATA_MATCH_0_0_0_MCHBAR", "", 0x00006D10, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1218[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_mask", "Data mask value used for comparing data during filter operations for Lites. If the mask bit in this register is 0, then the corresponding bit in the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the DATA_MATCH register must match the corresponding bit of the request data for a match."},
#else
{0, 31, 0x0000000000000000, "RW", "data_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1218[] = {{"B_CR_LITES2_DATA_MASK_0_0_0_MCHBAR", "", 0x00006D14, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1219[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{14, 31, 0x0000000000000000, "RW", "idi_length_match", "Enables length matching for IDI requests for Lites Group 3. Each bit, when set to 1, enables match for that length for an IDI request. Lites logic supports only lengths 0-16B for PRd and PortIn and only 64B for all other opcodes. \r\n"
"	  [list]\r\n"
"	    [*]Bit 31:64B                  \r\n"
"	    [*]Bit 30:16B                  \r\n"
"	    [*]Bit 29:15B                  \r\n"
"	    [*]Bit 28:14B                  \r\n"
"	    [*]Bit 27:13B                  \r\n"
"	    [*]Bit 26:12B                  \r\n"
"	    [*]Bit 25:11B                  \r\n"
"	    [*]Bit 24:10B                  \r\n"
"	    [*]Bit 23:9B                  \r\n"
"	    [*]Bit 22:8B                  \r\n"
"	    [*]Bit 21:7B                  \r\n"
"	    [*]Bit 20:6B                  \r\n"
"	    [*]Bit 19:5B                  \r\n"
"	    [*]Bit 18:4B                  \r\n"
"	    [*]Bit 17:3B                  \r\n"
"	    [*]Bit 16:2B                  \r\n"
"	    [*]Bit 15:1B                  \r\n"
"	    [*]Bit 14:0B\r\n"
"	  [/list]"},
#else
{14, 31, 0x0000000000000000, "RW", "idi_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{12, 13, 0x0000000000000000, "RW", "pii_length_match", "Enables length matching for PII requests for Lites Group 3. Each bit, when set to 1, enables length match for the PII request:\r\n"
"        [list]\r\n"
"        [*] Bit 13:64B\r\n"
"        [*] Bit 12:32B\r\n"
"        [/list]"},
#else
{12, 13, 0x0000000000000000, "RW", "pii_length_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{10, 11, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{10, 11, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 9, 0x0000000000000000, "RW", "slice_match", "[list]\r\n"
"              [*]00: All mask/match hits are suppressed \r\n"
"              [*]01: mask/match hits enabled only for Slice0 \r\n"
"              [*]10: mask/match hits enabled only for Slice1 \r\n"
"              [*]11: mask/match hits enabled for both Slices\r\n"
"              [/list]"},
#else
{8, 9, 0x0000000000000000, "RW", "slice_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 7, 0x0000000000000000, "RW", "dword_select", "Selects the dword within the 512bit data field that is compared for data mask/matches for Lites Group 3."},
#else
{4, 7, 0x0000000000000000, "RW", "dword_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RW", "enable_data_match", "When set, this field enables data matching on Lites Group 3."},
#else
{3, 3, 0x0000000000000000, "RW", "enable_data_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000000, "RW", "altu2creqview", "When set, address match/mask, opcode match and agent match registers are used to generate matches for the U2C request observation point. When clear, Badmit observation point matches are reported on the U2C request observation point."},
#else
{2, 2, 0x0000000000000000, "RW", "altu2creqview", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", "When set inverts the polarity of the address match/mask logic i.e. reports a match for addresses that are not in the specified range."},
#else
{1, 1, 0x0000000000000000, "RW", "invert_addr_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "enable_group", "Enables all match filters for Lites Group 3. The following are the observation points that contain match filters  Badmit logic within each slice after a transaction is successfully admitted into the B-Unit U2C request launch PMI datain for each PMI channel read data PMI dataout for each PMI channel write data agent data write to BRAM in each slice read data return on the live bypass and nonlive bypass paths in each slice.  To report a match at an observation point all match criteria for that point must be satisfied."},
#else
{0, 0, 0x0000000000000000, "RW", "enable_group", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1219[] = {{"B_CR_LITES3_CTL_0_0_0_MCHBAR", "", 0x00006D20, 9, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1220[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "opcode_match", "Bit vector that enables a match on the opcode for C2U IDI requests, PII A2B requests, and U2C IDI requests. All three observation points -- Badmit in both slices, and the U2C request interface -- use this same opcode match register. Each bit, when set, enables a match on the corresponding opcode, and when clear will suppress a match on the corresponding opcode. To match on any opcode, set all bits to 1.  \r\n"
"              [list]\r\n"
"              [*]Bit 31: C2U_Req_CRd  \r\n"
"              [*]Bit 30: C2U_Req_DRd  \r\n"
"              [*]Bit 29: C2U_Req_DRdPTE  \r\n"
"              [*]Bit 28: C2U_Req_SetMonitor  \r\n"
"              [*]Bit 27: C2U_Req_RFO,U2C_Req_LTWrite_piclet  \r\n"
"              [*]Bit 26: C2U_Req_PRd,U2C_Req_VLW_piclet  \r\n"
"              [*]Bit 25: C2U_Req_UcRdF  \r\n"
"              [*]Bit 24: C2U_Req_PortIn,U2C_Req_SnpCode  \r\n"
"              [*]Bit 23: C2U_Req_IntA,U2C_Req_SnpData  \r\n"
"              [*]Bit 22: C2U_Req_Lock  \r\n"
"              [*]Bit 21: C2U_Req_SplitLock,U2C_Req_IntLog_piclet  \r\n"
"              [*]Bit 20: C2U_Req_Unlock,U2C_Req_IntPhy_piclet  \r\n"
"              [*]Bit 19: C2U_Req_ItoM  \r\n"
"              [*]Bit 18: C2U_Req_SpCyc,U2C_Req_SnpInv  \r\n"
"              [*]Bit 17: C2U_Req_RdMonitor,U2C_Req_StopReq  \r\n"
"              [*]Bit 16: C2U_Req_ClrMonitor,U2C_Req_StartReq  \r\n"
"              [*]Bit 15: C2U_Req_CLFlush  \r\n"
"              [*]Bit 14: C2U_Req_WbMtoI,U2C_Req_IntLog_MSI  \r\n"
"              [*]Bit 13: C2U_Req_WbMtoE,U2C_Req_IntPhy_MSI  \r\n"
"              [*]Bit 12: C2U_Req_WiL  \r\n"
"              [*]Bit 11: C2U_Req_WCiL  \r\n"
"              [*]Bit 10: C2U_Req_WCilF  \r\n"
"              [*]Bit 9:  C2U_Req_PortOut  \r\n"
"              [*]Bit 8:  C2U_Req_IntPriUp,U2C_Req_LTWrite  \r\n"
"              [*]Bit 7:  C2U_Req_IntLog  \r\n"
"              [*]Bit 6:  C2U_Req_IntPhy  \r\n"
"              [*]Bit 5:  C2U_Req_EOI,U2C_Req_VLW  \r\n"
"              [*]Bit 4:  C2U_Req_ItoMWr  \r\n"
"              [*]Bit 3:  A2B_Req_SnoopedRead  \r\n"
"              [*]Bit 2:  A2B_Req_UnSnoopedRead,U2C_Req_IntPhy_IPI  \r\n"
"              [*]Bit 1:  A2B_Req_SnoopedWrite  \r\n"
"              [*]Bit 0:  A2B_Req_UnSnoopedWrite,U2C_Req_IntLog_IPI\r\n"
"              [/list]"},
#else
{0, 31, 0x0000000000000000, "RW", "opcode_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1220[] = {{"B_CR_LITES3_OPCODE_MATCH_0_0_0_MCHBAR", "", 0x00006D24, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1221[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "gt_match", "This field is used to match IDI ransactions from GT for Lites Group3. When set, enables a match for a transaction originating from GT. When clear, suppresses a match for a transaction from GT."},
#else
{31, 31, 0x0000000000000000, "RW", "gt_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 30, 0x0000000000000000, "RW", "vc_match", "This field is used to match VC Channel ID for PII transactions, for Lites Group3. Each bit, when set, enables a match for a transaction originating from that VC. When clear, the bit suppresses a match for a transaction from that VC.   \r\n"
"             [list]\r\n"
"             [*]Bit 30: VC14   \r\n"
"             [*]Bit 29: VC13   \r\n"
"             [*]Bit 28: VC12   \r\n"
"             [*]Bit 27: VC11   \r\n"
"             [*]Bit 26: VC10   \r\n"
"             [*]Bit 25: VC9   \r\n"
"             [*]Bit 24: VC8   \r\n"
"             [*]Bit 23: VC7   \r\n"
"             [*]Bit 22: VC6   \r\n"
"             [*]Bit 21: VC5   \r\n"
"             [*]Bit 20: VC4   \r\n"
"             [*]Bit 19: VC3   \r\n"
"             [*]Bit 18: VC2   \r\n"
"             [*]Bit 17: VC1   \r\n"
"             [*]Bit 16: VC0\r\n"
"             [/list]"},
#else
{16, 30, 0x0000000000000000, "RW", "vc_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", "This field is used to match Logical Processor Core ID for CPU IDI transactions, for Lites Group 3. Each bit, when set, enables a match for a transaction originating from that core. When clear, the bit suppresses a match for a transaction from that core. \r\n"
"              [list]\r\n"
"              [*]Bit 15: CPU7 Core1   \r\n"
"              [*]Bit 14: CPU7 Core0   \r\n"
"              [*]Bit 13: CPU6 Core1   \r\n"
"              [*]Bit 12: CPU6 Core0   \r\n"
"              [*]Bit 11: CPU5 Core1   \r\n"
"              [*]Bit 10: CPU5 Core0   \r\n"
"              [*]Bit 9:  CPU4 Core1   \r\n"
"              [*]Bit 8:  CPU4 Core0   \r\n"
"              [*]Bit 7:  CPU3 Core1   \r\n"
"              [*]Bit 6:  CPU3 Core0   \r\n"
"              [*]Bit 5:  CPU2 Core1   \r\n"
"              [*]Bit 4:  CPU2 Core0   \r\n"
"              [*]Bit 3:  CPU1 Core1   \r\n"
"              [*]Bit 2:  CPU1 Core0   \r\n"
"              [*]Bit 1:  CPU0 Core1   \r\n"
"              [*]Bit 0:  CPU0 Core0\r\n"
"              [/list]"},
#else
{0, 15, 0x0000000000000000, "RW", "cpu_core_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1221[] = {{"B_CR_LITES3_AGENT_MATCH_0_0_0_MCHBAR", "", 0x00006D28, 3, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1222[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 31, 0x0000000000000000, "RW", "intdata_mask", "This mask is for generating Lites Group 3 U2C request alternative view match.  Only bits [7:0] of this field are used; bits [15:8] are ignored.  If a mask bit in this register is 0, then the corresponding bit in the INTDATA_MATCH field is ignored. If the mask bit is 1, then the corresponding bit in the INTDATA_MATCH[7:0] field must match its corresponding u2c request IntData[15:8] bit for a match."},
#else
{16, 31, 0x0000000000000000, "RW", "intdata_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 15, 0x0000000000000000, "RW", "intdata_match", "U2C Request IntData[15:8] value is compared with bits [7:0] of this field to generate a match for the U2C request address match.  Bits [15:8] of this field are ignored.  Note that matching based on the IntData[7:0] bits is not supported."},
#else
{0, 15, 0x0000000000000000, "RW", "intdata_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1222[] = {{"B_CR_LITES3_U2CINTDATA_MATCH_0_0_0_MCHBAR", "", 0x00006D2C, 2, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1223[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_match", "Address value to match for Lites."},
#else
{3, 38, 0x0000000000000000, "RW", "address_match", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1223[] = {{"B_CR_LITES3_ADDR_MATCH_0_0_0_MCHBAR", "", 0x00006D30, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1224[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{39, 63, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{39, 63, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 38, 0x0000000000000000, "RW", "address_mask", "Address mask value used for comparing request address during filter operation for Lites. If the mask bit in this register is 0, then the corresponding bit in the ADDR_MATCH register is ignored. If the mask bit is 1,  then the corresponding bit in the ADDR_MATCH register must match the corresponding request address bit for a match."},
#else
{3, 38, 0x0000000000000000, "RW", "address_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 2, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 2, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1224[] = {{"B_CR_LITES3_ADDR_MASK_0_0_0_MCHBAR", "", 0x00006D38, 3, 0xFFFFFFFFFFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1225[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_match", "Data value to match for Lites"},
#else
{0, 31, 0x0000000000000000, "RW", "data_match", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1225[] = {{"B_CR_LITES3_DATA_MATCH_0_0_0_MCHBAR", "", 0x00006D40, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1226[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RW", "data_mask", "Data mask value used for comparing data during filter operations for Lites. If the mask bit in this register is 0, then the corresponding bit in the DATA_MATCH register is ignored. If the mask bit is 1, then the corresponding bit in the DATA_MATCH register must match the corresponding bit of the request data for a match."},
#else
{0, 31, 0x0000000000000000, "RW", "data_mask", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1226[] = {{"B_CR_LITES3_DATA_MASK_0_0_0_MCHBAR", "", 0x00006D44, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1227[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enable_lites", "[list]\r\n"
"              [*]0: Lites logic is disabled. All Lites Views will be driven to 0s.  \r\n"
"              [*]1: Lites logic is enabled.\r\n"
"              [/list]"},
#else
{31, 31, 0x0000000000000000, "RW", "enable_lites", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{27, 30, 0x0000000000000000, "RW", "emon_barb_cq_select", "Select barb conflictQ FIFO. \r\n"
"              [list]\r\n"
"              [*]0000 to 0111: pii0 to pii7 \r\n"
"              [*]1xx0: idi slice0 \r\n"
"              [*]1xx1: idi slice1\r\n"
"              [/list]"},
#else
{27, 30, 0x0000000000000000, "RW", "emon_barb_cq_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 26, 0x0000000000000000, "RW", "emon_barb_ingress_select", "Select barb ingress FIFO. \r\n"
"             [list]\r\n"
"             [*]000: IDI attach point -0 -mono | per slice fifo0\r\n"
"             [*]001: IDI attach point -0 -slice fifo1\r\n"
"             [*]010: IDI attach point -1 -mono | per slice fifo1\r\n"
"             [*]011: IDI attach point -1 - slice fifo\r\n"
"             [*]100: IDI attach point -2 -mono | GT slice0(bxt)\r\n"
"             [*]101: IDI attach point -2 - slice fifo | GT slice1(bxt)\r\n"
"             [*]110: IDI attach point -3 -mono | per slice fifo0\r\n"
"             [*]111: IDI attach point -3 - slice fifo1\r\n"
"             [/list]"},
#else
{24, 26, 0x0000000000000000, "RW", "emon_barb_ingress_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{13, 23, 0x0000000000000000, "RW", "emon_vc_mask", "B-Unit and T-Unit expose only the Emons corresponding to the VC(s) specified in this field (it is a mask)."},
#else
{13, 23, 0x0000000000000000, "RW", "emon_vc_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 12, 0x0000000000000000, "RW", "emon_idi_mask", "B-Unit and T-Unit expose only the Emons corresponding to the IDI agent(s) specified in this field (it is a mask). IDI agent refers to GLM modules and GT not Sunits."},
#else
{5, 12, 0x0000000000000000, "RW", "emon_idi_mask", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 4, 0x0000000000000000, "RW", "lites_idi_select", "B-Unit and T-Unit expose only the views corresponding to the IDI agent specified in this field. IDI agents only refer to GT and GLM modules, not Sunits. Used only on the C2U response views."},
#else
{2, 4, 0x0000000000000000, "RW", "lites_idi_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "lites_slice_select", "When set to 0, B-Unit and T-Unit expose only Slice0 views. No Lites observability of any transaction routed to Slice 1. When set to 1, B-Unit and T-Unit expose only Slice1 views.  No Lites observability of any transaction routed to Slice0."},
#else
{1, 1, 0x0000000000000000, "RW", "lites_slice_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "lites_pmi_select", "When set to 0, B-Unit exposes only PMI channel 0 views in either slice. No Lites observability of any transaction routed to PMI channel 1 in either slice. When set to 1, B-Unit exposes only PMI Channel 1 views in either slice."},
#else
{0, 0, 0x0000000000000000, "RW", "lites_pmi_select", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1227[] = {{"B_CR_LITESEMON_CTL_0_0_0_MCHBAR", "", 0x00006D48, 8, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1228[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000004, "RW", "agent3_weight", "Arbiter weight for Agent 3."},
#else
{24, 29, 0x0000000000000004, "RW", "agent3_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{22, 23, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "agent2_weight", "Arbiter weight for Agent 2."},
#else
{16, 21, 0x0000000000000004, "RW", "agent2_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "agent1_weight", "Arbiter weight for Agent 1."},
#else
{8, 13, 0x0000000000000004, "RW", "agent1_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_3", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "agent0_weight", "Arbiter weight for Agent 0."},
#else
{0, 5, 0x0000000000000004, "RW", "agent0_weight", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1228[] = {{"B_CR_BARBCTRL0", "", 0x00006D4C, 8, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1229[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000004, "RW", "agent7_weight", "Arbiter weight for Agent 7."},
#else
{24, 29, 0x0000000000000004, "RW", "agent7_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{22, 23, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "agent6_weight", "Arbiter weight for Agent 6."},
#else
{16, 21, 0x0000000000000004, "RW", "agent6_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "agent5_weight", "Arbiter weight for Agent 5."},
#else
{8, 13, 0x0000000000000004, "RW", "agent5_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_3", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "agent4_weight", "Arbiter weight for Agent 4."},
#else
{0, 5, 0x0000000000000004, "RW", "agent4_weight", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1229[] = {{"B_CR_BARBCTRL1", "", 0x00006D50, 8, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1230[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000004, "RW", "agent3_weight", "Arbiter weight for Agent 3."},
#else
{24, 29, 0x0000000000000004, "RW", "agent3_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{22, 23, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "agent2_weight", "Arbiter weight for Agent 2."},
#else
{16, 21, 0x0000000000000004, "RW", "agent2_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "agent1_weight", "Arbiter weight for Agent 1."},
#else
{8, 13, 0x0000000000000004, "RW", "agent1_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_3", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "agent0_weight", "Arbiter weight for Agent 0."},
#else
{0, 5, 0x0000000000000004, "RW", "agent0_weight", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1230[] = {{"B_CR_BSCHWT0", "", 0x00006D54, 8, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1231[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000004, "RW", "agent7_weight", "Arbiter weight for Agent 7."},
#else
{24, 29, 0x0000000000000004, "RW", "agent7_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{22, 23, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "agent6_weight", "Arbiter weight for Agent 6."},
#else
{16, 21, 0x0000000000000004, "RW", "agent6_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "agent5_weight", "Arbiter weight for Agent 5."},
#else
{8, 13, 0x0000000000000004, "RW", "agent5_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_3", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "agent4_weight", "Arbiter weight for Agent 4."},
#else
{0, 5, 0x0000000000000004, "RW", "agent4_weight", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1231[] = {{"B_CR_BSCHWT1", "", 0x00006D58, 8, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1232[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000004, "RW", "agent11_weight", "Arbiter weight for Agent 11."},
#else
{24, 29, 0x0000000000000004, "RW", "agent11_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{22, 23, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "agent10_weight", "Arbiter weight for Agent 10."},
#else
{16, 21, 0x0000000000000004, "RW", "agent10_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "agent9_weight", "Arbiter weight for Agent 9."},
#else
{8, 13, 0x0000000000000004, "RW", "agent9_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_3", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "agent8_weight", "Arbiter weight for Agent 8."},
#else
{0, 5, 0x0000000000000004, "RW", "agent8_weight", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1232[] = {{"B_CR_BSCHWT2", "", 0x00006D5C, 8, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1233[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{30, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{30, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 29, 0x0000000000000004, "RW", "agent15_weight", "Arbiter weight for Agent 15."},
#else
{24, 29, 0x0000000000000004, "RW", "agent15_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{22, 23, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{22, 23, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 21, 0x0000000000000004, "RW", "agent14_weight", "Arbiter weight for Agent 14."},
#else
{16, 21, 0x0000000000000004, "RW", "agent14_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 15, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{14, 15, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "agent13_weight", "Arbiter weight for Agent 13."},
#else
{8, 13, 0x0000000000000004, "RW", "agent13_weight", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_3", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_3", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "agent12_weight", "Arbiter weight for Agent 12."},
#else
{0, 5, 0x0000000000000004, "RW", "agent12_weight", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1233[] = {{"B_CR_BSCHWT3", "", 0x00006D60, 8, 0x00000000FFFFFFFF, 0x0000000004040404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1234[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{24, 31, 0x00000000000000FF, "RW", "flush_threshold", "All write commands are blocked at Badmit if the number of write commands in the Flush Pool exceeeds this value."},
#else
{24, 31, 0x00000000000000FF, "RW", "flush_threshold", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 23, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{17, 23, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 16, 0x0000000000000001, "RO/V", "all_entries_flushed", "All dirty entries in the B-Unit, in both slices, have been flushed."},
#else
{16, 16, 0x0000000000000001, "RO/V", "all_entries_flushed", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "dirty_lwm", "Low water mark for dirty entries retained by the B-Unit. B-Unit will immediately attempt to flush any dirty entry, hence setting the low water mark to 0."},
#else
{8, 15, 0x0000000000000000, "RW", "dirty_lwm", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000000, "RW", "dirty_hwm", "High water mark for dirty entries retained by the B-Unit. B-Unit will immediately attempt to flush any dirty entry, hence setting the low water mark to 0."},
#else
{0, 7, 0x0000000000000000, "RW", "dirty_hwm", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1234[] = {{"B_CR_BWFLUSH", "", 0x00006D64, 5, 0x00000000FFFFFFFF, 0x00000000FF010000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1235[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "disable_flush_weights", "When set to 1, disables flush weights. Flushing of dirty entries will start when Dirty Limit is HWM, and continue until Dirty Limit is LWM. No reads will be scheduled in between."},
#else
{31, 31, 0x0000000000000000, "RW", "disable_flush_weights", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 30, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{14, 30, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x0000000000000004, "RW", "write_weights", "Number of write requests sent to a PMI channel before switching to scheduling read requests, when use of flush weights is not disabled."},
#else
{8, 13, 0x0000000000000004, "RW", "write_weights", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x0000000000000004, "RW", "read_weights", "Number of read requests sent to a PMI channel before switching to scheduling write requests, when use of flush weights is not disabled."},
#else
{0, 5, 0x0000000000000004, "RW", "read_weights", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1235[] = {{"B_CR_BFLWT", "", 0x00006D68, 5, 0x00000000FFFFFFFF, 0x0000000000000404}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1236[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000001, "RW", "enable_isoc_weights", "When set to 1, enables switching from scheduling High Priority ISOC requests to scheduling Best Effort and Low Priority ISOC requests, based on ISOC weights and NONISOC weights."},
#else
{31, 31, 0x0000000000000001, "RW", "enable_isoc_weights", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{14, 30, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{14, 30, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 13, 0x000000000000003F, "RW", "isoc_request_weights", "Weight for high priority isochronous requests."},
#else
{8, 13, 0x000000000000003F, "RW", "isoc_request_weights", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 5, 0x000000000000000F, "RW", "non_isoc_request_weights", "Weight for non-high priority isochronous and best effort requests."},
#else
{0, 5, 0x000000000000000F, "RW", "non_isoc_request_weights", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1236[] = {{"B_CR_BISOCWT", "", 0x00006D6C, 5, 0x00000000FFFFFFFF, 0x0000000080003F0F}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1237[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "enable_read_invalidate_timer", "When set to 1, enables the BRAM to clear the RD_DONE bit and flush dirty data when a timer expires. Used when parity is not enabled, to force the B-Unit to not indefinitely cache previously read lines, and also to cause a flush of dirty data that has been written to the BRAM entry."},
#else
{31, 31, 0x0000000000000000, "RW", "enable_read_invalidate_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{26, 30, 0x0000000000000000, "RO", "reserved_2", "Reserved."},
#else
{26, 30, 0x0000000000000000, "RO", "reserved_2", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{25, 25, 0x0000000000000000, "RW", "dram_ecc_enable", "If DRAM ECC is enabled, the data error bits from the Dunit is used for indicating the derror for the corresponding transactions to the agents and forcing the poison bit when BUNIT PARITY is unsupported and Read for partial writes are enabled"},
#else
{25, 25, 0x0000000000000000, "RW", "dram_ecc_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{24, 24, 0x0000000000000000, "RW", "mot_disable_stall_arb_on_err", "If the HH widget gets an error, allow transactions to get arbitrated."},
#else
{24, 24, 0x0000000000000000, "RW", "mot_disable_stall_arb_on_err", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{16, 23, 0x000000000000000F, "RW", "bram_read_invalidate_time", "Timer threshold to clear rd_done bits or flush a BRAM entry, if dirty. The value specified is in multiples of 250ns. For each time interval specified, the read done status of one BRAM entry will be cleared based on a BTAG index which is then incremented to point to the next BRAM entry."},
#else
{16, 23, 0x000000000000000F, "RW", "bram_read_invalidate_time", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{8, 15, 0x0000000000000000, "RW", "casual_timer", "The number of clock cycles that the B-Unit waits before starting a casual dirty flush. Casual Flush feature will not be enabled by PND2 architecture. Instead, a dirty write will be made eligible for scheduling immediately."},
#else
{8, 15, 0x0000000000000000, "RW", "casual_timer", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{6, 7, 0x0000000000000000, "RO", "reserved_1", "Reserved."},
#else
{6, 7, 0x0000000000000000, "RO", "reserved_1", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{5, 5, 0x0000000000000001, "RW", "enable_64b_write", "When set, B-unit will send 64B PMI Write requests for transactions requiring write access to DRAM. Must always be set to one, otherwise functional errors may occur. "},
#else
{5, 5, 0x0000000000000001, "RW", "enable_64b_write", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 4, 0x0000000000000001, "RW", "enable_64b_read", "When set, B-unit will send 64B PMI read requests for transactions requiring read access to DRAM. Must always be set to one, otherwise functional errors may occur. "},
#else
{4, 4, 0x0000000000000001, "RW", "enable_64b_read", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{3, 3, 0x0000000000000000, "RO", "demand_scrub_enable", "This mode causes B-Unit to automatically issue a flush to PMI, thus writing correct data back to memory for any read request that returns with a correctable data error."},
#else
{3, 3, 0x0000000000000000, "RO", "demand_scrub_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 2, 0x0000000000000001, "RW", "enable_read_done_for_write", "Enable Any writes (IWB or normal writes) to set the read_done bit in bstat, which enables return of data from the BRAM cache instead of Memory."},
#else
{2, 2, 0x0000000000000001, "RW", "enable_read_done_for_write", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{1, 1, 0x0000000000000000, "RW", "miss_valid_entries", "This mode causes reads to clean valid B-Unit buffer entries to look like misses instead of hits. When this bit is set -- even when all requested bytes are valid and present in the BRAM data buffer -- B-Unit will send read requests over the PMI interface to re-fetch the data from DRAM, instead of returning it from the BRAM."},
#else
{1, 1, 0x0000000000000000, "RW", "miss_valid_entries", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "dirty_stall", "This mode causes reads or writes from any requester interface to dirty valid B-Unit buffer entries to stall on the appropriate requester interface until the entry has been flushed from the B-Unit."},
#else
{0, 0, 0x0000000000000000, "RW", "dirty_stall", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1237[] = {{"B_CR_BCTRL2", "", 0x00006D70, 13, 0x00000000FFFFFFFF, 0x00000000000F0034}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1238[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{8, 8, 0x0000000000000001, "RW", "slice_anti_starve_disable", "When set, B-unit will always make an available request in each instantiated per-slice C2U Ingress FIFO for all IDI attach points eligible for arbitration in their respective odd/even sa2xclk clock.   When clear, B-unit will mask a C2U Ingress Slice's available request from arbitration when SLICE_ANTI_STARVE_THRESHOLD consecutive requests has been granted for that IDI attach point from the other Slice Ingress FIFO.   Has no effect for IDI attach points that do not have per-slice Ingress FIFOs"},
#else
{8, 8, 0x0000000000000001, "RW", "slice_anti_starve_disable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 7, 0x0000000000000040, "RW", "slice_anti_starve_threshold", "Specifies the threshold for the number of consecutive requests B-admit arbiter will grant from the same Slice ingress FIFO for an IDI attachpoint, while the other Slice also has a request available"},
#else
{0, 7, 0x0000000000000040, "RW", "slice_anti_starve_threshold", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1238[] = {{"B_CR_BCTRL3", "", 0x00006D7C, 2, 0x00000000000001FF, 0x0000000000000140}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1239[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{21, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{21, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{20, 20, 0x0000000000000001, "RW", "mot_rs0_en", "RS Asset Classification bit for the MOT buffer. PII transactions from RS0 that hit the MOT buffer will be allowed access only when both of the following conditions are met: a) Request SAI is in the legal permitted list, as specified in the RAC/WAC policy registers, and b) MOT_RS0_EN bit is set to 1. PII RS0 transactions targeting DRAM that do not hit any enabled IMR or special protected regions will always be allowed access."},
#else
{20, 20, 0x0000000000000001, "RW", "mot_rs0_en", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 19, 0x0000000000000000, "RW", "imr_rs0_en", "RS Asset Classification bit for IMRs 0-19. PII transactions from RS0 that hit an enabled IMR address range will be allowed access only when both of the following conditions are met: a) Request SAI is in the legal permitted list as specified in the IMRs RAC/WAC policy registers and b) IMR_AC_RS bit corresponding to the IMR is set to 1. PII RS0 transactions targeting DRAM that do not hit any enabled IMR or special protected regions will always be allowed access."},
#else
{0, 19, 0x0000000000000000, "RW", "imr_rs0_en", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1239[] = {{"B_CR_AC_RS0_0_0_0_MCHBAR", "", 0x00006D74, 3, 0x00000000FFFFFFFF, 0x0000000000100000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1240[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040001000202, "RW", "ia_ctrl_pol", "Bit vector used to determine which agents are allowed access to the P_U_CODEWR_ALLRD_RAC, P_U_CODEWR_ALLRD_WAC, and P_U_CODEWR_ALLRD_CP registers, based on the value from the agent's 6bit SAI field."},
#else
{0, 63, 0x0000040001000202, "RW", "ia_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1240[] = {{"B_CR_P_U_CODEWR_ALLRD_CP_0_0_0_MCHBAR", "", 0x00006C28, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040001000202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1241[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "ia_sai_pol", "Bit vector used to determine which agents are allowed read access to the B-Unit Pcode/Ucode Write, All Read policy registers, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0xFFFFFFFFFFFFFFFF, "RO", "ia_sai_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1241[] = {{"B_CR_P_U_CODEWR_ALLRD_RAC_0_0_0_MCHBAR", "", 0x00006C30, 1, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1242[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x0000040001000202, "RW", "ia_sai_pol", "Bit vector used to determine which agents are allowed write access to the B-Unit IA Core Configuration registers, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x0000040001000202, "RW", "ia_sai_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1242[] = {{"B_CR_P_U_CODEWR_ALLRD_WAC_0_0_0_MCHBAR", "", 0x00006C38, 1, 0xFFFFFFFFFFFFFFFF, 0x0000040001000202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1243[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C0061010202, "RW", "mem_range_ctrl_pol", "Bit vector used to determine which agents are allowed write access to the BIOSWR_RAC, BIOSWR_WAC, and BIOSWR_CP registers, based on the value from each agent's 6bit SAI field."},
#else
{0, 63, 0x00000C0061010202, "RW", "mem_range_ctrl_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1243[] = {{"B_CR_BIOSWR_CP_0_0_0_MCHBAR", "", 0x00006C08, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C0061010202}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1244[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x80000C00630D0217, "RW", "mem_range_pol", "Bit vector used to determine which agents are allowed read access, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x80000C00630D0217, "RW", "mem_range_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1244[] = {{"B_CR_BIOSWR_RAC_0_0_0_MCHBAR", "", 0x00006C10, 1, 0xFFFFFFFFFFFFFFFF, 0x80000C00630D0217}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1245[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 63, 0x00000C00610C0212, "RW", "mem_range_pol", "Bit vector used to determine which agents are allowed write access, based on each agent's 6bit encoded SAI value."},
#else
{0, 63, 0x00000C00610C0212, "RW", "mem_range_pol", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1245[] = {{"B_CR_BIOSWR_WAC_0_0_0_MCHBAR", "", 0x00006C18, 1, 0xFFFFFFFFFFFFFFFF, 0x00000C00610C0212}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1246[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{16, 17, 0x0000000000000000, "RW", "rt_idi_agent", "IDI Agent Real-Time Traffic Mask Bits. Controls which IDI Agent supports Real-Time Traffic/Transactions. Only one IDI Agent needs to be selected for real-time traffic. Currently we don't support multiple IDI agents to be enabled for real-time traffic at the same time. This field will be active only when Bit 0:RT_ENABLE is set to '1'"},
#else
{16, 17, 0x0000000000000000, "RW", "rt_idi_agent", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000000, "RW", "rt_enable", "Global enable bit for Real-Time Support"},
#else
{0, 0, 0x0000000000000000, "RW", "rt_enable", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1246[] = {{"B_CR_RT_EN_0_0_0_MCHBAR", "", 0x00006D78, 2, 0x000000000003FFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1247[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "slice0_asym_enable", "Setting this bit to 0 disables asymmetric memory region 0; setting it to 1 enables the region."},
#else
{31, 31, 0x0000000000000000, "RW", "slice0_asym_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "slice0_asym_channel_select", "Specifies Channel Selected for ASYM Region Mapped To Slice 0"},
#else
{30, 30, 0x0000000000000000, "RW", "slice0_asym_channel_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 29, 0x0000000000000000, "RW", "slice0_asym_limit", "Specifies bits [38:28] of the highest address of asymmetric memory region 0 (in slice 0); all the lower bits of the region's highest address are equal to 1."},
#else
{19, 29, 0x0000000000000000, "RW", "slice0_asym_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RW", "slice0_asym_base", "Specifies bits [38:28] of the base address of asymmetric memory region 0 (in slice 0); all the lower bits of the region's base address are equal to 0."},
#else
{4, 14, 0x0000000000000000, "RW", "slice0_asym_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1247[] = {{"B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR", "", 0x00006E40, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1248[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "slice1_asym_enable", "Setting this bit to 0 disables asymmetric memory region 1; setting it to 1 enables the region."},
#else
{31, 31, 0x0000000000000000, "RW", "slice1_asym_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{30, 30, 0x0000000000000000, "RW", "slice1_asym_channel_select", "Specifies Channel Selected for ASYM Region Mapped To Slice 1."},
#else
{30, 30, 0x0000000000000000, "RW", "slice1_asym_channel_select", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{19, 29, 0x0000000000000000, "RW", "slice1_asym_limit", "Specifies bits [38:28] of the highest address of asymmetric memory region 1 (in slice 1); all the lower bits of the region's highest address are equal to 1."},
#else
{19, 29, 0x0000000000000000, "RW", "slice1_asym_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RW", "slice1_asym_base", "Specifies bits [38:28] of the base address of asymmetric memory region 1 (in slice 1); all the lower bits of the region's base address are equal to 0."},
#else
{4, 14, 0x0000000000000000, "RW", "slice1_asym_base", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1248[] = {{"B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR", "", 0x00006E44, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1249[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{31, 31, 0x0000000000000000, "RW", "asym_2way_interleave_enable", "Setting this bit to 0 disables 2Way Asymmetric Interleaving; setting it to 1 enables the region."},
#else
{31, 31, 0x0000000000000000, "RW", "asym_2way_interleave_enable", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{17, 27, 0x0000000000000000, "RW", "asym_2way_limit", "Specifies bits [38:28] of the highest address of Interleave Asymmetric Region; all the lower bits of the region's highest address are equal to 1."},
#else
{17, 27, 0x0000000000000000, "RW", "asym_2way_limit", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{4, 14, 0x0000000000000000, "RW", "asym_2way_base", "Specifies bits [38:28] of the base address of Interleave Asymmetric Region; all the lower bits of the region's base address are equal to 0."},
#else
{4, 14, 0x0000000000000000, "RW", "asym_2way_base", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{2, 3, 0x0000000000000000, "RW", "asym_2way_intlv_mode", "\r\n"
"               Going with 2 bits here.\r\n"
"               2'b00 : Asymmetric memory Split between Channel 0 of Slice 0 and Slice 1\r\n"
"               2'b01 : Asymmetric memory split between Channel 1 of Slice 0 and Slice 1\r\n"
"               2'b10 : Asymmetric memory split between Channel 0 and Channel 1 of Slice 0\r\n"
"               2'b11 : Asymmetric memory split between Channel 0 and Channel 1 of Slice 1\r\n"
"      "},
#else
{2, 3, 0x0000000000000000, "RW", "asym_2way_intlv_mode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1249[] = {{"B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR", "", 0x00006E50, 4, 0x00000000FFFFFFFF, 0x0000000000000000}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1250[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{1, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{1, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
#if DUMP_REGISTER_DESCRIPTIONS
{0, 0, 0x0000000000000001, "RW", "mc_signal_mode", "When set to 1, B-Unit will not allow any transaction with uncorrectable error or subsequent memory transaction to propagate through to Requester. This will essentially hang CPU and CPU will end up with IERR shutdown. Issue: When set to zero B-Unit will allow transaction with an uncorrectable error to propagate and signal MC event to CPU if enabled in IA32_MC5_CTL. If enabled MC event will be taken by CPU cores at the end of instruction boundary after it detected by ROB"},
#else
{0, 0, 0x0000000000000001, "RW", "mc_signal_mode", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1250[] = {{"B_CR_BMCMODE_LOW", "", 0x00006E48, 2, 0x00000000FFFFFFFF, 0x0000000000000001}};
#if DUMP_REGISTER_FIELDS
RegisterField RegisterFields1251[] = {
#if DUMP_REGISTER_DESCRIPTIONS
{0, 31, 0x0000000000000000, "RO", "reserved_0", "Reserved."},
#else
{0, 31, 0x0000000000000000, "RO", "reserved_0", NULL},
#endif
};
#endif // DUMP_REGISTER_FIELDS
RegisterInformation RegisterInfo1251[] = {{"B_CR_BMCMODE_HIGH", "", 0x00006E4C, 1, 0x00000000FFFFFFFF, 0x0000000000000000}};
Register Registers[] = {
#if DUMP_REGISTER_FIELDS
  {(RegisterInformation *)&RegisterInfo0, RegisterFields0}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1, RegisterFields1}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo2, RegisterFields2}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo3, RegisterFields3}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo4, RegisterFields4}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo5, RegisterFields5}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo6, RegisterFields6}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo7, RegisterFields7}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo8, RegisterFields8}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo9, RegisterFields9}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo10, RegisterFields10}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo11, RegisterFields11}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo12, RegisterFields12}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo13, RegisterFields13}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo14, RegisterFields14}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo15, RegisterFields15}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo16, RegisterFields16}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo17, RegisterFields17}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo18, RegisterFields18}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo19, RegisterFields19}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo20, RegisterFields20}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo21, RegisterFields21}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo22, RegisterFields22}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo23, RegisterFields23}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo24, RegisterFields24}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo25, RegisterFields25}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo26, RegisterFields26}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo27, RegisterFields27}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo28, RegisterFields28}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo29, RegisterFields29}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo30, RegisterFields30}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo31, RegisterFields31}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo32, RegisterFields32}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo33, RegisterFields33}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo34, RegisterFields34}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo35, RegisterFields35}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo36, RegisterFields36}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo37, RegisterFields37}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo38, RegisterFields38}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo39, RegisterFields39}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo40, RegisterFields40}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo41, RegisterFields41}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo42, RegisterFields42}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo43, RegisterFields43}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo44, RegisterFields44}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo45, RegisterFields45}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo46, RegisterFields46}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo47, RegisterFields47}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo48, RegisterFields48}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo49, RegisterFields49}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo50, RegisterFields50}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo51, RegisterFields51}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo52, RegisterFields52}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo53, RegisterFields53}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo54, RegisterFields54}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo55, RegisterFields55}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo56, RegisterFields56}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo57, RegisterFields57}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo58, RegisterFields58}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo59, RegisterFields59}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo60, RegisterFields60}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo61, RegisterFields61}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo62, RegisterFields62}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo63, RegisterFields63}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo64, RegisterFields64}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo65, RegisterFields65}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo66, RegisterFields66}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo67, RegisterFields67}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo68, RegisterFields68}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo69, RegisterFields69}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo70, RegisterFields70}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo71, RegisterFields71}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo72, RegisterFields72}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo73, RegisterFields73}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo74, RegisterFields74}, // DUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo75, RegisterFields75}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo76, RegisterFields76}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo77, RegisterFields77}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo78, RegisterFields78}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo79, RegisterFields79}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo80, RegisterFields80}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo81, RegisterFields81}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo82, RegisterFields82}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo83, RegisterFields83}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo84, RegisterFields84}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo85, RegisterFields85}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo86, RegisterFields86}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo87, RegisterFields87}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo88, RegisterFields88}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo89, RegisterFields89}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo90, RegisterFields90}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo91, RegisterFields91}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo92, RegisterFields92}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo93, RegisterFields93}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo94, RegisterFields94}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo95, RegisterFields95}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo96, RegisterFields96}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo97, RegisterFields97}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo98, RegisterFields98}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo99, RegisterFields99}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo100, RegisterFields100}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo101, RegisterFields101}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo102, RegisterFields102}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo103, RegisterFields103}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo104, RegisterFields104}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo105, RegisterFields105}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo106, RegisterFields106}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo107, RegisterFields107}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo108, RegisterFields108}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo109, RegisterFields109}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo110, RegisterFields110}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo111, RegisterFields111}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo112, RegisterFields112}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo113, RegisterFields113}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo114, RegisterFields114}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo115, RegisterFields115}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo116, RegisterFields116}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo117, RegisterFields117}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo118, RegisterFields118}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo119, RegisterFields119}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo120, RegisterFields120}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo121, RegisterFields121}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo122, RegisterFields122}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo123, RegisterFields123}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo124, RegisterFields124}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo125, RegisterFields125}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo126, RegisterFields126}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo127, RegisterFields127}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo128, RegisterFields128}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo129, RegisterFields129}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo130, RegisterFields130}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo131, RegisterFields131}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo132, RegisterFields132}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo133, RegisterFields133}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo134, RegisterFields134}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo135, RegisterFields135}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo136, RegisterFields136}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo137, RegisterFields137}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo138, RegisterFields138}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo139, RegisterFields139}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo140, RegisterFields140}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo141, RegisterFields141}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo142, RegisterFields142}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo143, RegisterFields143}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo144, RegisterFields144}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo145, RegisterFields145}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo146, RegisterFields146}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo147, RegisterFields147}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo148, RegisterFields148}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo149, RegisterFields149}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo150, RegisterFields150}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo151, RegisterFields151}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo152, RegisterFields152}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo153, RegisterFields153}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo154, RegisterFields154}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo155, RegisterFields155}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo156, RegisterFields156}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo157, RegisterFields157}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo158, RegisterFields158}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo159, RegisterFields159}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo160, RegisterFields160}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo161, RegisterFields161}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo162, RegisterFields162}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo163, RegisterFields163}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo164, RegisterFields164}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo165, RegisterFields165}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo166, RegisterFields166}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo167, RegisterFields167}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo168, RegisterFields168}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo169, RegisterFields169}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo170, RegisterFields170}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo171, RegisterFields171}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo172, RegisterFields172}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo173, RegisterFields173}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo174, RegisterFields174}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo175, RegisterFields175}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo176, RegisterFields176}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo177, RegisterFields177}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo178, RegisterFields178}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo179, RegisterFields179}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo180, RegisterFields180}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo181, RegisterFields181}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo182, RegisterFields182}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo183, RegisterFields183}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo184, RegisterFields184}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo185, RegisterFields185}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo186, RegisterFields186}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo187, RegisterFields187}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo188, RegisterFields188}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo189, RegisterFields189}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo190, RegisterFields190}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo191, RegisterFields191}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo192, RegisterFields192}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo193, RegisterFields193}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo194, RegisterFields194}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo195, RegisterFields195}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo196, RegisterFields196}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo197, RegisterFields197}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo198, RegisterFields198}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo199, RegisterFields199}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo200, RegisterFields200}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo201, RegisterFields201}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo202, RegisterFields202}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo203, RegisterFields203}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo204, RegisterFields204}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo205, RegisterFields205}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo206, RegisterFields206}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo207, RegisterFields207}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo208, RegisterFields208}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo209, RegisterFields209}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo210, RegisterFields210}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo211, RegisterFields211}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo212, RegisterFields212}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo213, RegisterFields213}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo214, RegisterFields214}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo215, RegisterFields215}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo216, RegisterFields216}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo217, RegisterFields217}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo218, RegisterFields218}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo219, RegisterFields219}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo220, RegisterFields220}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo221, RegisterFields221}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo222, RegisterFields222}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo223, RegisterFields223}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo224, RegisterFields224}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo225, RegisterFields225}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo226, RegisterFields226}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo227, RegisterFields227}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo228, RegisterFields228}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo229, RegisterFields229}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo230, RegisterFields230}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo231, RegisterFields231}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo232, RegisterFields232}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo233, RegisterFields233}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo234, RegisterFields234}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo235, RegisterFields235}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo236, RegisterFields236}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo237, RegisterFields237}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo238, RegisterFields238}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo239, RegisterFields239}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo240, RegisterFields240}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo241, RegisterFields241}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo242, RegisterFields242}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo243, RegisterFields243}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo244, RegisterFields244}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo245, RegisterFields245}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo246, RegisterFields246}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo247, RegisterFields247}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo248, RegisterFields248}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo249, RegisterFields249}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo250, RegisterFields250}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo251, RegisterFields251}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo252, RegisterFields252}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo253, RegisterFields253}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo254, RegisterFields254}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo255, RegisterFields255}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo256, RegisterFields256}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo257, RegisterFields257}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo258, RegisterFields258}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo259, RegisterFields259}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo260, RegisterFields260}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo261, RegisterFields261}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo262, RegisterFields262}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo263, RegisterFields263}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo264, RegisterFields264}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo265, RegisterFields265}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo266, RegisterFields266}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo267, RegisterFields267}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo268, RegisterFields268}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo269, RegisterFields269}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo270, RegisterFields270}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo271, RegisterFields271}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo272, RegisterFields272}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo273, RegisterFields273}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo274, RegisterFields274}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo275, RegisterFields275}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo276, RegisterFields276}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo277, RegisterFields277}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo278, RegisterFields278}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo279, RegisterFields279}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo280, RegisterFields280}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo281, RegisterFields281}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo282, RegisterFields282}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo283, RegisterFields283}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo284, RegisterFields284}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo285, RegisterFields285}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo286, RegisterFields286}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo287, RegisterFields287}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo288, RegisterFields288}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo289, RegisterFields289}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo290, RegisterFields290}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo291, RegisterFields291}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo292, RegisterFields292}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo293, RegisterFields293}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo294, RegisterFields294}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo295, RegisterFields295}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo296, RegisterFields296}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo297, RegisterFields297}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo298, RegisterFields298}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo299, RegisterFields299}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo300, RegisterFields300}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo301, RegisterFields301}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo302, RegisterFields302}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo303, RegisterFields303}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo304, RegisterFields304}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo305, RegisterFields305}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo306, RegisterFields306}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo307, RegisterFields307}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo308, RegisterFields308}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo309, RegisterFields309}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo310, RegisterFields310}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo311, RegisterFields311}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo312, RegisterFields312}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo313, RegisterFields313}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo314, RegisterFields314}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo315, RegisterFields315}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo316, RegisterFields316}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo317, RegisterFields317}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo318, RegisterFields318}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo319, RegisterFields319}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo320, RegisterFields320}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo321, RegisterFields321}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo322, RegisterFields322}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo323, RegisterFields323}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo324, RegisterFields324}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo325, RegisterFields325}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo326, RegisterFields326}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo327, RegisterFields327}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo328, RegisterFields328}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo329, RegisterFields329}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo330, RegisterFields330}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo331, RegisterFields331}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo332, RegisterFields332}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo333, RegisterFields333}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo334, RegisterFields334}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo335, RegisterFields335}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo336, RegisterFields336}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo337, RegisterFields337}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo338, RegisterFields338}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo339, RegisterFields339}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo340, RegisterFields340}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo341, RegisterFields341}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo342, RegisterFields342}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo343, RegisterFields343}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo344, RegisterFields344}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo345, RegisterFields345}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo346, RegisterFields346}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo347, RegisterFields347}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo348, RegisterFields348}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo349, RegisterFields349}, // CPGC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo350, RegisterFields350}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo351, RegisterFields351}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo352, RegisterFields352}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo353, RegisterFields353}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo354, RegisterFields354}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo355, RegisterFields355}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo356, RegisterFields356}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo357, RegisterFields357}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo358, RegisterFields358}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo359, RegisterFields359}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo360, RegisterFields360}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo361, RegisterFields361}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo362, RegisterFields362}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo363, RegisterFields363}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo364, RegisterFields364}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo365, RegisterFields365}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo366, RegisterFields366}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo367, RegisterFields367}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo368, RegisterFields368}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo369, RegisterFields369}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo370, RegisterFields370}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo371, RegisterFields371}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo372, RegisterFields372}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo373, RegisterFields373}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo374, RegisterFields374}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo375, RegisterFields375}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo376, RegisterFields376}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo377, RegisterFields377}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo378, RegisterFields378}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo379, RegisterFields379}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo380, RegisterFields380}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo381, RegisterFields381}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo382, RegisterFields382}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo383, RegisterFields383}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo384, RegisterFields384}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo385, RegisterFields385}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo386, RegisterFields386}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo387, RegisterFields387}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo388, RegisterFields388}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo389, RegisterFields389}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo390, RegisterFields390}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo391, RegisterFields391}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo392, RegisterFields392}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo393, RegisterFields393}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo394, RegisterFields394}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo395, RegisterFields395}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo396, RegisterFields396}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo397, RegisterFields397}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo398, RegisterFields398}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo399, RegisterFields399}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo400, RegisterFields400}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo401, RegisterFields401}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo402, RegisterFields402}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo403, RegisterFields403}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo404, RegisterFields404}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo405, RegisterFields405}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo406, RegisterFields406}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo407, RegisterFields407}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo408, RegisterFields408}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo409, RegisterFields409}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo410, RegisterFields410}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo411, RegisterFields411}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo412, RegisterFields412}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo413, RegisterFields413}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo414, RegisterFields414}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo415, RegisterFields415}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo416, RegisterFields416}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo417, RegisterFields417}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo418, RegisterFields418}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo419, RegisterFields419}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo420, RegisterFields420}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo421, RegisterFields421}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo422, RegisterFields422}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo423, RegisterFields423}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo424, RegisterFields424}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo425, RegisterFields425}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo426, RegisterFields426}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo427, RegisterFields427}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo428, RegisterFields428}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo429, RegisterFields429}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo430, RegisterFields430}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo431, RegisterFields431}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo432, RegisterFields432}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo433, RegisterFields433}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo434, RegisterFields434}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo435, RegisterFields435}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo436, RegisterFields436}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo437, RegisterFields437}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo438, RegisterFields438}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo439, RegisterFields439}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo440, RegisterFields440}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo441, RegisterFields441}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo442, RegisterFields442}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo443, RegisterFields443}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo444, RegisterFields444}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo445, RegisterFields445}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo446, RegisterFields446}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo447, RegisterFields447}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo448, RegisterFields448}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo449, RegisterFields449}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo450, RegisterFields450}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo451, RegisterFields451}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo452, RegisterFields452}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo453, RegisterFields453}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo454, RegisterFields454}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo455, RegisterFields455}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo456, RegisterFields456}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo457, RegisterFields457}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo458, RegisterFields458}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo459, RegisterFields459}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo460, RegisterFields460}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo461, RegisterFields461}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo462, RegisterFields462}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo463, RegisterFields463}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo464, RegisterFields464}, // DQ_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo465, RegisterFields465}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo466, RegisterFields466}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo467, RegisterFields467}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo468, RegisterFields468}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo469, RegisterFields469}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo470, RegisterFields470}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo471, RegisterFields471}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo472, RegisterFields472}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo473, RegisterFields473}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo474, RegisterFields474}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo475, RegisterFields475}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo476, RegisterFields476}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo477, RegisterFields477}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo478, RegisterFields478}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo479, RegisterFields479}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo480, RegisterFields480}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo481, RegisterFields481}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo482, RegisterFields482}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo483, RegisterFields483}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo484, RegisterFields484}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo485, RegisterFields485}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo486, RegisterFields486}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo487, RegisterFields487}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo488, RegisterFields488}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo489, RegisterFields489}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo490, RegisterFields490}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo491, RegisterFields491}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo492, RegisterFields492}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo493, RegisterFields493}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo494, RegisterFields494}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo495, RegisterFields495}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo496, RegisterFields496}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo497, RegisterFields497}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo498, RegisterFields498}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo499, RegisterFields499}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo500, RegisterFields500}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo501, RegisterFields501}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo502, RegisterFields502}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo503, RegisterFields503}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo504, RegisterFields504}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo505, RegisterFields505}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo506, RegisterFields506}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo507, RegisterFields507}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo508, RegisterFields508}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo509, RegisterFields509}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo510, RegisterFields510}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo511, RegisterFields511}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo512, RegisterFields512}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo513, RegisterFields513}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo514, RegisterFields514}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo515, RegisterFields515}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo516, RegisterFields516}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo517, RegisterFields517}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo518, RegisterFields518}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo519, RegisterFields519}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo520, RegisterFields520}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo521, RegisterFields521}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo522, RegisterFields522}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo523, RegisterFields523}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo524, RegisterFields524}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo525, RegisterFields525}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo526, RegisterFields526}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo527, RegisterFields527}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo528, RegisterFields528}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo529, RegisterFields529}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo530, RegisterFields530}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo531, RegisterFields531}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo532, RegisterFields532}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo533, RegisterFields533}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo534, RegisterFields534}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo535, RegisterFields535}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo536, RegisterFields536}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo537, RegisterFields537}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo538, RegisterFields538}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo539, RegisterFields539}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo540, RegisterFields540}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo541, RegisterFields541}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo542, RegisterFields542}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo543, RegisterFields543}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo544, RegisterFields544}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo545, RegisterFields545}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo546, RegisterFields546}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo547, RegisterFields547}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo548, RegisterFields548}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo549, RegisterFields549}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo550, RegisterFields550}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo551, RegisterFields551}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo552, RegisterFields552}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo553, RegisterFields553}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo554, RegisterFields554}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo555, RegisterFields555}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo556, RegisterFields556}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo557, RegisterFields557}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo558, RegisterFields558}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo559, RegisterFields559}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo560, RegisterFields560}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo561, RegisterFields561}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo562, RegisterFields562}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo563, RegisterFields563}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo564, RegisterFields564}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo565, RegisterFields565}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo566, RegisterFields566}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo567, RegisterFields567}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo568, RegisterFields568}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo569, RegisterFields569}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo570, RegisterFields570}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo571, RegisterFields571}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo572, RegisterFields572}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo573, RegisterFields573}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo574, RegisterFields574}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo575, RegisterFields575}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo576, RegisterFields576}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo577, RegisterFields577}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo578, RegisterFields578}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo579, RegisterFields579}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo580, RegisterFields580}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo581, RegisterFields581}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo582, RegisterFields582}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo583, RegisterFields583}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo584, RegisterFields584}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo585, RegisterFields585}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo586, RegisterFields586}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo587, RegisterFields587}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo588, RegisterFields588}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo589, RegisterFields589}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo590, RegisterFields590}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo591, RegisterFields591}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo592, RegisterFields592}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo593, RegisterFields593}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo594, RegisterFields594}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo595, RegisterFields595}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo596, RegisterFields596}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo597, RegisterFields597}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo598, RegisterFields598}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo599, RegisterFields599}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo600, RegisterFields600}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo601, RegisterFields601}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo602, RegisterFields602}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo603, RegisterFields603}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo604, RegisterFields604}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo605, RegisterFields605}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo606, RegisterFields606}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo607, RegisterFields607}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo608, RegisterFields608}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo609, RegisterFields609}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo610, RegisterFields610}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo611, RegisterFields611}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo612, RegisterFields612}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo613, RegisterFields613}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo614, RegisterFields614}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo615, RegisterFields615}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo616, RegisterFields616}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo617, RegisterFields617}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo618, RegisterFields618}, // CCC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo619, RegisterFields619}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo620, RegisterFields620}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo621, RegisterFields621}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo622, RegisterFields622}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo623, RegisterFields623}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo624, RegisterFields624}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo625, RegisterFields625}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo626, RegisterFields626}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo627, RegisterFields627}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo628, RegisterFields628}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo629, RegisterFields629}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo630, RegisterFields630}, // SAI_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo631, RegisterFields631}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo632, RegisterFields632}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo633, RegisterFields633}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo634, RegisterFields634}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo635, RegisterFields635}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo636, RegisterFields636}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo637, RegisterFields637}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo638, RegisterFields638}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo639, RegisterFields639}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo640, RegisterFields640}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo641, RegisterFields641}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo642, RegisterFields642}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo643, RegisterFields643}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo644, RegisterFields644}, // ADPLL_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo645, RegisterFields645}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo646, RegisterFields646}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo647, RegisterFields647}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo648, RegisterFields648}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo649, RegisterFields649}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo650, RegisterFields650}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo651, RegisterFields651}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo652, RegisterFields652}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo653, RegisterFields653}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo654, RegisterFields654}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo655, RegisterFields655}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo656, RegisterFields656}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo657, RegisterFields657}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo658, RegisterFields658}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo659, RegisterFields659}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo660, RegisterFields660}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo661, RegisterFields661}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo662, RegisterFields662}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo663, RegisterFields663}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo664, RegisterFields664}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo665, RegisterFields665}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo666, RegisterFields666}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo667, RegisterFields667}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo668, RegisterFields668}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo669, RegisterFields669}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo670, RegisterFields670}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo671, RegisterFields671}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo672, RegisterFields672}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo673, RegisterFields673}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo674, RegisterFields674}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo675, RegisterFields675}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo676, RegisterFields676}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo677, RegisterFields677}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo678, RegisterFields678}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo679, RegisterFields679}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo680, RegisterFields680}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo681, RegisterFields681}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo682, RegisterFields682}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo683, RegisterFields683}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo684, RegisterFields684}, // DPLVUG_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo685, RegisterFields685}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo686, RegisterFields686}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo687, RegisterFields687}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo688, RegisterFields688}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo689, RegisterFields689}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo690, RegisterFields690}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo691, RegisterFields691}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo692, RegisterFields692}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo693, RegisterFields693}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo694, RegisterFields694}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo695, RegisterFields695}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo696, RegisterFields696}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo697, RegisterFields697}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo698, RegisterFields698}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo699, RegisterFields699}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo700, RegisterFields700}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo701, RegisterFields701}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo702, RegisterFields702}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo703, RegisterFields703}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo704, RegisterFields704}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo705, RegisterFields705}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo706, RegisterFields706}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo707, RegisterFields707}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo708, RegisterFields708}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo709, RegisterFields709}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo710, RegisterFields710}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo711, RegisterFields711}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo712, RegisterFields712}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo713, RegisterFields713}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo714, RegisterFields714}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo715, RegisterFields715}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo716, RegisterFields716}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo717, RegisterFields717}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo718, RegisterFields718}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo719, RegisterFields719}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo720, RegisterFields720}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo721, RegisterFields721}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo722, RegisterFields722}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo723, RegisterFields723}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo724, RegisterFields724}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo725, RegisterFields725}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo726, RegisterFields726}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo727, RegisterFields727}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo728, RegisterFields728}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo729, RegisterFields729}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo730, RegisterFields730}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo731, RegisterFields731}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo732, RegisterFields732}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo733, RegisterFields733}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo734, RegisterFields734}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo735, RegisterFields735}, // DPIC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo736, RegisterFields736}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo737, RegisterFields737}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo738, RegisterFields738}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo739, RegisterFields739}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo740, RegisterFields740}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo741, RegisterFields741}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo742, RegisterFields742}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo743, RegisterFields743}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo744, RegisterFields744}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo745, RegisterFields745}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo746, RegisterFields746}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo747, RegisterFields747}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo748, RegisterFields748}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo749, RegisterFields749}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo750, RegisterFields750}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo751, RegisterFields751}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo752, RegisterFields752}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo753, RegisterFields753}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo754, RegisterFields754}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo755, RegisterFields755}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo756, RegisterFields756}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo757, RegisterFields757}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo758, RegisterFields758}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo759, RegisterFields759}, // DQDPIC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo760, RegisterFields760}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo761, RegisterFields761}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo762, RegisterFields762}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo763, RegisterFields763}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo764, RegisterFields764}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo765, RegisterFields765}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo766, RegisterFields766}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo767, RegisterFields767}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo768, RegisterFields768}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo769, RegisterFields769}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo770, RegisterFields770}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo771, RegisterFields771}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo772, RegisterFields772}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo773, RegisterFields773}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo774, RegisterFields774}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo775, RegisterFields775}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo776, RegisterFields776}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo777, RegisterFields777}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo778, RegisterFields778}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo779, RegisterFields779}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo780, RegisterFields780}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo781, RegisterFields781}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo782, RegisterFields782}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo783, RegisterFields783}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo784, RegisterFields784}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo785, RegisterFields785}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo786, RegisterFields786}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo787, RegisterFields787}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo788, RegisterFields788}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo789, RegisterFields789}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo790, RegisterFields790}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo791, RegisterFields791}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo792, RegisterFields792}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo793, RegisterFields793}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo794, RegisterFields794}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo795, RegisterFields795}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo796, RegisterFields796}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo797, RegisterFields797}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo798, RegisterFields798}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo799, RegisterFields799}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo800, RegisterFields800}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo801, RegisterFields801}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo802, RegisterFields802}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo803, RegisterFields803}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo804, RegisterFields804}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo805, RegisterFields805}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo806, RegisterFields806}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo807, RegisterFields807}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo808, RegisterFields808}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo809, RegisterFields809}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo810, RegisterFields810}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo811, RegisterFields811}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo812, RegisterFields812}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo813, RegisterFields813}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo814, RegisterFields814}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo815, RegisterFields815}, // DQDPLVUG_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo816, RegisterFields816}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo817, RegisterFields817}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo818, RegisterFields818}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo819, RegisterFields819}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo820, RegisterFields820}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo821, RegisterFields821}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo822, RegisterFields822}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo823, RegisterFields823}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo824, RegisterFields824}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo825, RegisterFields825}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo826, RegisterFields826}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo827, RegisterFields827}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo828, RegisterFields828}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo829, RegisterFields829}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo830, RegisterFields830}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo831, RegisterFields831}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo832, RegisterFields832}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo833, RegisterFields833}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo834, RegisterFields834}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo835, RegisterFields835}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo836, RegisterFields836}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo837, RegisterFields837}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo838, RegisterFields838}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo839, RegisterFields839}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo840, RegisterFields840}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo841, RegisterFields841}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo842, RegisterFields842}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo843, RegisterFields843}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo844, RegisterFields844}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo845, RegisterFields845}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo846, RegisterFields846}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo847, RegisterFields847}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo848, RegisterFields848}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo849, RegisterFields849}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo850, RegisterFields850}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo851, RegisterFields851}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo852, RegisterFields852}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo853, RegisterFields853}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo854, RegisterFields854}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo855, RegisterFields855}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo856, RegisterFields856}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo857, RegisterFields857}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo858, RegisterFields858}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo859, RegisterFields859}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo860, RegisterFields860}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo861, RegisterFields861}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo862, RegisterFields862}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo863, RegisterFields863}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo864, RegisterFields864}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo865, RegisterFields865}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo866, RegisterFields866}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo867, RegisterFields867}, // CUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo868, RegisterFields868}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo869, RegisterFields869}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo870, RegisterFields870}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo871, RegisterFields871}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo872, RegisterFields872}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo873, RegisterFields873}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo874, RegisterFields874}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo875, RegisterFields875}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo876, RegisterFields876}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo877, RegisterFields877}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo878, RegisterFields878}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo879, RegisterFields879}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo880, RegisterFields880}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo881, RegisterFields881}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo882, RegisterFields882}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo883, RegisterFields883}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo884, RegisterFields884}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo885, RegisterFields885}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo886, RegisterFields886}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo887, RegisterFields887}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo888, RegisterFields888}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo889, RegisterFields889}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo890, RegisterFields890}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo891, RegisterFields891}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo892, RegisterFields892}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo893, RegisterFields893}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo894, RegisterFields894}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo895, RegisterFields895}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo896, RegisterFields896}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo897, RegisterFields897}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo898, RegisterFields898}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo899, RegisterFields899}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo900, RegisterFields900}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo901, RegisterFields901}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo902, RegisterFields902}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo903, RegisterFields903}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo904, RegisterFields904}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo905, RegisterFields905}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo906, RegisterFields906}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo907, RegisterFields907}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo908, RegisterFields908}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo909, RegisterFields909}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo910, RegisterFields910}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo911, RegisterFields911}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo912, RegisterFields912}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo913, RegisterFields913}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo914, RegisterFields914}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo915, RegisterFields915}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo916, RegisterFields916}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo917, RegisterFields917}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo918, RegisterFields918}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo919, RegisterFields919}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo920, RegisterFields920}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo921, RegisterFields921}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo922, RegisterFields922}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo923, RegisterFields923}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo924, RegisterFields924}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo925, RegisterFields925}, // PUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo926, RegisterFields926}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo927, RegisterFields927}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo928, RegisterFields928}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo929, RegisterFields929}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo930, RegisterFields930}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo931, RegisterFields931}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo932, RegisterFields932}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo933, RegisterFields933}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo934, RegisterFields934}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo935, RegisterFields935}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo936, RegisterFields936}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo937, RegisterFields937}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo938, RegisterFields938}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo939, RegisterFields939}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo940, RegisterFields940}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo941, RegisterFields941}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo942, RegisterFields942}, // MLMC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo943, RegisterFields943}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo944, RegisterFields944}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo945, RegisterFields945}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo946, RegisterFields946}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo947, RegisterFields947}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo948, RegisterFields948}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo949, RegisterFields949}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo950, RegisterFields950}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo951, RegisterFields951}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo952, RegisterFields952}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo953, RegisterFields953}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo954, RegisterFields954}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo955, RegisterFields955}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo956, RegisterFields956}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo957, RegisterFields957}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo958, RegisterFields958}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo959, RegisterFields959}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo960, RegisterFields960}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo961, RegisterFields961}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo962, RegisterFields962}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo963, RegisterFields963}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo964, RegisterFields964}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo965, RegisterFields965}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo966, RegisterFields966}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo967, RegisterFields967}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo968, RegisterFields968}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo969, RegisterFields969}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo970, RegisterFields970}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo971, RegisterFields971}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo972, RegisterFields972}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo973, RegisterFields973}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo974, RegisterFields974}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo975, RegisterFields975}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo976, RegisterFields976}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo977, RegisterFields977}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo978, RegisterFields978}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo979, RegisterFields979}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo980, RegisterFields980}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo981, RegisterFields981}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo982, RegisterFields982}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo983, RegisterFields983}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo984, RegisterFields984}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo985, RegisterFields985}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo986, RegisterFields986}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo987, RegisterFields987}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo988, RegisterFields988}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo989, RegisterFields989}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo990, RegisterFields990}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo991, RegisterFields991}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo992, RegisterFields992}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo993, RegisterFields993}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo994, RegisterFields994}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo995, RegisterFields995}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo996, RegisterFields996}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo997, RegisterFields997}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo998, RegisterFields998}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo999, RegisterFields999}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1000, RegisterFields1000}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1001, RegisterFields1001}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1002, RegisterFields1002}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1003, RegisterFields1003}, // AUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo1004, RegisterFields1004}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1005, RegisterFields1005}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1006, RegisterFields1006}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1007, RegisterFields1007}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1008, RegisterFields1008}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1009, RegisterFields1009}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1010, RegisterFields1010}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1011, RegisterFields1011}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1012, RegisterFields1012}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1013, RegisterFields1013}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1014, RegisterFields1014}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1015, RegisterFields1015}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1016, RegisterFields1016}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1017, RegisterFields1017}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1018, RegisterFields1018}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1019, RegisterFields1019}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1020, RegisterFields1020}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1021, RegisterFields1021}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1022, RegisterFields1022}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1023, RegisterFields1023}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1024, RegisterFields1024}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1025, RegisterFields1025}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1026, RegisterFields1026}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1027, RegisterFields1027}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1028, RegisterFields1028}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1029, RegisterFields1029}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1030, RegisterFields1030}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1031, RegisterFields1031}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1032, RegisterFields1032}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1033, RegisterFields1033}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1034, RegisterFields1034}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1035, RegisterFields1035}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1036, RegisterFields1036}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1037, RegisterFields1037}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1038, RegisterFields1038}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1039, RegisterFields1039}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1040, RegisterFields1040}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1041, RegisterFields1041}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1042, RegisterFields1042}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1043, RegisterFields1043}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1044, RegisterFields1044}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1045, RegisterFields1045}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1046, RegisterFields1046}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1047, RegisterFields1047}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1048, RegisterFields1048}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1049, RegisterFields1049}, // P2SB_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo1050, RegisterFields1050}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1051, RegisterFields1051}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1052, RegisterFields1052}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1053, RegisterFields1053}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1054, RegisterFields1054}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1055, RegisterFields1055}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1056, RegisterFields1056}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1057, RegisterFields1057}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1058, RegisterFields1058}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1059, RegisterFields1059}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1060, RegisterFields1060}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1061, RegisterFields1061}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1062, RegisterFields1062}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1063, RegisterFields1063}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1064, RegisterFields1064}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1065, RegisterFields1065}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1066, RegisterFields1066}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1067, RegisterFields1067}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1068, RegisterFields1068}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1069, RegisterFields1069}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1070, RegisterFields1070}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1071, RegisterFields1071}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1072, RegisterFields1072}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1073, RegisterFields1073}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1074, RegisterFields1074}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1075, RegisterFields1075}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1076, RegisterFields1076}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1077, RegisterFields1077}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1078, RegisterFields1078}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1079, RegisterFields1079}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1080, RegisterFields1080}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1081, RegisterFields1081}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1082, RegisterFields1082}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1083, RegisterFields1083}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1084, RegisterFields1084}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1085, RegisterFields1085}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1086, RegisterFields1086}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1087, RegisterFields1087}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1088, RegisterFields1088}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1089, RegisterFields1089}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1090, RegisterFields1090}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1091, RegisterFields1091}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1092, RegisterFields1092}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1093, RegisterFields1093}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1094, RegisterFields1094}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1095, RegisterFields1095}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1096, RegisterFields1096}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1097, RegisterFields1097}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1098, RegisterFields1098}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1099, RegisterFields1099}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1100, RegisterFields1100}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1101, RegisterFields1101}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1102, RegisterFields1102}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1103, RegisterFields1103}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1104, RegisterFields1104}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1105, RegisterFields1105}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1106, RegisterFields1106}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1107, RegisterFields1107}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1108, RegisterFields1108}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1109, RegisterFields1109}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1110, RegisterFields1110}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1111, RegisterFields1111}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1112, RegisterFields1112}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1113, RegisterFields1113}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1114, RegisterFields1114}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1115, RegisterFields1115}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1116, RegisterFields1116}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1117, RegisterFields1117}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1118, RegisterFields1118}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1119, RegisterFields1119}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1120, RegisterFields1120}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1121, RegisterFields1121}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1122, RegisterFields1122}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1123, RegisterFields1123}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1124, RegisterFields1124}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1125, RegisterFields1125}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1126, RegisterFields1126}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1127, RegisterFields1127}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1128, RegisterFields1128}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1129, RegisterFields1129}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1130, RegisterFields1130}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1131, RegisterFields1131}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1132, RegisterFields1132}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1133, RegisterFields1133}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1134, RegisterFields1134}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1135, RegisterFields1135}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1136, RegisterFields1136}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1137, RegisterFields1137}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1138, RegisterFields1138}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1139, RegisterFields1139}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1140, RegisterFields1140}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1141, RegisterFields1141}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1142, RegisterFields1142}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1143, RegisterFields1143}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1144, RegisterFields1144}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1145, RegisterFields1145}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1146, RegisterFields1146}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1147, RegisterFields1147}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1148, RegisterFields1148}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1149, RegisterFields1149}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1150, RegisterFields1150}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1151, RegisterFields1151}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1152, RegisterFields1152}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1153, RegisterFields1153}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1154, RegisterFields1154}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1155, RegisterFields1155}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1156, RegisterFields1156}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1157, RegisterFields1157}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1158, RegisterFields1158}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1159, RegisterFields1159}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1160, RegisterFields1160}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1161, RegisterFields1161}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1162, RegisterFields1162}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1163, RegisterFields1163}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1164, RegisterFields1164}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1165, RegisterFields1165}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1166, RegisterFields1166}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1167, RegisterFields1167}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1168, RegisterFields1168}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1169, RegisterFields1169}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1170, RegisterFields1170}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1171, RegisterFields1171}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1172, RegisterFields1172}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1173, RegisterFields1173}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1174, RegisterFields1174}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1175, RegisterFields1175}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1176, RegisterFields1176}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1177, RegisterFields1177}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1178, RegisterFields1178}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1179, RegisterFields1179}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1180, RegisterFields1180}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1181, RegisterFields1181}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1182, RegisterFields1182}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1183, RegisterFields1183}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1184, RegisterFields1184}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1185, RegisterFields1185}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1186, RegisterFields1186}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1187, RegisterFields1187}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1188, RegisterFields1188}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1189, RegisterFields1189}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1190, RegisterFields1190}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1191, RegisterFields1191}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1192, RegisterFields1192}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1193, RegisterFields1193}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1194, RegisterFields1194}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1195, RegisterFields1195}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1196, RegisterFields1196}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1197, RegisterFields1197}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1198, RegisterFields1198}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1199, RegisterFields1199}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1200, RegisterFields1200}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1201, RegisterFields1201}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1202, RegisterFields1202}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1203, RegisterFields1203}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1204, RegisterFields1204}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1205, RegisterFields1205}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1206, RegisterFields1206}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1207, RegisterFields1207}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1208, RegisterFields1208}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1209, RegisterFields1209}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1210, RegisterFields1210}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1211, RegisterFields1211}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1212, RegisterFields1212}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1213, RegisterFields1213}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1214, RegisterFields1214}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1215, RegisterFields1215}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1216, RegisterFields1216}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1217, RegisterFields1217}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1218, RegisterFields1218}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1219, RegisterFields1219}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1220, RegisterFields1220}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1221, RegisterFields1221}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1222, RegisterFields1222}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1223, RegisterFields1223}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1224, RegisterFields1224}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1225, RegisterFields1225}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1226, RegisterFields1226}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1227, RegisterFields1227}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1228, RegisterFields1228}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1229, RegisterFields1229}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1230, RegisterFields1230}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1231, RegisterFields1231}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1232, RegisterFields1232}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1233, RegisterFields1233}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1234, RegisterFields1234}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1235, RegisterFields1235}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1236, RegisterFields1236}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1237, RegisterFields1237}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1238, RegisterFields1238}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1239, RegisterFields1239}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1240, RegisterFields1240}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1241, RegisterFields1241}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1242, RegisterFields1242}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1243, RegisterFields1243}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1244, RegisterFields1244}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1245, RegisterFields1245}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1246, RegisterFields1246}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1247, RegisterFields1247}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1248, RegisterFields1248}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1249, RegisterFields1249}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1250, RegisterFields1250}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1251, RegisterFields1251}, // BUNIT_BOXTYPE
{NULL, NULL},
#else
  {(RegisterInformation *)&RegisterInfo0, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo2, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo3, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo4, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo5, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo6, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo7, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo8, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo9, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo10, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo11, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo12, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo13, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo14, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo15, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo16, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo17, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo18, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo19, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo20, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo21, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo22, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo23, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo24, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo25, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo26, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo27, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo28, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo29, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo30, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo31, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo32, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo33, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo34, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo35, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo36, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo37, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo38, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo39, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo40, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo41, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo42, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo43, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo44, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo45, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo46, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo47, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo48, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo49, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo50, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo51, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo52, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo53, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo54, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo55, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo56, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo57, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo58, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo59, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo60, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo61, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo62, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo63, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo64, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo65, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo66, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo67, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo68, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo69, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo70, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo71, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo72, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo73, NULL}, // DUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo74, NULL}, // DUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo75, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo76, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo77, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo78, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo79, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo80, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo81, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo82, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo83, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo84, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo85, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo86, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo87, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo88, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo89, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo90, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo91, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo92, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo93, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo94, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo95, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo96, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo97, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo98, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo99, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo100, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo101, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo102, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo103, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo104, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo105, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo106, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo107, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo108, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo109, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo110, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo111, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo112, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo113, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo114, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo115, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo116, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo117, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo118, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo119, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo120, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo121, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo122, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo123, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo124, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo125, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo126, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo127, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo128, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo129, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo130, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo131, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo132, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo133, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo134, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo135, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo136, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo137, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo138, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo139, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo140, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo141, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo142, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo143, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo144, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo145, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo146, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo147, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo148, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo149, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo150, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo151, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo152, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo153, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo154, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo155, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo156, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo157, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo158, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo159, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo160, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo161, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo162, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo163, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo164, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo165, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo166, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo167, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo168, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo169, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo170, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo171, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo172, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo173, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo174, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo175, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo176, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo177, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo178, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo179, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo180, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo181, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo182, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo183, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo184, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo185, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo186, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo187, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo188, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo189, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo190, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo191, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo192, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo193, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo194, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo195, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo196, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo197, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo198, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo199, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo200, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo201, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo202, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo203, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo204, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo205, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo206, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo207, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo208, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo209, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo210, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo211, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo212, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo213, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo214, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo215, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo216, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo217, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo218, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo219, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo220, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo221, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo222, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo223, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo224, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo225, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo226, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo227, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo228, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo229, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo230, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo231, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo232, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo233, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo234, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo235, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo236, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo237, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo238, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo239, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo240, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo241, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo242, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo243, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo244, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo245, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo246, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo247, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo248, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo249, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo250, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo251, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo252, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo253, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo254, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo255, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo256, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo257, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo258, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo259, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo260, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo261, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo262, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo263, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo264, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo265, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo266, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo267, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo268, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo269, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo270, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo271, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo272, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo273, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo274, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo275, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo276, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo277, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo278, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo279, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo280, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo281, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo282, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo283, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo284, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo285, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo286, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo287, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo288, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo289, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo290, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo291, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo292, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo293, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo294, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo295, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo296, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo297, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo298, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo299, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo300, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo301, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo302, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo303, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo304, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo305, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo306, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo307, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo308, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo309, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo310, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo311, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo312, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo313, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo314, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo315, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo316, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo317, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo318, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo319, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo320, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo321, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo322, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo323, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo324, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo325, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo326, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo327, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo328, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo329, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo330, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo331, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo332, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo333, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo334, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo335, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo336, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo337, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo338, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo339, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo340, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo341, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo342, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo343, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo344, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo345, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo346, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo347, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo348, NULL}, // CPGC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo349, NULL}, // CPGC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo350, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo351, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo352, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo353, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo354, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo355, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo356, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo357, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo358, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo359, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo360, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo361, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo362, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo363, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo364, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo365, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo366, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo367, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo368, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo369, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo370, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo371, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo372, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo373, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo374, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo375, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo376, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo377, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo378, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo379, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo380, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo381, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo382, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo383, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo384, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo385, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo386, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo387, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo388, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo389, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo390, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo391, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo392, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo393, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo394, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo395, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo396, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo397, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo398, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo399, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo400, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo401, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo402, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo403, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo404, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo405, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo406, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo407, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo408, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo409, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo410, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo411, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo412, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo413, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo414, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo415, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo416, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo417, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo418, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo419, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo420, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo421, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo422, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo423, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo424, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo425, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo426, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo427, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo428, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo429, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo430, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo431, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo432, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo433, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo434, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo435, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo436, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo437, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo438, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo439, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo440, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo441, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo442, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo443, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo444, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo445, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo446, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo447, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo448, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo449, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo450, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo451, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo452, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo453, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo454, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo455, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo456, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo457, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo458, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo459, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo460, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo461, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo462, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo463, NULL}, // DQ_BOXTYPE
  {(RegisterInformation *)&RegisterInfo464, NULL}, // DQ_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo465, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo466, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo467, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo468, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo469, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo470, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo471, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo472, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo473, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo474, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo475, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo476, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo477, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo478, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo479, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo480, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo481, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo482, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo483, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo484, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo485, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo486, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo487, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo488, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo489, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo490, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo491, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo492, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo493, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo494, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo495, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo496, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo497, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo498, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo499, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo500, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo501, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo502, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo503, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo504, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo505, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo506, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo507, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo508, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo509, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo510, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo511, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo512, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo513, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo514, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo515, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo516, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo517, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo518, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo519, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo520, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo521, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo522, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo523, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo524, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo525, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo526, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo527, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo528, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo529, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo530, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo531, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo532, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo533, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo534, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo535, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo536, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo537, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo538, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo539, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo540, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo541, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo542, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo543, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo544, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo545, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo546, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo547, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo548, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo549, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo550, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo551, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo552, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo553, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo554, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo555, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo556, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo557, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo558, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo559, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo560, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo561, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo562, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo563, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo564, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo565, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo566, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo567, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo568, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo569, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo570, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo571, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo572, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo573, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo574, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo575, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo576, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo577, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo578, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo579, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo580, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo581, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo582, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo583, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo584, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo585, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo586, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo587, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo588, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo589, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo590, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo591, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo592, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo593, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo594, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo595, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo596, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo597, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo598, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo599, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo600, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo601, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo602, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo603, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo604, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo605, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo606, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo607, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo608, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo609, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo610, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo611, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo612, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo613, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo614, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo615, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo616, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo617, NULL}, // CCC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo618, NULL}, // CCC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo619, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo620, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo621, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo622, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo623, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo624, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo625, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo626, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo627, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo628, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo629, NULL}, // SAI_BOXTYPE
  {(RegisterInformation *)&RegisterInfo630, NULL}, // SAI_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo631, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo632, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo633, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo634, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo635, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo636, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo637, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo638, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo639, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo640, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo641, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo642, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo643, NULL}, // ADPLL_BOXTYPE
  {(RegisterInformation *)&RegisterInfo644, NULL}, // ADPLL_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo645, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo646, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo647, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo648, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo649, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo650, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo651, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo652, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo653, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo654, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo655, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo656, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo657, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo658, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo659, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo660, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo661, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo662, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo663, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo664, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo665, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo666, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo667, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo668, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo669, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo670, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo671, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo672, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo673, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo674, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo675, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo676, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo677, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo678, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo679, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo680, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo681, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo682, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo683, NULL}, // DPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo684, NULL}, // DPLVUG_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo685, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo686, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo687, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo688, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo689, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo690, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo691, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo692, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo693, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo694, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo695, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo696, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo697, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo698, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo699, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo700, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo701, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo702, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo703, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo704, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo705, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo706, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo707, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo708, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo709, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo710, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo711, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo712, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo713, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo714, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo715, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo716, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo717, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo718, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo719, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo720, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo721, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo722, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo723, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo724, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo725, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo726, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo727, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo728, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo729, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo730, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo731, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo732, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo733, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo734, NULL}, // DPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo735, NULL}, // DPIC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo736, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo737, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo738, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo739, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo740, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo741, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo742, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo743, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo744, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo745, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo746, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo747, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo748, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo749, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo750, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo751, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo752, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo753, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo754, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo755, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo756, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo757, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo758, NULL}, // DQDPIC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo759, NULL}, // DQDPIC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo760, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo761, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo762, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo763, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo764, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo765, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo766, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo767, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo768, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo769, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo770, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo771, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo772, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo773, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo774, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo775, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo776, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo777, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo778, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo779, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo780, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo781, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo782, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo783, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo784, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo785, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo786, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo787, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo788, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo789, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo790, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo791, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo792, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo793, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo794, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo795, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo796, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo797, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo798, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo799, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo800, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo801, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo802, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo803, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo804, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo805, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo806, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo807, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo808, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo809, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo810, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo811, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo812, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo813, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo814, NULL}, // DQDPLVUG_BOXTYPE
  {(RegisterInformation *)&RegisterInfo815, NULL}, // DQDPLVUG_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo816, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo817, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo818, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo819, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo820, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo821, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo822, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo823, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo824, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo825, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo826, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo827, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo828, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo829, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo830, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo831, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo832, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo833, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo834, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo835, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo836, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo837, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo838, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo839, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo840, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo841, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo842, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo843, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo844, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo845, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo846, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo847, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo848, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo849, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo850, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo851, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo852, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo853, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo854, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo855, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo856, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo857, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo858, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo859, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo860, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo861, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo862, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo863, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo864, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo865, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo866, NULL}, // CUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo867, NULL}, // CUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo868, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo869, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo870, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo871, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo872, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo873, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo874, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo875, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo876, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo877, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo878, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo879, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo880, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo881, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo882, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo883, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo884, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo885, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo886, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo887, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo888, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo889, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo890, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo891, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo892, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo893, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo894, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo895, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo896, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo897, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo898, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo899, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo900, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo901, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo902, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo903, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo904, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo905, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo906, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo907, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo908, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo909, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo910, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo911, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo912, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo913, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo914, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo915, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo916, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo917, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo918, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo919, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo920, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo921, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo922, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo923, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo924, NULL}, // PUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo925, NULL}, // PUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo926, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo927, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo928, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo929, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo930, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo931, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo932, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo933, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo934, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo935, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo936, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo937, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo938, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo939, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo940, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo941, NULL}, // MLMC_BOXTYPE
  {(RegisterInformation *)&RegisterInfo942, NULL}, // MLMC_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo943, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo944, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo945, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo946, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo947, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo948, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo949, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo950, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo951, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo952, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo953, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo954, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo955, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo956, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo957, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo958, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo959, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo960, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo961, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo962, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo963, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo964, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo965, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo966, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo967, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo968, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo969, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo970, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo971, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo972, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo973, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo974, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo975, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo976, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo977, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo978, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo979, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo980, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo981, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo982, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo983, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo984, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo985, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo986, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo987, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo988, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo989, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo990, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo991, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo992, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo993, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo994, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo995, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo996, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo997, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo998, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo999, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1000, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1001, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1002, NULL}, // AUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1003, NULL}, // AUNIT_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo1004, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1005, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1006, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1007, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1008, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1009, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1010, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1011, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1012, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1013, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1014, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1015, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1016, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1017, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1018, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1019, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1020, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1021, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1022, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1023, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1024, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1025, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1026, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1027, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1028, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1029, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1030, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1031, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1032, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1033, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1034, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1035, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1036, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1037, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1038, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1039, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1040, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1041, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1042, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1043, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1044, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1045, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1046, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1047, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1048, NULL}, // P2SB_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1049, NULL}, // P2SB_BOXTYPE
{NULL, NULL},
  {(RegisterInformation *)&RegisterInfo1050, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1051, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1052, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1053, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1054, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1055, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1056, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1057, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1058, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1059, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1060, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1061, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1062, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1063, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1064, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1065, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1066, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1067, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1068, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1069, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1070, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1071, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1072, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1073, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1074, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1075, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1076, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1077, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1078, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1079, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1080, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1081, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1082, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1083, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1084, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1085, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1086, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1087, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1088, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1089, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1090, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1091, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1092, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1093, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1094, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1095, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1096, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1097, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1098, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1099, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1100, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1101, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1102, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1103, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1104, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1105, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1106, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1107, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1108, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1109, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1110, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1111, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1112, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1113, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1114, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1115, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1116, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1117, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1118, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1119, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1120, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1121, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1122, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1123, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1124, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1125, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1126, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1127, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1128, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1129, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1130, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1131, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1132, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1133, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1134, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1135, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1136, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1137, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1138, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1139, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1140, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1141, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1142, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1143, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1144, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1145, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1146, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1147, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1148, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1149, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1150, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1151, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1152, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1153, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1154, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1155, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1156, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1157, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1158, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1159, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1160, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1161, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1162, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1163, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1164, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1165, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1166, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1167, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1168, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1169, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1170, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1171, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1172, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1173, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1174, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1175, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1176, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1177, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1178, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1179, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1180, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1181, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1182, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1183, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1184, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1185, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1186, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1187, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1188, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1189, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1190, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1191, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1192, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1193, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1194, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1195, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1196, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1197, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1198, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1199, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1200, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1201, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1202, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1203, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1204, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1205, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1206, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1207, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1208, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1209, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1210, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1211, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1212, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1213, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1214, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1215, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1216, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1217, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1218, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1219, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1220, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1221, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1222, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1223, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1224, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1225, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1226, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1227, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1228, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1229, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1230, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1231, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1232, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1233, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1234, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1235, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1236, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1237, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1238, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1239, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1240, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1241, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1242, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1243, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1244, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1245, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1246, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1247, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1248, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1249, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1250, NULL}, // BUNIT_BOXTYPE
  {(RegisterInformation *)&RegisterInfo1251, NULL}, // BUNIT_BOXTYPE
{NULL, NULL},
#endif // DUMP_REGISTER_FIELDS
};

#else
Register Registers[] = {{NULL, NULL}};
#endif // DUMP_REGISTER_NAMES

