/** @file
  File name:    MmrcProjectDataGenerated.c
  Input File:   BXTM_SOC.xlsx

  THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.

  If edits are needed in this file, they must be done via the MMRC tool.

  If there is additional project-specific data required by the MMRC, it
  can be placed in MmrcProjectData.c, which is used for non-tool-generated
  data

  This file contains data structures for a particular piece of silicon.
  These structures are fed to MmrcLibraries.c, which use them to initialize
  memory.

  @copyright
  Copyright (c) 2005-2016 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as 'Intel Reference Module' and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

  @par Specification
**/
#include "MmrcProjectData.h"
#include "MmrcLibraries.h"

TASK_DESCRIPTOR InitTasks [] = {
//  PC     BootMode                Function                            Description                       String Channel       Plat     Freq   Config               Tech
  { 0x000, S0|S5|FB|RS|EM|A0     , &DISPLAYMMRCVERSION               , EXTERNAL                         , 0x000, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x004, S0|S5|FB|RS|EM|A0|CSE , &MmrcConvertParams                , EXTERNAL                         , 0x001, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x001, S0|S5|FB| EM          , &MmrcExecuteTask                  , InitPunit                        , 0x002, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x002, S0|S5|FB| EM          , &MmrcExecuteTask                  , PollPunit                        , 0x003, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x003, 0                     , &SetupMRCFreqA                    , EXTERNAL                         , 0x004, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x007, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp1xm_seq      , 0x005, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x008, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp1p5_seq      , 0x006, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x009, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp2m_seq       , 0x007, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x010, RS                    , &MmrcExecuteTask                  , Wake_Chassis                     , 0x008, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x011, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp3m_seq       , 0x009, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x012, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp3_seq        , 0x00A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x013, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp3p75_seq     , 0x00B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x014, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp4m_seq       , 0x00C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x015, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_ldo_offsetcomp_seq        , 0x00D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x016, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp2p5_seq      , 0x00E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x017, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_ldo_offsetcomp_poll       , 0x00F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x018, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp4_seq        , 0x010, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x019, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp4p5_seq      , 0x011, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x020, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp5m_seq       , 0x012, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x021, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp5_seq        , 0x013, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x022, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp5p25_seq     , 0x014, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x023, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp5p5m_seq     , 0x015, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x024, S0|S5|FB|EM|A0        , &MmrcExecuteTask                  , PhyConfigComplete                , 0x016, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x025, A0                    , &MmrcExecuteTask                  , MRC_to_Tap_step32                , 0x017, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x025, S0|S5|FB|EM           , &MmrcExecuteTask                  , PollPunit                        , 0x018, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x026, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp5p5_seq      , 0x019, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x027, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp5p5_seq1     , 0x01A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x028, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp6_seq        , 0x01B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x032, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp6p5_seq      , 0x01C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x030, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp7_seq        , 0x01D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x031, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp7p5_seq      , 0x01E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x043, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp7p75_seq     , 0x01F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x033, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp8m_seq       , 0x020, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x034, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp8m_not_seq   , 0x021, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x035, 0                     , &MmrcExecuteTask                  , lp4_txdll_ovr_seq                , 0x022, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x036, 0                     , &MmrcExecuteTask                  , lp4_rxdll_ovr_seq                , 0x023, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x037, 0                     , &MmrcExecuteTask                  , lp4_rcomp_ovr_seq                , 0x024, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x038, 0                     , &MmrcExecuteTask                  , lp4_txdlycomp_ovr_seq            , 0x025, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x039, S0|S5|FB|RS|EM|A0     , &SetupMaxPI                       , EXTERNAL                         , 0x026, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x040, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp8m_seq       , 0x027, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x041, A0                    , &MmrcExecuteTask                  , MRC_to_Tap_step53p5              , 0x028, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x042, S0|S5|FB|EM|A0        , &MmrcExecuteTask                  , DunitResetComplete               , 0x029, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x044, RS|A0                 , &MmrcExecuteTask                  , modmem_init_lpddrgrp0_seq        , 0x02A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x045, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp10m_seq      , 0x02B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x013, S0|S5|FB              , &wiogrp6                          , EXTERNAL                         , 0x02C, ChNone  ,   P_SIL,   F_ALL,   C_ALL,             T_ALL},
  { 0x046, RS                    , &Channel10Only                    , EXTERNAL                         , 0x02D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x047, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , InitDunit                        , 0x02E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x048, RS                    , &MmrcExecuteTask                  , modmem_init_dramreset_seq_sim    , 0x02F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x049, S5|FB|EM|A0           , &MmrcExecuteTask                  , modmem_init_dramreset_seq        , 0x030, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x050, S5|FB|RS|EM|A0        , &MmrcExecuteTask                  , InitDunitWake                    , 0x031, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x051, S5|FB|RS|EM|A0        , &MmrcExecuteTask                  , PrepareForTraining               , 0x032, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0FB, S0|S3|FB              , &RestoreAlgos                     , EXTERNAL                         , 0x033, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x052, 0                     , &InitializeJedec                  , EXTERNAL                         , 0x034, ChAll   ,   P_SIM,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x053, S5|FB|RS|EM           , &InitializeJedec                  , EXTERNAL                         , 0x035, ChAll   ,   P_ALL,   F_ALL,   C_ALL,  T_LPDDR3|T_DDR3L},
  { 0x054, S5|FB|RS|A0           , &LP4MRProgramming_ODTVREF         , EXTERNAL                         , 0x036, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0FC, S5|RS|A0              , &L_CpgcInit                       , EXTERNAL                         , 0x037, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x055, S5|RS|A0              , &VOCTraining                      , INTERNAL                         , 0x038, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x056, 0                     , &SimMemTest                       , EXTERNAL                         , 0x039, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x057, S0|S5|FB|RS|A0        , &MmrcExecuteTask                  , DIFF_AMP_OVERRIDE                , 0x03A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x058, S5|FB|RS|A0           , &Lp4CBTEntryAllRanks              , EXTERNAL                         , 0x03B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x059, 0                     , &MmrcChangeHiFreq                 , EXTERNAL                         , 0x03C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x053, S5|RS|A0              , &PushOutCommandClockControl       , EXTERNAL                         , 0x03D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x054, S5|RS|A0              , &EarlyCommandTraining             , INTERNAL                         , 0x03E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x055, S5|RS|A0              , &PullBackCommandClockControl      , EXTERNAL                         , 0x03F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x060, 0                     , &MmrcChangeLoFreq                 , EXTERNAL                         , 0x040, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x061, RS                    , &MmrcExecuteTask                  , modmem_init_dramreset_seq_sim    , 0x041, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x062, S5|FB|A0              , &MmrcExecuteTask                  , modmem_init_dramreset_seq        , 0x042, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x063, S5|FB|RS|EM|A0        , &InitializeJedec                  , EXTERNAL                         , 0x043, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x064, S5|FB|RS|A0           , &LP4AllMRProgramming              , EXTERNAL                         , 0x044, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x065, 0                     , &MmrcChangeHiFreq                 , EXTERNAL                         , 0x045, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x066, S5|FB|RS|A0           , &LP4MRProgramming_MPCZQ           , EXTERNAL                         , 0x046, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x067, 0                     , &SimMemTest                       , EXTERNAL                         , 0x047, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x068, S5|RS|A0              , &ReceiveEnable                    , INTERNAL                         , 0x048, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x069, RS                    , &MmrcExecuteTask                  , DQ_DB_REGION_PROGRAM             , 0x049, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x070, S5|RS|A0              , &EarlyMprRead                     , INTERNAL                         , 0x04A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x071, S5|RS|A0              , &FineWriteLeveling                , INTERNAL                         , 0x04B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x072, 0                     , &SimMemTest                       , EXTERNAL                         , 0x04C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x073, S5|RS|A0              , &CoarseWriteLeveling              , INTERNAL                         , 0x04D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x074, RS                    , &SimMemTest                       , EXTERNAL                         , 0x04E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x075, S5|RS|A0              , &ReadTraining                     , INTERNAL                         , 0x04F, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x076, S5|RS|A0              , &WriteTraining                    , INTERNAL                         , 0x050, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x077, S5|RS|A0              , &CommandClockTraining             , INTERNAL                         , 0x051, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x07A, S5|A0                 , &ProgramCKE2xControl              , EXTERNAL                         , 0x052, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x080, S5|RS|A0              , &SearchRmtWrapper                 , EXTERNAL                         , 0x053, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0FA, S0|S5                 , &SaveAlgos                        , EXTERNAL                         , 0x054, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x078, S0|S5|FB|RS           , &PeriodicTraining                 , INTERNAL                         , 0x055, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x079, 0                     , &MmrcExecuteTask                  , HandlePostTraining               , 0x056, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x080, 0                     , &PhyViewTable                     , INTERNAL                         , 0x057, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x081, S5|FB|EM              , &ReadMRTQREF                      , EXTERNAL                         , 0x058, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A1, S5|FB|A0              , &DisplayLpddrInfo                 , EXTERNAL                         , 0x059, ChAll   ,   P_ALL,   F_ALL,   C_ALL, T_LPDDR4|T_LPDDR3},
  { 0x082, 0                     , &MemoryTest                       , INTERNAL                         , 0x05A, ChAllP  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x089, S5|RS|EM|A0           , &CpgcVATest                       , EXTERNAL                         , 0x05B, ChAllP  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x090, S0|S5|FB|RS|A0        , &MmrcExecuteTask                  , DIFF_AMP_RESTORE                 , 0x05C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x084, S5|FB|EM|A0           , &MmrcExecuteTask                  , TrainingDone                     , 0x05D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x085, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , ProgamFinalSettings              , 0x05E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x086, S0                    , &MmrcExecuteTask                  , ProgamFinalSettingsS0            , 0x05F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x083, S0|S5|FB              , &SetScrambler                     , EXTERNAL                         , 0x060, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x086, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp11m_seq      , 0x061, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x087, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp11_seq       , 0x062, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x088, S0|S5|FB|RS|EM|A0     , &MmrcExecuteTask                  , modmem_init_lpddrgrp12m_seq      , 0x063, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x089, 0                     , &CpgcVATest                       , EXTERNAL                         , 0x064, ChAllP  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x08A, S0|FB|S5|EM|A0        , &MmrcExecuteTask                  , CPGCModeComplete                 , 0x065, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x090, S0|S5|FB|EM           , &MmrcExecuteTask                  , PollPunit                        , 0x066, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x091, RS|A0                 , &MmrcExecuteTask                  , SetBGFRun                        , 0x067, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x092, S0|S5|FB|EM|CSE|A0    , &ProgramMemoryMap                 , EXTERNAL                         , 0x068, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x093, S5|FB|RS|EM|CSE|A0    , &MmrcExecuteTask                  , SetMrcDone                       , 0x069, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A0, S0|S5|FB|EM|A0        , &PostMrcDoneSettings              , EXTERNAL                         , 0x06A, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x094, S0                    , &S0_DunitWake                     , EXTERNAL                         , 0x06B, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x095, 0                     , &MmrcExecuteTask                  , EXESDTInit                       , 0x06C, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x081, S0                    , &ReadMRTQREF                      , EXTERNAL                         , 0x06D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x085, S0                    , &MmrcExecuteTask                  , ProgamFinalSettings              , 0x06E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x096, S0|S5|FB|EM|A0        , &MmrcExecuteTask                  , SetMLMC                          , 0x06F, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x096, S0|S5|FB|EM           , &MmrcExecuteTask                  , SetPunitMemDone                  , 0x070, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x097, EM|CSE                , &MemoryTest                       , INTERNAL                         , 0x071, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { TASK_FUNCTION_DESC_DONE },
};

#if CAPSULESTRINGS
char *CapsuleStrings[] = {
                 "DISPLAYMMRCVERSION",  // 0x000
                  "MmrcConvertParams",  // 0x001
                          "InitPunit",  // 0x002
                          "PollPunit",  // 0x003
                      "SetupMRCFreqA",  // 0x004
        "modmem_init_lpddrgrp1xm_seq",  // 0x005
        "modmem_init_lpddrgrp1p5_seq",  // 0x006
         "modmem_init_lpddrgrp2m_seq",  // 0x007
                       "Wake_Chassis",  // 0x008
         "modmem_init_lpddrgrp3m_seq",  // 0x009
          "modmem_init_lpddrgrp3_seq",  // 0x00A
       "modmem_init_lpddrgrp3p75_seq",  // 0x00B
         "modmem_init_lpddrgrp4m_seq",  // 0x00C
          "modmem_ldo_offsetcomp_seq",  // 0x00D
        "modmem_init_lpddrgrp2p5_seq",  // 0x00E
         "modmem_ldo_offsetcomp_poll",  // 0x00F
          "modmem_init_lpddrgrp4_seq",  // 0x010
        "modmem_init_lpddrgrp4p5_seq",  // 0x011
         "modmem_init_lpddrgrp5m_seq",  // 0x012
          "modmem_init_lpddrgrp5_seq",  // 0x013
       "modmem_init_lpddrgrp5p25_seq",  // 0x014
       "modmem_init_lpddrgrp5p5m_seq",  // 0x015
                  "PhyConfigComplete",  // 0x016
                  "MRC_to_Tap_step32",  // 0x017
                          "PollPunit",  // 0x018
        "modmem_init_lpddrgrp5p5_seq",  // 0x019
       "modmem_init_lpddrgrp5p5_seq1",  // 0x01A
          "modmem_init_lpddrgrp6_seq",  // 0x01B
        "modmem_init_lpddrgrp6p5_seq",  // 0x01C
          "modmem_init_lpddrgrp7_seq",  // 0x01D
        "modmem_init_lpddrgrp7p5_seq",  // 0x01E
       "modmem_init_lpddrgrp7p75_seq",  // 0x01F
         "modmem_init_lpddrgrp8m_seq",  // 0x020
     "modmem_init_lpddrgrp8m_not_seq",  // 0x021
                  "lp4_txdll_ovr_seq",  // 0x022
                  "lp4_rxdll_ovr_seq",  // 0x023
                  "lp4_rcomp_ovr_seq",  // 0x024
              "lp4_txdlycomp_ovr_seq",  // 0x025
                         "SetupMaxPI",  // 0x026
         "modmem_init_lpddrgrp8m_seq",  // 0x027
                "MRC_to_Tap_step53p5",  // 0x028
                 "DunitResetComplete",  // 0x029
          "modmem_init_lpddrgrp0_seq",  // 0x02A
        "modmem_init_lpddrgrp10m_seq",  // 0x02B
                            "wiogrp6",  // 0x02C
                      "Channel10Only",  // 0x02D
                          "InitDunit",  // 0x02E
      "modmem_init_dramreset_seq_sim",  // 0x02F
          "modmem_init_dramreset_seq",  // 0x030
                      "InitDunitWake",  // 0x031
                 "PrepareForTraining",  // 0x032
                       "RestoreAlgos",  // 0x033
                    "InitializeJedec",  // 0x034
                    "InitializeJedec",  // 0x035
           "LP4MRProgramming_ODTVREF",  // 0x036
                         "L_CpgcInit",  // 0x037
                        "VOCTraining",  // 0x038
                         "SimMemTest",  // 0x039
                  "DIFF_AMP_OVERRIDE",  // 0x03A
                "Lp4CBTEntryAllRanks",  // 0x03B
                   "MmrcChangeHiFreq",  // 0x03C
         "PushOutCommandClockControl",  // 0x03D
               "EarlyCommandTraining",  // 0x03E
        "PullBackCommandClockControl",  // 0x03F
                   "MmrcChangeLoFreq",  // 0x040
      "modmem_init_dramreset_seq_sim",  // 0x041
          "modmem_init_dramreset_seq",  // 0x042
                    "InitializeJedec",  // 0x043
                "LP4AllMRProgramming",  // 0x044
                   "MmrcChangeHiFreq",  // 0x045
             "LP4MRProgramming_MPCZQ",  // 0x046
                         "SimMemTest",  // 0x047
                      "ReceiveEnable",  // 0x048
               "DQ_DB_REGION_PROGRAM",  // 0x049
                       "EarlyMprRead",  // 0x04A
                  "FineWriteLeveling",  // 0x04B
                         "SimMemTest",  // 0x04C
                "CoarseWriteLeveling",  // 0x04D
                         "SimMemTest",  // 0x04E
                       "ReadTraining",  // 0x04F
                      "WriteTraining",  // 0x050
               "CommandClockTraining",  // 0x051
                "ProgramCKE2xControl",  // 0x052
                   "SearchRmtWrapper",  // 0x053
                          "SaveAlgos",  // 0x054
                   "PeriodicTraining",  // 0x055
                 "HandlePostTraining",  // 0x056
                       "PhyViewTable",  // 0x057
                        "ReadMRTQREF",  // 0x058
                   "DisplayLpddrInfo",  // 0x059
                         "MemoryTest",  // 0x05A
                         "CpgcVATest",  // 0x05B
                   "DIFF_AMP_RESTORE",  // 0x05C
                       "TrainingDone",  // 0x05D
                "ProgamFinalSettings",  // 0x05E
              "ProgamFinalSettingsS0",  // 0x05F
                       "SetScrambler",  // 0x060
        "modmem_init_lpddrgrp11m_seq",  // 0x061
         "modmem_init_lpddrgrp11_seq",  // 0x062
        "modmem_init_lpddrgrp12m_seq",  // 0x063
                         "CpgcVATest",  // 0x064
                   "CPGCModeComplete",  // 0x065
                          "PollPunit",  // 0x066
                          "SetBGFRun",  // 0x067
                   "ProgramMemoryMap",  // 0x068
                         "SetMrcDone",  // 0x069
                "PostMrcDoneSettings",  // 0x06A
                       "S0_DunitWake",  // 0x06B
                         "EXESDTInit",  // 0x06C
                        "ReadMRTQREF",  // 0x06D
                "ProgamFinalSettings",  // 0x06E
                            "SetMLMC",  // 0x06F
                    "SetPunitMemDone",  // 0x070
                         "MemoryTest",  // 0x071
                               "TEST",  // 0x072
                 "CPGC_ONE_TIME_INIT",  // 0x073
                        "SET_REF2XPH",  // 0x074
                     "CPGC_SETUP_ERT",  // 0x075
                      "CPGC_EXIT_ERT",  // 0x076
                    "CPGC_RUN_DIRECT",  // 0x077
                      "SEND_DRAM_CMD",  // 0x078
                  "CPGC_CHECK_ERRORS",  // 0x079
                   "CPGC_SETUP_DPAT0",  // 0x07A
                      "CPGC_RUN_TEST",  // 0x07B
                        "CPGC_ENABLE",  // 0x07C
                   "CPGC_RUN_TEST_OE",  // 0x07D
            "CPGC_RESETUP_WRITE_ONLY",  // 0x07E
             "CPGC_RESETUP_READ_ONLY",  // 0x07F
            "CPGC_RESETUP_WRITE_READ",  // 0x080
              "FINEWRITELEVEL_ENTRYa",  // 0x081
                       "CPGC_DISABLE",  // 0x082
                          "WRLVLMODE",  // 0x083
                      "CPGC_SETUP_VA",  // 0x084
                         "CPGC_LOOPS",  // 0x085
                  "ENTER_CA_TRAINING",  // 0x086
                 "ENTER_CA_TRAININGa",  // 0x087
                          "DRIVE_CKE",  // 0x088
                     "CPGC_STOP_TEST",  // 0x089
                            "DQCALRD",  // 0x08A
                "ENABLE_CKE_OVERRIDE",  // 0x08B
                   "EXIT_CA_TRAINING",  // 0x08C
                  "EXIT_CA_TRAININGa",  // 0x08D
                  "CPGC_CA_VREF_EXIT",  // 0x08E
                       "PRECHARGEALL",  // 0x08F
                   "CPGC_TARGET_BANK",  // 0x090
                        "CPGC_FIXVAR",  // 0x091
                 "CPGC_FIXVAR_REVERT",  // 0x092
                           "CPGC_MRS",  // 0x093
                  "CPGC_CA_TRAIN_DIS",  // 0x094
                 "CPGC_CA_TRAIN_EXIT",  // 0x095
                           "CPGC_RUN",  // 0x096
                         "CPGC_CADB1",  // 0x097
                     "CPGC_CADB1_DIS",  // 0x098
                  "CPGC_DESELECT_DIS",  // 0x099
                   "CPGC_DESELECT_EN",  // 0x09A
                    "CPGC_CADB1_BUFA",  // 0x09B
                    "CPGC_CADB1_BUFB",  // 0x09C
                   "CPGC_CWL_PATTERN",  // 0x09D
                    "LP4_FREQ_SWITCH",  // 0x09E
                         "RCVEN_Copy",  // 0x09F
                      "CPGC_EXIT_MRS",  // 0x0A0
                "RMT_CLEAR_REGISTERS",  // 0x0A1
              "RMT_GET_CMD_AND_VALUE",  // 0x0A2
                   "ConnectPmiToCpgc",  // 0x0A3
                     "CPGC_SETUP_LVL",  // 0x0A4
                  "CPGC_MPR_TRAINING",  // 0x0A5
        "CPGC_RUNTEST_PARALLEL_CLEAR",  // 0x0A6
        "CPGC_RUNTEST_PARALLEL_CHECK",  // 0x0A7
                     "CPGC_CADB_MODE",  // 0x0A8
               "CPGC_RESETUP_TRAFFIC",  // 0x0A9
                     "CPGC_DPAT_MODE",  // 0x0AA
                      "CPGC_LDO_CADB",  // 0x0AB
                      "CPGC_LDO_DPAT",  // 0x0AC
                 "CPGC_LDO_CADB_LFSR",  // 0x0AD
                 "CPGC_LDO_DPAT_LFSR",  // 0x0AE
                    "CPGC_RUN_TEST_L",  // 0x0AF
            "PERIODIC_TRAINING_START",  // 0x0B0
             "PERIODIC_TRAINING_READ",  // 0x0B1
          "PERIODIC_TRAINING_MNT_DIS",  // 0x0B2
               "PERIODIC_TRAINING_EN",  // 0x0B3
                        "RCVEN_ENTRY",  // 0x0B4
                         "RCVEN_EXIT",  // 0x0B5
                          "CPGC_INIT",  // 0x0B6
     "CPGC_UNI_LFSR_VICTIM_AGGRESSOR",  // 0x0B7
         "CPGC_SETUP_VICTIM_AGGRESOR",  // 0x0B8
                "CPGC_SETUP_ECC_INIT",  // 0x0B9
        "CPGC_SETUP_MEMINIT_AND_TEST",  // 0x0BA
                "CPGC_SETUP_2D_SWEEP",  // 0x0BB
            "CPGC_SETUP_MPR_TRAINING",  // 0x0BC
                       "CPGC_RUNTEST",  // 0x0BD
                  "CPGC_CLEAR_ERRORS",  // 0x0BE
               "RECEIVE_ENABLE_EXITx",  // 0x0BF
               "FINEWRITELEVEL_ENTRY",  // 0x0C0
                "FINEWRITELEVEL_EXIT",  // 0x0C1
                        "FORCEODT_ON",  // 0x0C2
                       "FORCEODT_OFF",  // 0x0C3
                       "FORCEODT_REL",  // 0x0C4
             "COARSEWRITELEVEL_ENTRY",  // 0x0C5
              "COARSEWRITELEVEL_EXIT",  // 0x0C6
          "EARLY_READ_TRAINING_ENTRY",  // 0x0C7
           "EARLY_READ_TRAINING_EXIT",  // 0x0C8
                    "ENABLE_MPR_MODE",  // 0x0C9
                   "DISABLE_MPR_MODE",  // 0x0CA
                 "READTRAINING_ENTRY",  // 0x0CB
                  "READTRAINING_EXIT",  // 0x0CC
                "WRITETRAINING_ENTRY",  // 0x0CD
                 "WRITETRAINING_EXIT",  // 0x0CE
         "COMMANDCLOCKTRAINING_ENTRY",  // 0x0CF
          "COMMANDCLOCKTRAINING_EXIT",  // 0x0D0
                    "CPGCSETUPFORCMD",  // 0x0D1
                      "CPGCSETUPCADB",  // 0x0D2
                         "RESETDRAMS",  // 0x0D3
              "CPGC_RUNTEST_PARALLEL",  // 0x0D4
            "CPGC_CHECK_ERR_PARALLEL",  // 0x0D5
                      "BREAKPOINTMRC",  // 0x0D6
              "CPGC_PREPARE_PARALLEL",  // 0x0D7
                  "WRITE_SCRATCHPADS",  // 0x0D8
                   "READ_SCRATCHPADS",  // 0x0D9
                     "LDO_TRAIN_INIT",  // 0x0DA
                    "LDO_TRAIN_INITx",  // 0x0DB
                       "SET_CA_SCALE",  // 0x0DC
                       "SET_DQ_SCALE",  // 0x0DD
                     "LDO_TRAIN_LOOP",  // 0x0DE
                 "VOC_TRAINING_ENTRY",  // 0x0DF
                 "VOC_GET_LDO_ENABLE",  // 0x0E0
                      "VOC_PHY_ENTRY",  // 0x0E1
             "VOC_COMP_VREF_AND_INIT",  // 0x0E2
            "VOC_GET_RCOMP_PUP_VALUE",  // 0x0E3
            "VOC_GET_RCOMP_PDN_VALUE",  // 0x0E4
         "VOC_SET_ODT_RCOMP_OVERRIDE",  // 0x0E5
                  "VOC_ENABLE_WLMODE",  // 0x0E6
                 "VOC_DISABLE_WLMODE",  // 0x0E7
                  "VOC_TRAINING_EXIT",  // 0x0E8
               "CPGC_GET_TEST_RESULT",  // 0x0E9
                "CPGC_SET_CHUNK_MASK",  // 0x0EA
                "CPGC_STOP_CLEAR_ERR",  // 0x0EB
                    "CPGC_START_TEST",  // 0x0EC
                  "CheckForWarmReset",  // 0x0ED
                                "xyz",  // 0x0EE
                         "InitDunitx",  // 0x0EF
                "InitDunitWakeRemove",  // 0x0F0
               "DunitFreqChangePart1",  // 0x0F1
                      "ChangePHYFreq",  // 0x0F2
               "DunitFreqChangePart3",  // 0x0F3
                    "MmapBeforeTrain",  // 0x0F4
                       "SetICBitDone",  // 0x0F5
               "ProgamFinalSettingsx",  // 0x0F6
                          "ReadFuses",  // 0x0F7
                   "EnableScrambling",  // 0x0F8
                   "SetMrcDoneRemove",  // 0x0F9
                        "SetMrcDonex",  // 0x0FA
                     "ReadBarAddress",  // 0x0FB
                 "WriteMchBarAddress",  // 0x0FC
                    "WriteBarAddress",  // 0x0FD
                      "WritePCIEXBAR",  // 0x0FE
               "SetAunitSliceChannel",  // 0x0FF
              "LockAunitSliceChannel",  // 0x100
                    "InitDunitWakeS0",  // 0x101
                     "MRC_to_Tap_CWL",  // 0x102
                       "S0_fixes_GET",  // 0x103
                       "S0_fixes_SET",  // 0x104
                 "InitDunitWakeS0pt1",  // 0x105
                      "ToggleBGF_RUN",  // 0x106
   "modmem_init_lpddrgrp3_seq_from_7",  // 0x107
                               "xxxx",  // 0x108
            "modmem_s0ix_entry_m_seq",  // 0x109
         "modmem_lp4_freq_switch_seq",  // 0x10A
     "modmem_ldo_offsetcomp_poll_seq",  // 0x10B
         "modmem_init_lpddrgrp0m_seq",  // 0x10C
                     "maxpi_dll_init",  // 0x10D
         "maxpi_override_coarse_init",  // 0x10E
                    "maxpi_set_codes",  // 0x10F
                    "maxpi_get_codes",  // 0x110
        "maxpi_override_coarse_final",  // 0x111
       "modmem_init_progcmdckctl_seq",  // 0x112
                   "maxpi_read_value",  // 0x113
                  "maxpi_write_value",  // 0x114
};
#endif //CAPSULESTRINGS

CONST SUBTASK_INDEX_OFFSET SubtaskOffsetIndex[MAX_SUBTASKS + 1] = {
  { 0x02E, InitDunit            },
};

CONST UINT8 InitData[] = {
  // FLAGS            CondVar                                    ADDRESS                                                BOXTYPE                     MASK                       ACTION/dPFCT               DELAY      #Cond  Cond                                                              Val
  //
  // InitPunit
  //
  xxxxx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR),                    
  ASSIGNDONE,
  //
  // PollPunit
  //
  xxxMx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxMx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00001000), MASK1(0x80)              , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp1xm_seq
  //
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x4),                                                         // // Enable override selects. , // Gated & Ungated Power Mux: vnn = ON, vcca = OFF
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG1_DPIC_REG)                       ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x20),                                                        // // Assert dfx reset
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x20),                                                        // // Enable Isolation from LVG,  // Gated Power Mux: vnn = ON, vcca = OFF;  Ungated Power Mux: vnn = ON, vcca = OFF
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x1),                                                        
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x2),                                                        
  xxxxx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000010)                           , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                         // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = ON, vcca = OFF
  xxxMx1xx                                      ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x1),                                                         // // Enable Isolation from LVUG
  xxxMx1xx                                      ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x1),                                                         // // NEEDED FOR SIM
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00001000), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                         // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = OFF
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00001000), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x2),                                                         // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx1xx                                      ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                         // // Disable Isolation from LVUG
  xxxMx1xx                                      ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                         // // NEEDED FOR SIM
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00001000), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x4),                                                         // // Switch the power mode config within PM controller, so that PM controller internally points to vcca = ON,  // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxxx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000100)                           , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0xF),                                                         // // stagger enable VCCA
  xxxxx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000100)                           , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0xFF),                                                        // // Gated Power Mux: vnn = OFF, vcca = ON;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                         // // Disable Isolation
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG1_DPIC_REG)                       ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                         // // Deassert dfx reset
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                         // // Remove cfg overrides and let PM controller control the power gates, // Gated Power Mux: vnn = OFF, vcca = ON;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                        VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp1p5_seq
  //
  xxxxx1xx                                      ,                VAL1(PTCTL0_DPLVUG_REG)                              ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_PTCTL0),                                           // static_0 : //LP4 training registers, static_0 : //LP4 training registers, static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxMx1xx                                      ,                VAL1(PTCTL0_DPLVUG_REG)                              ,  BB(DPLVUG,     _00000001), MASK1(0x38)              , AP(SET,       __F__),                   2,   F(F_1066|F_1600|F_2133|F_2933|F_3200),                            VAL1(0x0),                                                        F(F_2667),                                                        VAL1(0x30),                                                        // static_0 : //LP4 training registers
  xxxMx1xx                                      ,                VAL1(PTCTL0_DPLVUG_REG)                              ,  BB(DPLVUG,     _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT12_DPLVUG_REG)                           ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT34_DPLVUG_REG)                           ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT56_DPLVUG_REG)                           ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT78_DPLVUG_REG)                           ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT910_DPLVUG_REG)                          ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT1112_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT1314_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT1516_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT1718_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT1920_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT2122_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT2324_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT2526_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT2728_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT2930_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT3132_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT3334_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT3536_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT3738_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT3940_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT4142_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT4344_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT4546_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT4748_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT4950_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT5152_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT5354_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT5556_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT5758_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT5960_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT6162_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT6364_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT6566_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT6768_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                      ,                VAL1(PTROCNT6970_DPLVUG_REG)                         ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxMx1xx                                      ,                VAL1(TXFB_LDO_REG)                                   ,  BB(LDO,        _00000111), MASK3(0x7E00B)           , AP(SET,       _____),                                                                                          VAL3(0x64003),                                                     // modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXPANIC_LDO_REG)                                ,  BB(LDO,        _00001011), MASK3(0x4E03F)           , AP(SET,       _____),                                                                                          VAL3(0x4602D),                                                     // modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXFFDQ0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001001), MASK2(0x380F)            , AP(SET,       _____),                                                                                          VAL2(0x200A),                                                      // modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXFFDQ1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001001), MASK2(0x380F)            , AP(SET,       _____),                                                                                          VAL2(0x200A),                                                      // modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXFFCA0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001001), MASK2(0x380F)            , AP(SET,       _____),                                                                                          VAL2(0x200A),                                                      // modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXFFCA1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001001), MASK2(0x380F)            , AP(SET,       _____),                                                                                          VAL2(0x200A),                                                      // modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXPANICCOMP_LDO_REG)                            ,  BB(LDO,        _00001111), MASK4(0x3F03FFF)         , AP(SET,       _____),                                                                                          VAL4(0xF00F22),                                                    // modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq, modmem_ldoen_seq
  xxxMx1xx                                      ,                VAL1(TXSAOFFSET_LDO_REG)                             ,  BB(LDO,        _00000100), MASK1(0xFC)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // modmem_ldoen_seq
  xxxxx2xx                                      ,                VAL2(PTDATAMUXSEL_DQCCC_REG)                         ,  BB(DQCCC,      _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0x0),                                                         // static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp2m_seq
  //
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x10),                                                        // static_DIGCTL_m : 
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       __F__),                   9,   F(F_800),                                                         VAL1(0x0),                                                        F(F_1066),                                                        VAL1(0x1),                                                        F(F_1333),                                                        VAL1(0x2),                                                        F(F_1600),                                                        VAL1(0x3),                                                        F(F_1866),                                                        VAL1(0x9),                                                        F(F_2133),                                                        VAL1(0x4),                                                        F(F_2667),                                                        VAL1(0x6),                                                        F(F_2933),                                                        VAL1(0xA),                                                        F(F_3200),                                                        VAL1(0x7),                                                         // static_DIGCTL_m : 
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00000110), MASK2(0xFF60)            , AP(SET,       _____),                                                                                          VAL2(0x200),                                                       // static_DIGCTL_m : , static_DIGCTL_m : 
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00000010), MASK1(0x8)               , AP(SET,       __F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL1(0x0),                                                        FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL1(0x8),                                                        FT(F_1066|F_1600,T_LPDDR4),                                       VAL1(0x0),                                                        FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL1(0x8),                                                         // static_DIGCTL_m : 
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00000010), MASK1(0x4)               , AP(SET,       _____),                                                                                          VAL1(0x4),                                                         // static_DIGCTL_m : 
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00000010), MASK1(0x2)               , AP(SET,       __F_T),                   3,   FT(F_800|F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                   VAL1(0x2),                                                        FT(F_1066|F_1600,T_LPDDR4),                                       VAL1(0x2),                                                        FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL1(0x2),                                                         // static_DIGCTL_m : 
  xxxMx1xx                                      ,                VAL1(DIGCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00000001), MASK1(0x3C)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x2C),                                                        // static_DIGCTL_m : , static_DIGCTL_m : , static_DIGCTL_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx2xx                                      ,                VAL2(LPMODECTL0_DQCCC_REG)                           ,  BB(DQCCC,      _00001111), MASK4(0x77777707)        , AP(SET,       _____),                                                                                          VAL4(0x1000001),                                                  
  xxxMx2xx                                      ,                VAL2(LPMODECTL1_DQCCC_REG)                           ,  BB(DQCCC,      _00001101), MASK3(0x777FFF)          , AP(SET,       _____),                                                                                          VAL3(0x110003),                                                   
  xxxxx1xx                                      ,                VAL1(PLLDIVRATIOS_0_ADPLL_REG)                       ,  BB(ADPLL,      _00001100)                           , AP(SET,       __F_T),                   10,   FT(F_1866,T_LPDDR3),                                              VAL2(0x1C07),                                                     FT(F_1600,T_LPDDR3),                                              VAL2(0x1806),                                                     FT(F_1333,T_LPDDR3),                                              VAL2(0x2805),                                                     FT(F_1066,T_LPDDR3),                                              VAL2(0x2004),                                                     FT(F_800,T_LPDDR3),                                               VAL2(0x1803),                                                     FT(F_1066,T_LPDDR4),                                              VAL2(0x2002),                                                     FT(F_1600,T_LPDDR4),                                              VAL2(0x1803),                                                     FT(F_2133,T_LPDDR4),                                              VAL2(0x2004),                                                     FT(F_2667,T_LPDDR4),                                              VAL2(0x2805),                                                     FT(F_3200,T_LPDDR4),                                              VAL2(0x3006),                                                      // modmem_fbdiv_prog_seq, modmem_fbdiv_prog_seq
  xxxMx1xx                                      ,                VAL1(PLLDIVRATIOS_0_ADPLL_REG)                       ,  BB(ADPLL,      _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CONFIG_3_ADPLL_REG)                             ,  BB(ADPLL,      _00001111), MASK4(0xFFFFFFFE)        , AP(SET,       _____),                                                                                          VAL4(0x12),                                                        // modmem_fbdiv_prog_seq S9->E
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx1xx                                      ,                VAL1(PLLDIVCTL_DPIC_REG)                             ,  BB(DPIC,       _00001001), MASK2(0x131F)            , AP(SET,       _____),                                                                                          VAL2(0x1000),                                                      // static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxMx1xx                                      ,                VAL1(SPIDCLKCTL0_DPIC_REG)                           ,  BB(DPIC,       _00000110), MASK2(0x1FFF)            , AP(SET,       _____),                                                                                          VAL2(0x138A),                                                      // static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxMx1xx                                      ,                VAL1(SPIDCLKCTL0_DPIC_REG)                           ,  BB(DPIC,       _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   11,   FT(F_800,T_LPDDR3),                                               VAL1(0xC),                                                        FT(F_1066,T_LPDDR3),                                              VAL1(0x10),                                                       FT(F_1333,T_LPDDR3),                                              VAL1(0x14),                                                       FT(F_1600,T_LPDDR3),                                              VAL1(0x18),                                                       FT(F_1866,T_LPDDR3),                                              VAL1(0x1C),                                                       FT(F_1066,T_LPDDR4),                                              VAL1(0x8),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0xC),                                                        FT(F_2133,T_LPDDR4),                                              VAL1(0x10),                                                       FT(F_2667,T_LPDDR4),                                              VAL1(0x14),                                                       FT(F_2933,T_LPDDR4),                                              VAL1(0x16),                                                       FT(F_3200,T_LPDDR4),                                              VAL1(0x18),                                                        // static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00001100), MASK2(0x1F1)             , AP(SET,       _____),                                                                                          VAL2(0x51),                                                        // static_PLLCTL_m : , static_PLLCTL_m : 
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000010), MASK1(0x30)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066|F_1333,T_LPDDR3),                                 VAL1(0x10),                                                       FT(F_1600|F_1866,T_LPDDR3),                                       VAL1(0x0),                                                        FT(F_1066,T_LPDDR4),                                              VAL1(0x10),                                                       FT(F_1600|F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                  VAL1(0x0),                                                         // static_PLLCTL_m : 
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000011), MASK2(0x10D)             , AP(SET,       _____),                                                                                          VAL2(0x109),                                                       // static_PLLCTL_m : , static_PLLCTL_m : , static_PLLCTL_m : , static_PLLCTL_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  ASSIGNDONE,
  //
  // Wake_Chassis
  //
  xxxxx2xx                                      ,                VAL2(WAKE_CHASIS_DQCCC_REG)                          ,  BB(DQCCC,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x1),                                                         // Was the DRAM in self refresh?
  xxxxx2xx                                      ,                VAL2(WAKE_CHASIS_DQCCC_REG)                          ,  BB(DQCCC,      _00001111)                           , AP(POLL,      _____),                                                                                          VAL4(0x1),                                                         // Was the DRAM in self refresh?
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3m_seq
  //
  xxxMx1xx                                      ,                VAL1(CCCCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00001111), MASK4(0x11FFF07)         , AP(SET,       _____),                                                                                          VAL4(0x1FFF03),                                                    // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(WRDQCTL_DQCCC_REG)                              ,  BB(DQCCC,      _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x33),                                                        // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00001000), MASK1(0xFC)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00001000), MASK1(0x3)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x3),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                        // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x8)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x8),                                                         // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000110), MASK2(0x3FC)             , AP(SET,       _____),                                                                                          VAL2(0x354),                                                       // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x3)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000001)                           , AP(SET,       D_F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL2(DYN_DQCCC_WRDQSCTL),                                         FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL2(DYN_DQCCC_WRDQSCTL_1),                                       FT(F_1066|F_1600,T_LPDDR4),                                       VAL2(DYN_DQCCC_WRDQSCTL_2),                                       FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL2(DYN_DQCCC_WRDQSCTL_3),                                        // static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(RDVLDCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(RDVLDCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x70)              , AP(SET,       __F_T),                   3,   FT(F_800|F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                   VAL1(0x0),                                                        FT(F_1066|F_1600|F_2133|F_2933|F_3200,T_LPDDR4),                  VAL1(0x0),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x60),                                                        // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(RDVLDCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x7)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS_m : S4->0
  xxxxx1xx                                      ,                VAL1(RDVLDCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000001)                           , AP(SET,       D_F_T),                   7,   FT(F_800,T_LPDDR3),                                               VAL2(DYN_DQCCC_RDVLDCTL),                                         FT(F_1066,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_1),                                       FT(F_1333,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_2),                                       FT(F_1600,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_3),                                       FT(F_1866,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_4),                                       FT(F_1066|F_1600|F_2133|F_2933|F_3200,T_LPDDR4),                  VAL2(DYN_DQCCC_RDVLDCTL_5),                                       FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RDVLDCTL_6),                                        // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(RK2RKCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000010), MASK1(0x7)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x7),                                                         // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(RK2RKCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0xC2)              , AP(SET,       ___CT),                   2,   CT(C_POR,T_LPDDR4),                                               VAL1(0x0),                                                        CT(C_POR,T_LPDDR3),                                               VAL1(0x0),                                                         // static_DIGREGS_m :  Need to be revisted in BXT-B0, static_DIGREGS_m :  Need to be revisted in BXT-B0, static_DIGREGS_m :  Need to be revisted in BXT-B0
  xxxMx1xx                                      ,                VAL1(RK2RKCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(RK2RKCTL0_DQCCC_REG)                            ,  BB(DQCCC,      _00001100), MASK2(0xFFE0)            , AP(SET,       _____),                                                                                          VAL2(0xE0),                                                        // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(RK2RKCTL0_DQCCC_REG)                            ,  BB(DQCCC,      _00000110)                           , AP(SET,       D_F_T),                   3,   FT(F_800|F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                   VAL2(DYN_DQCCC_RK2RKCTL0),                                        FT(F_1066|F_1600,T_LPDDR4),                                       VAL2(DYN_DQCCC_RK2RKCTL0_1),                                      FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL2(DYN_DQCCC_RK2RKCTL0_2),                                       // static_DIGREGS_m : , static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(RK2RKCTL0_DQCCC_REG)                            ,  BB(DQCCC,      _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xF0),                                                        // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(LDOCTL0_DQCCC_REG)                              ,  BB(DQCCC,      _00001111), MASK4(0xFFFFFF0)         , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL4(0x0),                                                        T(T_LPDDR4),                                                      VAL4(0x1133110),                                                   // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : 
  xxxMx1xx                                      ,                VAL1(LDOCTL0_DQCCC_REG)                              ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(LDOCTL1_DQCCC_REG)                              ,  BB(DQCCC,      _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS_m : , static_DIGREGS_m : 
  xxxxx2xx                                      ,                VAL2(RXDLLRDCMDCTL0_DQCCC_REG)                       ,  BB(DQCCC,      _00000110)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXDLLRDCMDCTL0),                                    // static_DIGREGS_m : , static_DIGREGS_m : 
  xxxxx2xx                                      ,                VAL2(RXDLLRDCMDCTL0_DQCCC_REG)                       ,  BB(DQCCC,      _00000011)                           , AP(SET,       D_F_T),                   5,   FT(F_800,T_LPDDR3),                                               VAL2(DYN_DQCCC_RXDLLRDCMDCTL0_1),                                 FT(F_1066,T_LPDDR3),                                              VAL2(DYN_DQCCC_RXDLLRDCMDCTL0_2),                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL2(DYN_DQCCC_RXDLLRDCMDCTL0_3),                                 FT(F_1066|F_1600,T_LPDDR4),                                       VAL2(DYN_DQCCC_RXDLLRDCMDCTL0_4),                                 FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL2(DYN_DQCCC_RXDLLRDCMDCTL0_5),                                  // static_DIGREGS_m : 
  xxxMx2xx                                      ,                VAL2(RXDLLRDCMDCTL0_DQCCC_REG)                       ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   8,   FT(F_800,T_LPDDR3),                                               VAL1(0x5),                                                        FT(F_1066|F_1333,T_LPDDR3),                                       VAL1(0x6),                                                        FT(F_1600|F_1866,T_LPDDR3),                                       VAL1(0x7),                                                        FT(F_1066,T_LPDDR4),                                              VAL1(0x1),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0x20),                                                       FT(F_2133,T_LPDDR4),                                              VAL1(0x3),                                                        FT(F_2667|F_2933,T_LPDDR4),                                       VAL1(0x4),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x5),                                                         // static_DIGREGS_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3_seq
  //
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x3F)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x30),                                                        // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       __F_T),                   9,   FT(F_800,T_LPDDR3),                                               VAL1(0x71),                                                       FT(F_1066,T_LPDDR3),                                              VAL1(0x57),                                                       FT(F_1333,T_LPDDR3),                                              VAL1(0x47),                                                       FT(F_1600,T_LPDDR3),                                              VAL1(0x3D),                                                       FT(F_1866,T_LPDDR3),                                              VAL1(0x36),                                                       FT(F_1600,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_2133,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x5),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       __F__),                   5,   F(F_800),                                                         VAL1(0x6D),                                                       F(F_1066),                                                        VAL1(0x53),                                                       F(F_1333),                                                        VAL1(0x43),                                                       F(F_1600),                                                        VAL1(0x39),                                                       F(F_1866),                                                        VAL1(0x31),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                                                                                         VAL1(0x30),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       __F_T),                   9,   FT(F_800,T_LPDDR3),                                               VAL1(0x5),                                                        FT(F_1066,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1333,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1600,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1866,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_2133,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x5),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       __F__),                   5,   F(F_800),                                                         VAL1(0x5),                                                        F(F_1066),                                                        VAL1(0x5),                                                        F(F_1333),                                                        VAL1(0x5),                                                        F(F_1600),                                                        VAL1(0x5),                                                        F(F_1866),                                                        VAL1(0x5),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001000), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0xE),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQ_REG)                         ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000100)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQ_REG)                         ,  BB(DQ,         _00000100)                           , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                                                                                         VAL1(0x30),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0xE),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001000), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0xF),                                                        T(T_LPDDR4),                                                      VAL1(0x3),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQ_REG)                         ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000100)                           , AP(SET,       __F_T),                   9,   FT(F_800,T_LPDDR3),                                               VAL1(0x0),                                                        FT(F_1066,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1333,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1600,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1866,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0x45),                                                       FT(F_2133,T_LPDDR4),                                              VAL1(0x2C),                                                       FT(F_2667,T_LPDDR4),                                              VAL1(0x24),                                                       FT(F_3200,T_LPDDR4),                                              VAL1(0x1F),                                                        // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQ_REG)                         ,  BB(DQ,         _00000100)                           , AP(SET,       __F__),                   5,   F(F_800),                                                         VAL1(0x6D),                                                       F(F_1066),                                                        VAL1(0x53),                                                       F(F_1333),                                                        VAL1(0x43),                                                       F(F_1600),                                                        VAL1(0x39),                                                       F(F_1866),                                                        VAL1(0x31),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0xF),                                                        T(T_LPDDR4),                                                      VAL1(0x3),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       __F_T),                   9,   FT(F_800,T_LPDDR3),                                               VAL1(0x0),                                                        FT(F_1066,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1333,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1600,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1866,T_LPDDR3),                                              VAL1(0x0),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0x45),                                                       FT(F_2133,T_LPDDR4),                                              VAL1(0x2C),                                                       FT(F_2667,T_LPDDR4),                                              VAL1(0x24),                                                       FT(F_3200,T_LPDDR4),                                              VAL1(0x1F),                                                        // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP1CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       __F__),                   5,   F(F_800),                                                         VAL1(0x6D),                                                       F(F_1066),                                                        VAL1(0x53),                                                       F(F_1333),                                                        VAL1(0x43),                                                       F(F_1600),                                                        VAL1(0x45),                                                       F(F_1866),                                                        VAL1(0x31),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x4),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQ_REG)                         ,  BB(DQ,         _00001100), MASK2(0xFFF)             , AP(SET,       _____),                                                                                          VAL2(0x205),                                                       // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x4),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x29),                                                        // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x5),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(WKPUPPDNCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00001100), MASK2(0x7F7F)            , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL2(0x4242),                                                     T(T_LPDDR4),                                                      VAL2(0x202),                                                       // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(WKPUPPDNCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00000011), MASK2(0x7F7F)            , AP(SET,       _____),                                                                                          VAL2(0x4242),                                                      // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : 
  xxxxx1xx                                      ,                VAL1(RXDLLDQSRK1CTL_DQCCC_REG)                       ,  BB(DQCCC,      _00001100)                           , AP(SET,       __F__),                   8,   F(F_800),                                                         VAL2(0x7171),                                                     F(F_1066),                                                        VAL2(0x5757),                                                     F(F_1333),                                                        VAL2(0x4747),                                                     F(F_1600),                                                        VAL2(0x3D3D),                                                     F(F_1866),                                                        VAL2(0x2D2D),                                                     F(F_2133),                                                        VAL2(0x2F2F),                                                     F(F_2667),                                                        VAL2(0x2727),                                                     F(F_3200),                                                        VAL2(0x2323),                                                      // static_SIGGRPS : , static_SIGGRPS : 
  xxxxx1xx                                      ,                VAL1(RXDLLDQSRK0CTL_DQCCC_REG)                       ,  BB(DQCCC,      _00001111)                           , AP(SET,       __F__),                   8,   F(F_800),                                                         VAL4(0x71717171),                                                 F(F_1066),                                                        VAL4(0x57575757),                                                 F(F_1333),                                                        VAL4(0x47474747),                                                 F(F_1600),                                                        VAL4(0x3D3D3D3D),                                                 F(F_1866),                                                        VAL4(0x2D2D2D2D),                                                 F(F_2133),                                                        VAL4(0x2F2F2F2F),                                                 F(F_2667),                                                        VAL4(0x27272727),                                                 F(F_3200),                                                        VAL4(0x23232323),                                                  // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xC)               , AP(SET,       ___C_),                   1,   C(C_POR),                                                         VAL1(0x4),                                                         // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000011), MASK2(0x3C0)             , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL2(0x380),                                                      T(T_LPDDR4),                                                      VAL2(0x80),                                                        // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQ_REG)                         ,  BB(DQ,         _00000011), MASK2(0x3C0)             , AP(SET,       _____),                                                                                          VAL2(0x0),                                                         // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001), MASK1(0x30)              , AP(SET,       ___C_),                   1,   C(C_POR),                                                         VAL1(0x10),                                                        // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0xE),                                                        T(T_LPDDR4),                                                      VAL1(0x2),                                                         // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP6CTL_DQ_REG)                         ,  BB(DQ,         _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_SIGGRPS : 
  xxxMx1xx                                      ,                VAL1(FIFOPTRCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0xF),                                                        T(T_LPDDR4),                                                      VAL1(0xC),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(FIFOPTRCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(FIFOPTRCTL_DQ_REG)                              ,  BB(DQ,         _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(FIFOPTRCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000010), MASK1(0xE0)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL1(0x20),                                                       FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL1(0x0),                                                        FT(F_1066|F_1600,T_LPDDR4),                                       VAL1(0x20),                                                       FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(FIFOPTRCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000011), MASK2(0x1FF0)            , AP(SET,       _____),                                                                                          VAL2(0x100),                                                       // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(FIFOPTRCTL_DQ_REG)                              ,  BB(DQ,         _00000001), MASK1(0xF0)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(FIFOPTRCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RXODTSEGCTL_CC_DQCCC_REG)                       ,  BB(DQCCC,      _00001100), MASK2(0xFF40)            , AP(SET,       _____),                                                                                          VAL2(0x1100),                                                      // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RXODTSEGCTL_CC_DQCCC_REG)                       ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_CC),                                   FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_CC_1),                                 FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_CC_2),                                 FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_CC_3),                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00001100), MASK2(0xFF40)            , AP(SET,       _____),                                                                                          VAL2(0x6100),                                                      // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_DQ),                                   FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_DQ_1),                                 FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_DQ_2),                                 FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTSEGCTL_DQ_3),                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RXODTCTL_CC_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0xF3)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                        // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RXODTCTL_CC_DQCCC_REG)                          ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_CC),                                      FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_CC_1),                                    FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_CC_2),                                    FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_CC_3),                                     // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0xF0)              , AP(SET,       __F_T),                   3,   FT(F_800|F_1066|F_1333|F_1600,T_LPDDR3),                          VAL1(0x10),                                                       FT(F_1866,T_LPDDR3),                                              VAL1(0x30),                                                       FT(F_1066|F_1600|F_2133|F_2667|F_2933|F_3200,T_LPDDR4),           VAL1(0x10),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_DQ),                                      FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_DQ_1),                                    FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_DQ_2),                                    FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_RXODTCTL_DQ_3),                                     // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RCVENCTL_CC_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x8),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RCVENCTL_CC_DQCCC_REG)                          ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_CC),                                      FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_CC_1),                                    FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_CC_2),                                    FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_CC_3),                                     // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RCVENCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x8),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RCVENCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_DQ),                                      FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_DQ_1),                                    FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_DQ_2),                                    FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_RCVENCTL_DQ_3),                                     // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000)                           , AP(SET,       _____),                                                                                          VAL1(0x13),                                                        // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_CC),                                    FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_CC_1),                                  FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_CC_2),                                  FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_CC_3),                                   // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0xF0)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0xC)               , AP(SET,       __F__),                   2,   F(F_800|F_1066|F_1333|F_1600),                                    VAL1(0x0),                                                        F(F_1866|F_2133|F_2400|F_2667|F_3200),                            VAL1(0xC),                                                         // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001100), MASK2(0x3C0)             , AP(SET,       _____),                                                                                          VAL2(0x300),                                                       // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00000111)                           , AP(SET,       D_F_T),                   4,   FT(F_1600,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_DQ),                                    FT(F_2133,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_DQ_1),                                  FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_DQ_2),                                  FT(F_3200,T_LPDDR4),                                              VAL2(DYN_DQCCC_DIFFAMPCTL_DQ_3),                                   // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(AFEMISC1_DQCCC_REG)                             ,  BB(DQCCC,      _00001111), MASK4(0x7777777F)        , AP(SET,       _____),                                                                                          VAL4(0x77771110),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(AFEMISC0_DQCCC_REG)                             ,  BB(DQCCC,      _00001000)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(AFEMISC0_DQCCC_REG)                             ,  BB(DQCCC,      _00000110), MASK2(0xFF0F)            , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL2(0xF),                                                        T(T_LPDDR4),                                                      VAL2(0x5500),                                                      // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(AFEMISC0_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0xFC)              , AP(SET,       _____),                                                                                          VAL1(0xFC),                                                        // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(AFEMISC0_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x3),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLREF2XCTL_DQCCC_REG)                        ,  BB(DQCCC,      _00000110)                           , AP(SET,       __F__),                   9,   F(F_800),                                                         VAL2(0x9D69),                                                     F(F_1066),                                                        VAL2(0x734C),                                                     F(F_1333),                                                        VAL2(0x5E3F),                                                     F(F_1600),                                                        VAL2(0x4D33),                                                     F(F_1866),                                                        VAL2(0x432D),                                                     F(F_2133),                                                        VAL2(0x3B27),                                                     F(F_2667),                                                        VAL2(0x2F1F),                                                     F(F_2933),                                                        VAL2(0x2B1D),                                                     F(F_3200),                                                        VAL2(0x271A),                                                      // static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLREF2XCTL_DQCCC_REG)                        ,  BB(DQCCC,      _00000001)                           , AP(SET,       __F__),                   8,   F(F_800),                                                         VAL1(0x34),                                                       F(F_1066),                                                        VAL1(0x25),                                                       F(F_1333),                                                        VAL1(0x1F),                                                       F(F_1600),                                                        VAL1(0x19),                                                       F(F_1866),                                                        VAL1(0x17),                                                       F(F_2133),                                                        VAL1(0x14),                                                       F(F_2667|F_2933),                                                 VAL1(0xF),                                                        F(F_3200),                                                        VAL1(0xD),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(RXBL8PBDCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100), MASK1(0x40)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x40),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x8)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x4)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x4),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDRK0CTL1_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1F)              , AP(SET,       _____),                                                                                          VAL1(0x1F),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDRK0CTL0_DQCCC_REG)                         ,  BB(DQCCC,      _00000101), MASK2(0x1F1F)            , AP(SET,       _____),                                                                                          VAL2(0x1F1F),                                                      // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDBLCTL1_DQCCC_REG)                          ,  BB(DQCCC,      _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                          VAL4(0x1F1F1F1F),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDBLCTL0_DQCCC_REG)                          ,  BB(DQCCC,      _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                          VAL4(0x1F1F1F1F),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(OFFSETCNCLCTRL1_DQCCC_REG)                      ,  BB(DQCCC,      _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x0),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(OFFSETCNCLCTRL0_DQCCC_REG)                      ,  BB(DQCCC,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(CTLECTL2_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(CTLECTL1_DQCCC_REG)                             ,  BB(DQCCC,      _00001111), MASK4(0x7FFFFFFF)        , AP(SET,       _____),                                                                                          VAL4(0x412120A0),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(CTLECTL0_DQCCC_REG)                             ,  BB(DQCCC,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TCOCTL_DQCC_DQCCC_REG)                          ,  BB(DQCCC,      _00001111), MASK4(0x9F1F9F1F)        , AP(SET,       _____),                                                                                          VAL4(0x9F1F9F1F),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TCOCTL_DQ_DQCCC_REG)                            ,  BB(DQCCC,      _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                          VAL4(0x3F1F1F1F),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TCOCTL_CC_DQCCC_REG)                            ,  BB(DQCCC,      _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                          VAL4(0x3F1F1F1F),                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(DBREGIONCTL1_DPLVUG_REG)                        ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x680C1926),                                                  // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : 
  xxxxx1xx                                      ,                VAL1(DBREGIONCTL2_DPLVUG_REG)                        ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x33404D5A),                                                  // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : 
  xxxxx1xx                                      ,                VAL1(DBREGIONCTL3_DPLVUG_REG)                        ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xF50A5505),                                                  // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : 
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100), MASK1(0xC0)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3p75_seq
  //
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(POLL,      _____),                                                                                          VAL1(0x2),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp4m_seq
  //
  xxxMx1xx                                      ,                VAL1(RXDLLCTL_DQBLDM_DQCCC_REG)                      ,  BB(DQCCC,      _00001100), MASK2(0x1F35)            , AP(SET,       _____),                                                                                          VAL2(0x1325),                                                      // static_RXEN_m : S13->14, static_RXEN_m : , static_RXEN_m : S0->1, static_RXEN_m : , static_RXEN_m : 
  xxxMx1xx                                      ,                VAL1(RXDLLCTL_CCBLDM_DQCCC_REG)                      ,  BB(DQCCC,      _00000101), MASK2(0x501)             , AP(SET,       _____),                                                                                          VAL2(0x1),                                                         // static_RXEN_m : , static_RXEN_m : , static_RXEN_m : 
  ASSIGNDONE,
  //
  // modmem_ldo_offsetcomp_seq
  //
  xxxMx1xx                                      ,                VAL1(TXSAOFFSET_LDO_REG)                             ,  BB(LDO,        _00001000), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp2p5_seq
  //
  xxxMx1xx                                      ,                VAL1(LDOCTL1_DPIC_REG)                               ,  BB(DPIC,       _00000100), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_LDOREG : 
  xxxMx1xx                                      ,                VAL1(LDOCTL1_DPIC_REG)                               ,  BB(DPIC,       _00000010), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_LDOREG : 
  xxxMx1xx                                      ,                VAL1(LDOCTL1_DPIC_REG)                               ,  BB(DPIC,       _00000010), MASK1(0xF)               , AP(SET,       __F__),                   9,   F(F_800),                                                         VAL1(0x3),                                                        F(F_1066),                                                        VAL1(0x4),                                                        F(F_1333),                                                        VAL1(0x5),                                                        F(F_1600),                                                        VAL1(0x6),                                                        F(F_1866),                                                        VAL1(0x7),                                                        F(F_2133),                                                        VAL1(0x8),                                                        F(F_2667),                                                        VAL1(0xA),                                                        F(F_2933),                                                        VAL1(0xB),                                                        F(F_3200),                                                        VAL1(0xC),                                                         // static_LDOREG : 
  xxxxx1xx                                      ,                VAL1(LDOCTL1_DPIC_REG)                               ,  BB(DPIC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x5F),                                                        // static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : 
  xxxMx1xx                                      ,                VAL1(LDORSTCTL_DPIC_REG)                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_LDORSTREG : 
  ASSIGNDONE,
  //
  // modmem_ldo_offsetcomp_poll
  //
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp4_seq
  //
  xxxMx1xx                                      ,                VAL1(LDOONCTL_DPIC_REG)                              ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_LDOONREG : 
  xxxMx1xx                                      ,                VAL1(VREFCTL0_DQCCC_REG)                             ,  BB(DQCCC,      _00001100), MASK2(0xFF30)            , AP(SET,       _____),                                                                                          VAL2(0x3F30),                                                      // static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : 
  xxxMx1xx                                      ,                VAL1(VREFCTL0_DQCCC_REG)                             ,  BB(DQCCC,      _00000111), MASK3(0x1FFFF)           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL3(0x2020),                                                     T(T_LPDDR4),                                                      VAL3(0x10F0F),                                                     // static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000FA),
  xxxMx1xx                                      ,                VAL1(VREFCTL1_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x1),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_VREFEN_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000003E8),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp4p5_seq
  //
  xxxMx1xx                                      ,                VAL1(TXDLLCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000111), MASK3(0x13F0E)           , AP(SET,       _____),                                                                                          VAL3(0x13F0E),                                                     // static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5m_seq
  //
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                          VAL2(0x0),                                                         // static_3_m : , static_3_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_CFG1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFFF)        , AP(SET,       _____),                                                                                          VAL4(0x5010A0E),                                                   // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_CFG2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x707075),                                                    // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_CFG3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000011), MASK2(0xFFF)             , AP(SET,       _____),                                                                                          VAL2(0xF3F),                                                       // static_3_m : , static_3_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x3FC0FF)          , AP(SET,       _____),                                                                                          VAL3(0x8000),                                                      // static_3_m : , static_3_m : , static_3_m : , static_3_m : 
  xxNMx1xx, xxxxxCxx                            , C_(  0)      , VAL1(DPIC_LRCOMP_CTL0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x6)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_3_m :  
  xxNMx1xx, xxxxxCxx                            , C_(  1)      , VAL1(DPIC_LRCOMP_CTL0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x6)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_3_m :  
  xxNMx1xx, xxxxxCxx                            , C_(  2)      , VAL1(DPIC_LRCOMP_CTL0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x6)               , AP(SET,       _____),                                                                                          VAL1(0x6),                                                         // static_3_m :  
  xxNMx1xx, xxxxxCxx                            , C_(  3)      , VAL1(DPIC_LRCOMP_CTL0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x6)               , AP(SET,       _____),                                                                                          VAL1(0x6),                                                         // static_3_m :  
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_CTL0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x1BFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x1800800),                                                   // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_CTL1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                          VAL3(0xFC0),                                                       // static_3_m : , static_3_m : , static_3_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMPOVR_DPLVUG_REG)                   ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                          VAL3(0x74),                                                        // static_3_m : , static_3_m : , static_3_m : , static_3_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_LRCOMP_CTL2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x7FFFF)           , AP(SET,       _____),                                                                                          VAL3(0x1111),                                                      // static_3_m : , static_3_m : , static_3_m : , static_3_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x3FFFFFF6)        , AP(SET,       _____),                                                                                          VAL4(0x4000006),                                                   // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x7FFFFF)          , AP(SET,       _____),                                                                                          VAL3(0x200000),                                                    // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x7FFFFF)          , AP(SET,       _____),                                                                                          VAL3(0x200000),                                                    // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x7FFFFF)          , AP(SET,       _____),                                                                                          VAL3(0x200000),                                                    // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5_seq
  //
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_CFG1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFFF)        , AP(SET,       _____),                                                                                          VAL4(0x5010A0E),                                                   // static_4 : , static_4 : , static_4 : , static_4 : , static_4 : 
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_CFG2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0xFFFFFF3)         , AP(SET,       _____),                                                                                          VAL4(0xE0E0E1),                                                    // static_4 : , static_4 : , static_4 : , static_4 : 
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_CFG3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000011), MASK2(0xFFF)             , AP(SET,       _____),                                                                                          VAL2(0xF3F),                                                       // static_4 : , static_4 : 
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                  ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x39393939),                                                  // static_4 : , static_4 : , static_4 : , static_4 : 
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0x3838),                                                      // static_4 : , static_4 : 
  xxxMx2xx                                      ,                VAL2(DPIC_GRCOMP_CTL_DPIC_REG)                       ,  BB(DPIC,       _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x1FFFFF),                                                    // static_gcomp_4 : , static_gcomp_4 : , static_gcomp_4 : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p25_seq
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00001100), MASK2(0x801F)            , AP(SET,       _____),                                                                                          VAL2(0xF),                                                         // static_5 : , static_5 : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(SET,       __F__),                   9,   F(F_800),                                                         VAL1(0x19),                                                       F(F_1066),                                                        VAL1(0x13),                                                       F(F_1333),                                                        VAL1(0x10),                                                       F(F_1600),                                                        VAL1(0x10),                                                       F(F_1866),                                                        VAL1(0xE),                                                        F(F_2133),                                                        VAL1(0xC),                                                        F(F_2667),                                                        VAL1(0xA),                                                        F(F_2933),                                                        VAL1(0x9),                                                        F(F_3200),                                                        VAL1(0x8),                                                         // static_5 : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000001), MASK1(0x1F)              , AP(SET,       __F_T),                   10,   FT(F_800,T_LPDDR3),                                               VAL1(0x17),                                                       FT(F_1066,T_LPDDR3),                                              VAL1(0x11),                                                       FT(F_1333,T_LPDDR3),                                              VAL1(0xE),                                                        FT(F_1600,T_LPDDR3|T_LPDDR4),                                     VAL1(0xE),                                                        FT(F_1866,T_LPDDR3),                                              VAL1(0xB),                                                        FT(F_1066,T_LPDDR4),                                              VAL1(0x12),                                                       FT(F_2133,T_LPDDR4),                                              VAL1(0xA),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_2933,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x6),                                                         // static_5 : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p5m_seq
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_LPDDRTYPE_DQCCC_REG)                    ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_LOCKCTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001001), MASK2(0xC00F)            , AP(SET,       _____),                                                                                          VAL2(0x4003),                                                      // static_5_m : , static_5_m : , static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00001111), MASK4(0xCF0F0F0F)        , AP(SET,       _____),                                                                                          VAL4(0xF0F0F02),                                                   // static_5_m : , static_5_m : , static_5_m : , static_5_m : , static_5_m : , static_5_m : 
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINECODE_DQCCC_REG)                     ,  BB(DQCCC,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x641EF414),                                                  // static_5_m : , static_5_m : , static_5_m : , static_5_m : 
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINEMUXSEL_DQCCC_REG)                   ,  BB(DQCCC,      _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xE8),                                                        // static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FINECTL_DQCCC_REG)                      ,  BB(DQCCC,      _00001001), MASK2(0xE0FF)            , AP(SET,       _____),                                                                                          VAL2(0x203F),                                                      // static_5_m : , static_5_m : , static_5_m : , static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FINECODEOVR_DQCCC_REG)                  ,  BB(DQCCC,      _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                          VAL2(0x13),                                                        // static_5_m : , static_5_m : , static_5_m : 
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FPTIMER_DQCCC_REG)                      ,  BB(DQCCC,      _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0xFFFF),                                                      // static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_SAMPLEWAIT_DQCCC_REG)                   ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(SET,       __F_T),                   6,   FT(F_800,T_LPDDR3),                                               VAL1(0x8),                                                        FT(F_1066|F_1333,T_LPDDR3),                                       VAL1(0x7),                                                        FT(F_1600|F_1866,T_LPDDR3),                                       VAL1(0x6),                                                        FT(F_1066,T_LPDDR4),                                              VAL1(0x9),                                                        FT(F_1600|F_2133,T_LPDDR4),                                       VAL1(0x7),                                                        FT(F_2667|F_2933|F_3200,T_LPDDR4),                                VAL1(0x6),                                                         // static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_SAMPLEWAIT_DQCCC_REG)                   ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(SET,       __FC_),                   1,   FC(F_1600,C_POR),                                                 VAL1(0x7),                                                         // static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_SAMPLEWAIT_DQCCC_REG)                   ,  BB(DQCCC,      _00000001), MASK1(0x1F)              , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RXCOARSEOVR_DQCCC_REG)                  ,  BB(DQCCC,      _00001001), MASK2(0x800F)            , AP(SET,       _____),                                                                                          VAL2(0x2),                                                         // static_5_m : , static_5_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RXFINEOVR_DQCCC_REG)                    ,  BB(DQCCC,      _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                          VAL2(0x13),                                                        // static_5_m : , static_5_m : , static_5_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_RSTCTL_DPLVUG_REG)                  ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFFF)        , AP(SET,       _____),                                                                                          VAL4(0x112C1),                                                     // static_GRCOMP_RSTCTL_m : , static_GRCOMP_RSTCTL_m : , static_GRCOMP_RSTCTL_m : , static_GRCOMP_RSTCTL_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_RSTCTL_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_LRCOMP_RSTCTL_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RESET_DQCCC_REG)                        ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DLLCOMP_RSTCTL_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_PM_DELAY0_DPIC_REG)                        ,  BB(DPIC,       _00001111), MASK4(0xFFFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x10000),                                                     // static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY1_DPIC_REG)                        ,  BB(DPIC,       _00001000)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x2),                                                        T(T_LPDDR4),                                                      VAL1(0x4),                                                         // static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY1_DPIC_REG)                        ,  BB(DPIC,       _00000100)                           , AP(SET,       _____),                                                                                          VAL1(0x4),                                                         // static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY1_DPIC_REG)                        ,  BB(DPIC,       _00000011)                           , AP(SET,       _P___),                   3,   P(P_EMU),                                                         VAL2(0x3E8),                                                      P(P_SIM),                                                         VAL2(0x10),                                                       P(P_SIL),                                                         VAL2(0x6C),                                                        // static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY2_DPIC_REG)                        ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xE20202),                                                    // static_2_m : , static_2_m : , static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY3_DPIC_REG)                        ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x2000F),                                                     // static_2_m : , static_2_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_PM_DELAY4_DPIC_REG)                        ,  BB(DPIC,       _00001111), MASK4(0xFFFFF0F)         , AP(SET,       _____),                                                                                          VAL4(0x401200),                                                    // static_2_m : , static_2_m : , static_2_m : , static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY5_DPIC_REG)                        ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x2020202),                                                   // static_2_m : , static_2_m : , static_2_m : , static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY6_DPIC_REG)                        ,  BB(DPIC,       _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0x10000),                                                     // static_2_m : , static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY7_DPIC_REG)                        ,  BB(DPIC,       _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0xC8002),                                                     // static_2_m : , static_2_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_PM_DELAY8_DPIC_REG)                        ,  BB(DPIC,       _00001111), MASK4(0x1FFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x905222),                                                    // static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : 
  xxxxx2xx                                      ,                VAL2(DPIC_PM_DELAY9_DPIC_REG)                        ,  BB(DPIC,       _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0x1200C8),                                                    // static_2_m : , static_2_m : , static_2_m : , static_2_m : 
  ASSIGNDONE,
  //
  // PhyConfigComplete
  //
  xxxMx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // MRC_to_Tap_step32
  //
  xxxxx2xx                                      ,                VAL2(PUNIT_TAP_DUNIT_REG)                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p5_seq
  //
  xxxMx2xx                                      ,                VAL2(DPIC_PMSWMSG_DPIC_REG)                          ,  BB(DPIC,       _00000001), MASK1(0x80)              , AP(POLL,      _____),                                                                                          VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p5_seq1
  //
  xxxMx2xx                                      ,                VAL2(DPIC_PM_RSTB_DPIC_REG)                          ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_PM_RSTB_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CLKREQ_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_PMCLKREQ_m : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp6_seq
  //
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_TXDLYCOMP_INIT_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DLLCOMP_INIT_m : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp6p5_seq
  //
  xxNMx1xx, xxxxxCxx                            , C_(  1)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _P___),                   1,   P(P_SIM),                                                         VAL1(0x1),                                                         // static_GRCOMP_INIT : // write rcomp_init_comp to CH0 only, // Cold Boot: Do Init Rcomp or choose rcomp override mode (random decision), // Save and Restore flow: Choose rcomp override mode
  xxNMx1xx, xxxxxCxx                            , C_(  0)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _P___),                   1,   P(P_SIL),                                                         VAL1(0x1),                                                         // static_GRCOMP_INIT : // write rcomp_init_comp to CH0 only, // Cold Boot: Do Init Rcomp or choose rcomp override mode (random decision), // Save and Restore flow: Choose rcomp override mode
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7_seq
  //
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_CODE_STATUS_DQCCC_REG)                  ,  BB(DQCCC,      _00000100), MASK1(0x1F)              , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7p5_seq
  //
  xxNMx1xx, xxxxxCxx                            , C_(  1)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _P___),                   1,   P(P_SIM),                                                         VAL1(0x0),                                                        
  xxNMx1xx, xxxxxCxx                            , C_(  0)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _P___),                   1,   P(P_SIL),                                                         VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7p75_seq
  //
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                 ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1),                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_1),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_2),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_3),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                 ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2),                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_1),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_2),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_3),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                 ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000)                           , AP(SET,       D___T),                   1,   T(T_LPDDR3),                                                      VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3),                                
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_1),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010)                           , AP(SET,       D___T),                   1,   T(T_LPDDR3),                                                      VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_2),                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_3),                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000110), MASK2(0x3FC0)            , AP(SET,       _____),                                                                                          VAL2(0x0),                                                         // // Enable the override selects
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                          VAL2(0x3F3F),                                                     
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp8m_seq
  //
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx1xx                                      ,                VAL1(DIGRSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                         // static_DIGRSTCTL_m : , static_DIGRSTCTL_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx1xx                                      ,                VAL1(FIFOPTREN_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_FIFOPTREN_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx1xx                                      ,                VAL1(IOBUFACT_DIG_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                         // static_IOBUFACT_DIG_m : , static_IOBUFACT_DIG_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  xxxMx1xx                                      ,                VAL1(IOBUFACT_AFE_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                         // static_IOBUFACT_AFE_m : , static_IOBUFACT_AFE_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C5),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp8m_not_seq
  //
  xxxMx1xx                                      ,                VAL1(IOBUFACT_AFE_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_IOBUFACT_AFE_m : , static_IOBUFACT_AFE_m : 
  xxxMx1xx                                      ,                VAL1(IOBUFACT_DIG_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_IOBUFACT_DIG_m : , static_IOBUFACT_DIG_m : 
  xxxMx1xx                                      ,                VAL1(FIFOPTREN_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_FIFOPTREN_m : 
  xxxMx1xx                                      ,                VAL1(DIGRSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGRSTCTL_m : , static_DIGRSTCTL_m : 
  ASSIGNDONE,
  //
  // lp4_txdll_ovr_seq
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000100), MASK1(0x1F)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xC),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00001100), MASK2(0xF0F)             , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL2(0x404),                                                      
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FINECODEOVR_DQCCC_REG)                  ,  BB(DQCCC,      _00001001), MASK2(0x40FF)            , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL2(0x4080),                                                     
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00001000), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x80),                                                       
  xxxMx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00001000), MASK1(0xC0)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xC0),                                                       
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FINECODEOVR_DQCCC_REG)                  ,  BB(DQCCC,      _00001000), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // lp4_rxdll_ovr_seq
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RXCOARSEOVR_DQCCC_REG)                  ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x4),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RXFINEOVR_DQCCC_REG)                    ,  BB(DQCCC,      _00001001), MASK2(0x40FF)            , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL2(0x4080),                                                     
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RXCOARSEOVR_DQCCC_REG)                  ,  BB(DQCCC,      _00001000), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x80),                                                       
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RXFINEOVR_DQCCC_REG)                    ,  BB(DQCCC,      _00001000), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // lp4_rcomp_ovr_seq
  //
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL4(0x25292529),                                                 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL4(0x25292529),                                                 
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111), MASK4(0x7F7F7F7F)        , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL4(0x230023),                                                   
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL2(0x30),                                                       
  ASSIGNDONE,
  //
  // lp4_txdlycomp_ovr_seq
  //
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFE0)          , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL3(0x121E0),                                                    
  xxxxx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000011)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL2(0x90F),                                                      
  xxxxx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000011)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL2(0x90F),                                                      
  xxxxx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000011)                           , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL2(0x90F),                                                      
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_0_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x20)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DPIC_TXDLYCOMP_3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // MRC_to_Tap_step53p5
  //
  xxxxx2xx                                      ,                VAL2(PUNIT_TAP_DUNIT_REG)                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x1),                                                        
  ASSIGNDONE,
  //
  // DunitResetComplete
  //
  xxxMx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00000100), MASK1(0x2)               , AP(POLL,      _____),                                                                                          VAL1(0x2),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp0_seq
  //
  xxxMx1xx                                      ,                VAL1(LP4RSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                         // static_LP4RSTCTL : // cold boot only, static_LP4RSTCTL : // cold boot only, static_LP4RSTCTL : // cold boot only
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp10m_seq
  //
  xxxMx1xx                                      ,                VAL1(SPIDIC_DQCCC_REG)                               ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_SPIDIC_m : 
  ASSIGNDONE,
  //
  // InitDunit
  //
  xxxME1xx          , VAL2(SILICON_BXT_P0)      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00001000), MASK1(0xC0)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x40),                                                       
  xxxxx1xx                                      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRP0),                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00001100), MASK2(0xFC0)             , AP(SET,       ____T),                   3,   T(T_LPDDR3),                                                      VAL2(0x40),                                                       T(T_LPDDR4),                                                      VAL2(0xA80),                                                      T(T_WIO2),                                                        VAL2(0xC0),                                                        // LP3 is always BL8, LP4 is always BL32, and WIO2 is always BL8
  xxxxx1xx                                      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00000111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRP0_1),                                      
  xxxMx1xx                                      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x30)              , AP(SET,       ____T),                   3,   T(T_LPDDR3),                                                      VAL1(0x20),                                                       T(T_LPDDR4),                                                      VAL1(0x10),                                                       T(T_WIO2),                                                        VAL1(0x30),                                                        // LP3 - x32, LP4 - x16, WIO2 - x64
  xxxxx1xx                                      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRP0_2),                                      
  xxxxx1xx                                      ,                VAL1(D_CR_DTR0A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR0A),                                       
  xxxxx1xx                                      ,                VAL1(D_CR_DTR1A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR1A),                                        // N/A for WIO2, N/A for LP4/WIO2, N/A for LP3/WIO2
  xxxxx1xx                                      ,                VAL1(D_CR_DTR2A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR2A),                                       
  xxxxx1xx                                      ,                VAL1(D_CR_DTR3A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR3A),                                        // for HVM stretch mode only, Not Available for LP3
  xxxxx1xx                                      ,                VAL1(D_CR_DTR4A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR4A),                                       
  xxxxx1xx                                      ,                VAL1(D_CR_DTR5A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR5A),                                        // 1.875ns/DRAM Freq
  xxxxx1xx                                      ,                VAL1(D_CR_DTR6A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR6A),                                        // not in JEDEC spec, Def Value should be ok, Previously :TCKSRE, tRP + tRCD + RL + tCCD   , RL + tDQSCK +MRR/MRW BL/2 + 1, Max(WL + 1 + BL/2 + tWTR, tXP + tMRRI)
  xxxxx1xx                                      ,                VAL1(D_CR_DTR7A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR7A),                                       
  xxxxx1xx                                      ,                VAL1(D_CR_DTR8A_DUNIT_REG)                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR8A),                                        // PHY Spec, Depends on Technology, PHY Spec, Depends on Technology
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DSCH_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0xF)               , AP(SET,       ____T),                   3,   T(T_LPDDR3|T_DDR3L),                                              VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x8),                                                        T(T_WIO2),                                                        VAL1(0x4),                                                        
  xxxxx1xx                                      ,                VAL1(D_CR_SSKPD0_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_SSKPD0),                                      
  xxxxx1xx                                      ,                VAL1(D_CR_BONUS0_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_BONUS0),                                      
  xxxxx1xx                                      ,                VAL1(D_CR_BONUS1_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_BONUS1),                                      
  xxxxx2xx                                      ,                VAL2(D_CR_MR4_DESWIZZLE_DUNIT_REG)                   ,  BB(DUNIT,      _00000011)                           , AP(SET,       D___T),                   1,   T(T_LPDDR3|T_LPDDR4),                                             VAL2(DYN_DUNIT_D_CR_MR4_DESWIZZLE),                                // Check with Package Team, Check with Package Team, Check with Package Team, BXT-P is 3 bits
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq_sim
  //
  xxxMx1xx                                      ,                VAL1(LP4RSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x2),                                                         // Set Reset High, Latch Reset State
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  xxxMx1xx                                      ,                VAL1(LP4RSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000007D0),
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x13),                                                       
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq
  //
  xxxMx1xx                                      ,                VAL1(LP4RSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x2),                                                         // Set Reset High, Latch Reset State
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00030D40),
  xxxMx1xx                                      ,                VAL1(LP4RSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x001E8480),
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x13),                                                       
  ASSIGNDONE,
  //
  // InitDunitWake
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000101), MASK2(0x113)             , AP(SET,       _____),                                                                                          VAL2(0x113),                                                      
  xxxMx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x000000C8),                                                                        VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // PrepareForTraining
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                        // Prepare for training by switching PMI to CPGC
  xxxxx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00001000)                           , AP(SET,       D___T),                   2,   T(T_LPDDR3|T_LPDDR4),                                             VAL2(DYN_DUNIT_D_CR_BGF_CTL),                                     T(T_WIO2),                                                        VAL2(DYN_DUNIT_D_CR_BGF_CTL_1),                                   
  xxxxx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000110)                           , AP(SET_DELAY, D____), VAL4(0x0000001E),                                                                        VAL2(DYN_DUNIT_D_CR_BGF_CTL_2),                                   
  xxxMx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // DIFF_AMP_OVERRIDE
  //
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                          VAL2(CC_DQS_OVR_VAL),                                             
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                          VAL2(CC_DQS_OVR_SEL),                                             
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                          VAL2(CC_DQDM_OVR_VAL),                                            
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(CC_DQDM_OVR_SEL),                                            
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                          VAL2(BL_DQS_OVR_VAL),                                             
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                          VAL2(BL_DQS_OVR_SEL),                                             
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                          VAL2(BL_DQDM_OVR_VAL),                                            
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(BL_DQDM_OVR_SEL),                                            
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0xF),                                                        
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0xF),                                                        
  ASSIGNDONE,
  //
  // DQ_DB_REGION_PROGRAM
  //
  xxxxx1xx                                      ,                VAL1(DBREGIONCTL1_DPLVUG_REG)                        ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x680C1926),                                                 
  xxxxx1xx                                      ,                VAL1(DBREGIONCTL2_DPLVUG_REG)                        ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x33404D5A),                                                 
  xxxxx1xx                                      ,                VAL1(DBREGIONCTL3_DPLVUG_REG)                        ,  BB(DPLVUG,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xF50A5505),                                                 
  ASSIGNDONE,
  //
  // HandlePostTraining
  //
  ASSIGNDONE,
  //
  // DIFF_AMP_RESTORE
  //
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_CC_DQCCC_REG)                        ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DIFFAMPCTL_CC_4),                                  
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DIFFAMPCTL_DQ_4),                                  
  ASSIGNDONE,
  //
  // TrainingDone
  //
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x21)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                        // assert BGF reset
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                        VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // deassert BGF reset
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // ProgamFinalSettings
  //
  xxxxx1xx                                      ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRP0_3),                                      
  xxxxx1xx                                      ,                VAL1(D_CR_DPMC0_DUNIT_REG)                           ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DPMC0),                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxME1xx          , VAL2(BXT_A0_PO)           ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxME1xx          , VAL2(BXT_A0_PO)           ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x7)               , AP(SET,       _____),                                                                                          VAL1(0x4),                                                         // P0 POR=2
  xxxME1xx          , VAL2(SILICON_BXT_P0)      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // P0 POR=2
  xxxxx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DPMC1),                                        // Page time out time, need to confirm
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x18)              , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4),                                             VAL1(0x10),                                                       T(T_DDR3L),                                                       VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x18)              , AP(SET,       ___C_),                   1,   C(C_PO),                                                          VAL1(0x0),                                                         // Use C if all steppings same value
  xxxME1xx          , VAL2(BXT_A0_PO)           ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x18)              , AP(SET,       ____T),                   2,   T(T_LPDDR4),                                                      VAL1(0x10),                                                       T(T_LPDDR3|T_DDR3L),                                              VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x6)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4),                                             VAL1(0x6),                                                        T(T_DDR3L),                                                       VAL1(0x2),                                                        
  xxxME1xx          , VAL2(BXT_A0_WA)           ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x6)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRFC),                                         // 1x refresh rate. Still Open. Different for WIO2/LP3 vs LP4?
  xxxxx1xx                                      ,                VAL1(D_CR_DSCH_DUNIT_REG)                            ,  BB(DUNIT,      _00001110)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DSCH),                                         // change if it was changed for CPGC, change if it was changed for CPGC, change if it was changed for CPGC
  xxxxx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DCAL),                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x2)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4|T_DDR3L),                                     VAL1(0x2),                                                        T(T_WIO2),                                                        VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000011), MASK2(0x3FFF)            , AP(SET,       _____),                                                                                          VAL2(0x1063),                                                     
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4|T_DDR3L),                                     VAL1(0x0),                                                        T(T_WIO2),                                                        VAL1(0x1),                                                         // Enable ZQCal
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_TQCTL),                                        // 1ms, Kaleen Man
  xxxMx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       ___CT),                   3,   CT(C_POR,T_LPDDR4|T_LPDDR3),                                      VAL1(0x4),                                                        CT(C_POR,T_DDR3L),                                                VAL1(0x0),                                                        CT(C_PO,T_LPDDR4|T_LPDDR3|T_DDR3L),                               VAL1(0x0),                                                         // HSD1202170264 ; need to set 1 for E0 POR
  xxxME1xx          , VAL2(BXT_A0_WA)           ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // HSD1202170264 ; need to set 1 for E0 POR
  xxxMx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4),                                             VAL1(0x2),                                                        T(T_DDR3L),                                                       VAL1(0x0),                                                         // Depands on the package and DRAM type, contact Kaleen Man
  xxxME1xx          , VAL2(BXT_A0_WA)           ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       ____T),                   1,   T(T_LPDDR3),                                                      VAL1(0x0),                                                         // Depands on the package and DRAM type, contact Kaleen Man
  xxxMx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_DDR3L),                                                       VAL1(0x0),                                                        T(T_LPDDR3|T_LPDDR4),                                             VAL1(0x1),                                                         // Depands on the package and DRAM type, contact Kaleen Man
  xxxME1xx          , VAL2(BXT_A0_WA)           ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR3),                                                      VAL1(0x0),                                                         // Depands on the package and DRAM type, contact Kaleen Man
  xxxxx1xx                                      ,                VAL1(D_CR_TQOFFSET_DUNIT_REG)                        ,  BB(DUNIT,      _00001100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_TQOFFSET),                                     // write the DRAM Mode Register that contains Temp Offset
  xxxMx1xx                                      ,                VAL1(D_CR_DCBR_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0xA)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxME1xx          , VAL2(SILICON_BXT_P0_PO)   ,                VAL1(D_CR_DCBR_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DCBR_DUNIT_REG)                            ,  BB(DUNIT,      _00000011), MASK2(0x180)             , AP(SET,       _____),                                                                                          VAL2(0x80),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                       ,  BB(DUNIT,      _00001000), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                       
  xxxxx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00001000)                           , AP(SET,       DP__T),                   2,   PT(P_SIM,T_LPDDR3|T_LPDDR4),                                      VAL2(DYN_DUNIT_D_CR_BGF_CTL_3),                                   PT(P_SIM,T_WIO2),                                                 VAL2(DYN_DUNIT_D_CR_BGF_CTL_4),                                   
  xxxxx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000110)                           , AP(SET,       DP___),                   1,   P(P_SIM),                                                         VAL2(DYN_DUNIT_D_CR_BGF_CTL_5),                                   
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       ___C_),                   2,   C(C_PO),                                                          VAL1(0x0),                                                        C(C_POR),                                                         VAL1(0x4),                                                        
  xxxME2xx          , VAL2(BXT_A0_WA)           ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x18)              , AP(SET_DELAY, ___C_), VAL4(0x0000001E), 2,   C(C_PO),                                                          VAL1(0x8),                                                        C(C_POR),                                                         VAL1(0x0),                                                        
  xxxME2xx          , VAL2(BXT_A0_WA)           ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x18)              , AP(SET_DELAY, _____), VAL4(0x0000001E),                                                                        VAL1(0x8),                                                        
  xxxME2xx          , VAL2(SILICON_BXT_P0_PO)   ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0xC0)              , AP(SET_DELAY, _____), VAL4(0x0000001E),                                                                        VAL1(0x40),                                                       
  xxxME2xx          , VAL2(BXT_A0_WA)           ,                VAL2(D_CR_ACCIP_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x38)              , AP(SET,       _____),                                                                                          VAL1(0x28),                                                       
  xxxME2xx          , VAL2(BXT_A0_WA)           ,                VAL2(D_CR_RD_PROM1_DUNIT_REG)                        ,  BB(DUNIT,      _00001100), MASK2(0x1F0)             , AP(SET,       _____),                                                                                          VAL2(0x80),                                                       
  xxxMx2xx                                      ,                VAL2(D_CR_MMC_DUNIT_REG)                             ,  BB(DUNIT,      _00001111), MASK4(0x3800FC0)         , AP(SET,       _____),                                                                                          VAL4(0x2800400),                                                  
  xxxME2xx          , VAL2(BXT_A0_WA)           ,                VAL2(D_CR_MM_BLK_DUNIT_REG)                          ,  BB(DUNIT,      _00000010), MASK1(0x8)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_MMRDWR_AB_DUNIT_REG)                       ,  BB(DUNIT,      _00001111), MASK4(0x3F00FC0)         , AP(SET,       _____),                                                                                          VAL4(0x1000400),                                                  
  xxxMx2xx                                      ,                VAL2(D_CR_MMRDWR_CD_DUNIT_REG)                       ,  BB(DUNIT,      _00001111), MASK4(0x3F00FC0)         , AP(SET,       _____),                                                                                          VAL4(0x1000300),                                                  
  xxxMx2xx                                      ,                VAL2(D_CR_DL_THRS_DUNIT_REG)                         ,  BB(DUNIT,      _00000011), MASK2(0x7FF)             , AP(SET,       _____),                                                                                          VAL2(0x2),                                                        
  xxxxx2xx                                      ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)              ,  BB(DUNIT,      _00001111)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4),                                                      VAL2(DYN_DUNIT_D_CR_DQS_RETRAINING_CTL),                           // LPDDR4 only, Chris Mozak, ame value as LPDDR4 MR23, 500ns? Chris Mozak. Should not larger than interval
  xxxME2xx          , VAL2(BXT_PERIODIC_ENABLED),                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)              ,  BB(DUNIT,      _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x3),                                                         // LPDDR4 only, LPDDR4 only
  ASSIGNDONE,
  //
  // ProgamFinalSettingsS0
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x60)              , AP(SET,       _____),                                                                                          VAL1(0x60),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR3|T_LPDDR4|T_DDR3L),                                     VAL1(0x1),                                                         // Enable ZQCal
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp11m_seq
  //
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_CLKGATE_DPLVUG_REG)              ,  BB(DPLVUG,     _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                         // static_LRCOMP_CLKGATE_m : , static_LRCOMP_CLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_CLKGATE_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DPIC_GRCOMP_CLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATERDCTL_DQCCC_REG)                         ,  BB(DQCCC,      _00000110), MASK2(0xF77)             , AP(SET,       _____),                                                                                          VAL2(0xF33),                                                       // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATERDCTL_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL1(0x11),                                                       FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL1(0x14),                                                       FT(F_1066|F_1600,T_LPDDR4),                                       VAL1(0x18),                                                       FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL1(0x1D),                                                        // static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATEWRCTL_DQCCC_REG)                         ,  BB(DQCCC,      _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0xF),                                                         // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATEWRCTL_DQCCC_REG)                         ,  BB(DQCCC,      _00000010), MASK1(0x77)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL1(0x22),                                                       FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL1(0x33),                                                       FT(F_1066|F_1600|F_2133,T_LPDDR4),                                VAL1(0x22),                                                       FT(F_2667|F_2933|F_3200,T_LPDDR4),                                VAL1(0x33),                                                        // static_DQCLKGATE_m : , static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATEWRCTL_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL1(0xC),                                                        FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL1(0xE),                                                        FT(F_1066|F_1600,T_LPDDR4),                                       VAL1(0x15),                                                       FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL1(0x17),                                                        // static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATECTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100), MASK1(0x8)               , AP(SET,       ___C_),                   1,   C(C_POR),                                                         VAL1(0x0),                                                         // static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATECTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100), MASK1(0x7)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : 
  xxxMx1xx                                      ,                VAL1(CLKGATECTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066,T_LPDDR3),                                        VAL1(0x10),                                                       FT(F_1333|F_1600|F_1866,T_LPDDR3),                                VAL1(0x13),                                                       FT(F_1066|F_1600,T_LPDDR4),                                       VAL1(0x18),                                                       FT(F_2133|F_2667|F_2933|F_3200,T_LPDDR4),                         VAL1(0x1C),                                                        // static_DQCLKGATE_m : 
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CLKGATE_DPIC_REG)                       ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_PMCLKGATE_m : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp11_seq
  //
  xxNMx2xx, xxxxxCxx                            , C_(  1)      , VAL2(DPIC_GRCOMP_PERIODICCOMP_DPLVUG_REG)            ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _P___),                   1,   P(P_SIM),                                                         VAL1(0x0),                                                         // static_GRCOMP_PERIODICCOMP : 
  xxNMx2xx, xxxxxCxx                            , C_(  0)      , VAL2(DPIC_GRCOMP_PERIODICCOMP_DPLVUG_REG)            ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _P___),                   1,   P(P_SIL),                                                         VAL1(0x1),                                                         // static_GRCOMP_PERIODICCOMP : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp12m_seq
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_CLKUNGATE_DQCCC_REG)                    ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DLLCOMP_CLKUG_m : //CRI/DLLCOMP Clock Gating
  xxxMx1xx                                      ,                VAL1(DPIC_CRI_CFG_DPIC_REG)                          ,  BB(DPIC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x210),                                                       // static_CRIPGCTL_m : , static_CRIPGCTL_m : , static_CRIPGCTL_m :  Init Val 0
  ASSIGNDONE,
  //
  // CPGCModeComplete
  //
  xxxxx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00000101)                           , AP(SET,       D____),                                                                                          VAL2(DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_1),                  
  ASSIGNDONE,
  //
  // SetBGFRun
  //
  xxxxx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00001000)                           , AP(SET,       D___T),                   2,   T(T_LPDDR3|T_LPDDR4),                                             VAL2(DYN_DUNIT_D_CR_BGF_CTL_6),                                   T(T_WIO2),                                                        VAL2(DYN_DUNIT_D_CR_BGF_CTL_7),                                   
  xxxxx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000110)                           , AP(SET_DELAY, D____), VAL4(0x0000001E),                                                                        VAL2(DYN_DUNIT_D_CR_BGF_CTL_8),                                   
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // SetMrcDone
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000320),
  ASSIGNDONE,
  //
  // EXESDTInit
  //
  xxxMx2xx                                      ,                VAL2(MLM_CR_MISC_MLMC_REG)                           ,  BB(MLMC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // SetMLMC
  //
  xBxxx2xx                                      ,                VAL2(MLM_CR_CONFIG_MLMC_REG)                         , BB2(MLMC,       _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_MLMC_MLM_CR_CONFIG),                                     
  xxxxx2xx                                      ,                VAL2(MLM_CR_FM_CONFIG_MLMC_REG)                      ,  BB(MLMC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_MLMC_MLM_CR_FM_CONFIG),                                   // One bit for S N W E Dunits.
  xxxMx2xx                                      ,                VAL2(MLM_CR_MISC_MLMC_REG)                           ,  BB(MLMC,       _00000001), MASK1(0x2)               , AP(POLL,      _____),                                                                                          VAL1(0x2),                                                        
  ASSIGNDONE,
  //
  // SetPunitMemDone
  //
  xxxMx2xx                                      ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)        ,  BB(PUNIT,      _00000100), MASK1(0x8)               , AP(SET,       _____),                                                                                          VAL1(0x8),                                                        
  ASSIGNDONE,
  //
  // TEST
  //
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_TXDLLSIGGRP2CTL),                                  
  ASSIGNDONE,
  //
  // CPGC_ONE_TIME_INIT
  //
  xxNMx1xx, xxxxxxxS                            ,                VAL1(D_CR_DRP0_DUNIT_REG)                            ,  BB(DUNIT,      _00001000), MASK1(0xE)               , AP(SET,       ____T),                   3,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0xA),                                                        T(T_WIO2),                                                        VAL1(0x0),                                                         1, 0,  // 25
  xxxMx1xx                                      ,                VAL1(CPGC_SUBSEQ0_CTL_B_CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DSCH_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // 2 in order mode, 0:out of order
  xxxMx1xx                                      ,                VAL1(D_CR_DCBR_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x8)               , AP(SET,       _____),                                                                                          VAL1(0x8),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_CONTROL_CPGC_REG)                 ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_ADDRESS_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_DATA_INSTRUCTION_0__CPGC_REG)             ,  BB(CPGC,       _00000001), MASK1(0xF8)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxxx1xx                                      ,                VAL1(CPGC2_DATA_CONTROL_CPGC_REG)                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)        ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_1__CPGC_REG)        ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x81),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_CPGC_REG)    ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_CPGC_REG)    ,  BB(CPGC,       _00001011), MASK3(0xC3FFFF)          , AP(SET,       _____),                                                                                          VAL3(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_COL_REPEATS_CPGC_REG)                ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x81),                                                       
  xxxxx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)          ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_BUF_CTL_CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0x7077F)           , AP(SET,       _____),                                                                                          VAL3(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                         ,  BB(CPGC,       _00001111), MASK4(0x1FFFE0DB)        , AP(SET,       _____),                                                                                          VAL4(0x49),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_XTRA_LFSR_CFG_CPGC_REG)               ,  BB(CPGC,       _00001111), MASK4(0x3F9C9C9C)        , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x11111111),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x11224488),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_2__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x77777777),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_INVDCCTL_CPGC_REG)                    ,  BB(CPGC,       _00001101), MASK3(0xC01FFF)          , AP(SET,       _____),                                                                                          VAL3(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_INV_DC_MASK_LO_CPGC_REG)              ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_INV_DC_MASK_HI_CPGC_REG)              ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_DRAMDM_CPGC_REG)                      ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xFFFFFFFF),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_XDRAMDM_CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xFFFFFFFF),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_ADDRESS_AS_DATA_CTRL_CPGC_REG)        ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                  ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                  ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                  ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                  ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                  ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                  ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00001111), MASK4(0x1FFFF1FF)        , AP(SET,       _____),                                                                                          VAL4(0xC5270C5),                                                  
  xxxMx1xx                                      ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)            ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC_LB_SEQ_CFG_CPGC_REG)                       ,  BB(CPGC,       _00001111), MASK4(0xFF1FFFFF)        , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC_LB_SEQ_CTL_CPGC_REG)                       ,  BB(CPGC,       _00000011), MASK2(0x307F)            , AP(SET,       _____),                                                                                          VAL2(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000111), MASK3(0x207F40)          , AP(SET,       _____),                                                                                          VAL3(0x201000),                                                   
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_B_CPGC_REG)                        ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                       ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_CTL_CPGC_REG)                          ,  BB(CPGC,       _00001100)                           , AP(SET,       _____),                                                                                          VAL2(0xFFFF),                                                     
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_LNEN_LO_CPGC_REG)                      ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_LNEN_HI_CPGC_REG)                      ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   2,   T(T_LPDDR4|T_LPDDR3),                                             VAL4(0xFFFFFFFF),                                                 T(T_DDR3L),                                                       VAL4(0x0),                                                         // B0:less than 64 bit bus, this becomes error check mask for chunks
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_RANK_L2P_MAPPING_CPGC_REG)             ,  BB(CPGC,       _00001111), MASK4(0x77777777)        , AP(SET,       _____),                                                                                          VAL4(0x76543210),                                                  // RANK_1, RANK_0
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)           ,  BB(CPGC,       _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // A0 bug, cannot close page on bank0
  ASSIGNDONE,
  //
  // SET_REF2XPH
  //
  xxxMx1xx                                      ,                VAL1(TXDLLCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0xE)               , AP(SET,       _____),                                                                                          VAL1(0xE),                                                        
  xxxxx1xx                                      ,                VAL1(TXDLLREF2XCTL_DQCCC_REG)                        ,  BB(DQCCC,      _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0x4E341A),                                                   
  xxxMx1xx                                      ,                VAL1(TXDLLCTL_CCC_REG)                               ,  BB(CCC,        _00000001), MASK1(0xE)               , AP(SET,       _____),                                                                                          VAL1(0xE),                                                        
  xxxxx1xx                                      ,                VAL1(TXDLLREF2XCTL_CCC_REG)                          ,  BB(CCC,        _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0x4E341A),                                                   
  ASSIGNDONE,
  //
  // CPGC_SETUP_ERT
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // CPGC_EXIT_ERT
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_LNEN_LO_CPGC_REG)                      ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // CPGC_RUN_DIRECT
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x4),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // SEND_DRAM_CMD
  //
  xxxxx2xx                                      ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                        ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRAM_CMD),                                     // LP3 is always BL8, LP4 is always BL32, and WIO2 is always BL8, Rank Bit, MRRCMD, Issue Dynamic Command
  ASSIGNDONE,
  //
  // CPGC_CHECK_ERRORS
  //
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(REG_DATA),                                                   
  ASSIGNDONE,
  //
  // CPGC_SETUP_DPAT0
  //
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_0_),                               
  ASSIGNDONE,
  //
  // CPGC_RUN_TEST
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x4),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                       ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(BYTEGRP_ERR_STAT),                                           
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000010), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(ECC_ERR_STAT),                                               
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000001F4),
  ASSIGNDONE,
  //
  // CPGC_ENABLE
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCBR_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DSCH_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // set DUNIT to in order mode
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  ASSIGNDONE,
  //
  // CPGC_RUN_TEST_OE
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x4),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                       ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(CPGC_RESULT),                                                
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000003E8),
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x4),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                       ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(CPGC_RESULT),                                                
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000003E8),
  ASSIGNDONE,
  //
  // CPGC_RESETUP_WRITE_ONLY
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)        ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                        // can be removed, for safety
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BASE_REPEATS),                                
  xxxxx1xx                                      ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BLOCK_REPEATS),                               
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  ASSIGNDONE,
  //
  // CPGC_RESETUP_READ_ONLY
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)        ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                          VAL1(0x81),                                                       
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BASE_REPEATS_1),                              
  xxxxx1xx                                      ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BLOCK_REPEATS_1),                             
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  ASSIGNDONE,
  //
  // CPGC_RESETUP_WRITE_READ
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)        ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                        // can be removed, for safety
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_1__CPGC_REG)        ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                          VAL1(0x81),                                                        // can be removed, for safety
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                        // can be removed, for safety
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BASE_REPEATS_2),                              
  xxxxx1xx                                      ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BLOCK_REPEATS_2),                             
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  ASSIGNDONE,
  //
  // FINEWRITELEVEL_ENTRYa
  //
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(SET,       ____T),                   1,   T(T_LPDDR3),                                                      VAL1(0x3),                                                        
  ASSIGNDONE,
  //
  // CPGC_DISABLE
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCBR_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                          VAL1(0x4),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // WRLVLMODE
  //
  xxxxx1xx                                      ,                VAL1(WRLVL_DQCCC_REG)                                ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_WRLVL),                                            
  xxxxx1xx                                      ,                VAL1(WRLVL_CCC_REG)                                  ,  BB(CCC,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CCC_WRLVL),                                              
  ASSIGNDONE,
  //
  // CPGC_SETUP_VA
  //
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAA55AFC0),                                                  // 0xaa55afc0
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAF0FF00),                                                  // 0xaaf0ff00
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0xDB)              , AP(SET,       _____),                                                                                          VAL1(0x92),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_XTRA_LFSR_CFG_CPGC_REG)               ,  BB(CPGC,       _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_XTRA_LFSR_CFG),                            // LANE_ROTATE_RATE
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xAAAAAAAA),                                                 
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_XTRA_LFSR_CFG_CPGC_REG)               ,  BB(CPGC,       _00000111), MASK3(0x9C9C9C)          , AP(SET,       _____),                                                                                          VAL3(0x1C1C1C),                                                   
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                         ,  BB(CPGC,       _00001100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_CFG),                                      // RELOAD_LFSR_SEED_RATE, SAVE_LFSR_SEED_RATE
  ASSIGNDONE,
  //
  // CPGC_LOOPS
  //
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BASE_REPEATS_3),                               // NUM_BURSTS
  xxxxx1xx                                      ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_BLOCK_REPEATS_3),                              // LOOP_COUNT
  ASSIGNDONE,
  //
  // ENTER_CA_TRAINING
  //
  xxxMx1xx                                      ,                VAL1(CCCCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0xC0)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x10),                                                       
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0xC)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x3)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_DPAT_INVDCCTL_CPGC_REG)                    ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_INV_DC_MASK_LO_CPGC_REG)              ,  BB(CPGC,       _00001111)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4),                                                      VAL2(DYN_CPGC_CPGC_DPAT_INV_DC_MASK_LO),                          
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL4(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0xAA),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x80),                                                       
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL4(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL4(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x2),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000011), MASK2(0xFF80)            , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL2(0x3E00),                                                     
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x8)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x8),                                                        
  ASSIGNDONE,
  //
  // ENTER_CA_TRAININGa
  //
  xxxxx1xx                                      ,                VAL1(RDVLDCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000001)                           , AP(SET,       D_F_T),                   7,   FT(F_800,T_LPDDR3),                                               VAL2(DYN_DQCCC_RDVLDCTL_7),                                       FT(F_1066,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_8),                                       FT(F_1333,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_9),                                       FT(F_1600,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_10),                                      FT(F_1866,T_LPDDR3),                                              VAL2(DYN_DQCCC_RDVLDCTL_11),                                      FT(F_1066|F_1600|F_2133|F_3200,T_LPDDR4),                         VAL2(DYN_DQCCC_RDVLDCTL_12),                                      FT(F_2667,T_LPDDR4),                                              VAL2(DYN_DQCCC_RDVLDCTL_13),                                       // static_DIGREGS_m : 
  ASSIGNDONE,
  //
  // DRIVE_CKE
  //
  xxxxx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRMC),                                        
  ASSIGNDONE,
  //
  // CPGC_STOP_TEST
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  ASSIGNDONE,
  //
  // DQCALRD
  //
  xxxxx1xx                                      ,                VAL1(D_CR_DQCALRDATLO_DUNIT_REG)                     ,  BB(DUNIT,      _00001111)                           , AP(GET,       D____),                                                                                          VAL2(REG_DATA),                                                   
  ASSIGNDONE,
  //
  // ENABLE_CKE_OVERRIDE
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x13),                                                       
  ASSIGNDONE,
  //
  // EXIT_CA_TRAINING
  //
  xxxMx1xx                                      ,                VAL1(CCCCTL_DQCCC_REG)                               ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0xC0)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x40),                                                       
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x10),                                                       
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0xC)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x4),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000010), MASK1(0x3)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x3),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x8)               , AP(SET,       ____T),                   2,   T(T_LPDDR4),                                                      VAL1(0x8),                                                        T(T_LPDDR3),                                                      VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_INV_DC_MASK_LO_CPGC_REG)              ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL4(0x0),                                                        
  ASSIGNDONE,
  //
  // EXIT_CA_TRAININGa
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // CPGC_CA_VREF_EXIT
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // enable control during deselect
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // turn off always on
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                        // Setdirect mode
  ASSIGNDONE,
  //
  // PRECHARGEALL
  //
  xxxxx2xx                                      ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                        ,  BB(DUNIT,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRAM_CMD_1),                                  
  xxxxx2xx                                      ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                        ,  BB(DUNIT,      _00000111)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL3(0x1B),                                                       T(T_LPDDR4),                                                      VAL3(0x30),                                                        // precharge all 
  ASSIGNDONE,
  //
  // CPGC_TARGET_BANK
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)           ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A),                       
  ASSIGNDONE,
  //
  // CPGC_FIXVAR
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_SEQ_RANK_L2P_MAPPING_CPGC_REG)             ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_SEQ_RANK_L2P_MAPPING),                         
  ASSIGNDONE,
  //
  // CPGC_FIXVAR_REVERT
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                          VAL1(0x70),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)           ,  BB(CPGC,       _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_RANK_L2P_MAPPING_CPGC_REG)             ,  BB(CPGC,       _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // CPGC_MRS
  //
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CFG_CPGC_REG)                         ,  BB(CPGC,       _00000011), MASK2(0x333)             , AP(SET,       _____),                                                                                          VAL2(0x111),                                                       // pattern buff mode, pattern buff mode, pattern buff mode
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ0_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0xAAAA),                                                     
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ1_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0xCCCC),                                                     
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ2_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0xF0F0),                                                     
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x40),                                                        // MRS mode
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // set to always on mode
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_MRSCFG_CPGC_REG)                      ,  BB(CPGC,       _00001111), MASK4(0x3007071F)        , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         //  depending on #N mode, not working in RTL, used to strech CA
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_0_),                                  // 0xa4290
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                     ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                          VAL2(0x4F03),                                                      // Enable, set to 1, LP3: 0x2 = Rank0; 0x1 = Rank1
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0xA4290),                                                    
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                     ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                          VAL2(0x4F02),                                                      // Enable, set to 1, LP3: 0x2 = Rank0; 0x1 = Rank1
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_2_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_3_),                                 
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                     ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                          VAL2(0x4F03),                                                     
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                     ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                          VAL2(0x4F03),                                                     
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x1),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000001F4),
  ASSIGNDONE,
  //
  // CPGC_CA_TRAIN_DIS
  //
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0xA82A0),                                                     // training mode enable, MR41
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                     ,  BB(CPGC,       _00001000), MASK1(0x4F)              , AP(SET,       _____),                                                                                          VAL1(0x4F),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_MRSCFG_CPGC_REG)                      ,  BB(CPGC,       _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                     ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // CPGC_CA_TRAIN_EXIT
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                        // change to active mode
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // disable always on
  ASSIGNDONE,
  //
  // CPGC_RUN
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000001F4),
  ASSIGNDONE,
  //
  // CPGC_CADB1
  //
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x700FFFF),                                                   // CADB_BUFA0_BANK, CADB_BUFA0_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x5005555),                                                   // CADB_BUFA1_BANK, CADB_BUFA1_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x200AAAA),                                                   // CADB_BUFA2_BANK, CADB_BUFA2_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // CADB_BUFA3_BANK, CADB_BUFA3_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x700FFFF),                                                   // CADB_BUFA4_BANK, CADB_BUFA4_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x5005555),                                                   // CADB_BUFA5_BANK, CADB_BUFA5_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x200AAAA),                                                   // CADB_BUFA6_BANK, CADB_BUFA6_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x0),                                                         // CADB_BUFA7_BANK, CADB_BUFA7_ROW_COL
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000700),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000200),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000500),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000000),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_4__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000700),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_5__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000200),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_6__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000500),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFB_7__CPGC_REG)                     ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                          VAL4(0x40000000),                                                  // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00001111), MASK4(0xAFFFFFFF)        , AP(SET,       _____),                                                                                          VAL4(0x1C00),                                                      // 0, 0, 0, 0, 0, 0, 0, 7, 0, f, 1
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CFG_CPGC_REG)                         ,  BB(CPGC,       _00000011), MASK2(0x333)             , AP(SET,       _____),                                                                                          VAL2(0x222),                                                       // 2, 2, 2
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ0_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0x5D9),                                                       // 5d9
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ1_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0x71E),                                                       // 71e
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ2_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                          VAL2(0x0),                                                         // 0
  xxxMx1xx                                      ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)            ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                          VAL4(0x4C00000),                                                  
  xxxxx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_ADDRESS_SIZE),                                
  xxxxx1xx                                      ,                VAL1(CPGC2_ADDRESS_CONTROL_CPGC_REG)                 ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_ADDRESS_CONTROL),                             
  ASSIGNDONE,
  //
  // CPGC_CADB1_DIS
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // 1
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // 1
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x3C0),                                                       // 0, f, 1
  ASSIGNDONE,
  //
  // CPGC_DESELECT_DIS
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // 1
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // 1
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x3C0),                                                       // 0, f, 1
  xxxxx1xx                                      ,                VAL1(CPGC2_ADDRESS_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_CONTROL_CPGC_REG)                 ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                    ,  BB(CPGC,       _00001111), MASK4(0x1FFFF1FF)        , AP(SET,       _____),                                                                                          VAL4(0xC5270C5),                                                  
  xxxMx1xx                                      ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)            ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  ASSIGNDONE,
  //
  // CPGC_DESELECT_EN
  //
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                        // 1
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)   ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                        // 1
  xxxxx1xx                                      ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x7),                                                         // NUM_BURSTS
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x3D),                                                        // 0, f, 1
  xxxxx1xx                                      ,                VAL1(CPGC2_ADDRESS_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xC1),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                       
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                          VAL1(0x20),                                                       
  ASSIGNDONE,
  //
  // CPGC_CADB1_BUFA
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_0__1),                               
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_1_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_2__1),                               
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_3__1),                               
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_4_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_5_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_6_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFA_7_),                                 
  ASSIGNDONE,
  //
  // CPGC_CADB1_BUFB
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_0_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_1_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_2_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_3_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_4__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_4_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_5__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_5_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_6__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_6_),                                 
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_BUFB_7__CPGC_REG)                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_BUFB_7_),                                 
  ASSIGNDONE,
  //
  // CPGC_CWL_PATTERN
  //
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_0__1),                              // AGG_PATTERN
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_1_),                                // VIC_PATTERN
  ASSIGNDONE,
  //
  // LP4_FREQ_SWITCH
  //
  ASSIGNDONE,
  //
  // RCVEN_Copy
  //
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(RCVEN_RDPTR),                                                
  xxxxx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXODTCTL_DQ_4),                                    
  ASSIGNDONE,
  //
  // CPGC_EXIT_MRS
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // RMT_CLEAR_REGISTERS
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL),                                     
  ASSIGNDONE,
  //
  // RMT_GET_CMD_AND_VALUE
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL_1),                                   
  ASSIGNDONE,
  //
  // ConnectPmiToCpgc
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL_2),                                   
  ASSIGNDONE,
  //
  // CPGC_SETUP_LVL
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL_3),                                   
  ASSIGNDONE,
  //
  // CPGC_MPR_TRAINING
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL_4),                                   
  ASSIGNDONE,
  //
  // CPGC_RUNTEST_PARALLEL_CLEAR
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL_5),                                   
  ASSIGNDONE,
  //
  // CPGC_RUNTEST_PARALLEL_CHECK
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CTL_6),                                   
  ASSIGNDONE,
  //
  // CPGC_CADB_MODE
  //
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_CFG_CPGC_REG)                         ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_CFG),                                     
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ0_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_UNISEQ0_PBUF),                             // LDO_CADB_LFSR0
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ1_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_UNISEQ1_PBUF),                             // LDO_CADB_LFSR1
  xxxxx2xx                                      ,                VAL2(CPGC_CADB_UNISEQ2_PBUF_CPGC_REG)                ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_CADB_UNISEQ2_PBUF),                             // LDO_CADB_LFSR2
  ASSIGNDONE,
  //
  // CPGC_RESETUP_TRAFFIC
  //
  xxxxx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)        ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_),                    
  xxxMx1xx                                      ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_1__CPGC_REG)        ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                          VAL1(0x81),                                                        // can be removed, for safety
  xxxMx1xx                                      ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)          ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                        // can be removed, for safety
  ASSIGNDONE,
  //
  // CPGC_DPAT_MODE
  //
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_0__2),                             
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                   ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_1__1),                             
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_DPAT_CFG_1),                                   
  ASSIGNDONE,
  //
  // CPGC_LDO_CADB
  //
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x55555),                                                    
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0xAAAAA),                                                    
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0xFFFFF),                                                    
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x55555),                                                    
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0xAAAAA),                                                    
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0xFFFFF),                                                    
  ASSIGNDONE,
  //
  // CPGC_LDO_DPAT
  //
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xCC),                                                       
  ASSIGNDONE,
  //
  // CPGC_LDO_CADB_LFSR
  //
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x19),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x2A),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x33),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x34),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x2D),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x1E),                                                       
  xxxMx2xx                                      ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                     ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                          VAL3(0x7),                                                        
  ASSIGNDONE,
  //
  // CPGC_LDO_DPAT_LFSR
  //
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  xxxxx2xx                                      ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                  ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xAA),                                                       
  ASSIGNDONE,
  //
  // CPGC_RUN_TEST_L
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x4),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_ERR_CTL),                                      
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_LNEN_HI_CPGC_REG)                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_ERR_LNEN_HI),                                  
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                       ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(BYTEGRP_ERR_STAT),                                           
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)           ,  BB(CPGC,       _00000010)                           , AP(GET,       D____),                                                                                          VAL2(CHUNK_ERR_STAT),                                             
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_STAT03_CPGC_REG)                       ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                          VAL2(LANE_ERR_STAT_LO),                                           
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_STAT47_CPGC_REG)                       ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                          VAL2(LANE_ERR_STAT_HI),                                           
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)           ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(ECC_ERR_STAT),                                               
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_0__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT0),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_1__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT1),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_2__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT2),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_3__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT3),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_4__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT4),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_5__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT5),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_6__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT6),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_7__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT7),                                                 
  xxxMx2xx                                      ,                VAL2(CPGC_ERR_CNTR_8__CPGC_REG)                      ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                          VAL2(ERR_COUNT8),                                                 
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_START
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                          VAL1(0x13),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(TQPOLLEN_SAVE),                                              
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x60)              , AP(GET,       D____),                                                                                          VAL2(SRXZQC_SAVE),                                                
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(ZQDIS_SAVE),                                                 
  xxxMx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(OREFDIS_SAVE),                                               
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC0_DUNIT_REG)                           ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(DYNSREN_SAVE),                                               
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(DISPWRDN_SAVE),                                              
  xxxMx2xx                                      ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)              ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(DQS_RETAIN_EN_SAVE),                                         
  xxxMx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x61)              , AP(SET,       _____),                                                                                          VAL1(0x61),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC0_DUNIT_REG)                           ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxxx2xx                                      ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)              ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_1),                         // ame value as LPDDR4 MR23, 500ns? Chris Mozak. Should not larger than interval
  xxxMx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx2xx                                      ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)              ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_READ
  //
  xxxMx1xx                                      ,                VAL1(RDVLDCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                          VAL2(RDCMD2RDVLD),                                                
  xxxxx1xx                                      ,                VAL1(PTCTL0_DPLVUG_REG)                              ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_PTCTL0_1),                                        
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_MNT_DIS
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x10)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxxx1xx                                      ,                VAL1(D_CR_TQCTL_DUNIT_REG)                           ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_TQCTL_1),                                     
  xxxxx1xx                                      ,                VAL1(D_CR_DCAL_DUNIT_REG)                            ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DCAL_1),                                      
  xxxxx1xx                                      ,                VAL1(D_CR_DRFC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DRFC_1),                                      
  xxxxx1xx                                      ,                VAL1(D_CR_DPMC0_DUNIT_REG)                           ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DPMC0_1),                                     
  xxxxx1xx                                      ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DPMC1_1),                                     
  xxxxx2xx                                      ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)              ,  BB(DUNIT,      _00001101)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_2),                        
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_EN
  //
  xxxxx1xx                                      ,                VAL1(D_CR_DTR4A_DUNIT_REG)                           ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR4A_1),                                     
  xxxxx1xx                                      ,                VAL1(D_CR_DTR6A_DUNIT_REG)                           ,  BB(DUNIT,      _00000010)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_DTR6A_1),                                      // RL + tDQSCK +MRR/MRW BL/2 + 1
  xxxxx1xx                                      ,                VAL1(PTCTL0_DPLVUG_REG)                              ,  BB(DPLVUG,     _00001001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_PTCTL0_2),                                        
  ASSIGNDONE,
  //
  // RCVEN_ENTRY
  //
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(ODT_SEL_SAVE),                                               
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                          VAL2(ODT_VAL_SAVE),                                               
  xxxMx1xx                                      ,                VAL1(WKPUPPDNCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00000010), MASK1(0x3F)              , AP(GET,       D____),                                                                                          VAL2(WEAKPUP_SAVE),                                               
  xxxMx1xx                                      ,                VAL1(WKPUPPDNCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                          VAL2(WEAKPDN_SAVE),                                               
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(WKPUPPDNCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                          VAL2(0x707),                                                      
  ASSIGNDONE,
  //
  // RCVEN_EXIT
  //
  xxxxx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXODTCTL_DQ_5),                                    
  xxxxx1xx                                      ,                VAL1(WKPUPPDNCTL_DQCCC_REG)                          ,  BB(DQCCC,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_WKPUPPDNCTL),                                      
  ASSIGNDONE,
  //
  // CPGC_INIT
  //
  ASSIGNDONE,
  //
  // CPGC_UNI_LFSR_VICTIM_AGGRESSOR
  //
  ASSIGNDONE,
  //
  // CPGC_SETUP_VICTIM_AGGRESOR
  //
  ASSIGNDONE,
  //
  // CPGC_SETUP_ECC_INIT
  //
  ASSIGNDONE,
  //
  // CPGC_SETUP_MEMINIT_AND_TEST
  //
  ASSIGNDONE,
  //
  // CPGC_SETUP_2D_SWEEP
  //
  ASSIGNDONE,
  //
  // CPGC_SETUP_MPR_TRAINING
  //
  ASSIGNDONE,
  //
  // CPGC_RUNTEST
  //
  ASSIGNDONE,
  //
  // CPGC_CLEAR_ERRORS
  //
  ASSIGNDONE,
  //
  // RECEIVE_ENABLE_EXITx
  //
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP2CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXODTSEGCTL_DQ_4),                                 
  xxxxx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXODTCTL_DQ_6),                                    
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DIFFAMPCTL_DQ_5),                                  
  ASSIGNDONE,
  //
  // FINEWRITELEVEL_ENTRY
  //
  xxxxx1xx                                      ,                VAL1(WRDQCTL_DQCCC_REG)                              ,  BB(DQCCC,      _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0xFF),                                                       
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000110), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x11),                                                       
  ASSIGNDONE,
  //
  // FINEWRITELEVEL_EXIT
  //
  xxxxx1xx                                      ,                VAL1(WRDQCTL_DQCCC_REG)                              ,  BB(DQCCC,      _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x33),                                                       
  xxxMx1xx                                      ,                VAL1(WRDQSCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000110), MASK2(0x3FF)             , AP(SET,       _____),                                                                                          VAL2(0x355),                                                      
  ASSIGNDONE,
  //
  // FORCEODT_ON
  //
  ASSIGNDONE,
  //
  // FORCEODT_OFF
  //
  ASSIGNDONE,
  //
  // FORCEODT_REL
  //
  ASSIGNDONE,
  //
  // COARSEWRITELEVEL_ENTRY
  //
  ASSIGNDONE,
  //
  // COARSEWRITELEVEL_EXIT
  //
  ASSIGNDONE,
  //
  // EARLY_READ_TRAINING_ENTRY
  //
  ASSIGNDONE,
  //
  // EARLY_READ_TRAINING_EXIT
  //
  ASSIGNDONE,
  //
  // ENABLE_MPR_MODE
  //
  ASSIGNDONE,
  //
  // DISABLE_MPR_MODE
  //
  ASSIGNDONE,
  //
  // READTRAINING_ENTRY
  //
  xxxMx1xx                                      ,                VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100), MASK1(0x40)              , AP(SET,       _____),                                                                                          VAL1(0x40),                                                       
  xxxxx1xx                                      ,                VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0xFFFFFFFF),                                                 
  ASSIGNDONE,
  //
  // READTRAINING_EXIT
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                        ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                          VAL1(0x10),                                                       
  xxxMx1xx                                      ,                VAL1(D_CR_DTRC_DUNIT_REG)                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // WRITETRAINING_ENTRY
  //
  ASSIGNDONE,
  //
  // WRITETRAINING_EXIT
  //
  ASSIGNDONE,
  //
  // COMMANDCLOCKTRAINING_ENTRY
  //
  ASSIGNDONE,
  //
  // COMMANDCLOCKTRAINING_EXIT
  //
  ASSIGNDONE,
  //
  // CPGCSETUPFORCMD
  //
  ASSIGNDONE,
  //
  // CPGCSETUPCADB
  //
  ASSIGNDONE,
  //
  // RESETDRAMS
  //
  ASSIGNDONE,
  //
  // CPGC_RUNTEST_PARALLEL
  //
  ASSIGNDONE,
  //
  // CPGC_CHECK_ERR_PARALLEL
  //
  ASSIGNDONE,
  //
  // BREAKPOINTMRC
  //
  ASSIGNDONE,
  //
  // CPGC_PREPARE_PARALLEL
  //
  ASSIGNDONE,
  //
  // WRITE_SCRATCHPADS
  //
  xxxxx1xx                                      ,                VAL1(D_CR_SSKPD0_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_SSKPD0_1),                                    
  xxxxx1xx                                      ,                VAL1(D_CR_SSKPD1_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_SSKPD1),                                      
  ASSIGNDONE,
  //
  // READ_SCRATCHPADS
  //
  xxxxx1xx                                      ,                VAL1(D_CR_SSKPD0_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(GET,       D____),                                                                                          VAL2(SCRATCHPAD_VALUE0),                                          
  xxxxx1xx                                      ,                VAL1(D_CR_SSKPD1_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(GET,       D____),                                                                                          VAL2(SCRATCHPAD_VALUE1),                                          
  ASSIGNDONE,
  //
  // LDO_TRAIN_INIT
  //
  xxxxx1xx                                      ,                VAL1(TXPANIC_LDO_REG)                                ,  BB(LDO,        _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXPANIC),                                            
  xxxxx1xx                                      ,                VAL1(TXTCODE0_DVFS_LDO_REG)                          ,  BB(LDO,        _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x80000000),                                                 
  xxxxx1xx                                      ,                VAL1(TXTCODE1_DVFS_LDO_REG)                          ,  BB(LDO,        _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x80000000),                                                 
  xxxxx1xx                                      ,                VAL1(TXFB_LDO_REG)                                   ,  BB(LDO,        _00000111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFB),                                               
  xxxMx1xx                                      ,                VAL1(TXPANICCOMP_LDO_REG)                            ,  BB(LDO,        _00001111), MASK4(0x3F03FFF)         , AP(SET,       _____),                                                                                          VAL4(0x1501555),                                                  
  xxxxx1xx                                      ,                VAL1(TXFFDQ0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFDQ0_DVFS),                                       
  xxxxx1xx                                      ,                VAL1(TXFFDQ1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFDQ1_DVFS),                                       
  xxxxx1xx                                      ,                VAL1(TXFFCA0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFCA0_DVFS),                                       
  xxxxx1xx                                      ,                VAL1(TXFFCA1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFCA1_DVFS),                                       
  xxxMx1xx                                      ,                VAL1(TXFFDQ0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x4888888),                                                  
  xxxxx1xx                                      ,                VAL1(TXFFDQ1_DVFS_LDO_REG)                           ,  BB(LDO,        _00000111)                           , AP(SET,       _____),                                                                                          VAL3(0x888888),                                                   
  xxxMx1xx                                      ,                VAL1(TXFFCA0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x4888888),                                                  
  xxxMx1xx                                      ,                VAL1(TXFFCA1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                          VAL4(0x4888888),                                                  
  ASSIGNDONE,
  //
  // LDO_TRAIN_INITx
  //
  xxxMx1xx                                      ,                VAL1(TXSAOFFSET_LDO_REG)                             ,  BB(LDO,        _00001000), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // SET_CA_SCALE
  //
  xxxxx1xx                                      ,                VAL1(TXFFCA0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFCA0_DVFS_1),                                     
  xxxxx1xx                                      ,                VAL1(TXFFCA1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFCA1_DVFS_1),                                     
  ASSIGNDONE,
  //
  // SET_DQ_SCALE
  //
  xxxxx1xx                                      ,                VAL1(TXFFDQ0_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFDQ0_DVFS_1),                                     
  xxxxx1xx                                      ,                VAL1(TXFFDQ1_DVFS_LDO_REG)                           ,  BB(LDO,        _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFFDQ1_DVFS_1),                                     
  ASSIGNDONE,
  //
  // LDO_TRAIN_LOOP
  //
  xxxxx1xx                                      ,                VAL1(TXFB_LDO_REG)                                   ,  BB(LDO,        _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_LDO_TXFB_1),                                             
  ASSIGNDONE,
  //
  // VOC_TRAINING_ENTRY
  //
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Up_GRP0),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Dn_GRP0),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Up_GRP1),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Dn_GRP1),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Up_GRP2),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Dn_GRP2),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Up_GRP3),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Dn_GRP3),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Up_GRP4),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Dn_GRP4),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Up_GRP5),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Dn_GRP5),                                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_OVR_Up_En),                                            
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000010), MASK1(0x3F)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_OVR_Dn_En),                                            
  xxxMx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00001000), MASK1(0xE0)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Seg_Ovr_Val),                                          
  xxxMx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00001000), MASK1(0x10)              , AP(GET,       D____),                                                                                          VAL2(RCOMP_Seg_Ovr_En),                                           
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                          VAL2(DIFF_Ovr_Val),                                               
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                          VAL2(DIFF_Ovr_Val_sel),                                           
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                  ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                          VAL2(comp_vref_0),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                          VAL2(comp_vref_1),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                          VAL2(comp_vref_2),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                          VAL2(comp_vref_3),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                          VAL2(comp_vref_4),                                                
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                          VAL2(comp_vref_5),                                                
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(RX_ODTEN_OVR_SEL),                                           
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                          VAL2(RX_ODTEN_OVR_VAL),                                           
  xxxxx1xx                                      ,                VAL1(VREFCTL0_DQCCC_REG)                             ,  BB(DQCCC,      _00000001)                           , AP(GET,       D____),                                                                                          VAL2(RXCCVREFCTL),                                                
  xxxxx1xx                                      ,                VAL1(VREFCTL0_DQCCC_REG)                             ,  BB(DQCCC,      _00000010)                           , AP(GET,       D____),                                                                                          VAL2(RXBLVREFCTL),                                                
  ASSIGNDONE,
  //
  // VOC_GET_LDO_ENABLE
  //
  xxxMx1xx                                      ,                VAL1(TXFB_LDO_REG)                                   ,  BB(LDO,        _00000100), MASK1(0x4)               , AP(GET,       D____),                                                                                          VAL2(VOC_LDO_ENABLE),                                             
  ASSIGNDONE,
  //
  // VOC_PHY_ENTRY
  //
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                          VAL2(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00001000), MASK1(0xF0)              , AP(SET,       _____),                                                                                          VAL1(0x70),                                                        // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000), MASK1(0xC)               , AP(SET,       _____),                                                                                          VAL1(0xC),                                                        
  xxxMx1xx                                      ,                VAL1(OFFSETCNCLCTRL1_DQCCC_REG)                      ,  BB(DQCCC,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // VOC_COMP_VREF_AND_INIT
  //
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000010)                           , AP(SET_DELAY, D____), VAL4(0x00002710),                                                                        VAL2(DYN_DPLVUG_DPIC_GRCOMP_VREF_1),                              
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                    ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // VOC_GET_RCOMP_PUP_VALUE
  //
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                 ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                          VAL2(VOC_RCOMP_PUP),                                              
  ASSIGNDONE,
  //
  // VOC_GET_RCOMP_PDN_VALUE
  //
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                          VAL2(VOC_RCOMP_PDN),                                              
  ASSIGNDONE,
  //
  // VOC_SET_ODT_RCOMP_OVERRIDE
  //
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_4),                              
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                          VAL2(0x3F3F),                                                     
  ASSIGNDONE,
  //
  // VOC_ENABLE_WLMODE
  //
  xxxMx1xx                                      ,                VAL1(WRLVL_DQCCC_REG)                                ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // VOC_DISABLE_WLMODE
  //
  xxxMx1xx                                      ,                VAL1(WRLVL_DQCCC_REG)                                ,  BB(DQCCC,      _00001000), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // VOC_TRAINING_EXIT
  //
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_4),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_4),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                    ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_5),                              
  xxxxx1xx                                      ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_LRCOMP_PUPDOVR),                             
  xxxxx1xx                                      ,                VAL1(RXODTSEGCTL_DQ_DQCCC_REG)                       ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXODTSEGCTL_DQ_5),                                 
  xxxxx1xx                                      ,                VAL1(DIFFAMPCTL_DQ_DQCCC_REG)                        ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DIFFAMPCTL_DQ_6),                                  
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                  ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_GRCOMP_VREF_0),                              
  xxxxx1xx                                      ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPLVUG_DPIC_GRCOMP_VREF_1_1),                            
  xxxxx1xx                                      ,                VAL1(RXODTCTL_DQ_DQCCC_REG)                          ,  BB(DQCCC,      _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXODTCTL_DQ_7),                                    
  xxxxx1xx                                      ,                VAL1(VREFCTL0_DQCCC_REG)                             ,  BB(DQCCC,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_VREFCTL0),                                         
  ASSIGNDONE,
  //
  // CPGC_GET_TEST_RESULT
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                       ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(BYTEGRP_ERR_STAT),                                           
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)           ,  BB(CPGC,       _00000010)                           , AP(GET,       D____),                                                                                          VAL2(CHUNK_ERR_STAT),                                             
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_STAT03_CPGC_REG)                       ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                          VAL2(LANE_ERR_STAT_LO),                                           
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_STAT47_CPGC_REG)                       ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                          VAL2(LANE_ERR_STAT_HI),                                           
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)           ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                          VAL2(ECC_ERR_STAT),                                               
  ASSIGNDONE,
  //
  // CPGC_SET_CHUNK_MASK
  //
  xxxxx2xx                                      ,                VAL2(CPGC_ERR_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CPGC_CPGC_ERR_CTL_1),                                    
  ASSIGNDONE,
  //
  // CPGC_STOP_CLEAR_ERR
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                        VAL1(0x4),                                                        
  ASSIGNDONE,
  //
  // CPGC_START_TEST
  //
  xxxMx2xx                                      ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                          ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                        VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // CheckForWarmReset
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DSTAT_DUNIT_REG)                           ,  BB(DUNIT,      _00000010), MASK1(0x4)               , AP(GET,       D____),                                                                                          VAL2(DISR),                                                        // Was the DRAM in self refresh?
  xxxxx1xx                                      ,                VAL1(D_CR_SSKPD0_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(GET,       D____),                                                                                          VAL2(SSKPD0),                                                      // If 0, it means a warm reset occurred before MRC started. If 1, it means a warm reset occurred while MRC was running. If 2, a warm reset occurred after MRC was completed.
  ASSIGNDONE,
  //
  // xyz
  //
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00000011)                           , AP(SUBTASK,   _____),                                                                                          VAL2(InitDunit),                                                  
  ASSIGNDONE,
  //
  // InitDunitx
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DTR4A_DUNIT_REG)                           ,  BB(DUNIT,      _00000110), MASK2(0x3F0)             , AP(SET,       _____),                                                                                          VAL2(0x2C0),                                                      
  xxxMx1xx                                      ,                VAL1(D_CR_DTR5A_DUNIT_REG)                           ,  BB(DUNIT,      _00000111), MASK3(0x3E03F)           , AP(SET,       _____),                                                                                          VAL3(0x3E02C),                                                    
  ASSIGNDONE,
  //
  // InitDunitWakeRemove
  //
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // Wake the DRAMs (handle in punit)
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                         // Wait until DRAMs are awake
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // this should set in pcode
  ASSIGNDONE,
  //
  // DunitFreqChangePart1
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                         // Indicate we're waking from cold reset
  xxxMx1xx                                      ,                VAL1(D_CR_DPMC0_DUNIT_REG)                           ,  BB(DUNIT,      _00001000), MASK1(0x1F)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x4),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                         // Poll for the bit to go to zero
  ASSIGNDONE,
  //
  // ChangePHYFreq
  //
  ASSIGNDONE,
  //
  // DunitFreqChangePart3
  //
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                         // Wake the DRAMs (handle in punit)
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                         // Wait until DRAMs are awake
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET_DELAY, ____T), VAL4(0x000000C8), 1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                         // Done with cold wake
  ASSIGNDONE,
  //
  // MmapBeforeTrain
  //
  xxxMx1xx                                      ,                VAL1(TOLUD_0_0_0_PCI_CUNIT_REG)                      ,  BB(CUNIT,      _00001100), MASK2(0xFFF0)            , AP(SET,       _____),                                                                                          VAL2(0xE000),                                                     
  ASSIGNDONE,
  //
  // SetICBitDone
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DCO_DUNIT_REG)                             ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // ProgamFinalSettingsx
  //
  xxxME2xx          , VAL2(BXT_A0_WA)           ,                VAL2(D_CR_PGCB_CG_IDLE_TIMER_DUNIT_REG)              ,  BB(DUNIT,      _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x6),                                                         // Not a W/A
  xxxME1xx          , VAL2(BXT_A0_PO)           ,                VAL1(D_CR_DPMC1_DUNIT_REG)                           ,  BB(DUNIT,      _00000001), MASK1(0x6)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // ReadFuses
  //
  xxxxx1xx                                      ,                VAL1(D_CR_DFUSESTAT_DUNIT_REG)                       ,  BB(DUNIT,      _00000011)                           , AP(GET,       D____),                                                                                          VAL2(FUSESTAT),                                                   
  ASSIGNDONE,
  //
  // EnableScrambling
  //
  xxxxx1xx                                      ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                       ,  BB(DUNIT,      _00001011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DUNIT_D_CR_SCRAMCTRL),                                    // Random Number, Enable Bit
  ASSIGNDONE,
  //
  // SetMrcDoneRemove
  //
  xxxMx1xx                                      ,                VAL1(D_CR_DRMC_DUNIT_REG)                            ,  BB(DUNIT,      _00000100), MASK1(0x4)               , AP(SET,       _____),                                                                                          VAL1(0x4),                                                        
  ASSIGNDONE,
  //
  // SetMrcDonex
  //
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _P___),                   1,   P(P_SIM),                                                         VAL1(0x1),                                                         // this should set in pcode
  ASSIGNDONE,
  //
  // ReadBarAddress
  //
  xxxMx1xx                                      ,                VAL1(MCHBAR_LO_0_0_0_PCI_CUNIT_REG)                  ,  BB(CUNIT,      _00001110), MASK3(0xFFFF80)          , AP(GET,       D____),                                                                                          VAL2(MCHBAR),                                                      // Read mchbar address
  xxxxx1xx                                      ,                VAL1(BASE_ADDRESS_LO_P2SB_REG)                       ,  BB(P2SB,       _00001000)                           , AP(GET,       D____),                                                                                          VAL2(P2SBBAR),                                                     // Read PHY base adress
  xxxMx1xx                                      ,                VAL1(PCIEXBAR_LO_0_0_0_PCI_CUNIT_REG)                ,  BB(CUNIT,      _00001000), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(ECBASE_LO),                                                   // Read EC Base LO
  xxxMx1xx                                      ,                VAL1(PCIEXBAR_LO_0_0_0_PCI_CUNIT_REG)                ,  BB(CUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                          VAL2(ECBASE_EN),                                                   // Read EC Base EN
  xxxMx1xx                                      ,                VAL1(PCIEXBAR_HI_0_0_0_PCI_CUNIT_REG)                ,  BB(CUNIT,      _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                          VAL2(ECBASE_HI),                                                   // Read EC Base HI
  ASSIGNDONE,
  //
  // WriteMchBarAddress
  //
  xxxxx1xx                                      ,                VAL1(MCHBAR_LO_0_0_0_PCI_CUNIT_REG)                  ,  BB(CUNIT,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CUNIT_MCHBAR_LO_0_0_0_PCI),                               // Write mchbar address, Enable MchBar
  ASSIGNDONE,
  //
  // WriteBarAddress
  //
  xxxxx1xx                                      ,                VAL1(BASE_ADDRESS_LO_P2SB_REG)                       ,  BB(P2SB,       _00001000)                           , AP(SET,       D____),                                                                                          VAL2(DYN_P2SB_BASE_ADDRESS_LO),                                    // Write PHY base adress
  xxxxx1xx                                      ,                VAL1(BASE_ADDRESS_HI_P2SB_REG)                       ,  BB(P2SB,       _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(PCICMD_P2SB_REG)                                ,  BB(P2SB,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                        
  ASSIGNDONE,
  //
  // WritePCIEXBAR
  //
  xxxxx1xx                                      ,                VAL1(PCIEXBAR_LO_0_0_0_PCI_CUNIT_REG)                ,  BB(CUNIT,      _00001001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_CUNIT_PCIEXBAR_LO_0_0_0_PCI),                             // Write EC Base LO, Write EC Base EN
  xxxMx1xx                                      ,                VAL1(PCIEXBAR_HI_0_0_0_PCI_CUNIT_REG)                ,  BB(CUNIT,      _00000001), MASK1(0x7F)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // Write EC Base HI
  ASSIGNDONE,
  //
  // SetAunitSliceChannel
  //
  xBxMx2xx                                      ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG) , BB2(AUNIT,      _00010000), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // LockAunitSliceChannel
  //
  xBxMx2xx                                      ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG) , BB2(AUNIT,      _10000000), MASK1(0x80)              , AP(SET,       _____),                                                                                          VAL1(0x80),                                                       
  ASSIGNDONE,
  //
  // InitDunitWakeS0
  //
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // Wake the DRAMs (handle in punit)
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                         // Wait until DRAMs are awake
  xxxMx2xx                                      ,                VAL2(MLM_CR_MISC_MLMC_REG)                           ,  BB(MLMC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // set to 0
  ASSIGNDONE,
  //
  // MRC_to_Tap_CWL
  //
  xxxxx2xx                                      ,                VAL2(PUNIT_TAP_DUNIT_REG)                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x2),                                                        
  ASSIGNDONE,
  //
  // S0_fixes_GET
  //
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes0),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000001), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes1),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes2),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000010), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes3),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes4),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes5),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes6),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001000), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes7),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  0)      , VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100), MASK1(0x40)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes8),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes9),                                                  
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000001), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes10),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes11),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000010), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes12),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes13),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00000100), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes14),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001000), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(S0_Fixes15),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001000), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes16),                                                 
  xxNMx1xx, xxxxxxIx                            , _I(  1)      , VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100), MASK1(0x40)              , AP(GET,       D____),                                                                                          VAL2(S0_Fixes17),                                                 
  ASSIGNDONE,
  //
  // S0_fixes_SET
  //
  xxNxx1xx, xxxxxxIx                            , _I(  0)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXPBDBLCTL),                                       
  xxNxx1xx, xxxxxxIx                            , _I(  0)      , VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_TXPBDCTL1),                                        
  xxNxx1xx, xxxxxxIx                            , _I(  1)      , VAL1(RXPBDBLCTL_DQCCC_REG)                           ,  BB(DQCCC,      _00001111)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_RXPBDBLCTL_1),                                     
  xxNxx1xx, xxxxxxIx                            , _I(  1)      , VAL1(TXPBDCTL1_DQCCC_REG)                            ,  BB(DQCCC,      _00000100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_TXPBDCTL1_1),                                      
  ASSIGNDONE,
  //
  // InitDunitWakeS0pt1
  //
  xxxMx2xx                                      ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                     ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // Wake the DRAMs (handle in punit)
  ASSIGNDONE,
  //
  // ToggleBGF_RUN
  //
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET_DELAY, ____T), VAL4(0x000003E8), 1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                         ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3_seq_from_7
  //
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP0CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000100)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x29),                                                        // static_DIGREGS : 
  ASSIGNDONE,
  //
  // xxxx
  //
  xxxMx1xx                                      ,                VAL1(TXDLLCTL_DQ_REG)                                ,  BB(DQ,         _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_TXDLLCTL : , static_TXDLLCTL : 
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DLLCOMP_FBMUXSEL),                                 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_CODE_STATUS_DQCCC_REG)                  ,  BB(DQCCC,      _00000010), MASK1(0xF0)              , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  xxxxx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00001100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPIC_PLLCTL),                                            
  ASSIGNDONE,
  //
  // modmem_s0ix_entry_m_seq
  //
  xxxxx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000010)                           , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx2xx                                      ,                VAL2(DPIC_PM_PGOVR_DPIC_REG)                         ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                        
  xxxMx1xx                                      ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // // Enable Isolation from LVUG
  xxxMx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // // Gated Power Mux: vnn = ON, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = OFF, // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx1xx                                      ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                        ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Disable Isolation from LVUG
  xxxxx2xx                                      ,                VAL2(DPIC_PM_CONFIG0_DPIC_REG)                       ,  BB(DPIC,       _00000010)                           , AP(SET,       _____),                                                                                          VAL1(0xFF),                                                        // // stagger enable VNN, // Gated Power Mux: vnn = ON, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_lp4_freq_switch_seq
  //
  xxxMx1xx                                      ,                VAL1(DIGRSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Assert SPID RSTB
  xxxMx1xx                                      ,                VAL1(TXDLLCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Disable DLL and assert reset to Tx Dcomp and DLL Dcomp
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RESET_DQCCC_REG)                        ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Assert DLLCOMP RSTB
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_RSTCTL_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Assert TX DLL RSTB
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // // Disable PLL
  xxxMx1xx                                      ,                VAL1(SPIDCLKCTL0_DPIC_REG)                           ,  BB(DPIC,       _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   11,   FT(F_800,T_LPDDR3),                                               VAL1(0xC),                                                        FT(F_1066,T_LPDDR3),                                              VAL1(0x10),                                                       FT(F_1333,T_LPDDR3),                                              VAL1(0x14),                                                       FT(F_1600,T_LPDDR3),                                              VAL1(0x18),                                                       FT(F_1866,T_LPDDR3),                                              VAL1(0x1C),                                                       FT(F_1066,T_LPDDR4),                                              VAL1(0x8),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0xC),                                                        FT(F_2133,T_LPDDR4),                                              VAL1(0x10),                                                       FT(F_2667,T_LPDDR4),                                              VAL1(0x14),                                                       FT(F_2933,T_LPDDR4),                                              VAL1(0x16),                                                       FT(F_3200,T_LPDDR4),                                              VAL1(0x18),                                                        // // Configure PLL for POR frequency// modmem_fbdiv_prog_seq// USYNC counter setting for operating freq
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // // Enable PLL
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x0009FBF1),
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(POLL,      _____),                                                                                          VAL1(0x2),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(SET,       __F__),                   8,   F(F_800),                                                         VAL1(0x19),                                                       F(F_1066),                                                        VAL1(0x13),                                                       F(F_1333),                                                        VAL1(0x10),                                                       F(F_1600),                                                        VAL1(0xD),                                                        F(F_1866),                                                        VAL1(0xB),                                                        F(F_2133),                                                        VAL1(0x9),                                                        F(F_2667),                                                        VAL1(0x7),                                                        F(F_2933|F_3200),                                                 VAL1(0x6),                                                         // //Configure DLL for final operating frequency
  xxxMx2xx                                      ,                VAL2(DLLCOMP_SAMPLEWAIT_DQCCC_REG)                   ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(SET,       __F_T),                   6,   FT(F_800,T_LPDDR3),                                               VAL1(0x8),                                                        FT(F_1066|F_1333,T_LPDDR3),                                       VAL1(0x7),                                                        FT(F_1600|F_1866,T_LPDDR3),                                       VAL1(0x6),                                                        FT(F_1066,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_1600|F_2133,T_LPDDR4),                                       VAL1(0x6),                                                        FT(F_2667|F_2933|F_3200,T_LPDDR4),                                VAL1(0x5),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RESET_DQCCC_REG)                        ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // // Deassert DLLCOMP RSTB
  xxxMx1xx                                      ,                VAL1(DPIC_LRCOMP_RSTCTL_DPLVUG_REG)                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // // Deassert TX DLL RSTB
  xxxMx1xx                                      ,                VAL1(TXDLLCTL_DQCCC_REG)                             ,  BB(DQCCC,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // // Enable DLL
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_TXDLYCOMP_INIT_m : // TX and DLL COMP init
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DLLCOMP_INIT_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                        
  xxxMx1xx                                      ,                VAL1(DIGRSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                          VAL1(0x3),                                                         // // Deassert SPID RSTB
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // modmem_init_lpddrgrp6_seq: static_TXDLYCOMP_INIT_m : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // modmem_init_lpddrgrp6_seq: static_DLLCOMP_INIT_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x0000000A),
  xxxMx1xx                                      ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                 ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                         // modmem_init_lpddrgrp7_seq
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                          VAL1(0x0),                                                         // modmem_init_lpddrgrp7_seq
  xxxMx1xx                                      ,                VAL1(DIGRSTCTL_DQCCC_REG)                            ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // Deassert SPID RSTB
  ASSIGNDONE,
  //
  // modmem_ldo_offsetcomp_poll_seq
  //
  xxxMx1xx                                      ,                VAL1(TXSAOFFSET_LDO_REG)                             ,  BB(LDO,        _00001000), MASK1(0x1)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                      VAL1(0x0),                                                        
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp0m_seq
  //
  xxxxx1xx                                      ,                VAL1(SAI_CTRL_REG0_DDRSAI_REG)                       ,  BB(DDRSAI,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x41200200),                                                 
  xxxxx1xx                                      ,                VAL1(SAI_CTRL_REG0_1_DDRSAI_REG)                     ,  BB(DDRSAI,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x400),                                                      
  xxxxx1xx                                      ,                VAL1(SAI_RW_REG0_DDRSAI_REG)                         ,  BB(DDRSAI,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x41200200),                                                 
  xxxxx1xx                                      ,                VAL1(SAI_RW_REG0_1_DDRSAI_REG)                       ,  BB(DDRSAI,     _00001111)                           , AP(SET,       _____),                                                                                          VAL4(0x400),                                                      
  ASSIGNDONE,
  //
  // maxpi_dll_init
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_INIT_DQCCC_REG)                         ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DLLCOMP_INIT_m : 
  xxxxx1xx                                      ,                VAL1(0xFF)                                           ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00003E80),
  ASSIGNDONE,
  //
  // maxpi_override_coarse_init
  //
  xxxMx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00001100), MASK2(0x1F0)             , AP(SET,       _____),                                                                                          VAL2(0xF0),                                                       
  xxxMx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00001000), MASK1(0x4F)              , AP(SET,       _____),                                                                                          VAL1(0x4F),                                                       
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(SET,       __F__),                   9,   F(F_800),                                                         VAL1(0x19),                                                       F(F_1066),                                                        VAL1(0x13),                                                       F(F_1333),                                                        VAL1(0x10),                                                       F(F_1600),                                                        VAL1(0x10),                                                       F(F_1866),                                                        VAL1(0xE),                                                        F(F_2133),                                                        VAL1(0xC),                                                        F(F_2667),                                                        VAL1(0xA),                                                        F(F_2933),                                                        VAL1(0x9),                                                        F(F_3200),                                                        VAL1(0x8),                                                         // static_5 : 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000001), MASK1(0x1F)              , AP(SET,       __F_T),                   10,   FT(F_800,T_LPDDR3),                                               VAL1(0x17),                                                       FT(F_1066,T_LPDDR3),                                              VAL1(0x11),                                                       FT(F_1333,T_LPDDR3),                                              VAL1(0xE),                                                        FT(F_1600,T_LPDDR3|T_LPDDR4),                                     VAL1(0xE),                                                        FT(F_1866,T_LPDDR3),                                              VAL1(0xB),                                                        FT(F_1066,T_LPDDR4),                                              VAL1(0x12),                                                       FT(F_2133,T_LPDDR4),                                              VAL1(0xA),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_2933,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x6),                                                         // static_5 : 
  ASSIGNDONE,
  //
  // maxpi_set_codes
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RESET_DQCCC_REG)                        ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                        
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DLLCOMP_FBMUXSEL_1),                               
  xxxxx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DLLCOMP_COARSECODE),                               
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINECODE_DQCCC_REG)                     ,  BB(DQCCC,      _00000011)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DLLCOMP_FINECODE),                                 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_RESET_DQCCC_REG)                        ,  BB(DQCCC,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                        
  ASSIGNDONE,
  //
  // maxpi_get_codes
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000010), MASK1(0x1F)              , AP(GET,       D____),                                                                                          VAL2(MUX_MAX),                                                    
  xxxMx2xx                                      ,                VAL2(DLLCOMP_FBMUXSEL_DQCCC_REG)                     ,  BB(DQCCC,      _00000001), MASK1(0x1F)              , AP(GET,       D____),                                                                                          VAL2(MUX_MIN),                                                    
  xxxMx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(COARSE_MAX),                                                 
  xxxMx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00000001), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(COARSE_MIN),                                                 
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINECODE_DQCCC_REG)                     ,  BB(DQCCC,      _00001000)                           , AP(GET,       D____),                                                                                          VAL2(FINE_SOFT_MAX),                                              
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINECODE_DQCCC_REG)                     ,  BB(DQCCC,      _00000100)                           , AP(GET,       D____),                                                                                          VAL2(FINE_SOFT_MIN),                                              
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINECODE_DQCCC_REG)                     ,  BB(DQCCC,      _00000010)                           , AP(GET,       D____),                                                                                          VAL2(FINE_MAX),                                                   
  xxxxx2xx                                      ,                VAL2(DLLCOMP_FINECODE_DQCCC_REG)                     ,  BB(DQCCC,      _00000001)                           , AP(GET,       D____),                                                                                          VAL2(FINE_MIN),                                                   
  ASSIGNDONE,
  //
  // maxpi_override_coarse_final
  //
  xxxMx2xx                                      ,                VAL2(DLLCOMP_CODE_STATUS_DQCCC_REG)                  ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                          VAL2(SS_TEMP_VAR),                                                
  xxxxx1xx                                      ,                VAL1(PLLCTL_DPIC_REG)                                ,  BB(DPIC,       _00001100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DPIC_PLLCTL_1),                                          
  xxxxx2xx                                      ,                VAL2(DLLCOMP_COARSECODE_DQCCC_REG)                   ,  BB(DQCCC,      _00001100)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_DLLCOMP_COARSECODE_1),                             
  ASSIGNDONE,
  //
  // modmem_init_progcmdckctl_seq
  //
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x3F)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x30),                                                        // static_DIGREGS : , static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x1),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       __F_T),                   9,   FT(F_800,T_LPDDR3),                                               VAL1(0x71),                                                       FT(F_1066,T_LPDDR3),                                              VAL1(0x57),                                                       FT(F_1333,T_LPDDR3),                                              VAL1(0x47),                                                       FT(F_1600,T_LPDDR3),                                              VAL1(0x3D),                                                       FT(F_1866,T_LPDDR3),                                              VAL1(0x36),                                                       FT(F_1600,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_2133,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x5),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       __F__),                   5,   F(F_800),                                                         VAL1(0x6D),                                                       F(F_1066),                                                        VAL1(0x53),                                                       F(F_1333),                                                        VAL1(0x43),                                                       F(F_1600),                                                        VAL1(0x39),                                                       F(F_1866),                                                        VAL1(0x31),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0x30)              , AP(SET,       _____),                                                                                          VAL1(0x30),                                                                                                                         VAL1(0x30),                                                        // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000010), MASK1(0xF)               , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                      VAL1(0x0),                                                        T(T_LPDDR4),                                                      VAL1(0x0),                                                         // static_DIGREGS : 
  xxxMx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQ_REG)                         ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                          VAL1(0x2),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       __F_T),                   9,   FT(F_800,T_LPDDR3),                                               VAL1(0x5),                                                        FT(F_1066,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1333,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1600,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1866,T_LPDDR3),                                              VAL1(0x5),                                                        FT(F_1600,T_LPDDR4),                                              VAL1(0x7),                                                        FT(F_2133,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_2667,T_LPDDR4),                                              VAL1(0x5),                                                        FT(F_3200,T_LPDDR4),                                              VAL1(0x5),                                                         // static_DIGREGS : 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQ_REG)                         ,  BB(DQ,         _00000001)                           , AP(SET,       __F__),                   5,   F(F_800),                                                         VAL1(0x5),                                                        F(F_1066),                                                        VAL1(0x5),                                                        F(F_1333),                                                        VAL1(0x5),                                                        F(F_1600),                                                        VAL1(0x5),                                                        F(F_1866),                                                        VAL1(0x5),                                                         // static_DIGREGS : 
  ASSIGNDONE,
  //
  // maxpi_read_value
  //
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(GET,       D____),                                                                                          VAL2(MAXPI_GRP5),                                                 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(GET,       D____),                                                                                          VAL2(MAXPI_GRP4),                                                 
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(GET,       D____),                                                                                          VAL2(MAXPI_GRP3),                                                 
  ASSIGNDONE,
  //
  // maxpi_write_value
  //
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP5CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_TXDLLSIGGRP5CTL),                                  
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP4CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_TXDLLSIGGRP4CTL),                                  
  xxxxx1xx                                      ,                VAL1(TXDLLSIGGRP3CTL_DQCCC_REG)                      ,  BB(DQCCC,      _00000001)                           , AP(SET,       D____),                                                                                          VAL2(DYN_DQCCC_TXDLLSIGGRP3CTL),                                  
  ASSIGNDONE,
};

MMRC_STATUS
DynamicAssignmentGenerated (
  IN  OUT   UINT32        DynamicVars[MAX_CHANNELS][DYNVAR_MAX],
  IN        UINT8         Channel,
  IN        UINT16        Index,
  IN        UINTX        *Value
)
{
  P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_STRUCT *DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR;
  PTCTL0_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_PTCTL0;
  WRDQSCTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_WRDQSCTL;
  RDVLDCTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RDVLDCTL;
  RK2RKCTL0_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RK2RKCTL0;
  RXDLLRDCMDCTL0_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0;
  RXODTSEGCTL_CC_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RXODTSEGCTL_CC;
  RXODTSEGCTL_DQ_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ;
  RXODTCTL_CC_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RXODTCTL_CC;
  RXODTCTL_DQ_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RXODTCTL_DQ;
  RCVENCTL_CC_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RCVENCTL_CC;
  RCVENCTL_DQ_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RCVENCTL_DQ;
  DIFFAMPCTL_CC_DQCCC_STRUCT *DYNSTRUCT_DQCCC_DIFFAMPCTL_CC;
  DIFFAMPCTL_DQ_DQCCC_STRUCT *DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ;
  DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1;
  DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2;
  DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3;
  D_CR_DRP0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRP0;
  D_CR_DTR0A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR0A;
  D_CR_DTR1A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR1A;
  D_CR_DTR2A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR2A;
  D_CR_DTR3A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR3A;
  D_CR_DTR4A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR4A;
  D_CR_DTR5A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR5A;
  D_CR_DTR6A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR6A;
  D_CR_DTR7A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR7A;
  D_CR_DTR8A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR8A;
  D_CR_SSKPD0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_SSKPD0;
  D_CR_BONUS0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BONUS0;
  D_CR_BONUS1_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BONUS1;
  D_CR_MR4_DESWIZZLE_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE;
  D_CR_BGF_CTL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BGF_CTL;
  D_CR_DPMC0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DPMC0;
  D_CR_DPMC1_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DPMC1;
  D_CR_DRFC_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRFC;
  D_CR_DSCH_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DSCH;
  D_CR_DCAL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DCAL;
  D_CR_TQCTL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_TQCTL;
  D_CR_TQOFFSET_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_TQOFFSET;
  D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL;
  MLM_CR_CONFIG_MLMC_STRUCT *DYNSTRUCT_MLMC_MLM_CR_CONFIG;
  MLM_CR_FM_CONFIG_MLMC_STRUCT *DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG;
  TXDLLSIGGRP2CTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_TXDLLSIGGRP2CTL;
  D_CR_DRAM_CMD_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRAM_CMD;
  CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_;
  CPGC2_BASE_REPEATS_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS;
  CPGC2_BLOCK_REPEATS_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS;
  WRLVL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_WRLVL;
  WRLVL_CCC_STRUCT *DYNSTRUCT_CCC_WRLVL;
  CPGC_DPAT_XTRA_LFSR_CFG_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_XTRA_LFSR_CFG;
  CPGC_DPAT_CFG_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_CFG;
  CPGC_DPAT_INV_DC_MASK_LO_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_INV_DC_MASK_LO;
  D_CR_DRMC_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRMC;
  CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A;
  CPGC_SEQ_RANK_L2P_MAPPING_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_SEQ_RANK_L2P_MAPPING;
  CPGC_CADB_BUFA_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_;
  CPGC_CADB_BUFA_2__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_;
  CPGC_CADB_BUFA_3__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_;
  CPGC2_ADDRESS_SIZE_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE;
  CPGC2_ADDRESS_CONTROL_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_ADDRESS_CONTROL;
  CPGC_CADB_BUFA_1__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_;
  CPGC_CADB_BUFA_4__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_;
  CPGC_CADB_BUFA_5__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_;
  CPGC_CADB_BUFA_6__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_;
  CPGC_CADB_BUFA_7__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_;
  CPGC_CADB_BUFB_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_;
  CPGC_CADB_BUFB_1__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_;
  CPGC_CADB_BUFB_2__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_;
  CPGC_CADB_BUFB_3__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_;
  CPGC_CADB_BUFB_4__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_;
  CPGC_CADB_BUFB_5__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_;
  CPGC_CADB_BUFB_6__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_;
  CPGC_CADB_BUFB_7__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_;
  CPGC_DPAT_UNISEQ_1__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_;
  CPGC_CADB_CTL_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_CTL;
  CPGC_CADB_CFG_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_CFG;
  CPGC_CADB_UNISEQ0_PBUF_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ0_PBUF;
  CPGC_CADB_UNISEQ1_PBUF_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ1_PBUF;
  CPGC_CADB_UNISEQ2_PBUF_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ2_PBUF;
  CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_;
  CPGC_ERR_CTL_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_ERR_CTL;
  CPGC_ERR_LNEN_HI_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_ERR_LNEN_HI;
  WKPUPPDNCTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_WKPUPPDNCTL;
  D_CR_SSKPD1_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_SSKPD1;
  TXPANIC_LDO_STRUCT *DYNSTRUCT_LDO_TXPANIC;
  TXFB_LDO_STRUCT *DYNSTRUCT_LDO_TXFB;
  TXFFDQ0_DVFS_LDO_STRUCT *DYNSTRUCT_LDO_TXFFDQ0_DVFS;
  TXFFDQ1_DVFS_LDO_STRUCT *DYNSTRUCT_LDO_TXFFDQ1_DVFS;
  TXFFCA0_DVFS_LDO_STRUCT *DYNSTRUCT_LDO_TXFFCA0_DVFS;
  TXFFCA1_DVFS_LDO_STRUCT *DYNSTRUCT_LDO_TXFFCA1_DVFS;
  DPIC_GRCOMP_VREF_1_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1;
  DPIC_LRCOMP_PUPDOVR_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR;
  DPIC_GRCOMP_VREF_0_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0;
  VREFCTL0_DQCCC_STRUCT *DYNSTRUCT_DQCCC_VREFCTL0;
  D_CR_SCRAMCTRL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL;
  MCHBAR_LO_0_0_0_PCI_CUNIT_STRUCT *DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI;
  BASE_ADDRESS_LO_P2SB_STRUCT *DYNSTRUCT_P2SB_BASE_ADDRESS_LO;
  PCIEXBAR_LO_0_0_0_PCI_CUNIT_STRUCT *DYNSTRUCT_CUNIT_PCIEXBAR_LO_0_0_0_PCI;
  RXPBDBLCTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_RXPBDBLCTL;
  TXPBDCTL1_DQCCC_STRUCT *DYNSTRUCT_DQCCC_TXPBDCTL1;
  DLLCOMP_FBMUXSEL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL;
  PLLCTL_DPIC_STRUCT *DYNSTRUCT_DPIC_PLLCTL;
  DLLCOMP_COARSECODE_DQCCC_STRUCT *DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE;
  DLLCOMP_FINECODE_DQCCC_STRUCT *DYNSTRUCT_DQCCC_DLLCOMP_FINECODE;
  TXDLLSIGGRP5CTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_TXDLLSIGGRP5CTL;
  TXDLLSIGGRP4CTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_TXDLLSIGGRP4CTL;
  TXDLLSIGGRP3CTL_DQCCC_STRUCT *DYNSTRUCT_DQCCC_TXDLLSIGGRP3CTL;

  switch (Index) {
  case DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR:
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR = (P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_STRUCT *) Value;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch3_active = DynamicVars[Channel][FM_CH3];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch2_active = DynamicVars[Channel][FM_CH2];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch1_active = DynamicVars[Channel][FM_CH1];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch0_active = DynamicVars[Channel][FM_CH0];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.wio_only = 0x0;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_type_special = 0x0;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_type = DynamicVars[Channel][PUNIT_REQ_TYPE];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_data = DynamicVars[Channel][PUNIT_REQ_DATA];
    break;
  case DYN_DPLVUG_PTCTL0:
    DYNSTRUCT_DPLVUG_PTCTL0 = (PTCTL0_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL]/4) - 1;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.rk1initialindex = 0x0;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.rk0initialindex = 0x0;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.ptloadcode_dly = 0x3;
    break;
  case DYN_DQCCC_WRDQSCTL:
    DYNSTRUCT_DQCCC_WRDQSCTL = (WRDQSCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_WRDQSCTL->Bits.wrcmd2dqsstart = DynamicVars[Channel][WL]-2;
    break;
  case DYN_DQCCC_WRDQSCTL_1:
    DYNSTRUCT_DQCCC_WRDQSCTL = (WRDQSCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_WRDQSCTL->Bits.wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_DQCCC_WRDQSCTL_2:
    DYNSTRUCT_DQCCC_WRDQSCTL = (WRDQSCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_WRDQSCTL->Bits.wrcmd2dqsstart = (DynamicVars[Channel][WL]-3+3-1);
    break;
  case DYN_DQCCC_WRDQSCTL_3:
    DYNSTRUCT_DQCCC_WRDQSCTL = (WRDQSCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_WRDQSCTL->Bits.wrcmd2dqsstart = (DynamicVars[Channel][WL]-6+3-1);
    break;
  case DYN_DQCCC_RDVLDCTL:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = (DynamicVars[Channel][RL]/2);
    break;
  case DYN_DQCCC_RDVLDCTL_1:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+8)/2-4);
    break;
  case DYN_DQCCC_RDVLDCTL_2:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+9)/2-4);
    break;
  case DYN_DQCCC_RDVLDCTL_3:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+10)/2-4);
    break;
  case DYN_DQCCC_RDVLDCTL_4:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = (1+DynamicVars[Channel][RL]/2);
    break;
  case DYN_DQCCC_RDVLDCTL_5:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4));
    break;
  case DYN_DQCCC_RDVLDCTL_6:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4)-1);
    break;
  case DYN_DQCCC_RK2RKCTL0:
    DYNSTRUCT_DQCCC_RK2RKCTL0 = (RK2RKCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-3;
    DYNSTRUCT_DQCCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQCCC_RK2RKCTL0_1:
    DYNSTRUCT_DQCCC_RK2RKCTL0 = (RK2RKCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = (DynamicVars[Channel][WL]-4-1+3);
    DYNSTRUCT_DQCCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3+3;
    break;
  case DYN_DQCCC_RK2RKCTL0_2:
    DYNSTRUCT_DQCCC_RK2RKCTL0 = (RK2RKCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = (DynamicVars[Channel][WL]-7-1+3);
    DYNSTRUCT_DQCCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-6+3;
    break;
  case DYN_DQCCC_RXDLLRDCMDCTL0:
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rdcmd2rxdllupdt = DynamicVars[Channel][RL]-1;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rxdllupdtlen = 0x0;
    break;
  case DYN_DQCCC_RXDLLRDCMDCTL0_1:
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = DynamicVars[Channel][RL]-4+1-2-3;
    break;
  case DYN_DQCCC_RXDLLRDCMDCTL0_2:
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = ((DynamicVars[Channel][RL]-4+1-2-4)>0)?(DynamicVars[Channel][RL]-4+1-2-4):1;
    break;
  case DYN_DQCCC_RXDLLRDCMDCTL0_3:
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = DynamicVars[Channel][RL]-5+1-2-3;
    break;
  case DYN_DQCCC_RXDLLRDCMDCTL0_4:
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = ((DynamicVars[Channel][RL]-4+3+1-2-3-2)>0)?(DynamicVars[Channel][RL]-4+3+1-2-3-2):1;
    break;
  case DYN_DQCCC_RXDLLRDCMDCTL0_5:
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = ((DynamicVars[Channel][RL]-7+3+1-2-3-2)>0)?(DynamicVars[Channel][RL]-7+3+1-2-3-2):1;
    break;
  case DYN_DQCCC_RXODTSEGCTL_CC:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC = (RXODTSEGCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-2+3-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_CC_1:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC = (RXODTSEGCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5+3-1-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_CC_2:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC = (RXODTSEGCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5+3-1-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_CC_3:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC = (RXODTSEGCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtseglenbl4 = 0x8;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst1 = 0x0;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpst0 = 0x0;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_CC->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5+3-1-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_DQ:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ = (RXODTSEGCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-2+3-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_DQ_1:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ = (RXODTSEGCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5+3-1-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_DQ_2:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ = (RXODTSEGCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5+3-1-3;
    break;
  case DYN_DQCCC_RXODTSEGCTL_DQ_3:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ = (RXODTSEGCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtseglenbl4 = 0x8;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst1 = 0x0;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpst0 = 0x0;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5+3-1-3;
    break;
  case DYN_DQCCC_RXODTCTL_CC:
    DYNSTRUCT_DQCCC_RXODTCTL_CC = (RXODTCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-2+3-2;
    break;
  case DYN_DQCCC_RXODTCTL_CC_1:
    DYNSTRUCT_DQCCC_RXODTCTL_CC = (RXODTCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-5+3-1-2;
    break;
  case DYN_DQCCC_RXODTCTL_CC_2:
    DYNSTRUCT_DQCCC_RXODTCTL_CC = (RXODTCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-5+3-1-2;
    break;
  case DYN_DQCCC_RXODTCTL_CC_3:
    DYNSTRUCT_DQCCC_RXODTCTL_CC = (RXODTCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenlenbl4 = 0x6;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_CC->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-5+3-1-2;
    break;
  case DYN_DQCCC_RXODTCTL_DQ:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-2+3-2;
    break;
  case DYN_DQCCC_RXODTCTL_DQ_1:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-5+3-1-2;
    break;
  case DYN_DQCCC_RXODTCTL_DQ_2:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-5+3-1-2;
    break;
  case DYN_DQCCC_RXODTCTL_DQ_3:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x6;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-5+3-1-2;
    break;
  case DYN_DQCCC_RCVENCTL_CC:
    DYNSTRUCT_DQCCC_RCVENCTL_CC = (RCVENCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-2+3;
    break;
  case DYN_DQCCC_RCVENCTL_CC_1:
    DYNSTRUCT_DQCCC_RCVENCTL_CC = (RCVENCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-5+3-1;
    break;
  case DYN_DQCCC_RCVENCTL_CC_2:
    DYNSTRUCT_DQCCC_RCVENCTL_CC = (RCVENCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-5+3-1;
    break;
  case DYN_DQCCC_RCVENCTL_CC_3:
    DYNSTRUCT_DQCCC_RCVENCTL_CC = (RCVENCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_CC->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-5+3-1;
    break;
  case DYN_DQCCC_RCVENCTL_DQ:
    DYNSTRUCT_DQCCC_RCVENCTL_DQ = (RCVENCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-2+3;
    break;
  case DYN_DQCCC_RCVENCTL_DQ_1:
    DYNSTRUCT_DQCCC_RCVENCTL_DQ = (RCVENCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-5+3-1;
    break;
  case DYN_DQCCC_RCVENCTL_DQ_2:
    DYNSTRUCT_DQCCC_RCVENCTL_DQ = (RCVENCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-5+3-1;
    break;
  case DYN_DQCCC_RCVENCTL_DQ_3:
    DYNSTRUCT_DQCCC_RCVENCTL_DQ = (RCVENCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenlenbl4 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst1 = 0x1;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpst0 = 0x1;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQCCC_RCVENCTL_DQ->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-5+3-1;
    break;
  case DYN_DQCCC_DIFFAMPCTL_CC:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC = (DIFFAMPCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst1 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst0 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-2+3-6;
    break;
  case DYN_DQCCC_DIFFAMPCTL_CC_1:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC = (DIFFAMPCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst1 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst0 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenlenbl4 = 0xB;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-5+3-1-7;
    break;
  case DYN_DQCCC_DIFFAMPCTL_CC_2:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC = (DIFFAMPCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst1 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst0 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenlenbl4 = 0xC;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-5+3-1-9;
    break;
  case DYN_DQCCC_DIFFAMPCTL_CC_3:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC = (DIFFAMPCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst1 = 0x0;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpst0 = 0x0;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_diffampenlenbl4 = 0xF;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-5+3-1-10;
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpst0 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-2+3-6;
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ_1:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpst0 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenlenbl4 = 0xB;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-5+3-1-7;
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ_2:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpst0 = 0x1;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenlenbl4 = 0xC;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-5+3-1-9;
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ_3:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre1 = 0x3;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpst0 = 0x0;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_diffampenlenbl4 = 0xF;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-5+3-1-10;
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pu_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pd_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pu_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pd_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pu_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pd_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pu_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pd_override = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DUNIT_D_CR_DRP0:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.addrdec = DynamicVars[Channel][ADDRDEC];
    break;
  case DYN_DUNIT_D_CR_DRP0_1:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.eccen = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.bahen = DynamicVars[Channel][BAHEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rsien = DynamicVars[Channel][RSIEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.dden = DynamicVars[Channel][DDEN];
    break;
  case DYN_DUNIT_D_CR_DRP0_2:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rken1 = DynamicVars[Channel][RANK1_ENABLED];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rken0 = DynamicVars[Channel][RANK0_ENABLED];
    break;
  case DYN_DUNIT_D_CR_DTR0A:
    DYNSTRUCT_DUNIT_D_CR_DTR0A = (D_CR_DTR0A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.tckckeh = DynamicVars[Channel][TCKSRX];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.txsr = DynamicVars[Channel][TXSR];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.trcd = DynamicVars[Channel][TRCD];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.trppb = DynamicVars[Channel][TRPPB];
    break;
  case DYN_DUNIT_D_CR_DTR1A:
    DYNSTRUCT_DUNIT_D_CR_DTR1A = (D_CR_DTR1A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.txp = DynamicVars[Channel][TXP];
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.tzqcl = DynamicVars[Channel][TZQCL];
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.tzqcs = DynamicVars[Channel][TZQCS];
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.tzqlat = DynamicVars[Channel][TZQLAT];
    break;
  case DYN_DUNIT_D_CR_DTR2A:
    DYNSTRUCT_DUNIT_D_CR_DTR2A = (D_CR_DTR2A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR2A->Bits.nrfcab = DynamicVars[Channel][NRFCAB];
    DYNSTRUCT_DUNIT_D_CR_DTR2A->Bits.tcke = DynamicVars[Channel][TCKE];
    DYNSTRUCT_DUNIT_D_CR_DTR2A->Bits.nrefi = DynamicVars[Channel][NREFI];
    break;
  case DYN_DUNIT_D_CR_DTR3A:
    DYNSTRUCT_DUNIT_D_CR_DTR3A = (D_CR_DTR3A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.trtp = DynamicVars[Channel][TRTP];
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.tccd_inc = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.twtp = DynamicVars[Channel][TWTP];
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.tcmd = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.tcwl = DynamicVars[Channel][TCWL];
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.twmwsb = DynamicVars[Channel][TCCDMW];
    break;
  case DYN_DUNIT_D_CR_DTR4A:
    DYNSTRUCT_DUNIT_D_CR_DTR4A = (D_CR_DTR4A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.tfaw = DynamicVars[Channel][TFAW];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.twrdr = DynamicVars[Channel][TWRDR];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.trwdr = DynamicVars[Channel][TRWDR];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.twwdr = DynamicVars[Channel][TWWDR];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.trrdr = DynamicVars[Channel][TRRDR];
    break;
  case DYN_DUNIT_D_CR_DTR5A:
    DYNSTRUCT_DUNIT_D_CR_DTR5A = (D_CR_DTR5A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.trrd = DynamicVars[Channel][TRRD];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.tderate_inc = DynamicVars[Channel][TDERATE_INC];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.twwsr = DynamicVars[Channel][TWWSR];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.trrsr = DynamicVars[Channel][TRRSR];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.twrsr = DynamicVars[Channel][TWRSR];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.trwsr = DynamicVars[Channel][TRWSR];
    break;
  case DYN_DUNIT_D_CR_DTR6A:
    DYNSTRUCT_DUNIT_D_CR_DTR6A = (D_CR_DTR6A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.orefdly = 0x40;
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tckckel = DynamicVars[Channel][TCKCKEL];
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.mntdly = DynamicVars[Channel][MNTDLY];
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tpstmrblk = DynamicVars[Channel][TPSTMRBLK];
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tpremrblk = DynamicVars[Channel][TPREMRBLK];
    break;
  case DYN_DUNIT_D_CR_DTR7A:
    DYNSTRUCT_DUNIT_D_CR_DTR7A = (D_CR_DTR7A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.trpab = DynamicVars[Channel][TRPAB];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.tpstmrwblk = DynamicVars[Channel][TPSTMRWBLK];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.twrpden = DynamicVars[Channel][TWRPDEN];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.trdpden = DynamicVars[Channel][TRDPDEN];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.tras = DynamicVars[Channel][TRAS];
    break;
  case DYN_DUNIT_D_CR_DTR8A:
    DYNSTRUCT_DUNIT_D_CR_DTR8A = (D_CR_DTR8A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.tckesr = DynamicVars[Channel][TCKESR];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.lpmdtockedly = DynamicVars[Channel][TLPCKDLY];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.cketolpmddly = DynamicVars[Channel][TCKLPDLY];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.pwddly = DynamicVars[Channel][PWDDLY];
    break;
  case DYN_DUNIT_D_CR_SSKPD0:
    DYNSTRUCT_DUNIT_D_CR_SSKPD0 = (D_CR_SSKPD0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_SSKPD0->Bits.val = DynamicVars[Channel][SSKPD0];
    DYNSTRUCT_DUNIT_D_CR_SSKPD0->Bits.val = DynamicVars[Channel][SSKPD1];
    break;
  case DYN_DUNIT_D_CR_BONUS0:
    DYNSTRUCT_DUNIT_D_CR_BONUS0 = (D_CR_BONUS0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BONUS0->Bits.bonus0 = DynamicVars[Channel][BONUS0];
    break;
  case DYN_DUNIT_D_CR_BONUS1:
    DYNSTRUCT_DUNIT_D_CR_BONUS1 = (D_CR_BONUS1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BONUS1->Bits.bonus1 = DynamicVars[Channel][BONUS1];
    break;
  case DYN_DUNIT_D_CR_MR4_DESWIZZLE:
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE = (D_CR_MR4_DESWIZZLE_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit2_sel = DynamicVars[Channel][MR4_BIT2_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit1_sel = DynamicVars[Channel][MR4_BIT1_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit0_sel = DynamicVars[Channel][MR4_BIT0_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_byte_sel = DynamicVars[Channel][MR4_BYTE_SEL];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_1:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDDATA_RATIO_WIO2];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_2:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spidcmdclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.saclkby2_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DQCCC_DIFFAMPCTL_CC_4:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC = (DIFFAMPCTL_CC_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_dqsdiffampenovrval = DynamicVars[Channel][CC_DQS_OVR_VAL];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_dqsdiffampenovrsel = DynamicVars[Channel][CC_DQS_OVR_SEL];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_dqdmdiffampenovrval = DynamicVars[Channel][CC_DQDM_OVR_VAL];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_CC->Bits.cc_dqdmdiffampenovrsel = DynamicVars[Channel][CC_DQDM_OVR_SEL];
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ_4:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_dqsdiffampenovrval = DynamicVars[Channel][BL_DQS_OVR_VAL];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_dqsdiffampenovrsel = DynamicVars[Channel][BL_DQS_OVR_SEL];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_dqdmdiffampenovrval = DynamicVars[Channel][BL_DQDM_OVR_VAL];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_dqdmdiffampenovrsel = DynamicVars[Channel][BL_DQDM_OVR_SEL];
    break;
  case DYN_DUNIT_D_CR_DRP0_3:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.eccen = DynamicVars[Channel][ECCEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.bahen = DynamicVars[Channel][BAHEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rsien = DynamicVars[Channel][RSIEN];
    break;
  case DYN_DUNIT_D_CR_DPMC0:
    DYNSTRUCT_DUNIT_D_CR_DPMC0 = (D_CR_DPMC0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC0->Bits.dynsren = DynamicVars[Channel][DYNSREN];
    break;
  case DYN_DUNIT_D_CR_DPMC1:
    DYNSTRUCT_DUNIT_D_CR_DPMC1 = (D_CR_DPMC1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.pasr = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.pclsto = DynamicVars[Channel][PCLSTO];
    break;
  case DYN_DUNIT_D_CR_DRFC:
    DYNSTRUCT_DUNIT_D_CR_DRFC = (D_CR_DRFC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.minrefrate = DynamicVars[Channel][MINREFRATE];
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.refwmpnc = DynamicVars[Channel][REFWMPNC];
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.refwmhi = DynamicVars[Channel][REFWMHI];
    break;
  case DYN_DUNIT_D_CR_DSCH:
    DYNSTRUCT_DUNIT_D_CR_DSCH = (D_CR_DSCH_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.wpqcount = DynamicVars[Channel][WPQCOUNT];
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.rpqcount = DynamicVars[Channel][RPQCOUNT];
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.inordermode = 0x0;
    break;
  case DYN_DUNIT_D_CR_DCAL:
    DYNSTRUCT_DUNIT_D_CR_DCAL = (D_CR_DCAL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DCAL->Bits.srxzqc = DynamicVars[Channel][SRXZQC];
    break;
  case DYN_DUNIT_D_CR_TQCTL:
    DYNSTRUCT_DUNIT_D_CR_TQCTL = (D_CR_TQCTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQCTL->Bits.tqpollper = DynamicVars[Channel][TQPOLLPER];
    break;
  case DYN_DUNIT_D_CR_TQOFFSET:
    DYNSTRUCT_DUNIT_D_CR_TQOFFSET = (D_CR_TQOFFSET_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQOFFSET->Bits.mr_value = DynamicVars[Channel][MR_VALUE];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_3:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_4:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDDATA_RATIO_WIO2];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_5:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spidcmdclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.saclkby2_ratio = DynamicVars[Channel][SACLKBY2_RATIO];
    break;
  case DYN_DUNIT_D_CR_DQS_RETRAINING_CTL:
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL = (D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_int = DynamicVars[Channel][DQS_RETRAIN_INT];
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_osc_rt = DynamicVars[Channel][DQS_OSC_RT];
    break;
  case DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_1:
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR = (P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_STRUCT *) Value;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.cpgc_mode_complete = 0x1;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_data = DynamicVars[Channel][PUNIT_REQ_DATA];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_6:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_7:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDDATA_RATIO_WIO2];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_8:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spidcmdclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.saclkby2_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_MLMC_MLM_CR_CONFIG:
    DYNSTRUCT_MLMC_MLM_CR_CONFIG = (MLM_CR_CONFIG_MLMC_STRUCT *) Value;
    DYNSTRUCT_MLMC_MLM_CR_CONFIG->Bits.cr_1lm_mode = DynamicVars[Channel][ONE_LM_MODE];
    break;
  case DYN_MLMC_MLM_CR_FM_CONFIG:
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG = (MLM_CR_FM_CONFIG_MLMC_STRUCT *) Value;
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG->Bits.fm_chan_e_size = DynamicVars[Channel][FM_SIZE_CH10];
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG->Bits.fm_chan_w_size = DynamicVars[Channel][FM_SIZE_CH8];
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG->Bits.fm_chan_n_size = DynamicVars[Channel][FM_SIZE_CH9];
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG->Bits.fm_chan_s_size = DynamicVars[Channel][FM_SIZE_CH11];
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG->Bits.fm_active_dunits = DynamicVars[Channel][FM_ACTIVE_SNWE];
    DYNSTRUCT_MLMC_MLM_CR_FM_CONFIG->Bits.mem_init_done = 0x1;
    break;
  case DYN_DQCCC_TXDLLSIGGRP2CTL:
    DYNSTRUCT_DQCCC_TXDLLSIGGRP2CTL = (TXDLLSIGGRP2CTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_TXDLLSIGGRP2CTL->Bits.txdll_rk0siggrp02rdptroffset = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_DUNIT_D_CR_DRAM_CMD:
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD = (D_CR_DRAM_CMD_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.bl = DynamicVars[Channel][DRAM_CMD_BL];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.rank = DynamicVars[Channel][RANK];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.mrrcmd = DynamicVars[Channel][RDDCMD];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.data = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_0_:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_ = (CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_->Bits.pattern_buffer = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_CPGC_CPGC2_BASE_REPEATS:
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS = (CPGC2_BASE_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS->Bits.base_repeats = DynamicVars[Channel][NUM_BURSTS_EXP];
    break;
  case DYN_CPGC_CPGC2_BLOCK_REPEATS:
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS = (CPGC2_BLOCK_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS->Bits.block_repeats = DynamicVars[Channel][NUM_LOOPS_EXP];
    break;
  case DYN_CPGC_CPGC2_BASE_REPEATS_1:
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS = (CPGC2_BASE_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS->Bits.base_repeats = DynamicVars[Channel][NUM_BURSTS_EXP];
    break;
  case DYN_CPGC_CPGC2_BLOCK_REPEATS_1:
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS = (CPGC2_BLOCK_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS->Bits.block_repeats = DynamicVars[Channel][NUM_LOOPS_EXP];
    break;
  case DYN_CPGC_CPGC2_BASE_REPEATS_2:
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS = (CPGC2_BASE_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS->Bits.base_repeats = DynamicVars[Channel][NUM_BURSTS_EXP];
    break;
  case DYN_CPGC_CPGC2_BLOCK_REPEATS_2:
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS = (CPGC2_BLOCK_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS->Bits.block_repeats = DynamicVars[Channel][NUM_LOOPS_EXP];
    break;
  case DYN_DQCCC_WRLVL:
    DYNSTRUCT_DQCCC_WRLVL = (WRLVL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_WRLVL->Bits.bl_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    DYNSTRUCT_DQCCC_WRLVL->Bits.cc_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    break;
  case DYN_CCC_WRLVL:
    DYNSTRUCT_CCC_WRLVL = (WRLVL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRLVL->Bits.cc_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    break;
  case DYN_CPGC_CPGC_DPAT_XTRA_LFSR_CFG:
    DYNSTRUCT_CPGC_CPGC_DPAT_XTRA_LFSR_CFG = (CPGC_DPAT_XTRA_LFSR_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_XTRA_LFSR_CFG->Bits.lane_rotate_rate = DynamicVars[Channel][LANE_ROTATE_RATE];
    break;
  case DYN_CPGC_CPGC_DPAT_CFG:
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG = (CPGC_DPAT_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.reload_lfsr_seed_rate = DynamicVars[Channel][RELOAD_LFSR_SEED_RATE];
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.save_lfsr_seed_rate = DynamicVars[Channel][SAVE_LFSR_SEED_RATE];
    break;
  case DYN_CPGC_CPGC2_BASE_REPEATS_3:
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS = (CPGC2_BASE_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS->Bits.base_repeats = DynamicVars[Channel][NUM_BURSTS_EXP];
    break;
  case DYN_CPGC_CPGC2_BLOCK_REPEATS_3:
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS = (CPGC2_BLOCK_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS->Bits.block_repeats = DynamicVars[Channel][NUM_LOOPS_EXP];
    break;
  case DYN_CPGC_CPGC_DPAT_INV_DC_MASK_LO:
    DYNSTRUCT_CPGC_CPGC_DPAT_INV_DC_MASK_LO = (CPGC_DPAT_INV_DC_MASK_LO_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_INV_DC_MASK_LO->Bits.data_inv_dc_mask_lo = DynamicVars[Channel][CAVREF];
    break;
  case DYN_DQCCC_RDVLDCTL_7:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = (DynamicVars[Channel][RL]/2)-1;
    break;
  case DYN_DQCCC_RDVLDCTL_8:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+8)/2-4)-1;
    break;
  case DYN_DQCCC_RDVLDCTL_9:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+9)/2-4)-1;
    break;
  case DYN_DQCCC_RDVLDCTL_10:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+10)/2-4)-1;
    break;
  case DYN_DQCCC_RDVLDCTL_11:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = (1+DynamicVars[Channel][RL]/2)-1;
    break;
  case DYN_DQCCC_RDVLDCTL_12:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4) -1);
    break;
  case DYN_DQCCC_RDVLDCTL_13:
    DYNSTRUCT_DQCCC_RDVLDCTL = (RDVLDCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4)-1)-1;
    break;
  case DYN_DUNIT_D_CR_DRMC:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_DUNIT_D_CR_DRAM_CMD_1:
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD = (D_CR_DRAM_CMD_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.rank = DynamicVars[Channel][RANK_INDEX];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.mrrcmd = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.bl = 0x1;
    break;
  case DYN_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A:
    DYNSTRUCT_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A = (CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A->Bits.l2p_bank0_mapping = DynamicVars[Channel][TARGET_BANK];
    break;
  case DYN_CPGC_CPGC_SEQ_RANK_L2P_MAPPING:
    DYNSTRUCT_CPGC_CPGC_SEQ_RANK_L2P_MAPPING = (CPGC_SEQ_RANK_L2P_MAPPING_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_SEQ_RANK_L2P_MAPPING->Bits.l2p_rank0_mapping = DynamicVars[Channel][TARGET_RANK];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_0_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_ = (CPGC_CADB_BUFA_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.bank_addr = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_2_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_ = (CPGC_CADB_BUFA_2__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.bank_addr = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_3_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_ = (CPGC_CADB_BUFA_3__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.bank_addr = 0x0;
    break;
  case DYN_CPGC_CPGC2_ADDRESS_SIZE:
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE = (CPGC2_ADDRESS_SIZE_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_bits_col = DynamicVars[Channel][NUM_COLS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_bits_row = DynamicVars[Channel][NUM_ROWS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_num_banks = 0x7;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_num_ranks = 0x2;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.region_size_bits_col = DynamicVars[Channel][NUM_COLS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.region_size_bits_row = DynamicVars[Channel][NUM_ROWS];
    break;
  case DYN_CPGC_CPGC2_ADDRESS_CONTROL:
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_CONTROL = (CPGC2_ADDRESS_CONTROL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_CONTROL->Bits.address_decode_rotate_repeats = DynamicVars[Channel][ADD_ROTATE_RPT];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_0__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_ = (CPGC_CADB_BUFA_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA0_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA0_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_1_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_ = (CPGC_CADB_BUFA_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA1_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA1_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_2__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_ = (CPGC_CADB_BUFA_2__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA2_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA2_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_3__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_ = (CPGC_CADB_BUFA_3__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA3_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA3_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_4_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_ = (CPGC_CADB_BUFA_4__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA4_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA4_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_5_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_ = (CPGC_CADB_BUFA_5__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA5_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA5_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_6_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_ = (CPGC_CADB_BUFA_6__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA6_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA6_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_7_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_ = (CPGC_CADB_BUFA_7__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA7_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA7_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_0_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_ = (CPGC_CADB_BUFB_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cmd = DynamicVars[Channel][CADB_BUFB0_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_1_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_ = (CPGC_CADB_BUFB_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cmd = DynamicVars[Channel][CADB_BUFB1_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_2_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_ = (CPGC_CADB_BUFB_2__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cmd = DynamicVars[Channel][CADB_BUFB2_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_3_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_ = (CPGC_CADB_BUFB_3__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cmd = DynamicVars[Channel][CADB_BUFB3_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_4_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_ = (CPGC_CADB_BUFB_4__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cmd = DynamicVars[Channel][CADB_BUFB4_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_5_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_ = (CPGC_CADB_BUFB_5__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cmd = DynamicVars[Channel][CADB_BUFB5_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_6_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_ = (CPGC_CADB_BUFB_6__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cmd = DynamicVars[Channel][CADB_BUFB6_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_7_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_ = (CPGC_CADB_BUFB_7__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cmd = DynamicVars[Channel][CADB_BUFB7_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_0__1:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_ = (CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_->Bits.pattern_buffer = DynamicVars[Channel][AGG_PATTERN];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_1_:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_ = (CPGC_DPAT_UNISEQ_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_->Bits.pattern_buffer = DynamicVars[Channel][VIC_PATTERN];
    break;
  case DYN_DQCCC_RXODTCTL_DQ_4:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.rk0_odtenrdptroffset = DynamicVars[Channel][RCVEN_RDPTR];
    break;
  case DYN_CPGC_CPGC_CADB_CTL:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][RMT_COMMAND];
    break;
  case DYN_CPGC_CPGC_CADB_CTL_1:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][RMT_VALUE];
    break;
  case DYN_CPGC_CPGC_CADB_CTL_2:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][LANE_ROTATE_RATE];
    break;
  case DYN_CPGC_CPGC_CADB_CTL_3:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][RELOAD_LFSR_SEED_RATE];
    break;
  case DYN_CPGC_CPGC_CADB_CTL_4:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][VAR_SEG_HIGHADDR_HI];
    break;
  case DYN_CPGC_CPGC_CADB_CTL_5:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][VAR_SEG_HIGHADDR_LO];
    break;
  case DYN_CPGC_CPGC_CADB_CTL_6:
    DYNSTRUCT_CPGC_CPGC_CADB_CTL = (CPGC_CADB_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][FIX_SEGMENT_RANK_SELECT];
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][FIX_SEGMENT_RANK_SELECT_0];
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][FIX_SEGMENT_RANK_SELECT_1];
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][FIX_SEGMENT_RANK_SELECT_2];
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][FIX_SEGMENT_RANK_SELECT_3];
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][SEQ_START];
    DYNSTRUCT_CPGC_CPGC_CADB_CTL->Bits.cadb_mode = DynamicVars[Channel][SEQ_END];
    break;
  case DYN_CPGC_CPGC_CADB_CFG:
    DYNSTRUCT_CPGC_CPGC_CADB_CFG = (CPGC_CADB_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CFG->Bits.uniseq0_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_CADB_CFG->Bits.uniseq1_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_CADB_CFG->Bits.uniseq2_mode = DynamicVars[Channel][UNIMODE];
    break;
  case DYN_CPGC_CPGC_CADB_UNISEQ0_PBUF:
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ0_PBUF = (CPGC_CADB_UNISEQ0_PBUF_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ0_PBUF->Bits.cmd = DynamicVars[Channel][PATTERN0];
    break;
  case DYN_CPGC_CPGC_CADB_UNISEQ1_PBUF:
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ1_PBUF = (CPGC_CADB_UNISEQ1_PBUF_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ1_PBUF->Bits.cmd = DynamicVars[Channel][PATTERN1];
    break;
  case DYN_CPGC_CPGC_CADB_UNISEQ2_PBUF:
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ2_PBUF = (CPGC_CADB_UNISEQ2_PBUF_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ2_PBUF->Bits.cmd = DynamicVars[Channel][PATTERN2];
    break;
  case DYN_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_:
    DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_ = (CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_->Bits.last = DynamicVars[Channel][INSTR_LAST];
    DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_->Bits.command_start_pointer = DynamicVars[Channel][INSTR_POINTER];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_0__2:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_ = (CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_->Bits.pattern_buffer = DynamicVars[Channel][PATTERN0];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_1__1:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_ = (CPGC_DPAT_UNISEQ_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_->Bits.pattern_buffer = DynamicVars[Channel][PATTERN1];
    break;
  case DYN_CPGC_CPGC_DPAT_CFG_1:
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG = (CPGC_DPAT_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.uniseq2_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.uniseq1_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.uniseq0_mode = DynamicVars[Channel][UNIMODE];
    break;
  case DYN_CPGC_CPGC_ERR_CTL:
    DYNSTRUCT_CPGC_CPGC_ERR_CTL = (CPGC_ERR_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_ERR_CTL->Bits.errchk_mask_chunk = DynamicVars[Channel][CHUNK_ERR_MASK];
    break;
  case DYN_CPGC_CPGC_ERR_LNEN_HI:
    DYNSTRUCT_CPGC_CPGC_ERR_LNEN_HI = (CPGC_ERR_LNEN_HI_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_ERR_LNEN_HI->Bits.data_errchk_mask_hi = DynamicVars[Channel][CHUNK_ERR_MASK_LP];
    break;
  case DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_1:
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL = (D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_int = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_en = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_osc_rt = DynamicVars[Channel][DQS_OSC_RT];
    break;
  case DYN_DPLVUG_PTCTL0_1:
    DYNSTRUCT_DPLVUG_PTCTL0 = (PTCTL0_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.ptloadcode_dly = DynamicVars[Channel][PTLDCODE];
    break;
  case DYN_DUNIT_D_CR_TQCTL_1:
    DYNSTRUCT_DUNIT_D_CR_TQCTL = (D_CR_TQCTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQCTL->Bits.tqpollen = DynamicVars[Channel][TQPOLLEN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DCAL_1:
    DYNSTRUCT_DUNIT_D_CR_DCAL = (D_CR_DCAL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DCAL->Bits.srxzqc = DynamicVars[Channel][SRXZQC_SAVE];
    DYNSTRUCT_DUNIT_D_CR_DCAL->Bits.zqcdis = DynamicVars[Channel][ZQDIS_SAVE];
    break;
  case DYN_DUNIT_D_CR_DRFC_1:
    DYNSTRUCT_DUNIT_D_CR_DRFC = (D_CR_DRFC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.orefdis = DynamicVars[Channel][OREFDIS_SAVE];
    break;
  case DYN_DUNIT_D_CR_DPMC0_1:
    DYNSTRUCT_DUNIT_D_CR_DPMC0 = (D_CR_DPMC0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC0->Bits.dynsren = DynamicVars[Channel][DYNSREN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DPMC1_1:
    DYNSTRUCT_DUNIT_D_CR_DPMC1 = (D_CR_DPMC1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.dispwrdn = DynamicVars[Channel][DISPWRDN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_2:
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL = (D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_int = DynamicVars[Channel][DQS_RETRAIN_INT];
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_en = DynamicVars[Channel][DQS_RETAIN_EN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DTR4A_1:
    DYNSTRUCT_DUNIT_D_CR_DTR4A = (D_CR_DTR4A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.trwdr = DynamicVars[Channel][TRWDR];
    break;
  case DYN_DUNIT_D_CR_DTR6A_1:
    DYNSTRUCT_DUNIT_D_CR_DTR6A = (D_CR_DTR6A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tpstmrblk = DynamicVars[Channel][TPSTMRBLK];
    break;
  case DYN_DPLVUG_PTCTL0_2:
    DYNSTRUCT_DPLVUG_PTCTL0 = (PTCTL0_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.ptrdtype2rdvld = DynamicVars[Channel][RDCMD2RDVLD]-1;
    DYNSTRUCT_DPLVUG_PTCTL0->Bits.pten = 0x1;
    break;
  case DYN_DQCCC_RXODTCTL_DQ_5:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenovrsel = DynamicVars[Channel][ODT_SEL_SAVE];
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenovrval = DynamicVars[Channel][ODT_VAL_SAVE];
    break;
  case DYN_DQCCC_WKPUPPDNCTL:
    DYNSTRUCT_DQCCC_WKPUPPDNCTL = (WKPUPPDNCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_WKPUPPDNCTL->Bits.lvl_bl_weakpup = DynamicVars[Channel][WEAKPUP_SAVE];
    DYNSTRUCT_DQCCC_WKPUPPDNCTL->Bits.lvl_bl_weakpdn = DynamicVars[Channel][WEAKPDN_SAVE];
    break;
  case DYN_DQCCC_RXODTSEGCTL_DQ_4:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ = (RXODTSEGCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.rk0_odtsegenrdptroffset = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DQCCC_RXODTCTL_DQ_6:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.rk0_odtenrdptroffset = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ_5:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.rk0_diffampenrdptroffset = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DUNIT_D_CR_SSKPD0_1:
    DYNSTRUCT_DUNIT_D_CR_SSKPD0 = (D_CR_SSKPD0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_SSKPD0->Bits.val = DynamicVars[Channel][SCRATCHPAD_VALUE0];
    break;
  case DYN_DUNIT_D_CR_SSKPD1:
    DYNSTRUCT_DUNIT_D_CR_SSKPD1 = (D_CR_SSKPD1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_SSKPD1->Bits.val = DynamicVars[Channel][SCRATCHPAD_VALUE1];
    break;
  case DYN_LDO_TXPANIC:
    DYNSTRUCT_LDO_TXPANIC = (TXPANIC_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXPANIC->Bits.panicvlo = DynamicVars[Channel][PANICVLO];
    DYNSTRUCT_LDO_TXPANIC->Bits.panicvhi = DynamicVars[Channel][PANICVHI];
    DYNSTRUCT_LDO_TXPANIC->Bits.enpanicdq = 0x1;
    DYNSTRUCT_LDO_TXPANIC->Bits.enpanicca = 0x1;
    DYNSTRUCT_LDO_TXPANIC->Bits.enpanicclk = 0x3;
    DYNSTRUCT_LDO_TXPANIC->Bits.enpanicsr = 0x1;
    DYNSTRUCT_LDO_TXPANIC->Bits.enpdclkstop = 0x1;
    DYNSTRUCT_LDO_TXPANIC->Bits.enpdidle = 0x1;
    DYNSTRUCT_LDO_TXPANIC->Bits.pdcbit = 0x0;
    DYNSTRUCT_LDO_TXPANIC->Bits.viewdigch0 = 0x0;
    DYNSTRUCT_LDO_TXPANIC->Bits.viewdigch1 = 0x0;
    DYNSTRUCT_LDO_TXPANIC->Bits.viewana = 0x0;
    DYNSTRUCT_LDO_TXPANIC->Bits.enpanicdowncomp = 0x0;
    DYNSTRUCT_LDO_TXPANIC->Bits.forcepanicon = 0x1;
    break;
  case DYN_LDO_TXFB:
    DYNSTRUCT_LDO_TXFB = (TXFB_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFB->Bits.enmode = 0x3;
    DYNSTRUCT_LDO_TXFB->Bits.enfeedbackdrv = 0x0;
    DYNSTRUCT_LDO_TXFB->Bits.enregulator = 0x1;
    DYNSTRUCT_LDO_TXFB->Bits.maxripple = 0x1;
    DYNSTRUCT_LDO_TXFB->Bits.slowbw = 0x7;
    DYNSTRUCT_LDO_TXFB->Bits.fastbw = 0x1;
    DYNSTRUCT_LDO_TXFB->Bits.targetv = DynamicVars[Channel][TARGETV];
    DYNSTRUCT_LDO_TXFB->Bits.bypassregulator = 0x0;
    DYNSTRUCT_LDO_TXFB->Bits.enfeedforwardtrain = 0x0;
    break;
  case DYN_LDO_TXFFDQ0_DVFS:
    DYNSTRUCT_LDO_TXFFDQ0_DVFS = (TXFFDQ0_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFDQ0_DVFS->Bits.bgach = DynamicVars[Channel][BGACH];
    break;
  case DYN_LDO_TXFFDQ1_DVFS:
    DYNSTRUCT_LDO_TXFFDQ1_DVFS = (TXFFDQ1_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFDQ1_DVFS->Bits.bgach = DynamicVars[Channel][BGACH];
    break;
  case DYN_LDO_TXFFCA0_DVFS:
    DYNSTRUCT_LDO_TXFFCA0_DVFS = (TXFFCA0_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFCA0_DVFS->Bits.bgach = DynamicVars[Channel][BGACH];
    break;
  case DYN_LDO_TXFFCA1_DVFS:
    DYNSTRUCT_LDO_TXFFCA1_DVFS = (TXFFCA1_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFCA1_DVFS->Bits.bgach = DynamicVars[Channel][BGACH];
    break;
  case DYN_LDO_TXFFCA0_DVFS_1:
    DYNSTRUCT_LDO_TXFFCA0_DVFS = (TXFFCA0_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFCA0_DVFS->Bits.coeffscale = DynamicVars[Channel][LDOSCALE];
    break;
  case DYN_LDO_TXFFCA1_DVFS_1:
    DYNSTRUCT_LDO_TXFFCA1_DVFS = (TXFFCA1_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFCA1_DVFS->Bits.coeffscale = DynamicVars[Channel][LDOSCALE];
    break;
  case DYN_LDO_TXFFDQ0_DVFS_1:
    DYNSTRUCT_LDO_TXFFDQ0_DVFS = (TXFFDQ0_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFDQ0_DVFS->Bits.coeffscale = DynamicVars[Channel][LDOSCALE];
    break;
  case DYN_LDO_TXFFDQ1_DVFS_1:
    DYNSTRUCT_LDO_TXFFDQ1_DVFS = (TXFFDQ1_DVFS_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFFDQ1_DVFS->Bits.coeffscale = DynamicVars[Channel][LDOSCALE];
    break;
  case DYN_LDO_TXFB_1:
    DYNSTRUCT_LDO_TXFB = (TXFB_LDO_STRUCT *) Value;
    DYNSTRUCT_LDO_TXFB->Bits.enfeedforwardtrain = DynamicVars[Channel][LDOCOEF];
    DYNSTRUCT_LDO_TXFB->Bits.enfeedforwardtrain = 0x0;
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_VREF_1:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1 = (DPIC_GRCOMP_VREF_1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1->Bits.comp_vref_grp4 = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_4:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pu_override = DynamicVars[Channel][VOC_RCOMP_PUP];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pd_override = DynamicVars[Channel][VOC_RCOMP_PDN];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_4:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][RCOMP_Up_GRP0];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP0];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][RCOMP_Up_GRP1];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP1];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_4:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pu_override = DynamicVars[Channel][RCOMP_Up_GRP2];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP2];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pu_override = DynamicVars[Channel][RCOMP_Up_GRP3];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP3];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_5:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pu_override = DynamicVars[Channel][RCOMP_Up_GRP4];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP4];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pu_override = DynamicVars[Channel][RCOMP_Up_GRP5];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP5];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_PUPDOVR:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR = (DPIC_LRCOMP_PUPDOVR_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppu_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Up_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppd_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Dn_En];
    break;
  case DYN_DQCCC_RXODTSEGCTL_DQ_5:
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ = (RXODTSEGCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegovrval = DynamicVars[Channel][RCOMP_Seg_Ovr_Val];
    DYNSTRUCT_DQCCC_RXODTSEGCTL_DQ->Bits.bl_rxodtsegovrsel = DynamicVars[Channel][RCOMP_Seg_Ovr_En];
    break;
  case DYN_DQCCC_DIFFAMPCTL_DQ_6:
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ = (DIFFAMPCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_dqsdiffampenovrval = DynamicVars[Channel][DIFF_Ovr_Val];
    DYNSTRUCT_DQCCC_DIFFAMPCTL_DQ->Bits.bl_dqsdiffampenovrsel = DynamicVars[Channel][DIFF_Ovr_Val_sel];
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_VREF_0:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0 = (DPIC_GRCOMP_VREF_0_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp0 = DynamicVars[Channel][comp_vref_0];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp1 = DynamicVars[Channel][comp_vref_1];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp2 = DynamicVars[Channel][comp_vref_2];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp3 = DynamicVars[Channel][comp_vref_3];
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_VREF_1_1:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1 = (DPIC_GRCOMP_VREF_1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1->Bits.comp_vref_grp4 = DynamicVars[Channel][comp_vref_4];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1->Bits.comp_vref_grp5 = DynamicVars[Channel][comp_vref_5];
    break;
  case DYN_DQCCC_RXODTCTL_DQ_7:
    DYNSTRUCT_DQCCC_RXODTCTL_DQ = (RXODTCTL_DQ_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenovrsel = DynamicVars[Channel][RX_ODTEN_OVR_SEL];
    DYNSTRUCT_DQCCC_RXODTCTL_DQ->Bits.bl_rxodtenovrval = DynamicVars[Channel][RX_ODTEN_OVR_VAL];
    break;
  case DYN_DQCCC_VREFCTL0:
    DYNSTRUCT_DQCCC_VREFCTL0 = (VREFCTL0_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_VREFCTL0->Bits.vref_rxccvrefctrl = DynamicVars[Channel][RXCCVREFCTL];
    DYNSTRUCT_DQCCC_VREFCTL0->Bits.vref_rxblvrefctrl = DynamicVars[Channel][RXBLVREFCTL];
    break;
  case DYN_CPGC_CPGC_ERR_CTL_1:
    DYNSTRUCT_CPGC_CPGC_ERR_CTL = (CPGC_ERR_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_ERR_CTL->Bits.errchk_mask_chunk = DynamicVars[Channel][CHUNK_ERR_MASK];
    break;
  case DYN_DUNIT_D_CR_SCRAMCTRL:
    DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL = (D_CR_SCRAMCTRL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL->Bits.key = DynamicVars[Channel][SCRAMBLER_KEY];
    DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL->Bits.scrm_en = 0x1;
    break;
  case DYN_CUNIT_MCHBAR_LO_0_0_0_PCI:
    DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI = (MCHBAR_LO_0_0_0_PCI_CUNIT_STRUCT *) Value;
    DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI->Bits.base_addr = DynamicVars[Channel][MCHBAR];
    DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI->Bits.mchbaren = 0x1;
    break;
  case DYN_P2SB_BASE_ADDRESS_LO:
    DYNSTRUCT_P2SB_BASE_ADDRESS_LO = (BASE_ADDRESS_LO_P2SB_STRUCT *) Value;
    DYNSTRUCT_P2SB_BASE_ADDRESS_LO->Bits.baseaddress = DynamicVars[Channel][P2SBBAR];
    break;
  case DYN_CUNIT_PCIEXBAR_LO_0_0_0_PCI:
    DYNSTRUCT_CUNIT_PCIEXBAR_LO_0_0_0_PCI = (PCIEXBAR_LO_0_0_0_PCI_CUNIT_STRUCT *) Value;
    DYNSTRUCT_CUNIT_PCIEXBAR_LO_0_0_0_PCI->Bits.pciexbar = DynamicVars[Channel][ECBASE_LO];
    DYNSTRUCT_CUNIT_PCIEXBAR_LO_0_0_0_PCI->Bits.pciexbaren = 0x1;
    break;
  case DYN_DQCCC_RXPBDBLCTL:
    DYNSTRUCT_DQCCC_RXPBDBLCTL = (RXPBDBLCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq0rxpbdcode = DynamicVars[Channel][S0_Fixes0];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq1rxpbdcode = DynamicVars[Channel][S0_Fixes1];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq2rxpbdcode = DynamicVars[Channel][S0_Fixes2];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq3rxpbdcode = DynamicVars[Channel][S0_Fixes3];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq4rxpbdcode = DynamicVars[Channel][S0_Fixes4];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq5rxpbdcode = DynamicVars[Channel][S0_Fixes5];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq6rxpbdcode = DynamicVars[Channel][S0_Fixes6];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq7rxpbdcode = DynamicVars[Channel][S0_Fixes7];
    break;
  case DYN_DQCCC_TXPBDCTL1:
    DYNSTRUCT_DQCCC_TXPBDCTL1 = (TXPBDCTL1_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_TXPBDCTL1->Bits.rxdll_bl_rxpbden = DynamicVars[Channel][S0_Fixes8];
    break;
  case DYN_DQCCC_RXPBDBLCTL_1:
    DYNSTRUCT_DQCCC_RXPBDBLCTL = (RXPBDBLCTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq0rxpbdcode = DynamicVars[Channel][S0_Fixes9];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq1rxpbdcode = DynamicVars[Channel][S0_Fixes10];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq2rxpbdcode = DynamicVars[Channel][S0_Fixes11];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq3rxpbdcode = DynamicVars[Channel][S0_Fixes12];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq4rxpbdcode = DynamicVars[Channel][S0_Fixes13];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq5rxpbdcode = DynamicVars[Channel][S0_Fixes14];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq6rxpbdcode = DynamicVars[Channel][S0_Fixes15];
    DYNSTRUCT_DQCCC_RXPBDBLCTL->Bits.rxdll_bl_dq7rxpbdcode = DynamicVars[Channel][S0_Fixes16];
    break;
  case DYN_DQCCC_TXPBDCTL1_1:
    DYNSTRUCT_DQCCC_TXPBDCTL1 = (TXPBDCTL1_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_TXPBDCTL1->Bits.rxdll_bl_rxpbden = DynamicVars[Channel][S0_Fixes17];
    break;
  case DYN_DQCCC_DLLCOMP_FBMUXSEL:
    DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL = (DLLCOMP_FBMUXSEL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL->Bits.muxcode_max = DynamicVars[Channel][SS_TEMP_VAR];
    DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL->Bits.muxcode_min = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPIC_PLLCTL:
    DYNSTRUCT_DPIC_PLLCTL = (PLLCTL_DPIC_STRUCT *) Value;
    DYNSTRUCT_DPIC_PLLCTL->Bits.pll_cmn_fbclktrim = DynamicVars[Channel][SS_TEMP_VAR];
    DYNSTRUCT_DPIC_PLLCTL->Bits.pll_cmn_fbclktrim = 0x9;
    break;
  case DYN_DQCCC_DLLCOMP_FBMUXSEL_1:
    DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL = (DLLCOMP_FBMUXSEL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL->Bits.muxcode_max = DynamicVars[Channel][MUX_MAX];
    DYNSTRUCT_DQCCC_DLLCOMP_FBMUXSEL->Bits.muxcode_min = DynamicVars[Channel][MUX_MIN];
    break;
  case DYN_DQCCC_DLLCOMP_COARSECODE:
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE = (DLLCOMP_COARSECODE_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE->Bits.coarsecode_max = DynamicVars[Channel][COARSE_MAX];
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE->Bits.coarsecode_min = DynamicVars[Channel][COARSE_MIN];
    break;
  case DYN_DQCCC_DLLCOMP_FINECODE:
    DYNSTRUCT_DQCCC_DLLCOMP_FINECODE = (DLLCOMP_FINECODE_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DLLCOMP_FINECODE->Bits.finecode_max = DynamicVars[Channel][FINE_MAX];
    DYNSTRUCT_DQCCC_DLLCOMP_FINECODE->Bits.finecode_min = DynamicVars[Channel][FINE_MIN];
    break;
  case DYN_DPIC_PLLCTL_1:
    DYNSTRUCT_DPIC_PLLCTL = (PLLCTL_DPIC_STRUCT *) Value;
    DYNSTRUCT_DPIC_PLLCTL->Bits.pll_cmn_fbclktrim = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DQCCC_DLLCOMP_COARSECODE_1:
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE = (DLLCOMP_COARSECODE_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE->Bits.coarseicode_ovr_sel = 0x1;
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE->Bits.coarseicode_ovr = DynamicVars[Channel][SS_TEMP_VAR];
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE->Bits.coarsecode_ovr_sel = 0x0;
    DYNSTRUCT_DQCCC_DLLCOMP_COARSECODE->Bits.coarsecode_ovr = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DQCCC_TXDLLSIGGRP5CTL:
    DYNSTRUCT_DQCCC_TXDLLSIGGRP5CTL = (TXDLLSIGGRP5CTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_TXDLLSIGGRP5CTL->Bits.txdll_rk0siggrp05picode = DynamicVars[Channel][MAXPI_GRP5];
    break;
  case DYN_DQCCC_TXDLLSIGGRP4CTL:
    DYNSTRUCT_DQCCC_TXDLLSIGGRP4CTL = (TXDLLSIGGRP4CTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_TXDLLSIGGRP4CTL->Bits.txdll_rk0siggrp04picode = DynamicVars[Channel][MAXPI_GRP4];
    break;
  case DYN_DQCCC_TXDLLSIGGRP3CTL:
    DYNSTRUCT_DQCCC_TXDLLSIGGRP3CTL = (TXDLLSIGGRP3CTL_DQCCC_STRUCT *) Value;
    DYNSTRUCT_DQCCC_TXDLLSIGGRP3CTL->Bits.txdll_rk0siggrp03picode = DynamicVars[Channel][MAXPI_GRP3];
    break;
  default:
    *Value = 0xFFFFFFFF;
    break;
  }

  return MMRC_SUCCESS;
}

//
// Array of all MRS commands for a given channel.
//
#ifdef MR0_0
UINT16 MrsCommandIndex[MAX_RANKS][MR_COUNT] = {
{MR0_0, MR1_0, MR2_0},
{MR0_1, MR1_1, MR2_1},
};
#endif

//
// Table to convert a PFCT and IoLevel to a blueprint to access the correct IO GetSet tab.
//
CONST PFCT_AND_IO_LEVEL_TO_BLUEPRINT PfctAndIoLevelToBlueprint[MAX_IO_LEVELS] = {
//     Plat     Freq   Config               Tech      IoLevel         Blueprint
  {   P_ALL,   F_ALL,   C_ALL,          T_LPDDR3,    DdrLevel, BLUEPRINT_LPDDR3},
  {   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4,    DdrLevel, BLUEPRINT_LPDDR4},
};

INSTANCE_PORT_MAP InstancePortMapGenerated[MAX_BLUEPRINTS][MAX_BOXES] = {
  //TotalInst    Inst/Channel  StartIndex     R-Op     W-Op  Access Method  Access BAR   SimSupported     StrIndex
  { // BLUEPRINT_LPDDR3
    {     5,            1,         0,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000000}, // DUNIT
    {     5,            1,         5,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000040}, // CPGC
    {     8,            4,        10,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000156}, // DQCCC
    {     4,            2,        18,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000001BB}, // DQ
    {     4,            2,        22,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000021B}, // CCC
    {     4,            2,        26,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000027E}, // DPLVUG
    {     4,            2,        30,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002C9}, // ADPLL
    {     4,            2,        34,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002D8}, // LDO
    {     4,            2,        38,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002E3}, // DPIC
    {     4,            1,        42,         0xFF,    0xFF,    eBAR,          P2SBBAR,      FALSE,      0x0000030C}, // WIO2PHY
    {     1,            0,        46,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x0000030E}, // BUNIT
    {     1,            0,        47,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x0000042F}, // PUNIT
    {     1,            0,        48,         0xFF,    0xFF,    eBAR,           MCHBAR,      FALSE,      0x00000464}, // MLMC
    {     1,            0,        49,         0xFF,    0xFF,    ePCI,          MMRC_NA,       TRUE,      0x00000476}, // CUNIT
    {     1,            0,        50,         0xFF,    0xFF,    ePCI,          MMRC_NA,      FALSE,      0x000004AB}, // P2SB
    {     4,            2,        51,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000004DC}, // DDRSAI
    {     5,            1,        55,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x000004E9}, // SAI
    {     1,            0,        60,         0xFF,    0xFF,    eBAR,           MCHBAR,      FALSE,      0x000004F6}, // AUNIT
  },
  { // BLUEPRINT_LPDDR4
    {     5,            1,         0,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000000}, // DUNIT
    {     5,            1,         5,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000040}, // CPGC
    {     8,            2,        10,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000156}, // DQCCC
    {   255,          255,       255,         0xFF,    0xFF,    0xFF,          MMRC_NA,      FALSE,      0xFFFFFFFF}, // Invalid Box Type
    {   255,          255,       255,         0xFF,    0xFF,    0xFF,          MMRC_NA,      FALSE,      0xFFFFFFFF}, // Invalid Box Type
    {     4,            1,        26,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000027E}, // DPLVUG
    {     4,            1,        30,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002C9}, // ADPLL
    {     4,            1,        34,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002D8}, // LDO
    {     4,            1,        38,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002E3}, // DPIC
    {     4,            1,        42,         0x00,    0x01,     eSB,          MMRC_NA,      FALSE,      0x0000030C}, // WIO2PHY
    {     1,            0,        46,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x0000030E}, // BUNIT
    {     1,            0,        47,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x0000042F}, // PUNIT
    {     1,            0,        48,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000464}, // MLMC
    {     1,            0,        49,         0xFF,    0xFF,    ePCI,          MMRC_NA,       TRUE,      0x00000476}, // CUNIT
    {     1,            0,        50,         0xFF,    0xFF,    ePCI,          MMRC_NA,      FALSE,      0x000004AB}, // P2SB
    {     4,            1,        51,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000004DC}, // DDRSAI
    {   255,          255,       255,         0xFF,    0xFF,    0xFF,          MMRC_NA,      FALSE,      0xFFFFFFFF}, // Invalid Box Type
    {     1,            0,        60,         0xFF,    0xFF,    eBAR,           MCHBAR,      FALSE,      0x000004F6}, // AUNIT
  },
};

INSTANCE_PORT_OFFSET InstancePortOffsetGenerated[MAX_BLUEPRINTS][MAX_INSTANCE_PORTS] = {
  { // BLUEPRINT_LPDDR3
  {0x0000, 0x1000}, // DUNIT0
  {0x0000, 0x1200}, // DUNIT1
  {0x0000, 0x1400}, // DUNIT2
  {0x0000, 0x1600}, // DUNIT3
  {0x0000, 0x1800}, // DUNIT4
  {0x0012, 0x0000}, // CPGC0
  {0x0013, 0x0000}, // CPGC1
  {0x001A, 0x0000}, // CPGC2
  {0x001B, 0x0000}, // CPGC3
  {0x0000, 0x5000}, // CPGC4
  {0x001C, 0x0000}, // DQCCC0
  {0x001C, 0x0800}, // DQCCC1
  {0x001D, 0x0000}, // DQCCC2
  {0x001D, 0x0800}, // DQCCC3
  {0x0015, 0x0000}, // DQCCC4
  {0x0015, 0x0800}, // DQCCC5
  {0x0016, 0x0000}, // DQCCC6
  {0x0016, 0x0800}, // DQCCC7
  {0x001D, 0x0000}, // DQ0
  {0x001D, 0x0800}, // DQ1
  {0x0016, 0x0000}, // DQ2
  {0x0016, 0x0800}, // DQ3
  {0x001C, 0x0000}, // CCC0
  {0x001C, 0x0800}, // CCC1
  {0x0015, 0x0000}, // CCC2
  {0x0015, 0x0800}, // CCC3
  {0x001C, 0x1800}, // DPLVUG0
  {0x001D, 0x1800}, // DPLVUG1
  {0x0015, 0x1800}, // DPLVUG2
  {0x0016, 0x1800}, // DPLVUG3
  {0x001C, 0x2000}, // ADPLL0
  {0x001D, 0x2000}, // ADPLL1
  {0x0015, 0x2000}, // ADPLL2
  {0x0016, 0x2000}, // ADPLL3
  {0x001C, 0x2800}, // LDO0
  {0x001D, 0x2800}, // LDO1
  {0x0015, 0x2800}, // LDO2
  {0x0016, 0x2800}, // LDO3
  {0x001C, 0x1000}, // DPIC0
  {0x001D, 0x1000}, // DPIC1
  {0x0015, 0x1000}, // DPIC2
  {0x0016, 0x1000}, // DPIC3
  {0x0070, 0x0000}, // WIO2PHY0
  {0x0071, 0x0000}, // WIO2PHY1
  {0x0072, 0x0000}, // WIO2PHY2
  {0x0073, 0x0000}, // WIO2PHY3
  {0x0000, 0x0000}, // BUNIT0
  {0x0000, 0x0000}, // PUNIT0
  {0x0000, 0x0000}, // MLMC0
  {0x0000, 0x0000}, // CUNIT0
  {0x0068, 0x0000}, // P2SB0
  {0x0015, 0xF800}, // DDRSAI0
  {0x001D, 0xF800}, // DDRSAI1
  {0x0016, 0xF800}, // DDRSAI2
  {0x001C, 0xF800}, // DDRSAI3
  {0x0000, 0xF800}, // SAI0
  {0x0000, 0xF800}, // SAI1
  {0x0000, 0xF800}, // SAI2
  {0x0000, 0xF800}, // SAI3
  {0x0000, 0xF800}, // SAI4
  {0x0000, 0x0000}, // AUNIT0
  },
  { // BLUEPRINT_LPDDR4
  {0x0000, 0x1000}, // DUNIT0
  {0x0000, 0x1200}, // DUNIT1
  {0x0000, 0x1400}, // DUNIT2
  {0x0000, 0x1600}, // DUNIT3
  {0x0000, 0x1800}, // DUNIT4
  {0x0012, 0x0000}, // CPGC0
  {0x0013, 0x0000}, // CPGC1
  {0x001A, 0x0000}, // CPGC2
  {0x001B, 0x0000}, // CPGC3
  {0x0000, 0x5000}, // CPGC4
  {0x001C, 0x0000}, // DQCCC0
  {0x001C, 0x0800}, // DQCCC1
  {0x0015, 0x0000}, // DQCCC2
  {0x0015, 0x0800}, // DQCCC3
  {0x001D, 0x0000}, // DQCCC4
  {0x001D, 0x0800}, // DQCCC5
  {0x0016, 0x0000}, // DQCCC6
  {0x0016, 0x0800}, // DQCCC7
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0x001C, 0x1800}, // DPLVUG0
  {0x0015, 0x1800}, // DPLVUG1
  {0x001D, 0x1800}, // DPLVUG2
  {0x0016, 0x1800}, // DPLVUG3
  {0x001C, 0x2000}, // ADPLL0
  {0x0015, 0x2000}, // ADPLL1
  {0x001D, 0x2000}, // ADPLL2
  {0x0016, 0x2000}, // ADPLL3
  {0x001C, 0x2800}, // LDO0
  {0x0015, 0x2800}, // LDO1
  {0x001D, 0x2800}, // LDO2
  {0x0016, 0x2800}, // LDO3
  {0x001C, 0x1000}, // DPIC0
  {0x0015, 0x1000}, // DPIC1
  {0x001D, 0x1000}, // DPIC2
  {0x0016, 0x1000}, // DPIC3
  {0x0070, 0x0000}, // WIO2PHY0
  {0x0071, 0x0000}, // WIO2PHY1
  {0x0072, 0x0000}, // WIO2PHY2
  {0x0073, 0x0000}, // WIO2PHY3
  {0x0000, 0x0000}, // BUNIT0
  {0x0000, 0x0000}, // PUNIT0
  {0x0000, 0x0000}, // MLMC0
  {0x0000, 0x0000}, // CUNIT0
  {0x0068, 0x0000}, // P2SB0
  {0x0015, 0xF800}, // DDRSAI0
  {0x001D, 0xF800}, // DDRSAI1
  {0x0016, 0xF800}, // DDRSAI2
  {0x001C, 0xF800}, // DDRSAI3
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0xFFFF, 0xFFFF}, // Invalid BoxType
  {0x0000, 0x0000}, // AUNIT0
  },
};

UINT8 ChannelToInstanceMapGenerated[MAX_BLUEPRINTS][MAX_BOXES][MAX_CHANNELS] = {
//CH00  CH01  CH02  CH03  
  { // BLUEPRINT_LPDDR3
  {0x00, 0x01, 0x02, 0x03}, // DUNIT
  {0x00, 0x01, 0x02, 0x03}, // CPGC
  {0xFF, 0xFF, 0x00, 0x04}, // DQCCC
  {0xFF, 0xFF, 0x00, 0x02}, // DQ
  {0xFF, 0xFF, 0x00, 0x02}, // CCC
  {0xFF, 0xFF, 0x00, 0x02}, // DPLVUG
  {0xFF, 0xFF, 0x00, 0x02}, // ADPLL
  {0xFF, 0xFF, 0x00, 0x02}, // LDO
  {0xFF, 0xFF, 0x00, 0x02}, // DPIC
  {0x00, 0x00, 0x01, 0x01}, // WIO2PHY
  {0x00, 0x00, 0x00, 0x00}, // BUNIT
  {0x00, 0x00, 0x00, 0x00}, // PUNIT
  {0x00, 0x00, 0x00, 0x00}, // MLMC
  {0x00, 0x00, 0x00, 0x00}, // CUNIT
  {0x00, 0x00, 0x00, 0x00}, // P2SB
  {0xFF, 0xFF, 0x00, 0x02}, // DDRSAI
  {0x00, 0x01, 0x02, 0x03}, // SAI
  {0x00, 0x00, 0x00, 0x00}, // AUNIT
  },
  { // BLUEPRINT_LPDDR4
  {0x00, 0x01, 0x02, 0x03}, // DUNIT
  {0x00, 0x01, 0x02, 0x03}, // CPGC
  {0x00, 0x02, 0x04, 0x06}, // DQCCC
  {0xFF, 0xFF, 0xFF, 0xFF}, // INVALID ENTRY
  {0xFF, 0xFF, 0xFF, 0xFF}, // INVALID ENTRY
  {0x00, 0x01, 0x02, 0x03}, // DPLVUG
  {0x00, 0x01, 0x02, 0x03}, // ADPLL
  {0x00, 0x01, 0x02, 0x03}, // LDO
  {0x00, 0x01, 0x02, 0x03}, // DPIC
  {0x00, 0x00, 0x01, 0x01}, // WIO2PHY
  {0x00, 0x00, 0x00, 0x00}, // BUNIT
  {0x00, 0x00, 0x00, 0x00}, // PUNIT
  {0x00, 0x00, 0x00, 0x00}, // MLMC
  {0x00, 0x00, 0x00, 0x00}, // CUNIT
  {0x00, 0x00, 0x00, 0x00}, // P2SB
  {0x00, 0x01, 0x02, 0x03}, // DDRSAI
  {0xFF, 0xFF, 0xFF, 0xFF}, // INVALID ENTRY
  {0x00, 0x00, 0x00, 0x00}, // AUNIT
  },
};

#if CAPSULESTRINGS
CONST UINT8 UnitStringsGenerated[MAX_BLUEPRINTS][MAX_BOXES][MAX_BOXNAME_LENGTH] = {
  { // BLUEPRINT_LPDDR3
  {"DUNIT  "}, // 000
  {"CPGC   "}, // 001
  {"DQCCC  "}, // 002
  {"DQ     "}, // 003
  {"CCC    "}, // 004
  {"DPLVUG "}, // 005
  {"ADPLL  "}, // 006
  {"LDO    "}, // 007
  {"DPIC   "}, // 008
  {"WIO2PHY"}, // 009
  {"BUNIT  "}, // 00A
  {"PUNIT  "}, // 00B
  {"MLMC   "}, // 00C
  {"CUNIT  "}, // 00D
  {"P2SB   "}, // 00E
  {"DDRSAI "}, // 00F
  {"SAI    "}, // 010
  {"AUNIT  "}, // 011
  },
  { // BLUEPRINT_LPDDR4
  {"DUNIT  "}, // 000
  {"CPGC   "}, // 001
  {"DQCCC  "}, // 002
  {"INVALID"}, // INVALID ENTRY
  {"INVALID"}, // INVALID ENTRY
  {"DPLVUG "}, // 005
  {"ADPLL  "}, // 006
  {"LDO    "}, // 007
  {"DPIC   "}, // 008
  {"WIO2PHY"}, // 009
  {"BUNIT  "}, // 00A
  {"PUNIT  "}, // 00B
  {"MLMC   "}, // 00C
  {"CUNIT  "}, // 00D
  {"P2SB   "}, // 00E
  {"DDRSAI "}, // 00F
  {"INVALID"}, // INVALID ENTRY
  {"AUNIT  "}, // 011
  },
};
#endif // CAPSULESTRINGS

//
// Floorplan layout to map logical channel and strobe to a physical channel and strobe.
//
CONST FLOORPLAN FloorPlanGenerated[MAX_BLUEPRINTS][MAX_CHANNELS][MAX_STROBES] = {
//     S0       S1       S2       S3  
  { // BLUEPRINT_LPDDR3
  {  {0,0},   {0,1},   {0,2},   {0,3}}, // CH0
  {  {1,0},   {1,1},   {1,2},   {1,3}}, // CH1
  {  {2,0},   {2,1},   {2,2},   {2,3}}, // CH2
  {  {3,0},   {3,1},   {3,2},   {3,3}}, // CH3
  },
  { // BLUEPRINT_LPDDR4
  {  {0,0},   {0,1},   {0,2},   {0,3}}, // CH0
  {  {1,0},   {1,1},   {1,2},   {1,3}}, // CH1
  {  {2,0},   {2,1},   {2,2},   {2,3}}, // CH2
  {  {3,0},   {3,1},   {3,2},   {3,3}}, // CH3
  },
};
//
// Given a base register (i.e. Strobe0/Rank0's copy of the register, these tables index to the correct register location for a given strobe/rank.
//
CONST INT16 StrobeToRegisterGenerated[MAX_BLUEPRINTS][MAX_STROBES][2] = {
//  Sub-box Offset  Register Offset
  { // BLUEPRINT_LPDDR3
  {0,              0},             // S0
  {0,              0},             // S1
  {0,              0},             // S2
  {0,              0},             // S3
  },
  { // BLUEPRINT_LPDDR4
  {0,              0},             // S0
  {0,              0},             // S1
  {0,              0},             // S2
  {0,              0},             // S3
  },
};

CONST INT16 RankToRegisterGenerated[MAX_BLUEPRINTS][MAX_RANKS][2] = {
//  Sub-box Offset  Register Offset
  { // BLUEPRINT_LPDDR3
   {0,              0},             // R0
   {0,              0},             // R1
  },
  { // BLUEPRINT_LPDDR4
   {0,              0},             // R0
   {0,              0},             // R1
  },
};
//
// Mapping of GSM_GT enumerated types to internal MMRC define.
//
UINT16 GsmGtToMmrcDefine[] = {
  MmrcRecEnDelay,
  MmrcRxDqsDelay,
  MMRC_NA,
  MmrcRxDqsPDelay,
  MmrcRxDqsNDelay,
  MmrcRxVref,
  MMRC_NA,
  MmrcRxDqBitDelay,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MmrcTxDqsDelay,
  MmrcTxDqDelay,
  MmrcTxVref,
  MMRC_NA,
  MmrcTxDqBitDelay,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MmrcCmdAll,
  MmrcCmdGrp0,
  MmrcCmdGrp1,
  MMRC_NA,
  MmrcCtlAll,
  MmrcCtlGrp0,
  MmrcCtlGrp1,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MmrcCkAll,
  MmrcCkGrp0,
  MmrcCkGrp1,
  MmrcTxCaVref,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
};
//
// Mapping of GSM_CSN enumerated types to internal MMRC define.
//
UINT16 GsmCsnToMmrcDefine[] = {
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
};
//
// External functions that need to be called for GetSet elements which require and external function to read/write the element.
//
EXTERNAL_GETSET_FUNCTION ExternalFunctions [] = {
{ GetSetTxDqBitDelay }, // TxDqBitDelay
{ GetSetDqDelay }, // TxDqDelay
{ GetSetTxVref }, // TxVref
{ GetSetTxCaVref }, // TxCaVref
};
//
// DLL indexes into the HalfClk array for analog and digital DLLs.
//
UINT8 ADdllGenerated[MAX_BLUEPRINTS][2] = {
  // BLUEPRINT_LPDDR3
  {MMRC_NA, 0  },

  // BLUEPRINT_LPDDR4
  {MMRC_NA, 0  },

};
//
// The number of ticks in the 2X clock for analog and digital DLL. These can change depending on frequency.
//
UINT16 HalfClkGenerated[MAX_BLUEPRINTS][MAX_DLL_COUNT][NUM_FREQ] = {
  { // BLUEPRINT_LPDDR3
  { 248,  184,  152,  104,  104,   96,   80,   72,   68,   64  }, //  Digital DLL
  },
  { // BLUEPRINT_LPDDR4
  { 248,  184,  152,  104,  104,   96,   80,   72,   68,   64  }, //  Digital DLL
  },
};
//
// This array has all delays listed for analog DLL and digital DLL (depending on which are present), per frequency. Typically the first two delays on each line are the 1X clock and 2X clock.
//
UINT16 GranularityGenerated[MAX_BLUEPRINTS][MAX_DLL_COUNT][NUM_FREQ][MAX_NUM_DELAY_ELEMENTS] = {
  { // BLUEPRINT_LPDDR3
  // Digital DLL
  {
    {  496,  248,    1}, //  800
    {  368,  184,    1}, //  1066
    {  304,  152,    1}, //  1333
    {  208,  104,    1}, //  1600
    {  208,  104,    1}, //  1866
    {  192,   96,    1}, //  2133
    {  160,   80,    1}, //  2400
    {  144,   72,    1}, //  2667
    {  136,   68,    1}, //  2933
    {  128,   64,    1}, //  3200
  },
  },
  { // BLUEPRINT_LPDDR4
  // Digital DLL
  {
    {  496,  248,    1}, //  800
    {  368,  184,    1}, //  1066
    {  304,  152,    1}, //  1333
    {  208,  104,    1}, //  1600
    {  208,  104,    1}, //  1866
    {  192,   96,    1}, //  2133
    {  160,   80,    1}, //  2400
    {  144,   72,    1}, //  2667
    {  136,   68,    1}, //  2933
    {  128,   64,    1}, //  3200
  },
  },
};
//
// Clock crossings or deadbands. If the the delay value is between Min and Max, then InVal is used for the clock crossing.
// If Absolute is TRUE, InVal is programmed directly into the register. If FALSE, it is added to the current value of the register.
//
CLOCK_CROSSINGS ClockCrossingsGenerated[MAX_BLUEPRINTS][MAX_NUM_CC_RANGES]  = {
  // CcNum Min%  Max%  InVal Absolute
  { // BLUEPRINT_LPDDR3
  {    0,    0,   25,    3,    TRUE}, // CC0
  {    0,   25,   50,    1,    TRUE}, // CC0
  {    0,   50,   75,    0,    TRUE}, // CC0
  {    0,   75,  100,    2,    TRUE}, // CC0
  {    1,    0,   25,    1,    TRUE}, // CC1
  {    1,   25,   50,    1,    TRUE}, // CC1
  {    1,   50,   75,    0,    TRUE}, // CC1
  {    1,   75,  100,    1,    TRUE}, // CC1
  {    2,    0,   25,   -1,   FALSE}, // CC2
  {    2,   25,   50,   -1,   FALSE}, // CC2
  {    2,   50,   75,    0,   FALSE}, // CC2
  {    2,   75,  100,   -1,   FALSE}, // CC2
  },
  { // BLUEPRINT_LPDDR4
  {    0,    0,   25,    3,    TRUE}, // CC0
  {    0,   25,   50,    1,    TRUE}, // CC0
  {    0,   50,   75,    0,    TRUE}, // CC0
  {    0,   75,  100,    2,    TRUE}, // CC0
  {    1,    0,   25,    1,    TRUE}, // CC1
  {    1,   25,   50,    1,    TRUE}, // CC1
  {    1,   50,   75,    0,    TRUE}, // CC1
  {    1,   75,  100,    1,    TRUE}, // CC1
  {    2,    0,   25,   -1,   FALSE}, // CC2
  {    2,   25,   50,   -1,   FALSE}, // CC2
  {    2,   50,   75,    0,   FALSE}, // CC2
  {    2,   75,  100,   -1,   FALSE}, // CC2
  },
};
//
// Digital DLL ranges. These are used to specify the min and max of the Digital DLL range per frequency. Also describes any holes in the range like ValleyView had.
//
const DIGITAL_DLL_LIST DigitalDllRangesGenerated[MAX_BLUEPRINTS][NUM_FREQ] = {
  { // BLUEPRINT_LPDDR3
  // PI     Min0     Max0     Min1     Max1
  { 248,       0,     247, MMRC_NA, MMRC_NA}, // 800
  { 184,       0,     183, MMRC_NA, MMRC_NA}, // 1066
  { 152,       0,     151, MMRC_NA, MMRC_NA}, // 1333
  { 104,       0,     103, MMRC_NA, MMRC_NA}, // 1600
  { 104,       0,     103, MMRC_NA, MMRC_NA}, // 1866
  {  96,       0,      95, MMRC_NA, MMRC_NA}, // 2133
  {  80,       0,      79, MMRC_NA, MMRC_NA}, // 2400
  {  72,       0,      71, MMRC_NA, MMRC_NA}, // 2667
  {  68,       0,      67, MMRC_NA, MMRC_NA}, // 2933
  {  64,       0,      63, MMRC_NA, MMRC_NA}, // 3200
  },
  { // BLUEPRINT_LPDDR4
  // PI     Min0     Max0     Min1     Max1
  { 248,       0,     247, MMRC_NA, MMRC_NA}, // 800
  { 184,       0,     183, MMRC_NA, MMRC_NA}, // 1066
  { 152,       0,     151, MMRC_NA, MMRC_NA}, // 1333
  { 104,       0,     103, MMRC_NA, MMRC_NA}, // 1600
  { 104,       0,     103, MMRC_NA, MMRC_NA}, // 1866
  {  96,       0,      95, MMRC_NA, MMRC_NA}, // 2133
  {  80,       0,      79, MMRC_NA, MMRC_NA}, // 2400
  {  72,       0,      71, MMRC_NA, MMRC_NA}, // 2667
  {  68,       0,      67, MMRC_NA, MMRC_NA}, // 2933
  {  64,       0,      63, MMRC_NA, MMRC_NA}, // 3200
  },
};
//
// List out the number of signal groups and the strings for each signal group.
//
SIGNAL_INFO SignalInfoGenerated[MAX_BLUEPRINTS][MAX_SIGNAL_INFO_ELEMENTS] = {
  { // BLUEPRINT_LPDDR3
// SigGrp NextFreq FreqIndex        VREF      Minus1            SigName
  {     1,       1,        0,    MMRC_NA,    MMRC_NA, "TxDqDelay_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "TxDqsDelay"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,           "CkGrp0"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,           "CkGrp1"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CmdGrp0"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CmdGrp1"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CtlGrp0"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CtlGrp1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RecEnDelay"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,      "RxDqsNDelay"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,      "RxDqsPDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "Ctle"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "Ctle_Cap"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "Ctle_Res"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "DQS_CNT_RESET"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "FifoReset"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "Grp6_2x"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "PerCompSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RecEnSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,     "RxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxOdtOvr"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxOdtVal"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocEnDq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxVocEnDqs"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxVocVal"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,     "TxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxDqDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "TxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "WR_LVL_MODE"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "WR_LVL_MODE_C"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "WrLvlSmp"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,   "RxDiffampOvrDq"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,  "RxDiffampOvrDqs"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,   "RxDiffampValDq"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,  "RxDiffampValDqs"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,    "INVALID ENTRY"},
  },
  { // BLUEPRINT_LPDDR4
// SigGrp NextFreq FreqIndex        VREF      Minus1            SigName
  {     1,       1,        0,    MMRC_NA,    MMRC_NA, "TxDqDelay_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "TxDqsDelay"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,           "CkGrp0"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,           "CkGrp1"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CmdGrp0"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CmdGrp1"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CtlGrp0"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,          "CtlGrp1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RecEnDelay"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,      "RxDqsNDelay"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,      "RxDqsPDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "CkeAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "Ctle"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "Ctle_Cap"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "Ctle_Res"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "CURRENT_INDEX"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "DiffampOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "DQS_CNT_RESET"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "FifoReset"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "Grp6_2x"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "INITIAL_INDEX"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "MuxcodeMax"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "MuxcodeMin"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "OdtEnOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "OdtSegEnOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RecEnSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,     "RxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxOdtOvr"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxOdtVal"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocEnDq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxVocEnDqs"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxVocSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "TxCaVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,     "TxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxDqDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "TxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "WR_LVL_MODE"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "WR_LVL_MODE_C"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "WrLvlSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "WrPtrEn"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,   "RxDiffampOvrDq"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,  "RxDiffampOvrDqs"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,   "RxDiffampValDq"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,  "RxDiffampValDqs"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal0"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal1"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal2"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal3"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal4"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal5"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal6"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal7"},
  },
};
//
// Layer to get the right number of Algos
//
CONST UINT8 NumberAlgosGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_ALGOS_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_ALGOS_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right number of CC Dependent Elements
//
CONST UINT8 NumberOfDependantElementsGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_CC_DEPENDENT_ELEMENTS_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_CC_DEPENDENT_ELEMENTS_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right number of Delay Elements per Algo
//
CONST UINT8 NumberOfDelayElementsPerAlgoGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_DELAY_ELEMENTS_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_DELAY_ELEMENTS_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right number of CC Elements
//
CONST UINT8 NumberOfCCElementsGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_CC_ELEMENTS_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_CC_ELEMENTS_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right number of CC Ranges
//
CONST UINT8 NumberOfCCRangesGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_CC_RANGES_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_CC_RANGES_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right number of elementes (delay + CC) per Algo
//
CONST UINT8 NumberOfElementsPerAlgoGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_ELEMENTS_PER_ALGO_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_ELEMENTS_PER_ALGO_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right number of DVFS frequencies supported
//
CONST UINT8 NumberOfFrequenciesGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR3
  NUM_DVFS_BLUEPRINT_LPDDR3,
  // BLUEPRINT_LPDDR4
  NUM_DVFS_BLUEPRINT_LPDDR4,
};
//
// Layer to get the right offset of a Delay
//
CONST INDEX_TO_OFFSET_LAYER DelayIndexToOffsetLayerGenerated[MAX_BLUEPRINTS][MAX_NUM_ALGOS] = {
  { // BLUEPRINT_LPDDR3
  {TxDqDelay_Actual_BLUEPRINT_LPDDR3},
  {TxDqsDelay_BLUEPRINT_LPDDR3},
  {CkGrp0_BLUEPRINT_LPDDR3},
  {CkGrp1_BLUEPRINT_LPDDR3},
  {CmdGrp0_BLUEPRINT_LPDDR3},
  {CmdGrp1_BLUEPRINT_LPDDR3},
  {CtlGrp0_BLUEPRINT_LPDDR3},
  {CtlGrp1_BLUEPRINT_LPDDR3},
  {RecEnDelay_BLUEPRINT_LPDDR3},
  {RxDqsNDelay_BLUEPRINT_LPDDR3},
  {RxDqsPDelay_BLUEPRINT_LPDDR3},
  },
  { // BLUEPRINT_LPDDR4
  {TxDqDelay_Actual_BLUEPRINT_LPDDR4},
  {TxDqsDelay_BLUEPRINT_LPDDR4},
  {CkGrp0_BLUEPRINT_LPDDR4},
  {CkGrp1_BLUEPRINT_LPDDR4},
  {CmdGrp0_BLUEPRINT_LPDDR4},
  {CmdGrp1_BLUEPRINT_LPDDR4},
  {CtlGrp0_BLUEPRINT_LPDDR4},
  {CtlGrp1_BLUEPRINT_LPDDR4},
  {RecEnDelay_BLUEPRINT_LPDDR4},
  {RxDqsNDelay_BLUEPRINT_LPDDR4},
  {RxDqsPDelay_BLUEPRINT_LPDDR4},
  },
};
//
// Layer to get the right offset of a Group
//
CONST INDEX_TO_OFFSET_LAYER GroupIndexToOffsetLayerGenerated[MAX_BLUEPRINTS][MAX_NUM_GROUP] = {
  { // BLUEPRINT_LPDDR3
  {CkAll_BLUEPRINT_LPDDR3},
  {CmdAll_BLUEPRINT_LPDDR3},
  {CtlAll_BLUEPRINT_LPDDR3},
  {R_BLUEPRINT_LPDDR3},
  {RxDqsDelay_BLUEPRINT_LPDDR3},
  },
  { // BLUEPRINT_LPDDR4
  {CkAll_BLUEPRINT_LPDDR4},
  {CmdAll_BLUEPRINT_LPDDR4},
  {CtlAll_BLUEPRINT_LPDDR4},
  {R_BLUEPRINT_LPDDR4},
  {RxDqsDelay_BLUEPRINT_LPDDR4},
  },
};
//
// Layer to get the right offset of a Unique
//
CONST INDEX_TO_OFFSET_LAYER UniqueIndexToOffsetLayerGenerated[MAX_BLUEPRINTS][MAX_NUM_UNIQUE] = {
  { // BLUEPRINT_LPDDR3
  {Ctle_BLUEPRINT_LPDDR3},
  {Ctle_Cap_BLUEPRINT_LPDDR3},
  {Ctle_Res_BLUEPRINT_LPDDR3},
  {DQS_CNT_RESET_BLUEPRINT_LPDDR3},
  {FifoReset_BLUEPRINT_LPDDR3},
  {Grp6_2x_BLUEPRINT_LPDDR3},
  {PerCompSmp_BLUEPRINT_LPDDR3},
  {RecEnSmp_BLUEPRINT_LPDDR3},
  {RxDqBitDelay_BLUEPRINT_LPDDR3},
  {RxOdtOvr_BLUEPRINT_LPDDR3},
  {RxOdtVal_BLUEPRINT_LPDDR3},
  {RxVocEnDq_BLUEPRINT_LPDDR3},
  {RxVocEnDqs_BLUEPRINT_LPDDR3},
  {RxVocVal_BLUEPRINT_LPDDR3},
  {RxVref_BLUEPRINT_LPDDR3},
  {TxDqBitDelay_BLUEPRINT_LPDDR3},
  {TxDqDelay_BLUEPRINT_LPDDR3},
  {TxVref_BLUEPRINT_LPDDR3},
  {WR_LVL_MODE_BLUEPRINT_LPDDR3},
  {WR_LVL_MODE_C_BLUEPRINT_LPDDR3},
  {WrLvlSmp_BLUEPRINT_LPDDR3},
  {RxDiffampOvrDq_BLUEPRINT_LPDDR3},
  {RxDiffampOvrDqs_BLUEPRINT_LPDDR3},
  {RxDiffampValDq_BLUEPRINT_LPDDR3},
  {RxDiffampValDqs_BLUEPRINT_LPDDR3},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  },
  { // BLUEPRINT_LPDDR4
  {Ctle_BLUEPRINT_LPDDR4},
  {Ctle_Cap_BLUEPRINT_LPDDR4},
  {Ctle_Res_BLUEPRINT_LPDDR4},
  {DQS_CNT_RESET_BLUEPRINT_LPDDR4},
  {FifoReset_BLUEPRINT_LPDDR4},
  {Grp6_2x_BLUEPRINT_LPDDR4},
  {REG_UNDEFINED},
  {RecEnSmp_BLUEPRINT_LPDDR4},
  {RxDqBitDelay_BLUEPRINT_LPDDR4},
  {RxOdtOvr_BLUEPRINT_LPDDR4},
  {RxOdtVal_BLUEPRINT_LPDDR4},
  {RxVocEnDq_BLUEPRINT_LPDDR4},
  {RxVocEnDqs_BLUEPRINT_LPDDR4},
  {REG_UNDEFINED},
  {RxVref_BLUEPRINT_LPDDR4},
  {TxDqBitDelay_BLUEPRINT_LPDDR4},
  {TxDqDelay_BLUEPRINT_LPDDR4},
  {TxVref_BLUEPRINT_LPDDR4},
  {WR_LVL_MODE_BLUEPRINT_LPDDR4},
  {WR_LVL_MODE_C_BLUEPRINT_LPDDR4},
  {WrLvlSmp_BLUEPRINT_LPDDR4},
  {RxDiffampOvrDq_BLUEPRINT_LPDDR4},
  {RxDiffampOvrDqs_BLUEPRINT_LPDDR4},
  {RxDiffampValDq_BLUEPRINT_LPDDR4},
  {RxDiffampValDqs_BLUEPRINT_LPDDR4},
  {CkeAll_BLUEPRINT_LPDDR4},
  {CURRENT_INDEX_BLUEPRINT_LPDDR4},
  {DiffampOff_BLUEPRINT_LPDDR4},
  {INITIAL_INDEX_BLUEPRINT_LPDDR4},
  {MuxcodeMax_BLUEPRINT_LPDDR4},
  {MuxcodeMin_BLUEPRINT_LPDDR4},
  {OdtEnOff_BLUEPRINT_LPDDR4},
  {OdtSegEnOff_BLUEPRINT_LPDDR4},
  {RxVocSmp_BLUEPRINT_LPDDR4},
  {TxCaVref_BLUEPRINT_LPDDR4},
  {WrPtrEn_BLUEPRINT_LPDDR4},
  {RxVocVal0_BLUEPRINT_LPDDR4},
  {RxVocVal1_BLUEPRINT_LPDDR4},
  {RxVocVal2_BLUEPRINT_LPDDR4},
  {RxVocVal3_BLUEPRINT_LPDDR4},
  {RxVocVal4_BLUEPRINT_LPDDR4},
  {RxVocVal5_BLUEPRINT_LPDDR4},
  {RxVocVal6_BLUEPRINT_LPDDR4},
  {RxVocVal7_BLUEPRINT_LPDDR4},
  },
};
//
// This array has all delays, VREFs, clock crossings, and other DDRIO elements that MRC needs to access on a per-strobe or per-bit level.
//
CONST GET_SET_ELEMENTS ElementsGenerated[MAX_BLUEPRINTS][MAX_NUM_ELEMENTS] = {
  // BoxType,    Location                                                                    CacheIndex  Attribs       SB   Sb       NB   Nb       BB   Bb    MaxValue       Delay  
  //             RANK 0                                RANK 1                                
  { // BLUEPRINT_LPDDR3
  {DQ        , {{WRDQSCTL_DQ_REG           ,  0,  5}, {WRDQSCTL_DQ_REG           ,  0,  5}},       0x82,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0000, TxDqDelay_Actual Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG    ,  8, 11}, {TXDLLSIGGRP0CTL_DQ_REG    , 24, 27}},       0x84,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0001, TxDqDelay_Actual Granularity HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG    ,  0,  7}, {TXDLLSIGGRP0CTL_DQ_REG    , 16, 23}},       0x84,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0002, TxDqDelay_Actual Granularity 1
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG    ,  4,  5}, {TXDLLSIGGRP6CTL_DQ_REG    ,  4,  5}},       0x85,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0003, TxDqDelay_Actual CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0004, TxDqDelay_Actual CC1
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG    ,  8, 11}, {TXDLLSIGGRP0CTL_DQ_REG    ,  8, 11}},       0x84,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0005, TxDqDelay_Actual CC2
  {DQ        , {{WRDQSCTL_DQ_REG           ,  0,  5}, {WRDQSCTL_DQ_REG           ,  0,  5}},       0x82,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0006, TxDqsDelay Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG    ,  8, 11}, {TXDLLSIGGRP1CTL_DQ_REG    , 24, 27}},       0x83,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0007, TxDqsDelay Granularity HC
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG    ,  0,  7}, {TXDLLSIGGRP1CTL_DQ_REG    , 16, 23}},       0x83,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0008, TxDqsDelay Granularity 1
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG    , 12, 13}, {TXDLLSIGGRP1CTL_DQ_REG    , 28, 29}},       0x83,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0009, TxDqsDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x000A, TxDqsDelay CC1
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG    ,  8, 11}, {TXDLLSIGGRP1CTL_DQ_REG    ,  8, 11}},       0x83,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000B, TxDqsDelay CC2
  {CCC       , {{RCVENCTL_DQ_CCC_REG       ,  0,  5}, {RCVENCTL_DQ_CCC_REG       ,  0,  5}},       0x89,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x000C, CkGrp0 Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP4CTL_CCC_REG   ,  8, 11}, {TXDLLSIGGRP4CTL_CCC_REG   ,  8, 11}},       0x8A,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000D, CkGrp0 Granularity HC
  {CCC       , {{TXDLLSIGGRP4CTL_CCC_REG   ,  0,  7}, {TXDLLSIGGRP4CTL_CCC_REG   ,  0,  7}},       0x8A,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x000E, CkGrp0 Granularity 1
  {CCC       , {{TXDLLSIGGRP4CTL_CCC_REG   , 12, 13}, {TXDLLSIGGRP4CTL_CCC_REG   , 12, 13}},       0x8A,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x000F, CkGrp0 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0010, CkGrp0 CC1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0011, CkGrp0 CC2
  {CCC       , {{RCVENCTL_DQ_CCC_REG       ,  0,  5}, {RCVENCTL_DQ_CCC_REG       ,  0,  5}},       0x89,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0012, CkGrp1 Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP4CTLA_CCC_REG  ,  8, 11}, {TXDLLSIGGRP4CTLA_CCC_REG  ,  8, 11}},       0x8B,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0013, CkGrp1 Granularity HC
  {CCC       , {{TXDLLSIGGRP4CTLA_CCC_REG  ,  0,  7}, {TXDLLSIGGRP4CTLA_CCC_REG  ,  0,  7}},       0x8B,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0014, CkGrp1 Granularity 1
  {CCC       , {{TXDLLSIGGRP4CTLA_CCC_REG  , 12, 13}, {TXDLLSIGGRP4CTLA_CCC_REG  , 12, 13}},       0x8B,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0015, CkGrp1 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0016, CkGrp1 CC1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0017, CkGrp1 CC2
  {CCC       , {{RCVENCTL_DQ_CCC_REG       ,  0,  5}, {RCVENCTL_DQ_CCC_REG       ,  0,  5}},       0x89,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0018, CmdGrp0 Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP3CTL_CCC_REG   ,  8, 11}, {TXDLLSIGGRP3CTL_CCC_REG   ,  8, 11}},       0x8C,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0019, CmdGrp0 Granularity HC
  {CCC       , {{TXDLLSIGGRP3CTL_CCC_REG   ,  0,  7}, {TXDLLSIGGRP3CTL_CCC_REG   ,  0,  7}},       0x8C,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x001A, CmdGrp0 Granularity 1
  {CCC       , {{TXDLLSIGGRP3CTL_CCC_REG   , 12, 13}, {TXDLLSIGGRP3CTL_CCC_REG   , 12, 13}},       0x8C,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x001B, CmdGrp0 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x001C, CmdGrp0 CC1
  {CCC       , {{TXDLLSIGGRP3CTL_CCC_REG   ,  8, 11}, {TXDLLSIGGRP3CTL_CCC_REG   ,  8, 11}},       0x8C,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001D, CmdGrp0 CC2
  {CCC       , {{RCVENCTL_DQ_CCC_REG       ,  0,  5}, {RCVENCTL_DQ_CCC_REG       ,  0,  5}},       0x89,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x001E, CmdGrp1 Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP3CTLA_CCC_REG  ,  8, 11}, {TXDLLSIGGRP3CTLA_CCC_REG  ,  8, 11}},       0x8D,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001F, CmdGrp1 Granularity HC
  {CCC       , {{TXDLLSIGGRP3CTLA_CCC_REG  ,  0,  7}, {TXDLLSIGGRP3CTLA_CCC_REG  ,  0,  7}},       0x8D,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0020, CmdGrp1 Granularity 1
  {CCC       , {{TXDLLSIGGRP3CTLA_CCC_REG  , 12, 13}, {TXDLLSIGGRP3CTLA_CCC_REG  , 12, 13}},       0x8D,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0021, CmdGrp1 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0022, CmdGrp1 CC1
  {CCC       , {{TXDLLSIGGRP3CTLA_CCC_REG  ,  8, 11}, {TXDLLSIGGRP3CTLA_CCC_REG  ,  8, 11}},       0x8D,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0023, CmdGrp1 CC2
  {CCC       , {{RCVENCTL_DQ_CCC_REG       ,  0,  5}, {RCVENCTL_DQ_CCC_REG       ,  0,  5}},       0x89,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0024, CtlGrp0 Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP5CTL_CCC_REG   ,  8, 11}, {TXDLLSIGGRP5CTL_CCC_REG   ,  8, 11}},       0x8E,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0025, CtlGrp0 Granularity HC
  {CCC       , {{TXDLLSIGGRP5CTL_CCC_REG   ,  0,  7}, {TXDLLSIGGRP5CTL_CCC_REG   ,  0,  7}},       0x8E,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0026, CtlGrp0 Granularity 1
  {CCC       , {{TXDLLSIGGRP5CTL_CCC_REG   , 12, 13}, {TXDLLSIGGRP5CTL_CCC_REG   , 12, 13}},       0x8E,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0027, CtlGrp0 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0028, CtlGrp0 CC1
  {CCC       , {{TXDLLSIGGRP5CTL_CCC_REG   ,  8, 11}, {TXDLLSIGGRP5CTL_CCC_REG   ,  8, 11}},       0x8E,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0029, CtlGrp0 CC2
  {CCC       , {{RCVENCTL_DQ_CCC_REG       ,  0,  5}, {RCVENCTL_DQ_CCC_REG       ,  0,  5}},       0x89,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x002A, CtlGrp1 Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP5CTLA_CCC_REG  ,  8, 11}, {TXDLLSIGGRP5CTLA_CCC_REG  ,  8, 11}},       0x8F,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x002B, CtlGrp1 Granularity HC
  {CCC       , {{TXDLLSIGGRP5CTLA_CCC_REG  ,  0,  7}, {TXDLLSIGGRP5CTLA_CCC_REG  ,  0,  7}},       0x8F,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x002C, CtlGrp1 Granularity 1
  {CCC       , {{TXDLLSIGGRP5CTLA_CCC_REG  , 12, 13}, {TXDLLSIGGRP5CTLA_CCC_REG  , 12, 13}},       0x8F,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x002D, CtlGrp1 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002E, CtlGrp1 CC1
  {CCC       , {{TXDLLSIGGRP5CTLA_CCC_REG  ,  8, 11}, {TXDLLSIGGRP5CTLA_CCC_REG  ,  8, 11}},       0x8F,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x002F, CtlGrp1 CC2
  {DQ        , {{RCVENCTL_DQ_DQ_REG        ,  0,  5}, {RCVENCTL_DQ_DQ_REG        ,  0,  5}},       0x80,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0030, RecEnDelay Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG    ,  8, 11}, {TXDLLSIGGRP2CTL_DQ_REG    , 24, 27}},       0x81,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0031, RecEnDelay Granularity HC
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG    ,  0,  7}, {TXDLLSIGGRP2CTL_DQ_REG    , 16, 23}},       0x81,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0032, RecEnDelay Granularity 1
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG    , 12, 13}, {TXDLLSIGGRP2CTL_DQ_REG    , 28, 29}},       0x81,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0033, RecEnDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0034, RecEnDelay CC1
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG    ,  8, 11}, {TXDLLSIGGRP2CTL_DQ_REG    , 24, 27}},       0x81,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0035, RecEnDelay CC2
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0036, RxDqsNDelay
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0037, RxDqsNDelay
  {DQ        , {{RXDLLDQSRK0CTL_DQ_REG     , 16, 23}, {RXDLLDQSRK1CTL_DQ_REG     , 16, 23}},       0x90,   {0x00},       0, -16,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0038, RxDqsNDelay Granularity 1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0039, RxDqsNDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003A, RxDqsNDelay CC1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003B, RxDqsNDelay CC2
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003C, RxDqsPDelay
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003D, RxDqsPDelay
  {DQ        , {{RXDLLDQSRK0CTL_DQ_REG     , 24, 31}, {RXDLLDQSRK1CTL_DQ_REG     , 24, 31}},       0x90,   {0x00},       0, -16,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x003E, RxDqsPDelay Granularity 1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003F, RxDqsPDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0040, RxDqsPDelay CC1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0041, RxDqsPDelay CC2
  {DQCCC     , {{CTLECTL1_DQCCC_REG        ,  6,  6}, {CTLECTL1_DQCCC_REG        ,  6,  6}},       0x94,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0042, Ctle
  {DQCCC     , {{CTLECTL0_DQCCC_REG        , 14, 15}, {CTLECTL0_DQCCC_REG        , 14, 15}},       0xC1,   {0x10},    2048,   0,       0,   0,       0,  -2, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0043, Ctle_Cap
  {DQCCC     , {{CTLECTL0_DQCCC_REG        , 30, 31}, {CTLECTL0_DQCCC_REG        , 30, 31}},       0xC1,   {0x10},    2048,   0,       0,   0,       0,  -2, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0044, Ctle_Res
  {DQ        , {{RCVENCTL_DQ_DQ_REG        , 27, 27}, {RCVENCTL_DQ_DQ_REG        , 27, 27}},       0x80,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0045, DQS_CNT_RESET
  {DQ        , {{DIGRSTCTL_DQ_REG          ,  1,  1}, {DIGRSTCTL_DQ_REG          ,  1,  1}},       0x92,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0046, FifoReset
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG    ,  0,  3}, {TXDLLSIGGRP6CTL_DQ_REG    ,  0,  3}},       0x85,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0047, Grp6_2x
  {DQ        , {{WRLVL_DQ_REG              ,  8, 15}, {WRLVL_DQ_REG              ,  8, 15}},       0x91,   {0x00},       0,   8,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0048, PerCompSmp
  {DQ        , {{RCVENCTL_DQ_DQ_REG        , 31, 31}, {RCVENCTL_DQ_DQ_REG        , 31, 31}},       0x80,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0049, RecEnSmp
  {DQ        , {{RXPBDBLCTL_DQ_REG         ,  0,  3}, {RXPBDBLCTL_DQ_REG         ,  0,  3}},       0xC0,   {0x10},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x004A, RxDqBitDelay
  {DQ        , {{RXODTCTL_DQ_DQ_REG        , 24, 24}, {RXODTCTL_DQ_DQ_REG        , 24, 24}},       0x96,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x004B, RxOdtOvr
  {DQ        , {{RXODTCTL_DQ_DQ_REG        , 25, 25}, {RXODTCTL_DQ_DQ_REG        , 25, 25}},       0x96,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x004C, RxOdtVal
  {DQ        , {{OFFSETCNCLCTRL1_DQ_REG    , 16, 16}, {OFFSETCNCLCTRL1_DQ_REG    , 16, 16}},       0x97,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x004D, RxVocEnDq
  {DQ        , {{OFFSETCNCLCTRL1_DQ_REG    , 17, 17}, {OFFSETCNCLCTRL1_DQ_REG    , 17, 17}},       0x97,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x004E, RxVocEnDqs
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG    , 28, 31}, {OFFSETCNCLCTRL0_DQ_REG    , 28, 31}},       0xC2,   {0x10},    2048,   0,       0,   0,       0,  -4, 0x00000001,          0,     R2R_ENABLE}, // Type 0x004F, RxVocVal
  {DQ        , {{VREFCTL0_DQ_REG           ,  0,  7}, {VREFCTL0_DQ_REG           ,  0,  7}},       0x93,   {0x00},       0,   8,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0050, RxVref
  {EXTERNAL  , {{TxDqBitDelay_FUNC         ,  0,  0}, {TxDqBitDelay_FUNC         ,  0,  0}},       0x88,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0051, TxDqBitDelay
  {EXTERNAL  , {{TxDqDelay_FUNC            ,  0,  0}, {TxDqDelay_FUNC            ,  0,  0}},       0x86,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0052, TxDqDelay
  {EXTERNAL  , {{TxVref_FUNC               ,  0,  0}, {TxVref_FUNC               ,  0,  0}},       0x87,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0053, TxVref
  {DQ        , {{WRLVL_DQ_REG              , 24, 24}, {WRLVL_DQ_REG              , 24, 24}},       0x91,   {0x00},       0,   1,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0054, WR_LVL_MODE
  {DQ        , {{WRLVL_DQ_REG              , 25, 25}, {WRLVL_DQ_REG              , 25, 25}},       0x91,   {0x00},       0,   1,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0055, WR_LVL_MODE_C
  {DQ        , {{WRLVL_DQ_REG              ,  0,  0}, {WRLVL_DQ_REG              ,  0,  0}},       0x91,   {0x00},       0,   1,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0056, WrLvlSmp
  {DQ        , {{DIFFAMPCTL_DQ_DQ_REG      , 24, 24}, {DIFFAMPCTL_DQ_DQ_REG      , 24, 24}},       0x95,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0057, RxDiffampOvrDq
  {DQ        , {{DIFFAMPCTL_DQ_DQ_REG      , 26, 26}, {DIFFAMPCTL_DQ_DQ_REG      , 26, 26}},       0x95,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0058, RxDiffampOvrDqs
  {DQ        , {{DIFFAMPCTL_DQ_DQ_REG      , 25, 25}, {DIFFAMPCTL_DQ_DQ_REG      , 25, 25}},       0x95,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0059, RxDiffampValDq
  {DQ        , {{DIFFAMPCTL_DQ_DQ_REG      , 27, 27}, {DIFFAMPCTL_DQ_DQ_REG      , 27, 27}},       0x95,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x005A, RxDiffampValDqs
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  },
  { // BLUEPRINT_LPDDR4
  {DQCCC     , {{WRDQSCTL_DQCCC_REG        ,  0,  5}, {WRDQSCTL_DQCCC_REG        ,  0,  5}},       0x02,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0000, TxDqDelay_Actual Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP0CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP0CTL_DQCCC_REG ,  8, 11}},       0x04,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0001, TxDqDelay_Actual Granularity HC
  {DQCCC     , {{TXDLLSIGGRP0CTL_DQCCC_REG ,  0,  7}, {TXDLLSIGGRP0CTL_DQCCC_REG ,  0,  7}},       0x04,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0002, TxDqDelay_Actual Granularity 1
  {DQCCC     , {{TXDLLSIGGRP6CTL_DQCCC_REG ,  4,  5}, {TXDLLSIGGRP6CTL_DQCCC_REG ,  4,  5}},       0x05,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0003, TxDqDelay_Actual CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0004, TxDqDelay_Actual CC1
  {DQCCC     , {{TXDLLSIGGRP0CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP0CTL_DQCCC_REG ,  8, 11}},       0x04,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0005, TxDqDelay_Actual CC2
  {DQCCC     , {{WRDQSCTL_DQCCC_REG        ,  0,  5}, {WRDQSCTL_DQCCC_REG        ,  0,  5}},       0x02,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0006, TxDqsDelay Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP1CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP1CTL_DQCCC_REG ,  8, 11}},       0x03,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0007, TxDqsDelay Granularity HC
  {DQCCC     , {{TXDLLSIGGRP1CTL_DQCCC_REG ,  0,  7}, {TXDLLSIGGRP1CTL_DQCCC_REG ,  0,  7}},       0x03,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0008, TxDqsDelay Granularity 1
  {DQCCC     , {{TXDLLSIGGRP1CTL_DQCCC_REG , 12, 13}, {TXDLLSIGGRP1CTL_DQCCC_REG , 12, 13}},       0x03,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0009, TxDqsDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x000A, TxDqsDelay CC1
  {DQCCC     , {{TXDLLSIGGRP1CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP1CTL_DQCCC_REG ,  8, 11}},       0x03,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000B, TxDqsDelay CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x000C, CkGrp0 Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP4CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP4CTL_DQCCC_REG ,  8, 11}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000D, CkGrp0 Granularity HC
  {DQCCC     , {{TXDLLSIGGRP4CTL_DQCCC_REG ,  0,  7}, {TXDLLSIGGRP4CTL_DQCCC_REG ,  0,  7}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x000E, CkGrp0 Granularity 1
  {DQCCC     , {{TXDLLSIGGRP4CTL_DQCCC_REG , 12, 13}, {TXDLLSIGGRP4CTL_DQCCC_REG , 12, 13}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x000F, CkGrp0 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0010, CkGrp0 CC1
  {DQCCC     , {{TXDLLSIGGRP4CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP4CTL_DQCCC_REG ,  8, 11}},       0x0A,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0011, CkGrp0 CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0012, CkGrp1 Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP4CTLA_DQCCC_REG,  8, 11}, {TXDLLSIGGRP4CTLA_DQCCC_REG,  8, 11}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0013, CkGrp1 Granularity HC
  {DQCCC     , {{TXDLLSIGGRP4CTLA_DQCCC_REG,  0,  7}, {TXDLLSIGGRP4CTLA_DQCCC_REG,  0,  7}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0014, CkGrp1 Granularity 1
  {DQCCC     , {{TXDLLSIGGRP4CTLA_DQCCC_REG, 12, 13}, {TXDLLSIGGRP4CTLA_DQCCC_REG, 12, 13}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0015, CkGrp1 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0016, CkGrp1 CC1
  {DQCCC     , {{TXDLLSIGGRP4CTLA_DQCCC_REG,  8, 11}, {TXDLLSIGGRP4CTLA_DQCCC_REG,  8, 11}},       0x0B,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0017, CkGrp1 CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0018, CmdGrp0 Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP3CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP3CTL_DQCCC_REG ,  8, 11}},       0x0C,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0019, CmdGrp0 Granularity HC
  {DQCCC     , {{TXDLLSIGGRP3CTL_DQCCC_REG ,  0,  7}, {TXDLLSIGGRP3CTL_DQCCC_REG ,  0,  7}},       0x0C,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x001A, CmdGrp0 Granularity 1
  {DQCCC     , {{TXDLLSIGGRP3CTL_DQCCC_REG , 12, 13}, {TXDLLSIGGRP3CTL_DQCCC_REG , 12, 13}},       0x0C,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x001B, CmdGrp0 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x001C, CmdGrp0 CC1
  {DQCCC     , {{TXDLLSIGGRP3CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP3CTL_DQCCC_REG ,  8, 11}},       0x0C,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001D, CmdGrp0 CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x001E, CmdGrp1 Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP3CTLA_DQCCC_REG,  8, 11}, {TXDLLSIGGRP3CTLA_DQCCC_REG,  8, 11}},       0x0D,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001F, CmdGrp1 Granularity HC
  {DQCCC     , {{TXDLLSIGGRP3CTLA_DQCCC_REG,  0,  7}, {TXDLLSIGGRP3CTLA_DQCCC_REG,  0,  7}},       0x0D,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0020, CmdGrp1 Granularity 1
  {DQCCC     , {{TXDLLSIGGRP3CTLA_DQCCC_REG, 12, 13}, {TXDLLSIGGRP3CTLA_DQCCC_REG, 12, 13}},       0x0D,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0021, CmdGrp1 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0022, CmdGrp1 CC1
  {DQCCC     , {{TXDLLSIGGRP3CTLA_DQCCC_REG,  8, 11}, {TXDLLSIGGRP3CTLA_DQCCC_REG,  8, 11}},       0x0D,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0023, CmdGrp1 CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0024, CtlGrp0 Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP5CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP5CTL_DQCCC_REG ,  8, 11}},       0x0E,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0025, CtlGrp0 Granularity HC
  {DQCCC     , {{TXDLLSIGGRP5CTL_DQCCC_REG ,  0,  7}, {TXDLLSIGGRP5CTL_DQCCC_REG ,  0,  7}},       0x0E,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0026, CtlGrp0 Granularity 1
  {DQCCC     , {{TXDLLSIGGRP5CTL_DQCCC_REG , 12, 13}, {TXDLLSIGGRP5CTL_DQCCC_REG , 12, 13}},       0x0E,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0027, CtlGrp0 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0028, CtlGrp0 CC1
  {DQCCC     , {{TXDLLSIGGRP5CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP5CTL_DQCCC_REG ,  8, 11}},       0x0E,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0029, CtlGrp0 CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x002A, CtlGrp1 Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP5CTLA_DQCCC_REG,  8, 11}, {TXDLLSIGGRP5CTLA_DQCCC_REG,  8, 11}},       0x0F,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x002B, CtlGrp1 Granularity HC
  {DQCCC     , {{TXDLLSIGGRP5CTLA_DQCCC_REG,  0,  7}, {TXDLLSIGGRP5CTLA_DQCCC_REG,  0,  7}},       0x0F,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x002C, CtlGrp1 Granularity 1
  {DQCCC     , {{TXDLLSIGGRP5CTLA_DQCCC_REG, 12, 13}, {TXDLLSIGGRP5CTLA_DQCCC_REG, 12, 13}},       0x0F,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x002D, CtlGrp1 CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002E, CtlGrp1 CC1
  {DQCCC     , {{TXDLLSIGGRP5CTLA_DQCCC_REG,  8, 11}, {TXDLLSIGGRP5CTLA_DQCCC_REG,  8, 11}},       0x0F,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x002F, CtlGrp1 CC2
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     ,  0,  5}, {RCVENCTL_DQ_DQCCC_REG     ,  0,  5}},       0x00,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0030, RecEnDelay Granularity 2*HC
  {DQCCC     , {{TXDLLSIGGRP2CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP2CTL_DQCCC_REG ,  8, 11}},       0x01,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0031, RecEnDelay Granularity HC
  {DQCCC     , {{TXDLLSIGGRP2CTL_DQCCC_REG ,  0,  7}, {TXDLLSIGGRP2CTL_DQCCC_REG ,  0,  7}},       0x01,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0032, RecEnDelay Granularity 1
  {DQCCC     , {{TXDLLSIGGRP2CTL_DQCCC_REG , 12, 13}, {TXDLLSIGGRP2CTL_DQCCC_REG , 12, 13}},       0x01,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0033, RecEnDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0034, RecEnDelay CC1
  {DQCCC     , {{TXDLLSIGGRP2CTL_DQCCC_REG ,  8, 11}, {TXDLLSIGGRP2CTL_DQCCC_REG ,  8, 11}},       0x01,   {0x21},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0035, RecEnDelay CC2
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0036, RxDqsNDelay
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0037, RxDqsNDelay
  {DQCCC     , {{RXDLLDQSRK0CTL_DQCCC_REG  , 16, 23}, {RXDLLDQSRK0CTL_DQCCC_REG  , 16, 23}},       0x10,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0038, RxDqsNDelay Granularity 1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0039, RxDqsNDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003A, RxDqsNDelay CC1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003B, RxDqsNDelay CC2
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003C, RxDqsPDelay
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003D, RxDqsPDelay
  {DQCCC     , {{RXDLLDQSRK0CTL_DQCCC_REG  , 24, 31}, {RXDLLDQSRK0CTL_DQCCC_REG  , 24, 31}},       0x10,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x003E, RxDqsPDelay Granularity 1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003F, RxDqsPDelay CC0
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0040, RxDqsPDelay CC1
  {0xFF      , {{0xFF                      ,  0,  0}, {0xFF                      ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0041, RxDqsPDelay CC2
  {DQCCC     , {{TXDLLSIGGRP6CTL_DQCCC_REG , 16, 19}, {TXDLLSIGGRP6CTL_DQCCC_REG , 16, 19}},       0x05,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0042, CkeAll
  {DQCCC     , {{CTLECTL1_DQCCC_REG        ,  6,  6}, {CTLECTL1_DQCCC_REG        ,  6,  6}},       0x13,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0043, Ctle
  {DQCCC     , {{CTLECTL0_DQCCC_REG        , 14, 15}, {CTLECTL0_DQCCC_REG        , 14, 15}},       0x41,   {0x10},    2048,   0,       0,   0,       0,  -2, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0044, Ctle_Cap
  {DQCCC     , {{CTLECTL0_DQCCC_REG        , 30, 31}, {CTLECTL0_DQCCC_REG        , 30, 31}},       0x41,   {0x10},    2048,   0,       0,   0,       0,  -2, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0045, Ctle_Res
  {DPLVUG    , {{PTCTL1_DPLVUG_REG         ,  1,  7}, {PTCTL1_DPLVUG_REG         ,  9, 15}},       0x84,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000007f,          0,     R2R_ENABLE}, // Type 0x0046, CURRENT_INDEX
  {DQCCC     , {{DIFFAMPCTL_DQ_DQCCC_REG   , 28, 31}, {DIFFAMPCTL_DQ_DQCCC_REG   , 28, 31}},       0x14,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0047, DiffampOff
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     , 27, 27}, {RCVENCTL_DQ_DQCCC_REG     , 27, 27}},       0x80,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0048, DQS_CNT_RESET
  {DQCCC     , {{DIGRSTCTL_DQCCC_REG       ,  1,  1}, {DIGRSTCTL_DQCCC_REG       ,  1,  1}},       0x82,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0049, FifoReset
  {DQCCC     , {{TXDLLSIGGRP6CTL_DQCCC_REG ,  0,  3}, {TXDLLSIGGRP6CTL_DQCCC_REG ,  0,  3}},       0x05,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x004A, Grp6_2x
  {DPLVUG    , {{PTCTL0_DPLVUG_REG         , 10, 16}, {PTCTL0_DPLVUG_REG         , 17, 23}},       0x00,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000007f,          0,     R2R_ENABLE}, // Type 0x004B, INITIAL_INDEX
  {DQCCC     , {{DLLCOMP_FBMUXSEL_DQCCC_REG,  8, 12}, {DLLCOMP_FBMUXSEL_DQCCC_REG,  8, 12}},       0x1A,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,     R2R_ENABLE}, // Type 0x004C, MuxcodeMax
  {DQCCC     , {{DLLCOMP_FBMUXSEL_DQCCC_REG,  0,  4}, {DLLCOMP_FBMUXSEL_DQCCC_REG,  0,  4}},       0x1A,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,     R2R_ENABLE}, // Type 0x004D, MuxcodeMin
  {DQCCC     , {{RXODTCTL_DQ_DQCCC_REG     , 28, 31}, {RXODTCTL_DQ_DQCCC_REG     , 28, 31}},       0x15,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x004E, OdtEnOff
  {DQCCC     , {{RXODTSEGCTL_DQ_DQCCC_REG  , 24, 27}, {RXODTSEGCTL_DQ_DQCCC_REG  , 24, 27}},       0x19,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x004F, OdtSegEnOff
  {DQCCC     , {{RCVENCTL_DQ_DQCCC_REG     , 31, 31}, {RCVENCTL_DQ_DQCCC_REG     , 31, 31}},       0x80,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0050, RecEnSmp
  {DQCCC     , {{RXPBDBLCTL_DQCCC_REG      ,  0,  3}, {RXPBDBLCTL_DQCCC_REG      ,  0,  3}},       0x40,   {0x10},    2048,   0,       0,   0,       0,   4, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0051, RxDqBitDelay
  {DQCCC     , {{RXODTCTL_DQ_DQCCC_REG     , 24, 24}, {RXODTCTL_DQ_DQCCC_REG     , 24, 24}},       0x15,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0052, RxOdtOvr
  {DQCCC     , {{RXODTCTL_DQ_DQCCC_REG     , 25, 25}, {RXODTCTL_DQ_DQCCC_REG     , 25, 25}},       0x15,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0053, RxOdtVal
  {DQCCC     , {{OFFSETCNCLCTRL1_DQCCC_REG , 16, 16}, {OFFSETCNCLCTRL1_DQCCC_REG , 16, 16}},       0x16,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0054, RxVocEnDq
  {DQCCC     , {{OFFSETCNCLCTRL1_DQCCC_REG , 17, 17}, {OFFSETCNCLCTRL1_DQCCC_REG , 17, 17}},       0x16,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0055, RxVocEnDqs
  {DQCCC     , {{WRLVL_DQCCC_REG           ,  8, 15}, {WRLVL_DQCCC_REG           ,  8, 15}},       0x81,   {0x00},    2048,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0056, RxVocSmp
  {DQCCC     , {{VREFCTL0_DQCCC_REG        ,  8, 15}, {VREFCTL0_DQCCC_REG        ,  8, 15}},       0x12,   {0x00},    2048,  -8,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0057, RxVref
  {EXTERNAL  , {{TxCaVref_FUNC             ,  0,  0}, {TxCaVref_FUNC             ,  0,  0}},       0x08,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0058, TxCaVref
  {EXTERNAL  , {{TxDqBitDelay_FUNC         ,  0,  0}, {TxDqBitDelay_FUNC         ,  0,  0}},       0x09,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0059, TxDqBitDelay
  {EXTERNAL  , {{TxDqDelay_FUNC            ,  0,  0}, {TxDqDelay_FUNC            ,  0,  0}},       0x06,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x005A, TxDqDelay
  {EXTERNAL  , {{TxVref_FUNC               ,  0,  0}, {TxVref_FUNC               ,  0,  0}},       0x07,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x005B, TxVref
  {DQCCC     , {{WRLVL_DQCCC_REG           , 24, 24}, {WRLVL_DQCCC_REG           , 24, 24}},       0x11,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x005C, WR_LVL_MODE
  {DQCCC     , {{WRLVL_DQCCC_REG           , 25, 25}, {WRLVL_DQCCC_REG           , 25, 25}},       0x11,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x005D, WR_LVL_MODE_C
  {DQCCC     , {{WRLVL_DQCCC_REG           ,  0,  0}, {WRLVL_DQCCC_REG           ,  0,  0}},       0x81,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x005E, WrLvlSmp
  {DQCCC     , {{FIFOPTREN_DQCCC_REG       ,  0,  0}, {FIFOPTREN_DQCCC_REG       ,  0,  0}},       0x83,   {0x00},    2048,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x005F, WrPtrEn
  {DQCCC     , {{DIFFAMPCTL_DQ_DQCCC_REG   , 24, 24}, {DIFFAMPCTL_DQ_DQCCC_REG   , 24, 24}},       0x14,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0060, RxDiffampOvrDq
  {DQCCC     , {{DIFFAMPCTL_DQ_DQCCC_REG   , 26, 26}, {DIFFAMPCTL_DQ_DQCCC_REG   , 26, 26}},       0x14,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0061, RxDiffampOvrDqs
  {DQCCC     , {{DIFFAMPCTL_DQ_DQCCC_REG   , 25, 25}, {DIFFAMPCTL_DQ_DQCCC_REG   , 25, 25}},       0x14,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0062, RxDiffampValDq
  {DQCCC     , {{DIFFAMPCTL_DQ_DQCCC_REG   , 27, 27}, {DIFFAMPCTL_DQ_DQCCC_REG   , 27, 27}},       0x14,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0063, RxDiffampValDqs
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG , 28, 31}, {OFFSETCNCLCTRL0_DQCCC_REG , 28, 31}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0064, RxVocVal0
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG , 24, 27}, {OFFSETCNCLCTRL0_DQCCC_REG , 24, 27}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0065, RxVocVal1
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG , 20, 23}, {OFFSETCNCLCTRL0_DQCCC_REG , 20, 23}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0066, RxVocVal2
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG , 16, 19}, {OFFSETCNCLCTRL0_DQCCC_REG , 16, 19}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0067, RxVocVal3
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG , 12, 15}, {OFFSETCNCLCTRL0_DQCCC_REG , 12, 15}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0068, RxVocVal4
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG ,  8, 11}, {OFFSETCNCLCTRL0_DQCCC_REG ,  8, 11}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0069, RxVocVal5
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG ,  4,  7}, {OFFSETCNCLCTRL0_DQCCC_REG ,  4,  7}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x006A, RxVocVal6
  {DQCCC     , {{OFFSETCNCLCTRL0_DQCCC_REG ,  0,  3}, {OFFSETCNCLCTRL0_DQCCC_REG ,  0,  3}},       0x17,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x006B, RxVocVal7
  },
};

//
// Blueprint project defines
//
UINT32 ECT_MIN_CMD_GENERATED[MAX_BLUEPRINTS] = {ECT_MIN_CMD_BLUEPRINT_LPDDR3  , ECT_MIN_CMD_BLUEPRINT_LPDDR4  };
UINT32 ECT_MAX_CMD_GENERATED[MAX_BLUEPRINTS] = {ECT_MAX_CMD_BLUEPRINT_LPDDR3  , ECT_MAX_CMD_BLUEPRINT_LPDDR4  };
UINT32 ECT_STEP_CMD_GENERATED[MAX_BLUEPRINTS] = {ECT_STEP_CMD_BLUEPRINT_LPDDR3 , ECT_STEP_CMD_BLUEPRINT_LPDDR4 };
UINT32 ECT_MIN_CTL_GENERATED[MAX_BLUEPRINTS] = {ECT_MIN_CTL_BLUEPRINT_LPDDR3  , ECT_MIN_CTL_BLUEPRINT_LPDDR4  };
UINT32 ECT_MAX_CTL_GENERATED[MAX_BLUEPRINTS] = {ECT_MAX_CTL_BLUEPRINT_LPDDR3  , ECT_MAX_CTL_BLUEPRINT_LPDDR4  };
UINT32 ECT_STEP_CTL_GENERATED[MAX_BLUEPRINTS] = {ECT_STEP_CTL_BLUEPRINT_LPDDR3 , ECT_STEP_CTL_BLUEPRINT_LPDDR4 };
