## @file
# This package provides FSP platform specific modules.
#
# @copyright
#  INTEL CONFIDENTIAL
#  Copyright 2010 - 2018 Intel Corporation.
#
#  The source code contained or described herein and all documents related to the
#  source code ("Material") are owned by Intel Corporation or its suppliers or
#  licensors. Title to the Material remains with Intel Corporation or its suppliers
#  and licensors. The Material may contain trade secrets and proprietary and
#  confidential information of Intel Corporation and its suppliers and licensors,
#  and is protected by worldwide copyright and trade secret laws and treaty
#  provisions. No part of the Material may be used, copied, reproduced, modified,
#  published, uploaded, posted, transmitted, distributed, or disclosed in any way
#  without Intel's prior express written permission.
#
#  No license under any patent, copyright, trade secret or other intellectual
#  property right is granted to or conferred upon you by disclosure or delivery
#  of the Materials, either expressly, by implication, inducement, estoppel or
#  otherwise. Any license under such intellectual property rights must be
#  express and approved by Intel in writing.
#
#  Unless otherwise agreed by Intel in writing, you may not remove or alter
#  this notice or any other notice embedded in Materials by Intel or
#  Intel's suppliers or licensors in any way.
#
#  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
#  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
#  the terms of your license agreement with Intel or your vendor. This file may
#  be modified by the user, subject to additional terms of the license agreement.
#
# @par Specification
##

[Defines]
DEFINE FLASH_BASE           = 0xFFF6C000
DEFINE FLASH_BLOCK_SIZE     = 0x00000100

#
# Flash Size for Visual Studio and GCC
#
!if ($(TARGET) == RELEASE)
DEFINE FLASH_SIZE           = 0x00097000     #FSP Size = 604 KB
DEFINE FLASH_NUM_BLOCKS     = 0x970          #The number of blocks
DEFINE FSP_S_SIZE           = 0x0002F000     #FSP-S size = 188 KB
!else
DEFINE FLASH_SIZE           = 0x000AF000     #FSP Size = 700 KB
DEFINE FLASH_NUM_BLOCKS     = 0xAF0          #The number of blocks
DEFINE FSP_S_SIZE           = 0x00047000     #FSP-S size = 284 KB
!endif

SET gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspsBase  = 0x00000000
SET gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize  = $(FSP_S_SIZE)             

SET gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspmBase  = $(FSP_S_SIZE)    
SET gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize  = $(FSP_IBBM_SIZE)        #FSP-M size

SET gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFsptBase  = $(FSP_S_SIZE) + $(FSP_IBBM_SIZE)
SET gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize  = $(FSP_IBBL_SIZE)        #FSP-T size

################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into  the Flash Device Image.  Each FD section
# defines one flash "device" image.  A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash"  image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.GLK]
#
# This FD currently contains all FV regions needed full BROXTON_FSP.fd
#
BaseAddress   = $(FLASH_BASE) | gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaBaseAddress
Size          = $(FLASH_SIZE) | gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaSize
ErasePolarity = 1
BlockSize     = $(FLASH_BLOCK_SIZE)
NumBlocks     = $(FLASH_NUM_BLOCKS)          #The number of blocks for 2Mb FLASH Device.

SET gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase = $(FLASH_BASE) + (gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspmBase)

#FSP-C
#gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspCOffset|gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspCSize
#FV = FSP-C

#FSP-S
gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspsBase|gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspsSize
FV = FSP-S

#FSP-M
gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspmBase|gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFspmSize
FV = FSP-M

#FSP-T
gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFsptBase|gGeminilakeFspPkgTokenSpaceGuid.PcdFlashFvFsptSize
FV = FSP-T

################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file.  This section also defines order the components and modules are positioned
# within the image.  The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FSP-T]
BlockSize          = $(FLASH_BLOCK_SIZE)
FvBaseAddress      = $(IBBL_BASE_ADDRESS)
FvAlignment        = 16         #FV alignment and FV attributes setting.
ERASE_POLARITY     = 1
MEMORY_MAPPED      = TRUE
STICKY_WRITE       = TRUE
LOCK_CAP           = TRUE
LOCK_STATUS        = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP  = TRUE
WRITE_STATUS       = TRUE
WRITE_LOCK_CAP     = TRUE
WRITE_LOCK_STATUS  = TRUE
READ_DISABLED_CAP  = TRUE
READ_ENABLED_CAP   = TRUE
READ_STATUS        = TRUE
READ_LOCK_CAP      = TRUE
READ_LOCK_STATUS   = TRUE
FvNameGuid         = 52F1AFB6-78A6-448f-8274-F370549AC5D0

#
# FSP header
#
INF  RuleOverride = FSPHEADER   $(FSP_PACKAGE)/FspHeader/FspHeader.inf

#
# Project specific configuration data files
#
!ifndef $(CFG_PREBUILD)
FILE RAW = $(FSP_T_UPD_FFS_GUID) {
    SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_T_UPD_TOOL_GUID).bin
}
!endif

INF RuleOverride = RELOC   IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf

[FV.FSP-M]
BlockSize          = $(FLASH_BLOCK_SIZE)
FvBaseAddress      = $(IBBM_BASE_ADDRESS)
FvAlignment        = 16         #FV alignment and FV attributes setting.
ERASE_POLARITY     = 1
MEMORY_MAPPED      = TRUE
STICKY_WRITE       = TRUE
LOCK_CAP           = TRUE
LOCK_STATUS        = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP  = TRUE
WRITE_STATUS       = TRUE
WRITE_LOCK_CAP     = TRUE
WRITE_LOCK_STATUS  = TRUE
READ_DISABLED_CAP  = TRUE
READ_ENABLED_CAP   = TRUE
READ_STATUS        = TRUE
READ_LOCK_CAP      = TRUE
READ_LOCK_STATUS   = TRUE
FvNameGuid         = F32DB7DF-C5BC-423c-9416-08F1FA26A282

#
# FSP header
#
INF  RuleOverride = FSPHEADER   $(FSP_PACKAGE)/FspHeader/FspHeader.inf

#
# Project specific configuration data files
#
!ifndef $(CFG_PREBUILD)
FILE RAW = $(FSP_M_UPD_FFS_GUID) {
    SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_M_UPD_TOOL_GUID).bin
}
!endif

#
# It is important to keep the proper order for these PEIMs
# for this implementation
#
INF RuleOverride = RELOC    $(FSP_PACKAGE)/Override/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf  # FSPO-0003: RoyalParkOverrideContent

INF $(FSP_PACKAGE)/Override/MdeModulePkg/Core/Pei/PeiMain.inf
INF $(FSP_PACKAGE)/Override/MdeModulePkg/Universal/PCD/Pei/Pcd.inf

#
# Project specific PEIMs
#
INF $(FSP_PACKAGE)/FspInit/Pei/FspInitPreMem.inf
INF $(PLATFORM_SI_PACKAGE)/SiInit/Pei/SiInitPreMem.inf
!if ($(VP_BIOS_ENABLE) == TRUE)
    INF $(PLATFORM_SI_PACKAGE)/NorthCluster/MemoryInit/MemoryInitFsp.inf
!else
  INF $(PLATFORM_SI_PACKAGE)/NorthCluster/MemoryInitGlk/MemoryInitFsp.inf
!endif


#
# Description file
#
FILE RAW = D9093578-08EB-44DF-B9D8-D0C1D3D55D96 {
    SECTION RAW = $(FSP_PACKAGE)/FspDescription/FspDescription.txt
}


[FV.FSP-S]
BlockSize          = $(FLASH_BLOCK_SIZE)
FvBaseAddress      = $(IBBR_BASE_ADDRESS)
FvAlignment        = 16         #FV alignment and FV attributes setting.
ERASE_POLARITY     = 1
MEMORY_MAPPED      = TRUE
STICKY_WRITE       = TRUE
LOCK_CAP           = TRUE
LOCK_STATUS        = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP  = TRUE
WRITE_STATUS       = TRUE
WRITE_LOCK_CAP     = TRUE
WRITE_LOCK_STATUS  = TRUE
READ_DISABLED_CAP  = TRUE
READ_ENABLED_CAP   = TRUE
READ_STATUS        = TRUE
READ_LOCK_CAP      = TRUE
READ_LOCK_STATUS   = TRUE
FvNameGuid         = 1B5C27FE-F01C-4fbc-AEAE-341B2E992A17

#
# FSP header
#
INF RuleOverride = FSPHEADER   $(FSP_PACKAGE)/FspHeader/FspHeader.inf

#
# Project specific configuration data files
#
!ifndef $(CFG_PREBUILD)
FILE RAW = $(FSP_S_UPD_FFS_GUID) {
    SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_S_UPD_TOOL_GUID).bin
}
!endif

#
# It is important to keep the proper order for these PEIMs
# for this implementation
#
INF RuleOverride = RELOC   IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf

INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
INF RuleOverride = PE32    $(FSP_PACKAGE)/FspInit/Pei/FspInit.inf
#
# CpuMp PEIM for MpService PPI
#
INF RuleOverride = PE32    $(PLATFORM_SI_PACKAGE)/Override/UefiCpuPkg/CpuMpPei/CpuMpPei.inf
INF RuleOverride = PE32    $(PLATFORM_SI_PACKAGE)/SiInit/Pei/SiInitFsp.inf

FILE PEIM = BA37F2C5-B0F3-4a95-B55F-F25F4F6F8452 {
    SECTION COMPRESS {
!if ($(PEI_DEBUG_GOP_BUILD) == TRUE) AND ($(TARGET) == RELEASE)
        SECTION PE32 = $(PLATFORM_SI_PACKAGE)/NorthCluster/IntelGraphicsPeim/Binaries/GELK/IntelGraphicsPeim_D.efi
!else
        SECTION PE32 = $(PLATFORM_SI_PACKAGE)/NorthCluster/IntelGraphicsPeim/Binaries/GELK/IntelGraphicsPeim.efi
!endif
        SECTION PEI_DEPEX_EXP = {gEfiPeiStallPpiGuid}
        SECTION UI = "IntelGraphicsPeim"
    }
}

INF RuleOverride = PE32    $(PLATFORM_SI_PACKAGE)/SouthCluster/ScInit/Dxe/ScInitDxeFsp.inf
INF RuleOverride = PE32    IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf

# [FV.FSP-C]
# BlockSize          = $(FLASH_BLOCK_SIZE)
# FvAlignment        = 16         #FV alignment and FV attributes setting.
# ERASE_POLARITY     = 1
# MEMORY_MAPPED      = TRUE
# STICKY_WRITE       = TRUE
# LOCK_CAP           = TRUE
# LOCK_STATUS        = TRUE
# WRITE_DISABLED_CAP = TRUE
# WRITE_ENABLED_CAP  = TRUE
# WRITE_STATUS       = TRUE
# WRITE_LOCK_CAP     = TRUE
# WRITE_LOCK_STATUS  = TRUE
# READ_DISABLED_CAP  = TRUE
# READ_ENABLED_CAP   = TRUE
# READ_STATUS        = TRUE
# READ_LOCK_CAP      = TRUE
# READ_LOCK_STATUS   = TRUE
# FvNameGuid         = B6DA8044-458A-421F-B569-8B500D9481A8

#
# #
# # FSP header
# #
# INF RuleOverride = FSPHEADER   $(FSP_PACKAGE)/FspHeader/FspHeader.inf

#
# #
# # Project specific configuration data files
# #
# !ifndef $(CFG_PREBUILD)
# FILE RAW = $(FSP_C_UPD_TOOL_GUID) {
#     SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_C_UPD_TOOL_GUID).bin
# }
# !endif

[Rule.Common.SEC]
  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
    TE  TE    Align = 8       $(INF_OUTPUT)/$(MODULE_NAME).efi
  }

[Rule.Common.SEC.RELOC]
  FILE SEC = $(NAMED_GUID) {
    TE  TE    Align = 8       $(INF_OUTPUT)/$(MODULE_NAME).efi
  }

[Rule.Common.PEI_CORE]
  FILE PEI_CORE = $(NAMED_GUID)            {
    TE       TE               $(INF_OUTPUT)/$(MODULE_NAME).efi
    UI       STRING="$(MODULE_NAME)" Optional
    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  }

[Rule.Common.PEIM.NORELOC]
  FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED  {
     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
     TE        TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
     UI        STRING="$(MODULE_NAME)" Optional
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  }

[Rule.Common.PEIM]
  FILE PEIM = $(NAMED_GUID)               {
     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
     TE        TE                        $(INF_OUTPUT)/$(MODULE_NAME).efi
     UI        STRING="$(MODULE_NAME)" Optional
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  }

[Rule.Common.PEIM.PE32]
  FILE PEIM = $(NAMED_GUID)               {
     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
     COMPRESS {
        PE32      PE32                   $(INF_OUTPUT)/$(MODULE_NAME).efi
        UI        STRING="$(MODULE_NAME)" Optional
        VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
     }
  }

[Rule.Common.PEIM.BINARY]
  FILE PEIM = $(NAMED_GUID)               {
     PEI_DEPEX PEI_DEPEX Optional        |.depex
     PE32      PE32    Align=Auto        |.efi
     UI        STRING="$(MODULE_NAME)" Optional
     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  }

[Rule.Common.USER_DEFINED.FSPHEADER]
  FILE RAW = $(NAMED_GUID)               {
     RAW BIN                  |.acpi
  }
