/** @file
  File name:    MmrcProjectDataGenerated.c
  Input File:   BXTP_SOC.xlsx

  THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.

  If edits are needed in this file, they must be done via the MMRC tool.

  If there is additional project-specific data required by the MMRC, it
  can be placed in MmrcProjectData.c, which is used for non-tool-generated
  data

  This file contains data structures for a particular piece of silicon.
  These structures are fed to MmrcLibraries.c, which use them to initialize
  memory.

  @copyright
  Copyright (c) 2005-2016 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as 'Intel Reference Module' and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

  @par Specification
**/
#include "MmrcProjectData.h"
#include "MmrcLibraries.h"

TASK_DESCRIPTOR InitTasks [] = {
//  PC     BootMode                        Function                               Description                          String Channel       Plat     Freq   Config               Tech
  { 0x000, S3|S0W|S0C|S5|FB|RS|EM|A0     , &DISPLAYMMRCVERSION                  , EXTERNAL                            , 0x000, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x001, S3|S0W|S0C|S5|FB|RS|EM|A0|CSE , &MmrcCheckFreqConfig                 , EXTERNAL                            , 0x001, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x002, S3|S0W|S0C|S5|FB|RS|EM|A0|CSE , &MmrcConvertParams                   , EXTERNAL                            , 0x002, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0F1, S5|FB                         , &SWSetHiFrequency                    , EXTERNAL                            , 0x003, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x003, S3|S0W|S0C|S5|FB|EM           , &MmrcExecuteTask                     , InitPunit                           , 0x004, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x004, S3|S0W|S0C|S5|FB|EM           , &MmrcExecuteTask                     , PollPunit                           , 0x005, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x005, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , sai_init_seq                        , 0x006, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x006, RS|EM|A0                      , &MmrcExecuteTask                     , modmem_init_lpddrgrp1xm_seq         , 0x007, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x007, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp1p5_seq         , 0x008, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x008, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp2m_seq          , 0x009, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x009, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp3m_seq          , 0x00A, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x010, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp3_seq           , 0x00B, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x011, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp3p75_seq        , 0x00C, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x012, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp4m_seq          , 0x00D, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x013, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_bxtp_ldo_offsetcomp_seq      , 0x00E, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x014, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp2p5_seq         , 0x00F, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x015, S5|FB|RS|EM|A0                , &MmrcExecuteTask                     , modmem_bxtp_ldo_offsetcomp_poll_seq , 0x010, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x015, S3|S0W|S0C                    , &MmrcExecuteTask                     , modmem_bxtp_ldo_offsetcomp_poll_seq , 0x011, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x016, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp4_seq           , 0x012, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x017, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp4p5_seq         , 0x013, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x018, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp5m_seq          , 0x014, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x019, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp5_seq           , 0x015, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x020, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp5p25_seq        , 0x016, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x021, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp5p5m_seq        , 0x017, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x022, S3|S0W|S0C|S5|FB|EM|A0        , &MmrcExecuteTask                     , PhyConfigComplete                   , 0x018, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x023, S3|S0W|S0C|S5|FB| EM|A0       , &MmrcExecuteTask                     , PollPunit                           , 0x019, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x024, S3|S0W|S0C|S5| FB|EM|A0       , &MmrcExecuteTask                     , DunitResetComplete                  , 0x01A, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x025, RS                            , &MmrcExecuteTask                     , wake_dunit                          , 0x01B, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x026, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp5p5_seq         , 0x01C, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x027, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp6_seq           , 0x01D, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x028, S3|S0C|S0W|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp6p5_seq         , 0x01E, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x030, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp7_seq           , 0x01F, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x031, S3|S0C|S0W|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp7p5_seq         , 0x020, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x036, S3|S0C|S0W|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp7p75_seq        , 0x021, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x036, S3|S0C|S0W|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp7p75_lp4seq     , 0x022, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0F1, S5                            , &HWSetBootFrequency                  , EXTERNAL                            , 0x023, ChNone  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x039, S5                            , &SetupMaxPI                          , EXTERNAL                            , 0x024, ChNone  ,   P_ALL,   F_ALL,   C_ALL,   T_LPDDR3|T_DDR3},
  { 0x039, S3|S0W|S0C|FB|RS|EM|A0        , &SetupMaxPI                          , EXTERNAL                            , 0x025, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x03C, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp8m_seq          , 0x026, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x03D, S5|FB|RS|EM|A0                , &MmrcExecuteTask                     , modmem_init_lpddrgrp0_seq           , 0x027, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x03E, S0C                           , &MmrcExecuteTask                     , modmem_init_lpddrgrp0_seq           , 0x028, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,   T_LPDDR4|T_DDR3},
  { 0x03F, S3|S0W|S0C|S5|FB|RS|EM|A0     , &ClkGatePhy                          , EXTERNAL                            , 0x029, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x040, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp10m_seq         , 0x02A, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x041, S5|FB|RS|EM|A0                , &Channel0Only                        , EXTERNAL                            , 0x02B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0F1, S5                            , &SWSetHiFrequency                    , EXTERNAL                            , 0x02C, ChNone  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x043, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcCheckECCEnable                  , EXTERNAL                            , 0x02D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,            T_DDR3},
  { 0x047, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , InitDunit                           , 0x02E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x044, S5|RS|EM|A0                   , &SwitchTo2NWrapper                   , EXTERNAL                            , 0x02F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,            T_DDR3},
  { 0x049, S5|FB|A0                      , &DramPhysicalReset                   , EXTERNAL                            , 0x030, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x04A, S5|FB|RS|EM|A0                , &MmrcExecuteTask                     , InitDunitWake                       , 0x031, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0F1, S5                            , &SWSetBootFrequency                  , EXTERNAL                            , 0x032, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x04B, S3|S0W|S0C|S5|FB|RS|EM|A0     , &R2RDynamicSetup                     , INTERNAL                            , 0x033, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x04C, S5|FB|RS|EM|A0                , &MmrcExecuteTask                     , PrepareForTraining                  , 0x034, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0FB, S0W|S0C|S3|FB                 , &RestoreAlgos                        , EXTERNAL                            , 0x035, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0C0, S5|FB|RS|EM|A0                , &InitializeJedec                     , EXTERNAL                            , 0x036, ChAll   ,   P_ALL,   F_ALL,   C_ALL,   T_LPDDR3|T_DDR3},
  { 0x04E, S5|FB|A0                      , &LP4MRProgramming_ODTVREF            , EXTERNAL                            , 0x037, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x04F, S5|RS|A0                      , &DiffAmpOverride_PostAstep           , EXTERNAL                            , 0x038, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x04F, S3|S0C|S0W|S5|FB|RS|A0        , &DiffAmpOverride_AstepOnly           , EXTERNAL                            , 0x039, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A0, S5                            , &VOCTraining                         , INTERNAL                            , 0x03A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x050, S5|FB|RS|A0                   , &MmrcExecuteTask                     , CPGC_ONE_TIME_INIT                  , 0x03B, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x051, S5                            , &Lp4CBTEntryAllRanks                 , EXTERNAL                            , 0x03C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0F1, S5                            , &HWSetHiFrequency                    , EXTERNAL                            , 0x03D, ChNone  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0A2, S5                            , &EarlyCommandTraining                , EXTERNAL                            , 0x03E, ChAll   ,   P_ALL,   F_ALL,   C_ALL, T_LPDDR3|T_LPDDR4},
  { 0x056, S5                            , &Lp4CBTExitAllRanks                  , EXTERNAL                            , 0x03F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x058, RS                            , &MmrcExecuteTask                     , modmem_init_dramreset_seq_sim       , 0x040, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0B2, S5|FB|RS|EM|A0                , &CompleteJedecInit                   , EXTERNAL                            , 0x041, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x069, S5|FB|RS|A0                   , &MmrcExecuteTask                     , CPGC_ONE_TIME_INIT                  , 0x042, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x06A, S3|S0C|S0W|S5|FB|RS|A0        , &DiffAmpOverride_AstepOnly           , EXTERNAL                            , 0x043, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A5, S5|RS|EM|A0                   , &ReceiveEnable                       , INTERNAL                            , 0x044, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A6, S5|RS|EM|A0                   , &EarlyMprRead                        , INTERNAL                            , 0x045, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A7, S5|RS|EM|A0                   , &FineWriteLeveling                   , EXTERNAL                            , 0x046, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x076, S5|FB|A0                      , &MmrcExecuteTask                     , modmem_init_dramreset_seq           , 0x047, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,            T_DDR3},
  { 0x0C0, S5|FB|RS|EM|A0                , &InitializeJedec                     , EXTERNAL                            , 0x048, ChAll   ,   P_ALL,   F_ALL,   C_ALL,   T_LPDDR3|T_DDR3},
  { 0x076, S5                            , &DramPhysicalReset                   , EXTERNAL                            , 0x049, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x04E, S5                            , &LP4MRProgramming_ODTVREF            , EXTERNAL                            , 0x04A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0C0, S5                            , &InitializeJedec                     , EXTERNAL                            , 0x04B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x061, S5                            , &LP4AllMRProgramming                 , EXTERNAL                            , 0x04C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x063, S5                            , &LP4MRProgramming_MPCZQ              , EXTERNAL                            , 0x04D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x066, FB                            , &CompleteJedecInit                   , EXTERNAL                            , 0x04E, ChNone  ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x0A8, RS|EM|A0|S5                   , &CoarseWriteLeveling                 , EXTERNAL                            , 0x04F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0DF, S3|S0W|S0C|S5|FB|RS|EM|A0     , &SetWeakOdt                          , EXTERNAL                            , 0x050, ChAllF  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x078, S5|RS|A0                      , &DiffAmpRestore_PostAstep            , EXTERNAL                            , 0x051, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A9, RS|EM|A0|S5                   , &ReadTraining                        , INTERNAL                            , 0x052, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0A4, RS|EM|A0|S5                   , &WriteTraining                       , INTERNAL                            , 0x053, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x00A, RS|EM|A0|S5                   , &SetupPHYRankTurnaroundSettings      , INTERNAL                            , 0x054, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0AB, RS|EM|A0|S5                   , &LateCommandTraining                 , INTERNAL                            , 0x055, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x078, S3|S0C|S0W|S5|FB|RS|A0        , &UpdateCke                           , EXTERNAL                            , 0x056, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x078, S3|S0C|S0W|S5|FB|RS|A0        , &DiffAmpRestore_AstepOnly            , EXTERNAL                            , 0x057, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0AC, RS|EM|A0|S5                   , &RDCMD2RDVLDTraining                 , EXTERNAL                            , 0x058, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0D0, S5|FB|RS|A0                   , &SearchRmtWrapper                    , EXTERNAL                            , 0x059, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0FA, S5                            , &SaveAlgos                           , EXTERNAL                            , 0x05A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0AA, S5|FB                         , &PeriodicTraining                    , INTERNAL                            , 0x05B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4},
  { 0x080, FB|RS|A0                      , &MmrcExecuteTask                     , CPGC_ONE_TIME_INIT                  , 0x05C, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x081, S5|RS|A0                      , &CpgcVATest                          , EXTERNAL                            , 0x05D, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x083, S5|FB|S0W|S3|S0C              , &ReadMRTQREF                         , EXTERNAL                            , 0x05E, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x084, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , ProgramSelfRefresh                  , 0x05F, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x085, S3|S0C|S0W|S5|FB|RS|A0        , &SetScrambler                        , EXTERNAL                            , 0x060, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x0DE, S0C|S5|FB|RS|EM|A0            , &InitializeMemory                    , EXTERNAL                            , 0x061, ChAll   ,   P_ALL,   F_ALL,   C_ALL,            T_DDR3},
  { 0x084, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , ProgramFinalSettings                , 0x062, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x082, S5|FB|EM|A0                   , &MmrcExecuteTask                     , TrainingDone                        , 0x063, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x086, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp11m_seq         , 0x064, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x087, S3|S0W|S0C|S5|FB|RS|EM|A0     , &MmrcExecuteTask                     , modmem_init_lpddrgrp12m_seq         , 0x065, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x088, S3|S0W|S0C|S5|FB|EM|A0        , &MmrcExecuteTask                     , CPGCModeComplete                    , 0x066, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x089, S3|S0W|S0C|S5|FB|EM           , &MmrcExecuteTask                     , PollPunit                           , 0x067, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x090, S3|S0W|S0C|S5|FB|EM|CSE|A0    , &ProgramMemoryMap                    , EXTERNAL                            , 0x068, ChNone  ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x091, S0C|S5|FB|RS|EM|CSE|A0        , &MmrcExecuteTask                     , SetMrcDone                          , 0x069, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x092, S3|S0W|S0C                    , &MmrcExecuteTask                     , InitDunitWakeS0set                  , 0x06A, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { 0x093, S3|S0W|S0C                    , &MmrcExecuteTask                     , InitDunitWakeS0poll                 , 0x06B, ChAll   ,   P_ALL,   F_ALL,   C_ALL,             T_ALL},
  { TASK_FUNCTION_DESC_DONE },
};

#if CAPSULESTRINGS
char *CapsuleStrings[] = {
                    "DISPLAYMMRCVERSION",  // 0x000
                   "MmrcCheckFreqConfig",  // 0x001
                     "MmrcConvertParams",  // 0x002
                      "SWSetHiFrequency",  // 0x003
                             "InitPunit",  // 0x004
                             "PollPunit",  // 0x005
                          "sai_init_seq",  // 0x006
           "modmem_init_lpddrgrp1xm_seq",  // 0x007
           "modmem_init_lpddrgrp1p5_seq",  // 0x008
            "modmem_init_lpddrgrp2m_seq",  // 0x009
            "modmem_init_lpddrgrp3m_seq",  // 0x00A
             "modmem_init_lpddrgrp3_seq",  // 0x00B
          "modmem_init_lpddrgrp3p75_seq",  // 0x00C
            "modmem_init_lpddrgrp4m_seq",  // 0x00D
        "modmem_bxtp_ldo_offsetcomp_seq",  // 0x00E
           "modmem_init_lpddrgrp2p5_seq",  // 0x00F
   "modmem_bxtp_ldo_offsetcomp_poll_seq",  // 0x010
   "modmem_bxtp_ldo_offsetcomp_poll_seq",  // 0x011
             "modmem_init_lpddrgrp4_seq",  // 0x012
           "modmem_init_lpddrgrp4p5_seq",  // 0x013
            "modmem_init_lpddrgrp5m_seq",  // 0x014
             "modmem_init_lpddrgrp5_seq",  // 0x015
          "modmem_init_lpddrgrp5p25_seq",  // 0x016
          "modmem_init_lpddrgrp5p5m_seq",  // 0x017
                     "PhyConfigComplete",  // 0x018
                             "PollPunit",  // 0x019
                    "DunitResetComplete",  // 0x01A
                            "wake_dunit",  // 0x01B
           "modmem_init_lpddrgrp5p5_seq",  // 0x01C
             "modmem_init_lpddrgrp6_seq",  // 0x01D
           "modmem_init_lpddrgrp6p5_seq",  // 0x01E
             "modmem_init_lpddrgrp7_seq",  // 0x01F
           "modmem_init_lpddrgrp7p5_seq",  // 0x020
          "modmem_init_lpddrgrp7p75_seq",  // 0x021
       "modmem_init_lpddrgrp7p75_lp4seq",  // 0x022
                    "HWSetBootFrequency",  // 0x023
                            "SetupMaxPI",  // 0x024
                            "SetupMaxPI",  // 0x025
            "modmem_init_lpddrgrp8m_seq",  // 0x026
             "modmem_init_lpddrgrp0_seq",  // 0x027
             "modmem_init_lpddrgrp0_seq",  // 0x028
                            "ClkGatePhy",  // 0x029
           "modmem_init_lpddrgrp10m_seq",  // 0x02A
                          "Channel0Only",  // 0x02B
                      "SWSetHiFrequency",  // 0x02C
                    "MmrcCheckECCEnable",  // 0x02D
                             "InitDunit",  // 0x02E
                     "SwitchTo2NWrapper",  // 0x02F
                     "DramPhysicalReset",  // 0x030
                         "InitDunitWake",  // 0x031
                    "SWSetBootFrequency",  // 0x032
                       "R2RDynamicSetup",  // 0x033
                    "PrepareForTraining",  // 0x034
                          "RestoreAlgos",  // 0x035
                       "InitializeJedec",  // 0x036
              "LP4MRProgramming_ODTVREF",  // 0x037
             "DiffAmpOverride_PostAstep",  // 0x038
             "DiffAmpOverride_AstepOnly",  // 0x039
                           "VOCTraining",  // 0x03A
                    "CPGC_ONE_TIME_INIT",  // 0x03B
                   "Lp4CBTEntryAllRanks",  // 0x03C
                      "HWSetHiFrequency",  // 0x03D
                  "EarlyCommandTraining",  // 0x03E
                    "Lp4CBTExitAllRanks",  // 0x03F
         "modmem_init_dramreset_seq_sim",  // 0x040
                     "CompleteJedecInit",  // 0x041
                    "CPGC_ONE_TIME_INIT",  // 0x042
             "DiffAmpOverride_AstepOnly",  // 0x043
                         "ReceiveEnable",  // 0x044
                          "EarlyMprRead",  // 0x045
                     "FineWriteLeveling",  // 0x046
             "modmem_init_dramreset_seq",  // 0x047
                       "InitializeJedec",  // 0x048
                     "DramPhysicalReset",  // 0x049
              "LP4MRProgramming_ODTVREF",  // 0x04A
                       "InitializeJedec",  // 0x04B
                   "LP4AllMRProgramming",  // 0x04C
                "LP4MRProgramming_MPCZQ",  // 0x04D
                     "CompleteJedecInit",  // 0x04E
                   "CoarseWriteLeveling",  // 0x04F
                            "SetWeakOdt",  // 0x050
              "DiffAmpRestore_PostAstep",  // 0x051
                          "ReadTraining",  // 0x052
                         "WriteTraining",  // 0x053
        "SetupPHYRankTurnaroundSettings",  // 0x054
                   "LateCommandTraining",  // 0x055
                             "UpdateCke",  // 0x056
              "DiffAmpRestore_AstepOnly",  // 0x057
                   "RDCMD2RDVLDTraining",  // 0x058
                      "SearchRmtWrapper",  // 0x059
                             "SaveAlgos",  // 0x05A
                      "PeriodicTraining",  // 0x05B
                    "CPGC_ONE_TIME_INIT",  // 0x05C
                            "CpgcVATest",  // 0x05D
                           "ReadMRTQREF",  // 0x05E
                    "ProgramSelfRefresh",  // 0x05F
                          "SetScrambler",  // 0x060
                      "InitializeMemory",  // 0x061
                  "ProgramFinalSettings",  // 0x062
                          "TrainingDone",  // 0x063
           "modmem_init_lpddrgrp11m_seq",  // 0x064
           "modmem_init_lpddrgrp12m_seq",  // 0x065
                      "CPGCModeComplete",  // 0x066
                             "PollPunit",  // 0x067
                      "ProgramMemoryMap",  // 0x068
                            "SetMrcDone",  // 0x069
                    "InitDunitWakeS0set",  // 0x06A
                   "InitDunitWakeS0poll",  // 0x06B
            "modmem_init_lpddrgrp10_seq",  // 0x06C
           "modmem_lp4_freq_switch_seq1",  // 0x06D
           "modmem_lp4_freq_switch_seq2",  // 0x06E
          "modmem_lp4_freq_switch_seq2a",  // 0x06F
           "modmem_lp4_freq_switch_seq3",  // 0x070
       "modmem_init_dramreset_seq_lp4_a",  // 0x071
       "modmem_init_dramreset_seq_lp4_b",  // 0x072
       "modmem_init_dramreset_seq_lp4_c",  // 0x073
       "modmem_init_dramreset_seq_lp4_d",  // 0x074
                        "maxpi_dll_init",  // 0x075
            "maxpi_override_coarse_init",  // 0x076
                       "maxpi_set_codes",  // 0x077
                       "maxpi_get_codes",  // 0x078
           "maxpi_override_coarse_final",  // 0x079
                          "WEAK_ODT_SET",  // 0x07A
                          "ECC_PHY_INIT",  // 0x07B
          "modmem_init_progcmdckctl_seq",  // 0x07C
                  "DunitFreqChangePart1",  // 0x07D
                         "ChangePHYFreq",  // 0x07E
                  "DunitFreqChangePart3",  // 0x07F
                          "SetICBitDone",  // 0x080
                      "ProgramECCEnable",  // 0x081
                             "ReadFuses",  // 0x082
                      "EnableScrambling",  // 0x083
                      "SetMrcDoneRemove",  // 0x084
                        "ReadBarAddress",  // 0x085
                    "WriteMchBarAddress",  // 0x086
                       "WriteBarAddress",  // 0x087
                       "SetSliceChannel",  // 0x088
                 "LockAunitSliceChannel",  // 0x089
                      "DisableDynamicSr",  // 0x08A
                             "ReadPunit",  // 0x08B
                       "SetPunitMemDone",  // 0x08C
                            "RESETDRAMS",  // 0x08D
                          "ECCClockGate",  // 0x08E
                     "HALF_CFG_PWR_GATE",  // 0x08F
                            "SwitchTo2N",  // 0x090
                            "SwitchTo1N",  // 0x091
                             "WRLVLMODE",  // 0x092
                       "DiffAmpOverride",  // 0x093
                        "DiffAmpRestore",  // 0x094
                         "SEND_DRAM_CMD",  // 0x095
                         "CPGC_RUN_KIRK",  // 0x096
                                   "xyz",  // 0x097
                           "FORCEODT_ON",  // 0x098
                          "FORCEODT_OFF",  // 0x099
                          "FORCEODT_REL",  // 0x09A
                     "READTRAINING_EXIT",  // 0x09B
                          "CPGC_DISABLE",  // 0x09C
                  "SetAunitSliceChannel",  // 0x09D
                       "CPGC_RUN_TEST_L",  // 0x09E
                        "CPGC_SETUP_ERT",  // 0x09F
                         "CPGC_EXIT_ERT",  // 0x0A0
                       "CPGC_RUN_DIRECT",  // 0x0A1
                     "CPGC_CHECK_ERRORS",  // 0x0A2
                      "CPGC_SETUP_DPAT0",  // 0x0A3
                         "CPGC_RUN_TEST",  // 0x0A4
                           "CPGC_ENABLE",  // 0x0A5
               "CPGC_RESETUP_WRITE_READ",  // 0x0A6
                  "DQ_DB_REGION_PROGRAM",  // 0x0A7
                         "CPGC_SETUP_VA",  // 0x0A8
                            "CPGC_LOOPS",  // 0x0A9
                             "DRIVE_CKE",  // 0x0AA
                        "CPGC_STOP_TEST",  // 0x0AB
                               "DQCALRD",  // 0x0AC
                   "ENABLE_CKE_OVERRIDE",  // 0x0AD
                          "PRECHARGEALL",  // 0x0AE
                      "CPGC_TARGET_BANK",  // 0x0AF
                           "CPGC_FIXVAR",  // 0x0B0
                    "CPGC_FIXVAR_REVERT",  // 0x0B1
                              "CPGC_MRS",  // 0x0B2
                            "CPGC_CADB1",  // 0x0B3
                     "CPGC_DESELECT_DIS",  // 0x0B4
                      "CPGC_DESELECT_EN",  // 0x0B5
                       "CPGC_CADB1_BUFA",  // 0x0B6
                       "CPGC_CADB1_BUFB",  // 0x0B7
                      "CPGC_CWL_PATTERN",  // 0x0B8
                         "CPGC_EXIT_MRS",  // 0x0B9
                        "CPGC_CADB_MODE",  // 0x0BA
                  "CPGC_RESETUP_TRAFFIC",  // 0x0BB
                        "CPGC_DPAT_MODE",  // 0x0BC
                         "CPGC_LDO_CADB",  // 0x0BD
                         "CPGC_LDO_DPAT",  // 0x0BE
                    "CPGC_LDO_CADB_LFSR",  // 0x0BF
                    "CPGC_LDO_DPAT_LFSR",  // 0x0C0
             "EARLY_READ_TRAINING_ENTRY",  // 0x0C1
              "EARLY_READ_TRAINING_EXIT",  // 0x0C2
                  "FINEWRITELEVEL_ENTRY",  // 0x0C3
                  "FINEWRITELEVEL_SHAPE",  // 0x0C4
                   "FINEWRITELEVEL_EXIT",  // 0x0C5
                     "ENTER_CA_TRAINING",  // 0x0C6
                      "EXIT_CA_TRAINING",  // 0x0C7
                             "ECT_ENTRY",  // 0x0C8
                           "RCVEN_ENTRY",  // 0x0C9
                            "RCVEN_EXIT",  // 0x0CA
                    "VOC_TRAINING_ENTRY",  // 0x0CB
                    "VOC_GET_LDO_ENABLE",  // 0x0CC
                         "VOC_PHY_ENTRY",  // 0x0CD
                "VOC_COMP_VREF_AND_INIT",  // 0x0CE
               "VOC_GET_RCOMP_PUP_VALUE",  // 0x0CF
               "VOC_GET_RCOMP_PDN_VALUE",  // 0x0D0
            "VOC_SET_ODT_RCOMP_OVERRIDE",  // 0x0D1
                     "VOC_ENABLE_WLMODE",  // 0x0D2
                    "VOC_DISABLE_WLMODE",  // 0x0D3
                     "VOC_TRAINING_EXIT",  // 0x0D4
               "PERIODIC_TRAINING_START",  // 0x0D5
                "PERIODIC_TRAINING_READ",  // 0x0D6
             "PERIODIC_TRAINING_MNT_DIS",  // 0x0D7
                  "PERIODIC_TRAINING_EN",  // 0x0D8
                  "CPGC_GET_TEST_RESULT",  // 0x0D9
                   "CPGC_SET_CHUNK_MASK",  // 0x0DA
                   "CPGC_STOP_CLEAR_ERR",  // 0x0DB
                       "CPGC_START_TEST",  // 0x0DC
                       "gen_rxpbden_set",  // 0x0DD
                           "CPGC_ECC_EN",  // 0x0DE
                              "MEM_INIT",  // 0x0DF
                             "MNTEN_SET",  // 0x0E0
                             "MNTEN_CLR",  // 0x0E1
                    "READTRAINING_ENTRY",  // 0x0E2
};
#endif //CAPSULESTRINGS

CONST SUBTASK_INDEX_OFFSET SubtaskOffsetIndex[MAX_SUBTASKS + 1] = {
  { 0x096, CPGC_RUN_KIRK        },
  {  (UINT16)(UINT32)NULL, (UINT16)(UINT32)NULL }
};

CONST UINT8 InitData[] = {
  // FLAGS            CondVar                                      ADDRESS                                                                 BOXTYPE                     MASK                       ACTION/dPFCT               DELAY      #Cond  Cond                                                                                       Val
  //
  // InitPunit
  //
  xxxMx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00001000), MASK1(0x7)               , AP(SET,       ____T),                   3,   T(T_LPDDR3),                                                                               VAL1(0x1),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x2),                                                                                 T(T_DDR3),                                                                                 VAL1(0x4),
  xxxxx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR),
  ASSIGNDONE,
  //
  // PollPunit
  //
  xxxMx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  xxxMx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00001000), MASK1(0x80)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // sai_init_seq
  //
  xxxxx2xx                                        ,                VAL2(SAI_CTRL_REG0_SAI_REG)                                           ,  BB(SAI,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x41200200),
  xxxxx2xx                                        ,                VAL2(SAI_CTRL_REG0_1_SAI_REG)                                         ,  BB(SAI,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x400),
  xxxxx2xx                                        ,                VAL2(SAI_RW_REG0_SAI_REG)                                             ,  BB(SAI,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x41200200),
  xxxxx2xx                                        ,                VAL2(SAI_RW_REG0_1_SAI_REG)                                           ,  BB(SAI,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x400),
  xxxxx2xx                                        ,                VAL2(REG_POLICY0_SAI_REG)                                             ,  BB(SAI,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x3),
  xxxxx2xx                                        ,                VAL2(REG_POLICY1_SAI_REG)                                             ,  BB(SAI,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x3),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp1xm_seq
  //
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000003E8),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH0_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x80)              , AP(GET,       D____),                                                                                                                   VAL2(TEMP),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x4),                                                                                  // // Enable override selects. , // Gated & Ungated Power Mux: vnn = ON, vcca = OFF
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x4),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG1_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // // Assert dfx reset
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG1_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // // Enable Isolation from LVG,  // Gated Power Mux: vnn = ON, vcca = OFF;  Ungated Power Mux: vnn = ON, vcca = OFF
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxxx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000010)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = ON, vcca = OFF
  xxxxx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000010)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                                         ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // // Enable Isolation from LVUG
  xxxMx1xx                                        ,                VAL1(LVUGSUPPLYCTL0_DQDPIC_REG)                                       ,  BB(DQDPIC,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00001000), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                                                 VAL1(0x0),                                                                                  // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = OFF
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00001000), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx1xx                                        ,                VAL1(LVUGSUPPLYCTL0_DPIC_REG)                                         ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // // Disable Isolation from LVUG
  xxxMx1xx                                        ,                VAL1(LVUGSUPPLYCTL0_DQDPIC_REG)                                       ,  BB(DQDPIC,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00001000), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                                                 VAL1(0x4),                                                                                  // // Switch the power mode config within PM controller, so that PM controller internally points to vcca = ON,  // Gated Power Mux: vnn = OFF, vcca = OFF;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxxx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000100)                           , AP(SET,       _____),                                                                                                                   VAL1(0xF),                                                                                  // // stagger enable VCCA
  xxxxx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000100)                           , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                                                 VAL1(0xF),
  xxxxx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000100)                           , AP(SET,       _____),                                                                                                                   VAL1(0xFF),                                                                                 // // Gated Power Mux: vnn = OFF, vcca = ON;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxxx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000100)                           , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                                                 VAL1(0xFF),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // // Disable Isolation
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG0_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG1_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                                                 VAL1(0x0),                                                                                  // // Deassert dfx reset
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CONFIG1_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // // Remove cfg overrides and let PM controller control the power gates, // Gated Power Mux: vnn = OFF, vcca = ON;  Ungated Power Mux: vnn = OFF, vcca = ON
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_PGOVR_DPIC_REG)                                      ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp1p5_seq
  //
  xxxMx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00000011), MASK2(0x3C7)             , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL2(0x40),                                                                                 // static_0 : //LP4 training registers, static_0 : //LP4 training registers, static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxMx1xx                                        ,                VAL1(PTCTL1_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00000011), MASK2(0xFEFE)            , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL2(0x0),
  xxxxx1xx                                        ,                VAL1(PTROCNT12_DQDPLVUG_REG)                                          ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT34_DQDPLVUG_REG)                                          ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT56_DQDPLVUG_REG)                                          ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT78_DQDPLVUG_REG)                                          ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT910_DQDPLVUG_REG)                                         ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT1112_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT1314_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT1516_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT1718_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT1920_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT2122_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT2324_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT2526_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT2728_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT2930_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT3132_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT3334_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT3536_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT3738_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT3940_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT4142_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT4344_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT4546_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT4748_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT4950_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT5152_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT5354_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT5556_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT5758_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT5960_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT6162_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT6364_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT6566_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT6768_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx1xx                                        ,                VAL1(PTROCNT6970_DQDPLVUG_REG)                                        ,  BB(DQDPLVUG,   _00001111)                           , AP(SET_DELAY, ____T), VAL4(0x0000000A), 1,   T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_0 : //LP4 training registers, static_0 : //LP4 training registers
  xxxxx2xx                                        ,                VAL2(PTDATAMUXSEL_DQ_REG)                                             ,  BB(DQ,         _00000111)                           , AP(SET_DELAY, ____T), VAL4(0x0000000A), 1,   T(T_LPDDR4),                                                                               VAL3(0x0),                                                                                  // static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB, static_LP4TRAIN : // VccFAR (LDO) registers below //, // TXFFDQ0_DVFS , // TXFFCA0_DVFS , // TXTCODE0_DVFS , // TXPANIC , // TXPANICCOMP, // TXFB
  xxxMx1xx                                        ,                VAL1(CONFIG_0_ADPLL_REG)                                              ,  BB(ADPLL,      _00001000), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp2m_seq
  //
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x20),                                                                                T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x10),                                                                                 // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       __F__),                   5,   F(F_1333),                                                                                 VAL1(0x2),                                                                                 F(F_1600),                                                                                 VAL1(0x3),                                                                                 F(F_1866),                                                                                 VAL1(0x4),                                                                                 F(F_2133),                                                                                 VAL1(0x5),                                                                                 F(F_2400),                                                                                 VAL1(0x6),                                                                                  // static_DIGCTL_m :
  xxxxx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000100)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x2B),                                                                                T(T_LPDDR3),                                                                               VAL1(0x2B),                                                                                T(T_LPDDR4),                                                                               VAL1(0x16),                                                                                 // static_DIGCTL_m :
  xxxxx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DIGCTL),                                                                       // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000010), MASK1(0x8)               , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x0),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x8),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x8),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x8),                                                                                  // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000010), MASK1(0x4)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x4),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000010), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000001), MASK1(0x70)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x50),                                                                                 // static_DIGCTL_m : , static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000001), MASK1(0x8)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_CCC_REG)                                                  ,  BB(CCC,        _00000001), MASK1(0x6)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x2),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x4),                                                                                  // static_DIGCTL_m : , static_DIGCTL_m :
  xxxMx2xx                                        ,                VAL2(CH1_DIGCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x10),                                                                                 // static_DIGCTL_m :
  xxxMx2xx                                        ,                VAL2(CH1_DIGCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       __F__),                   5,   F(F_1333),                                                                                 VAL1(0x2),                                                                                 F(F_1600),                                                                                 VAL1(0x3),                                                                                 F(F_1866),                                                                                 VAL1(0x4),                                                                                 F(F_2133),                                                                                 VAL1(0x5),                                                                                 F(F_2400),                                                                                 VAL1(0x6),                                                                                  // static_DIGCTL_m :
  xxxME2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(CH1_DIGCTL_CCC_REG)                                              ,  BB(CCC,        _00000010), MASK1(0x4)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x4),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x4),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x4),                                                                                  // static_DIGCTL_m :
  xxxME2xx          , VAL2(BXT_P_A0)              ,                VAL2(CH1_DIGCTL_CCC_REG)                                              ,  BB(CCC,        _00000010), MASK1(0x4)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x4),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGCTL_m :
  xxxxx2xx                                        ,                VAL2(CH1_DIGCTL_CCC_REG)                                              ,  BB(CCC,        _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_CH1_DIGCTL),                                                                   // static_DIGCTL_m : , static_DIGCTL_m :
  xxxMx2xx                                        ,                VAL2(CH1_DIGCTL_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x1C)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0xC),                                                                                  // static_DIGCTL_m : , static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x20),                                                                                T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x10),                                                                                 // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       __F__),                   5,   F(F_1333),                                                                                 VAL1(0x2),                                                                                 F(F_1600),                                                                                 VAL1(0x3),                                                                                 F(F_1866),                                                                                 VAL1(0x4),                                                                                 F(F_2133),                                                                                 VAL1(0x5),                                                                                 F(F_2400),                                                                                 VAL1(0x6),                                                                                  // static_DIGCTL_m :
  xxxxx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000100)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x2B),                                                                                T(T_LPDDR3),                                                                               VAL1(0x2B),                                                                                T(T_LPDDR4),                                                                               VAL1(0x16),                                                                                 // static_DIGCTL_m :
  xxxxx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DIGCTL),                                                                        // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000010), MASK1(0x8)               , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x0),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x8),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x8),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x8),                                                                                  // static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000011), MASK2(0x240)             , AP(SET,       _____),                                                                                                                   VAL2(0x200),                                                                                // static_DIGCTL_m : , static_DIGCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000001), MASK1(0x3C)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x2C),                                                                                 // static_DIGCTL_m : , static_DIGCTL_m : , static_DIGCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  xxxMx1xx                                        ,                VAL1(SFRCONFIG_0_ADPLL_REG)                                           ,  BB(ADPLL,      _00000110), MASK2(0xFFC0)            , AP(SET,       _____),                                                                                                                   VAL2(0x88C0),                                                                               // sfr fix from hsd, sfr fix from hsd, sfr fix from hsd, sfr fix from hsd
  xxxxx1xx                                        ,                VAL1(PLLDIVRATIOS_0_ADPLL_REG)                                        ,  BB(ADPLL,      _00001100)                           , AP(SET,       __F_T),                   7,   FT(F_1333,T_DDR3|T_LPDDR3),                                                                VAL2(0x2805),                                                                              FT(F_1600,T_DDR3|T_LPDDR3),                                                                VAL2(0x1806),                                                                              FT(F_1866,T_LPDDR3|T_DDR3),                                                                VAL2(0x1C07),                                                                              FT(F_1600,T_LPDDR4),                                                                       VAL2(0x1803),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x2004),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x4809),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x4809),
  xxxMx1xx                                        ,                VAL1(PLLDIVRATIOS_0_ADPLL_REG)                                        ,  BB(ADPLL,      _00000010), MASK1(0xF0)              , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2666,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_3200,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x0),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0x0),                                                                                 FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x0),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CONFIG_3_ADPLL_REG)                                              ,  BB(ADPLL,      _00000001), MASK1(0xFE)              , AP(SET,       _____),                                                                                                                   VAL1(0x12),                                                                                 // modmem_fbdiv_prog_seq S9->E
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL_DPIC_REG)                                              ,  BB(DPIC,       _00001000), MASK1(0x13)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),                                                                                 // static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL_DPIC_REG)                                              ,  BB(DPIC,       _00000001), MASK1(0x1F)              , AP(SET,       __F_T),                   4,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL1(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL1(0x0),                                                                                 FT(F_1066|F_1600|F_2133|F_2666|F_2933|F_3200,T_LPDDR4),                                    VAL1(0x0),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x1),                                                                                  // static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxMx1xx                                        ,                VAL1(SPIDCLKCTL0_DPIC_REG)                                            ,  BB(DPIC,       _00000110), MASK2(0x1FFF)            , AP(SET,       _____),                                                                                                                   VAL2(0x1388),                                                                               // static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here, static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxMx1xx                                        ,                VAL1(SPIDCLKCTL0_DPIC_REG)                                            ,  BB(DPIC,       _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   6,   FT(F_1333,T_DDR3|T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1600,T_DDR3|T_LPDDR3),                                                                VAL1(0x18),                                                                                FT(F_1866,T_DDR3|T_LPDDR3),                                                                VAL1(0x1C),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0xC),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x10),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x12),                                                                                 // static_0_m : // Registers in ADPLL cfg space get programmed here
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00001100), MASK2(0x1F0)             , AP(SET,       __F_T),                   6,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL2(0x70),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL2(0x90),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL2(0x90),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL2(0x90),                                                                                FT(F_2133|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL2(0xA0),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL2(0x70),                                                                                 // static_PLLCTL_m :
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_PLLCTL_m :
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000010), MASK1(0x30)              , AP(SET,       __F_T),                   4,   FT(F_1600|F_1866,T_DDR3),                                                                  VAL1(0x0),                                                                                 FT(F_1333,T_LPDDR3),                                                                       VAL1(0x10),                                                                                FT(F_1600|F_1866,T_LPDDR3),                                                                VAL1(0x0),                                                                                 FT(F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                    VAL1(0x0),                                                                                  // static_PLLCTL_m :
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000011), MASK2(0x10D)             , AP(SET,       _____),                                                                                                                   VAL2(0x109),                                                                                // static_PLLCTL_m : , static_PLLCTL_m : , static_PLLCTL_m : , static_PLLCTL_m :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3m_seq
  //
  xxxMx1xx                                        ,                VAL1(CCCCTL_CCC_REG)                                                  ,  BB(CCC,        _00001100), MASK2(0x23C)             , AP(SET,       _____),                                                                                                                   VAL2(0x3C),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(CCCCTL_CCC_REG)                                                  ,  BB(CCC,        _00000111), MASK3(0x3FF84)           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL3(0x3FF84),                                                                             T(T_LPDDR3),                                                                               VAL3(0x3F780),                                                                             T(T_LPDDR4),                                                                               VAL3(0x3FF84),                                                                              // static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(CCCCTL_CCC_REG)                                                  ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQCTL_CCC_REG)                                                 ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x33),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0xFC)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0xFC),                                                                                T(T_LPDDR4),                                                                               VAL1(0xFC),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_CCC_REG)                                                ,  BB(CCC,        _00001110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_WRDQSCTL),                                                                     // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CCC_REG)                                                ,  BB(CCC,        _00000010), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_CCC_REG)                                                ,  BB(CCC,        _00000001)                           , AP(SET,       D_F_T),                   7,   FT(F_1066,T_DDR3),                                                                         VAL2(DYN_CCC_WRDQSCTL_1),                                                                  FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL2(DYN_CCC_WRDQSCTL_2),                                                                  FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_CCC_WRDQSCTL_3),                                                                  FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL2(DYN_CCC_WRDQSCTL_4),                                                                  FT(F_1066,T_LPDDR4),                                                                       VAL2(DYN_CCC_WRDQSCTL_5),                                                                  FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_CCC_WRDQSCTL_6),                                                                  FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_CCC_WRDQSCTL_7),                                                                   // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RDVLDCTL_CCC_REG)                                                ,  BB(CCC,        _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RDVLDCTL_CCC_REG)                                                ,  BB(CCC,        _00000010), MASK1(0x7)               , AP(SET,       __F_T),                   4,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2400|F_2133,T_LPDDR4),                                                                VAL1(0x0),                                                                                 FT(F_1600|F_1866,T_DDR3),                                                                  VAL1(0x0),                                                                                 FT(F_1866|F_1600,T_LPDDR3),                                                                VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RDVLDCTL_CCC_REG)                                                ,  BB(CCC,        _00000001)                           , AP(SET,       D_F_T),                   8,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL2(DYN_CCC_RDVLDCTL),                                                                    FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_CCC_RDVLDCTL_1),                                                                  FT(F_1333,T_LPDDR3),                                                                       VAL2(DYN_CCC_RDVLDCTL_2),                                                                  FT(F_1600,T_LPDDR3),                                                                       VAL2(DYN_CCC_RDVLDCTL_3),                                                                  FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_CCC_RDVLDCTL_4),                                                                  FT(F_1066|F_1600|F_2133|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_CCC_RDVLDCTL_5),                                                                  FT(F_2400|F_2666,T_LPDDR4),                                                                VAL2(DYN_CCC_RDVLDCTL_6),                                                                  FT(F_1866,T_DDR3),                                                                         VAL2(DYN_CCC_RDVLDCTL_7),                                                                   // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_CCC_REG)                                               ,  BB(CCC,        _00000010), MASK1(0x37)              , AP(SET,       _____),                                                                                                                   VAL1(0x7),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0xC2)              , AP(SET,       __F_T),                   5,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL1(0x0),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0xC2),                                                                                FT(F_1066|F_1333|F_1600,T_LPDDR3),                                                         VAL1(0x0),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0xC2),                                                                                FT(F_1066|F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                             VAL1(0xC2),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL0_CCC_REG)                                               ,  BB(CCC,        _00001100), MASK2(0xFFE0)            , AP(SET,       _____),                                                                                                                   VAL2(0x30E0),                                                                               // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RK2RKCTL0_CCC_REG)                                               ,  BB(CCC,        _00000110)                           , AP(SET,       D_F_T),                   5,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL2(DYN_CCC_RK2RKCTL0),                                                                   FT(F_1866,T_DDR3),                                                                         VAL2(DYN_CCC_RK2RKCTL0_1),                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL2(DYN_CCC_RK2RKCTL0_2),                                                                 FT(F_1066|F_1600,T_LPDDR4),                                                                VAL2(DYN_CCC_RK2RKCTL0_3),                                                                 FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_CCC_RK2RKCTL0_4),                                                                  // static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RK2RKCTL0_CCC_REG)                                               ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x70),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(WRLVL_CCC_REG)                                                   ,  BB(CCC,        _00001011), MASK3(0xEFF05)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(LDOCTL0_CCC_REG)                                                 ,  BB(CCC,        _00001111), MASK4(0xFFFFFFF)         , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL4(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL4(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL4(0x1133111),                                                                            // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(LDOCTL1_CCC_REG)                                                 ,  BB(CCC,        _00000001)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x11),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(LPMODECTL0_CCC_REG)                                              ,  BB(CCC,        _00001111), MASK4(0x77777707)        , AP(SET,       _____),                                                                                                                   VAL4(0x1000001),                                                                            // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(LPMODECTL1_CCC_REG)                                              ,  BB(CCC,        _00001100), MASK2(0x7740)            , AP(SET,       _____),                                                                                                                   VAL2(0x1100),                                                                               // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(LPMODECTL1_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0x20)              , AP(SET,       ____T),                   2,   T(T_LPDDR4|T_LPDDR3),                                                                      VAL1(0x20),                                                                                T(T_DDR3),                                                                                 VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(LPMODECTL1_CCC_REG)                                              ,  BB(CCC,        _00000101), MASK2(0x1F07)            , AP(SET,       _____),                                                                                                                   VAL2(0x1),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RXDLLRDCMDCTL0_CCC_REG)                                          ,  BB(CCC,        _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_RXDLLRDCMDCTL0),                                                               // static_DIGREGS_m :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(RXDLLRDCMDCTL0_CCC_REG)                                          ,  BB(CCC,        _00000110), MASK2(0x3F0)             , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS_m :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(RXDLLRDCMDCTL0_CCC_REG)                                          ,  BB(CCC,        _00000110), MASK2(0x3F0)             , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL2(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL2(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL2(0x40),                                                                                 // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RXDLLRDCMDCTL0_CCC_REG)                                          ,  BB(CCC,        _00000011)                           , AP(SET,       D_F_T),                   6,   FT(F_1066,T_DDR3),                                                                         VAL2(DYN_CCC_RXDLLRDCMDCTL0_1),                                                            FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL2(DYN_CCC_RXDLLRDCMDCTL0_2),                                                            FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_CCC_RXDLLRDCMDCTL0_3),                                                            FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL2(DYN_CCC_RXDLLRDCMDCTL0_4),                                                            FT(F_1066|F_1600,T_LPDDR4),                                                                VAL2(DYN_CCC_RXDLLRDCMDCTL0_5),                                                            FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_CCC_RXDLLRDCMDCTL0_6),                                                             // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RXDLLRDCMDCTL0_CCC_REG)                                          ,  BB(CCC,        _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   6,   FT(F_1333,T_DDR3|T_LPDDR3),                                                                VAL1(0x13),                                                                                FT(F_1600,T_DDR3|T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1866,T_DDR3|T_LPDDR3),                                                                VAL1(0x17),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0x23),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x24),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x25),                                                                                 // static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(CH1_CCCCTL_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0x3C)              , AP(SET,       _____),                                                                                                                   VAL1(0x3C),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(CH1_CCCCTL_CCC_REG)                                              ,  BB(CCC,        _00000111), MASK3(0x3FF84)           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL3(0x3FF84),                                                                             T(T_LPDDR3),                                                                               VAL3(0x3F780),                                                                             T(T_LPDDR4),                                                                               VAL3(0x3FF84),                                                                              // static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(CH1_CCCCTL_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(CH1_LDOCTL1_CCC_REG)                                             ,  BB(CCC,        _00000011), MASK2(0xFFF)             , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL2(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL2(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL2(0x111),                                                                                // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQCTL_DQ_REG)                                                  ,  BB(DQ,         _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x3333),                                                                               // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00001110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_WRDQSCTL_CC),                                                                   // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000001)                           , AP(SET,       D_F_T),                   7,   FT(F_1066,T_DDR3),                                                                         VAL2(DYN_DQ_WRDQSCTL_CC_1),                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL2(DYN_DQ_WRDQSCTL_CC_2),                                                                FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_DQ_WRDQSCTL_CC_3),                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL2(DYN_DQ_WRDQSCTL_CC_4),                                                                FT(F_1066,T_LPDDR4),                                                                       VAL2(DYN_DQ_WRDQSCTL_CC_5),                                                                FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_WRDQSCTL_CC_6),                                                                FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_DQ_WRDQSCTL_CC_7),                                                                 // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00001110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_WRDQSCTL_BL),                                                                   // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000001)                           , AP(SET,       D_F_T),                   7,   FT(F_1066,T_DDR3),                                                                         VAL2(DYN_DQ_WRDQSCTL_BL_1),                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL2(DYN_DQ_WRDQSCTL_BL_2),                                                                FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_DQ_WRDQSCTL_BL_3),                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL2(DYN_DQ_WRDQSCTL_BL_4),                                                                FT(F_1066,T_LPDDR4),                                                                       VAL2(DYN_DQ_WRDQSCTL_BL_5),                                                                FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_WRDQSCTL_BL_6),                                                                FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_DQ_WRDQSCTL_BL_7),                                                                 // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RDVLDCTL_DQ_REG)                                                 ,  BB(DQ,         _00000100)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RDVLDCTL_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0x70)              , AP(SET,       __F_T),                   4,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL1(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL1(0x0),                                                                                 FT(F_1066|F_1600|F_2133|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x0),                                                                                 FT(F_2400|F_2666,T_LPDDR4),                                                                VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RDVLDCTL_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0x7)               , AP(SET,       __F_T),                   4,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2400|F_2133,T_LPDDR4),                                                                VAL1(0x0),                                                                                 FT(F_1600|F_1866,T_DDR3),                                                                  VAL1(0x0),                                                                                 FT(F_1866|F_1600,T_LPDDR3),                                                                VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RDVLDCTL_DQ_REG)                                                 ,  BB(DQ,         _00000001)                           , AP(SET,       D_F_T),                   8,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL2(DYN_DQ_RDVLDCTL),                                                                     FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_DQ_RDVLDCTL_1),                                                                   FT(F_1333,T_LPDDR3),                                                                       VAL2(DYN_DQ_RDVLDCTL_2),                                                                   FT(F_1600,T_LPDDR3),                                                                       VAL2(DYN_DQ_RDVLDCTL_3),                                                                   FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RDVLDCTL_4),                                                                   FT(F_1066|F_1600|F_2133|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_DQ_RDVLDCTL_5),                                                                   FT(F_2400|F_2666,T_LPDDR4),                                                                VAL2(DYN_DQ_RDVLDCTL_6),                                                                   FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RDVLDCTL_7),                                                                    // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_DQ_REG)                                                ,  BB(DQ,         _00000010), MASK1(0x37)              , AP(SET,       _____),                                                                                                                   VAL1(0x7),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0xF8)              , AP(SET,       __F_T),                   5,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL1(0x0),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0xF8),                                                                                FT(F_1066|F_1333|F_1600,T_LPDDR3),                                                         VAL1(0x0),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0xF8),                                                                                FT(F_1066|F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                             VAL1(0xF8),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x2)               , AP(SET,       __F_T),                   5,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL1(0x0),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0x2),                                                                                 FT(F_1066|F_1333|F_1600,T_LPDDR3),                                                         VAL1(0x0),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0x2),                                                                                 FT(F_1066|F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                             VAL1(0x2),                                                                                  // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL1_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RK2RKCTL0_DQ_REG)                                                ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x30),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL0_DQ_REG)                                                ,  BB(DQ,         _00000100), MASK1(0x80)              , AP(SET,       __F_T),                   4,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL1(0x80),                                                                                FT(F_1066|F_1333|F_1600,T_LPDDR3),                                                         VAL1(0x0),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0x0),                                                                                 FT(F_1066|F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                             VAL1(0x80),                                                                                 // static_DIGREGS_m :
  xxxMx1xx                                        ,                VAL1(RK2RKCTL0_DQ_REG)                                                ,  BB(DQ,         _00000100), MASK1(0x60)              , AP(SET,       _____),                                                                                                                   VAL1(0x60),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RK2RKCTL0_DQ_REG)                                                ,  BB(DQ,         _00000110)                           , AP(SET,       D_F_T),                   6,   FT(F_1066|F_1333|F_1600,T_DDR3),                                                           VAL2(DYN_DQ_RK2RKCTL0),                                                                    FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RK2RKCTL0_1),                                                                  FT(F_1066|F_1333|F_1600,T_LPDDR3),                                                         VAL2(DYN_DQ_RK2RKCTL0_2),                                                                  FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RK2RKCTL0_3),                                                                  FT(F_1066|F_1600,T_LPDDR4),                                                                VAL2(DYN_DQ_RK2RKCTL0_4),                                                                  FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_DQ_RK2RKCTL0_5),                                                                   // static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RK2RKCTL0_DQ_REG)                                                ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x70),                                                                                 // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx2xx                                        ,                VAL2(LDOCTL1_DQ_REG)                                                  ,  BB(DQ,         _00000111)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL3(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL3(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL3(0x224422),                                                                             // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx2xx                                        ,                VAL2(LDOCTL0_DQ_REG)                                                  ,  BB(DQ,         _00000111)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL3(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL3(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL3(0x224422),                                                                             // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(LPMODECTL0_DQ_REG)                                               ,  BB(DQ,         _00001111), MASK4(0x77777707)        , AP(SET,       _____),                                                                                                                   VAL4(0x1000001),                                                                            // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(LPMODECTL1_DQ_REG)                                               ,  BB(DQ,         _00001100), MASK2(0x7740)            , AP(SET,       _____),                                                                                                                   VAL2(0x1100),                                                                               // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(LPMODECTL1_DQ_REG)                                               ,  BB(DQ,         _00000100), MASK1(0x20)              , AP(SET,       ____T),                   2,   T(T_LPDDR4|T_LPDDR3),                                                                      VAL1(0x20),                                                                                T(T_DDR3),                                                                                 VAL1(0x0),                                                                                  // static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(LPMODECTL1_DQ_REG)                                               ,  BB(DQ,         _00000101), MASK2(0x1FFF)            , AP(SET,       _____),                                                                                                                   VAL2(0x1),                                                                                  // static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx2xx                                        ,                VAL2(RXDLLRDCMDCTL0_DQ_REG)                                           ,  BB(DQ,         _00000110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXDLLRDCMDCTL0),                                                                // static_DIGREGS_m : , static_DIGREGS_m :
  xxxxx2xx                                        ,                VAL2(RXDLLRDCMDCTL0_DQ_REG)                                           ,  BB(DQ,         _00000011)                           , AP(SET,       D_F_T),                   6,   FT(F_1066,T_DDR3),                                                                         VAL2(DYN_DQ_RXDLLRDCMDCTL0_1),                                                             FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL2(DYN_DQ_RXDLLRDCMDCTL0_2),                                                             FT(F_1066,T_LPDDR3),                                                                       VAL2(DYN_DQ_RXDLLRDCMDCTL0_3),                                                             FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL2(DYN_DQ_RXDLLRDCMDCTL0_4),                                                             FT(F_1066|F_1600,T_LPDDR4),                                                                VAL2(DYN_DQ_RXDLLRDCMDCTL0_5),                                                             FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL2(DYN_DQ_RXDLLRDCMDCTL0_6),                                                              // static_DIGREGS_m :
  xxxMx2xx                                        ,                VAL2(RXDLLRDCMDCTL0_DQ_REG)                                           ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   6,   FT(F_1333,T_DDR3|T_LPDDR3),                                                                VAL1(0x13),                                                                                FT(F_1600,T_DDR3|T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1866,T_DDR3|T_LPDDR3),                                                                VAL1(0x17),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0x23),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x24),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x25),                                                                                 // static_DIGREGS_m :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3_seq
  //
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP3CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3107),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3104),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3103),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3002),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3107),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3105),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3107),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3205),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3207),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP2CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3107),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3104),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3103),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3002),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3107),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3105),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3107),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3205),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3207),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3109),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3107),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP0CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3100),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3100),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x23F),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0x336),                                                                               FT(F_1333,T_LPDDR3),                                                                       VAL2(0x33F),                                                                                // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxxx1xx                                        ,                VAL1(RXDLLDQSRK1CTL_CCC_REG)                                          ,  BB(CCC,        _00001100)                           , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3D3D),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3131),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x2C2C),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x2727),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x2424),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3D3D),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x2D2D),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3D3D),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x2E2E),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3D3D),                                                                               // static_SIGGRPS : , static_SIGGRPS :
  xxxxx1xx                                        ,                VAL1(RXDLLDQSRK0CTL_CCC_REG)                                          ,  BB(CCC,        _00000011)                           , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3D3D),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x2F2F),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x2B2B),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x2727),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x2323),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3D3D),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x2D2D),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3D3D),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x2D2D),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3D3D),                                                                               // static_SIGGRPS : , static_SIGGRPS :
  xxxME1xR          , VAL2(RANK1_ENABLED)         ,                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x215D),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x214B),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP3CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3107),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3104),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3103),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3002),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3107),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3105),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3107),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3205),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3207),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP2CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3107),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3104),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3103),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3002),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3107),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3105),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3107),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3205),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3207),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3109),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3107),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP0CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3100),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3100),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x23F),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0x336),                                                                               FT(F_1333,T_LPDDR3),                                                                       VAL2(0x33F),                                                                                // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxME2xR          , VAL2(RANK1_ENABLED)         ,                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x215D),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x214B),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLSIGGRP2CTL_CCC_REG)                                     ,  BB(CCC,        _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x30013001),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x30013001),                                                                          FT(F_2400,T_LPDDR4),                                                                       VAL4(0x30013001),                                                                          FT(F_2666,T_LPDDR4),                                                                       VAL4(0x30013001),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x30013001),                                                                          FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x31013101),                                                                          FT(F_1866,T_DDR3),                                                                         VAL4(0x31013101),                                                                          FT(F_1600,T_LPDDR3),                                                                       VAL4(0x30013001),                                                                          FT(F_1866,T_LPDDR3),                                                                       VAL4(0x30013001),                                                                          FT(F_1333,T_LPDDR3),                                                                       VAL4(0x31013101),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x10C0107),                                                                           FT(F_2133,T_LPDDR4),                                                                       VAL4(0x1070104),                                                                           FT(F_2400,T_LPDDR4),                                                                       VAL4(0x1070103),                                                                           FT(F_2666,T_LPDDR4),                                                                       VAL4(0x1060103),                                                                           FT(F_3200,T_LPDDR4),                                                                       VAL4(0x1040102),                                                                           FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x310C3107),                                                                          FT(F_1866,T_DDR3),                                                                         VAL4(0x310A3105),                                                                          FT(F_1600,T_LPDDR3),                                                                       VAL4(0x13F013B),                                                                           FT(F_1866,T_LPDDR3),                                                                       VAL4(0x1360132),                                                                           FT(F_1333,T_LPDDR3),                                                                       VAL4(0x23F023B),                                                                            // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLSIGGRP0CTL_CCC_REG)                                     ,  BB(CCC,        _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x24A0245),                                                                           FT(F_2133,T_LPDDR4),                                                                       VAL4(0x2370233),                                                                           FT(F_2400,T_LPDDR4),                                                                       VAL4(0x230022D),                                                                           FT(F_2666,T_LPDDR4),                                                                       VAL4(0x22B0227),                                                                           FT(F_3200,T_LPDDR4),                                                                       VAL4(0x2230221),                                                                           FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x14A0145),                                                                           FT(F_1866,T_DDR3),                                                                         VAL4(0x13F013B),                                                                           FT(F_1600,T_LPDDR3),                                                                       VAL4(0x20C0207),                                                                           FT(F_1866,T_LPDDR3),                                                                       VAL4(0x20A0205),                                                                           FT(F_1333,T_LPDDR3),                                                                       VAL4(0x30C0307),                                                                            // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP5CTL_DQ_REG)                                          ,  BB(DQ,         _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x31013101),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP4CTL_DQ_REG)                                          ,  BB(DQ,         _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x31073107),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x31073104),                                                                          FT(F_2400,T_LPDDR4),                                                                       VAL4(0x31073103),                                                                          FT(F_2666,T_LPDDR4),                                                                       VAL4(0x31033103),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x31043102),                                                                          FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x31073107),                                                                          FT(F_1866,T_DDR3),                                                                         VAL4(0x31053105),                                                                          FT(F_1333|F_1600,T_LPDDR3),                                                                VAL4(0x13B013B),                                                                           FT(F_1866,T_LPDDR3),                                                                       VAL4(0x1360132),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP3CTL_DQ_REG)                                          ,  BB(DQ,         _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x3450345),                                                                           FT(F_2133,T_LPDDR4),                                                                       VAL4(0x3370333),                                                                           FT(F_2400,T_LPDDR4),                                                                       VAL4(0x330032D),                                                                           FT(F_2666,T_LPDDR4),                                                                       VAL4(0x3270327),                                                                           FT(F_3200,T_LPDDR4),                                                                       VAL4(0x3230321),                                                                           FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x145),                                                                               FT(F_1866,T_DDR3),                                                                         VAL4(0x13B013B),                                                                           FT(F_1333|F_1600,T_LPDDR3),                                                                VAL4(0x32073207),                                                                          FT(F_1866,T_LPDDR3),                                                                       VAL4(0x320A3205),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP2CTL_DQ_REG)                                          ,  BB(DQ,         _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x31013101),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP1CTL_DQ_REG)                                          ,  BB(DQ,         _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x31073107),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x31073104),                                                                          FT(F_2400,T_LPDDR4),                                                                       VAL4(0x31073103),                                                                          FT(F_2666,T_LPDDR4),                                                                       VAL4(0x31033103),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x31043102),                                                                          FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x31073107),                                                                          FT(F_1866,T_DDR3),                                                                         VAL4(0x31053105),                                                                          FT(F_1333|F_1600,T_LPDDR3),                                                                VAL4(0x13B013B),                                                                           FT(F_1866,T_LPDDR3),                                                                       VAL4(0x1360132),                                                                            // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP0CTL_DQ_REG)                                          ,  BB(DQ,         _00001111), MASK4(0x3FFF3FFF)        , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x3450345),                                                                           FT(F_2133,T_LPDDR4),                                                                       VAL4(0x3370333),                                                                           FT(F_2400,T_LPDDR4),                                                                       VAL4(0x330032D),                                                                           FT(F_2666,T_LPDDR4),                                                                       VAL4(0x3270327),                                                                           FT(F_3200,T_LPDDR4),                                                                       VAL4(0x3230321),                                                                           FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x145),                                                                               FT(F_1866,T_DDR3),                                                                         VAL4(0x13B013B),                                                                           FT(F_1333|F_1600,T_LPDDR3),                                                                VAL4(0x32073207),                                                                          FT(F_1866,T_LPDDR3),                                                                       VAL4(0x320A3205),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxxx1xx                                        ,                VAL1(RXDLLDQSRK1CTL_DQ_REG)                                           ,  BB(DQ,         _00001111)                           , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x3D3D3D3D),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x31313131),                                                                          FT(F_2400,T_LPDDR4),                                                                       VAL4(0x2C2C2C2C),                                                                          FT(F_2666,T_LPDDR4),                                                                       VAL4(0x27272727),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x24242424),                                                                          FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x3D3D3D3D),                                                                          FT(F_1866,T_DDR3),                                                                         VAL4(0x2D2D2D2D),                                                                          FT(F_1333|F_1600,T_LPDDR3),                                                                VAL4(0x3D3D3D3D),                                                                          FT(F_1866,T_LPDDR3),                                                                       VAL4(0x2E2E2E2E),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxxx1xx                                        ,                VAL1(RXDLLDQSRK0CTL_DQ_REG)                                           ,  BB(DQ,         _00001111)                           , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL4(0x3D3D3D3D),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x2F2F2F2F),                                                                          FT(F_2400,T_LPDDR4),                                                                       VAL4(0x2B2B2B2B),                                                                          FT(F_2666,T_LPDDR4),                                                                       VAL4(0x27272727),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x23232323),                                                                          FT(F_1333|F_1600,T_DDR3),                                                                  VAL4(0x3D3D3D3D),                                                                          FT(F_1866,T_DDR3),                                                                         VAL4(0x2D2D2D2D),                                                                          FT(F_1333|F_1600,T_LPDDR3),                                                                VAL4(0x3D3D3D3D),                                                                          FT(F_1866,T_LPDDR3),                                                                       VAL4(0x2D2D2D2D),                                                                           // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(TXDLLSIGGRP6CTL_DQ_REG)                                          ,  BB(DQ,         _00000011), MASK2(0xFFF)             , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_2666,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_3200,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0xC71),                                                                               FT(F_1866,T_DDR3),                                                                         VAL2(0xC71),                                                                               FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(0xC30),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0xC30),                                                                                // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx2xx                                        ,                VAL2(TXDLLSIGGRP7CTL_DQ_REG)                                          ,  BB(DQ,         _00000011), MASK2(0xFFF)             , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_2666,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_3200,T_LPDDR4),                                                                       VAL2(0xC71),                                                                               FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0xC71),                                                                               FT(F_1866,T_DDR3),                                                                         VAL2(0xC71),                                                                               FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(0xC30),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0xC30),                                                                                // static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS : , static_SIGGRPS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_CCC_REG)                                              ,  BB(CCC,        _00001100), MASK2(0x1FE0)            , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL2(0x1240),                                                                              T(T_LPDDR3),                                                                               VAL2(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_CCC_REG)                                              ,  BB(CCC,        _00000010), MASK1(0xE0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x20),                                                                                 // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_CCC_REG)                                              ,  BB(CCC,        _00000011), MASK2(0x1FFF)            , AP(SET,       _____),                                                                                                                   VAL2(0x302),                                                                                // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),                                                                                 // non-ECC case force ODT OFF (SEL=1, VAL=0), non-ECC case force ODT OFF (SEL=1, VAL=0)
  xxxME1xx          , VAL2(ECCEN_BXT_P_POST_A0)   ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // ECC case let ODT be DYNAMIC (SEL=0, VAL=don't care)
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x2),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x1),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00000100), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_CCC_RXODTSEGCTL),                                                                 FT(F_1866,T_DDR3),                                                                         VAL2(DYN_CCC_RXODTSEGCTL_1),                                                               FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_CCC_RXODTSEGCTL_2),                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_CCC_RXODTSEGCTL_3),                                                               FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_CCC_RXODTSEGCTL_4),                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_CCC_RXODTSEGCTL_5),                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_CCC_RXODTSEGCTL_6),                                                                // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXODTCTL_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x20),                                                                                T(T_LPDDR3),                                                                               VAL1(0x10),                                                                                T(T_LPDDR4),                                                                               VAL1(0x10),                                                                                 // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXODTCTL_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTCTL_CCC_REG)                                                ,  BB(CCC,        _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_CCC_RXODTCTL),                                                                    FT(F_1866,T_DDR3),                                                                         VAL2(DYN_CCC_RXODTCTL_1),                                                                  FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_CCC_RXODTCTL_2),                                                                  FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_CCC_RXODTCTL_3),                                                                  FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_CCC_RXODTCTL_4),                                                                  FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_CCC_RXODTCTL_5),                                                                  FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_CCC_RXODTCTL_6),                                                                   // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RCVENCTL_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xC),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RCVENCTL_CCC_REG)                                                ,  BB(CCC,        _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_CCC_RCVENCTL),                                                                    FT(F_1866,T_DDR3),                                                                         VAL2(DYN_CCC_RCVENCTL_1),                                                                  FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_CCC_RCVENCTL_2),                                                                  FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_CCC_RCVENCTL_3),                                                                  FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_CCC_RCVENCTL_4),                                                                  FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_CCC_RCVENCTL_5),                                                                  FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_CCC_RCVENCTL_6),                                                                   // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x20),                                                                                T(T_LPDDR3),                                                                               VAL1(0x10),                                                                                T(T_LPDDR4),                                                                               VAL1(0x10),                                                                                 // static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x10),                                                                                T(T_LPDDR3),                                                                               VAL1(0x10),                                                                                T(T_LPDDR4),                                                                               VAL1(0x10),                                                                                 // Turn on DIFFAMP early when DYNAMIC
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xC)               , AP(SET,       _____),                                                                                                                   VAL1(0x4),                                                                                  // ECC diffamp OFF for non-ECC, ECC diffamp OFF for non-ECC
  xxxME1xx          , VAL2(ECCEN_BXT_P_POST_A0)   ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // ECC DYNAMIC diffamp for ECC
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // ECC diffamp OFF for non-ECC, ECC diffamp OFF for non-ECC
  xxxME1xx          , VAL2(ECCEN_BXT_P_POST_A0)   ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // ECC DYNAMIC diffamp for ECC
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0xFC)              , AP(SET,       __F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x74),                                                                                FT(F_1866,T_DDR3),                                                                         VAL1(0x74),                                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x30),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x30),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0x74),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x74),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x74),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_CCC_DIFFAMPCTL),                                                                  FT(F_1866,T_DDR3),                                                                         VAL2(DYN_CCC_DIFFAMPCTL_1),                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_CCC_DIFFAMPCTL_2),                                                                FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_3),                                                                FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_4),                                                                FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_5),                                                                FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_6),                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0x3)               , AP(SET,       __F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x1),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0x1),                                                                                 FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x2),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0x2),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x2),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x2),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x2),                                                                                  // static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00000010), MASK1(0x3F)              , AP(SET,       __F_T),                   4,   FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_DDR3),           VAL1(0x12),                                                                                FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR4),         VAL1(0x13),                                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0xA),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0xB),                                                                                  // Large window for DYNAMIC DIFFAMP
  xxxxE1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00000001)                           , AP(SET,       D_F_T),                   6,   FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_DDR3),           VAL2(DYN_CCC_DIFFAMPCTL_7),                                                                FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_8),                                                                FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_9),                                                                FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_10),                                                               FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_CCC_DIFFAMPCTL_11),                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_CCC_DIFFAMPCTL_12),                                                                // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL4(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL4(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL4(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(AFEMISC1_CCC_REG)                                                ,  BB(CCC,        _00001111), MASK4(0x77777770)        , AP(SET,       _____),                                                                                                                   VAL4(0x77771110),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CH0_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000110), MASK2(0x3FFC)            , AP(SET,       _____),                                                                                                                   VAL2(0x28),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CH0_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000010), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x3),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x3),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(CH0_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xFF),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(TXDLLREF2XCTL_CCC_REG)                                           ,  BB(CCC,        _00000111)                           , AP(SET,       __F__),                   5,   F(F_1333),                                                                                 VAL3(0x5E3F1F),                                                                            F(F_1600),                                                                                 VAL3(0x4E341A),                                                                            F(F_1866),                                                                                 VAL3(0x432D17),                                                                            F(F_2133),                                                                                 VAL3(0x3B2714),                                                                            F(F_2400),                                                                                 VAL3(0x2F1F0F),                                                                             // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXBL8PBDCTL_CCC_REG)                                             ,  BB(CCC,        _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXPBDBLCTL_CCC_REG)                                              ,  BB(CCC,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDCTL1_CCC_REG)                                               ,  BB(CCC,        _00000101), MASK2(0xC00F)            , AP(SET,       _____),                                                                                                                   VAL2(0xF),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDRK0CTL1_CCC_REG)                                            ,  BB(CCC,        _00000001), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x1F),                                                                                 // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDRK0CTL0_CCC_REG)                                            ,  BB(CCC,        _00000101), MASK2(0x1F1F)            , AP(SET,       _____),                                                                                                                   VAL2(0x1F1F),                                                                               // static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL1_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x1F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL0_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x1F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(OFFSETCNCLCTRL1_CCC_REG)                                         ,  BB(CCC,        _00000111)                           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_DIGREGS : PO_SAFE, static_DIGREGS : PO_SAFE, static_DIGREGS : PO_SAFE, static_DIGREGS : PO_SAFE, static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(OFFSETCNCLCTRL0_CCC_REG)                                         ,  BB(CCC,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL2_CCC_REG)                                                ,  BB(CCC,        _00000111), MASK3(0xFFFEFC)          , AP(SET,       _____),                                                                                                                   VAL3(0x14C10),                                                                              // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0x40)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x40),                                                                                T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_CCC_REG)                                                ,  BB(CCC,        _00001110), MASK3(0x3FFFF0)          , AP(SET,       _____),                                                                                                                   VAL3(0x31160),                                                                              // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_CCC_REG)                                                ,  BB(CCC,        _00000001), MASK1(0x80)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x80),                                                                                T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_CCC_REG)                                                ,  BB(CCC,        _00000001), MASK1(0x7F)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_A0)              ,                VAL1(CTLECTL0_CCC_REG)                                                ,  BB(CCC,        _00001100)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(CTLECTL0_CCC_REG)                                                ,  BB(CCC,        _00001100)                           , AP(SET,       ____T),                   2,   T(T_DDR3),                                                                                 VAL2(0xAAAA),                                                                              T(T_LPDDR3|T_LPDDR4),                                                                      VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(CTLECTL0_CCC_REG)                                                ,  BB(CCC,        _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TCOCTL_DQCC_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x9F1F9F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x9F1F9F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TCOCTL_CCC_REG)                                                  ,  BB(CCC,        _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x3F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP6CTL_CCC_REG)                                         ,  BB(CCC,        _00000111), MASK3(0x3FC78F)          , AP(SET,       __F_T),                   9,   FT(F_1600,T_LPDDR4),                                                                       VAL3(0x88000),                                                                             FT(F_2133,T_LPDDR4),                                                                       VAL3(0x88000),                                                                             FT(F_2400,T_LPDDR4),                                                                       VAL3(0x88000),                                                                             FT(F_2666,T_LPDDR4),                                                                       VAL3(0x44000),                                                                             FT(F_3200,T_LPDDR4),                                                                       VAL3(0x44000),                                                                             FT(F_1333|F_1600,T_DDR3),                                                                  VAL3(0x88081),                                                                             FT(F_1866,T_DDR3),                                                                         VAL3(0x88081),                                                                             FT(F_1333|F_1600,T_LPDDR3),                                                                VAL3(0x88000),                                                                             FT(F_1866,T_LPDDR3),                                                                       VAL3(0x88000),                                                                              // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_FIFOPTRCTL_CCC_REG)                                          ,  BB(CCC,        _00000100), MASK1(0x1E)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_FIFOPTRCTL_CCC_REG)                                          ,  BB(CCC,        _00000010), MASK1(0xE0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x20),                                                                                 // static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_FIFOPTRCTL_CCC_REG)                                          ,  BB(CCC,        _00000011), MASK2(0x1F0F)            , AP(SET,       _____),                                                                                                                   VAL2(0x300),                                                                                // static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_RCVENCTL_CCC_REG)                                            ,  BB(CCC,        _00001000), MASK1(0x8)               , AP(SET,       _____),                                                                                                                   VAL1(0x8),                                                                                  // static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(ECC_WKPUPPDNCTL_CCC_REG)                                         ,  BB(CCC,        _00001100), MASK2(0x7F7F)            , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000110), MASK2(0x3FFC)            , AP(SET,       _____),                                                                                                                   VAL2(0x28),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000010), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x3),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x3),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxxx2xx                                        ,                VAL2(CH1_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xFF),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(ECC_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000110), MASK2(0x3FFC)            , AP(SET,       _____),                                                                                                                   VAL2(0x28),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(ECC_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000010), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x3),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x3),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxxx2xx                                        ,                VAL2(ECC_AFEMISC0_CCC_REG)                                            ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xFF),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CH1_TCOCTL_DQCC_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x9F1F)            , AP(SET,       _____),                                                                                                                   VAL2(0x9F1F),                                                                               // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CCC0_TCOCTL_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x3F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(CCC1_TCOCTL_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x3F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(ECC_TXPBDCTL1_CCC_REG)                                           ,  BB(CCC,        _00000101), MASK2(0x4003)            , AP(SET,       _____),                                                                                                                   VAL2(0x3),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(ECC_AFEMISC1_CCC_REG)                                            ,  BB(CCC,        _00000111), MASK3(0x771DC)           , AP(SET,       _____),                                                                                                                   VAL3(0x77044),                                                                              // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(FIFOPTRCTL_DQ_REG)                                               ,  BB(DQ,         _00001100)                           , AP(SET,       D___T),                   3,   T(T_DDR3),                                                                                 VAL2(DYN_DQ_FIFOPTRCTL),                                                                   T(T_LPDDR3),                                                                               VAL2(DYN_DQ_FIFOPTRCTL_1),                                                                 T(T_LPDDR4),                                                                               VAL2(DYN_DQ_FIFOPTRCTL_2),                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_DQ_REG)                                               ,  BB(DQ,         _00000100), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_DQ_REG)                                               ,  BB(DQ,         _00000010), MASK1(0xE0)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x20),                                                                                 // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(FIFOPTRCTL_DQ_REG)                                               ,  BB(DQ,         _00000011), MASK2(0x1FFF)            , AP(SET,       _____),                                                                                                                   VAL2(0x322),                                                                                // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_BL13_DQ_REG)                                         ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_BL13_DQ_REG)                                         ,  BB(DQ,         _00000100), MASK1(0x40)              , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x40),                                                                                 // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_BL13_DQ_REG)                                         ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_RXODTSEGCTL_BL13),                                                             FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RXODTSEGCTL_BL13_1),                                                           FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_RXODTSEGCTL_BL13_2),                                                           FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL13_3),                                                           FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL13_4),                                                           FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL13_5),                                                           FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL13_6),                                                            // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00000100), MASK1(0x40)              , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x40),                                                                                 // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_RXODTSEGCTL_BL02),                                                             FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RXODTSEGCTL_BL02_1),                                                           FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_RXODTSEGCTL_BL02_2),                                                           FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL02_3),                                                           FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL02_4),                                                           FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL02_5),                                                           FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTSEGCTL_BL02_6),                                                            // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_RXODTCTL_BL13),                                                                FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RXODTCTL_BL13_1),                                                              FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_RXODTCTL_BL13_2),                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RXODTCTL_BL13_3),                                                              FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTCTL_BL13_4),                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTCTL_BL13_5),                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTCTL_BL13_6),                                                               // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_RXODTCTL_DQ),                                                                  FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RXODTCTL_DQ_1),                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_RXODTCTL_DQ_2),                                                                FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RXODTCTL_DQ_3),                                                                FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTCTL_DQ_4),                                                                FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTCTL_DQ_5),                                                                FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_RXODTCTL_DQ_6),                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RCVENCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x18),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RCVENCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_RCVENCTL_BL13),                                                                FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RCVENCTL_BL13_1),                                                              FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_RCVENCTL_BL13_2),                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RCVENCTL_BL13_3),                                                              FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_RCVENCTL_BL13_4),                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_RCVENCTL_BL13_5),                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_RCVENCTL_BL13_6),                                                               // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RCVENCTL_BL02_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x18),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RCVENCTL_BL02_DQ_REG)                                            ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_RCVENCTL_BL02),                                                                FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_RCVENCTL_BL02_1),                                                              FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_RCVENCTL_BL02_2),                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_RCVENCTL_BL02_3),                                                              FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_RCVENCTL_BL02_4),                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_RCVENCTL_BL02_5),                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_RCVENCTL_BL02_6),                                                               // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x1A),                                                                                 // Turn on DIFFAMP early when DYNAMIC, For LP3 keep DIFFAMP OVERRIDE ON for now (val=1), Keep LP3 in DIFAMP OVERRIDE mode for now, others Dynamic, For LP3 KEEP DIFFAMP OVERRIDE ON for now (val=1), Keep LP3 in DIFAMP OVERRIDE mode for now, others Dynamic
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00000100), MASK1(0xFC)              , AP(SET,       __F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x74),                                                                                FT(F_1866,T_DDR3),                                                                         VAL1(0x74),                                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x30),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x30),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0x74),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x74),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x74),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_DIFFAMPCTL_BL13),                                                              FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_DIFFAMPCTL_BL13_1),                                                            FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_DIFFAMPCTL_BL13_2),                                                            FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_3),                                                            FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_4),                                                            FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_5),                                                            FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_6),                                                             // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       __F_T),                   6,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x1),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0x1),                                                                                 FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR3),         VAL1(0x3),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x2),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x2),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x2),                                                                                  // static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x3F)              , AP(SET,       __F_T),                   3,   FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_DDR3),           VAL1(0x12),                                                                                FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR4),         VAL1(0x13),                                                                                FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR3),         VAL1(0xF),                                                                                  // Large window for DYNAMIC DIFFAMP
  xxxxE1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00000001)                           , AP(SET,       D_F_T),                   5,   FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_DDR3),           VAL2(DYN_DQ_DIFFAMPCTL_BL13_7),                                                            FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_8),                                                            FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_9),                                                            FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL13_10),                                                           FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR3),         VAL2(DYN_DQ_DIFFAMPCTL_BL13_11),                                                            // Turn on DIFFAMP early when DYNAMIC
  xxxxE1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x1A),                                                                                 // Turn on DIFFAMP early when DYNAMIC, For LP3 keep DIFFAMP OVERRIDE ON for now (val=1), Keep LP3 in DIFAMP OVERRIDE mode for now, others Dynamic, For LP3 KEEP DIFFAMP OVERRIDE ON for now (val=1), Keep LP3 in DIFAMP OVERRIDE mode for now, others Dynamic
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00000100), MASK1(0xFC)              , AP(SET,       __F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x74),                                                                                FT(F_1866,T_DDR3),                                                                         VAL1(0x74),                                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x30),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x30),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0x74),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x74),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x74),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE1xx          , VAL2(BXT_P_A0)              ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00000111)                           , AP(SET,       D_F_T),                   7,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(DYN_DQ_DIFFAMPCTL_BL02),                                                              FT(F_1866,T_DDR3),                                                                         VAL2(DYN_DQ_DIFFAMPCTL_BL02_1),                                                            FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(DYN_DQ_DIFFAMPCTL_BL02_2),                                                            FT(F_1866,T_LPDDR3),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_3),                                                            FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_4),                                                            FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_5),                                                            FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_6),                                                             // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       __F_T),                   6,   FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x1),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0x1),                                                                                 FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR3),         VAL1(0x3),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x2),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x2),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x2),                                                                                  // static_DIGREGS :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x3F)              , AP(SET,       __F_T),                   3,   FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_DDR3),           VAL1(0x12),                                                                                FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR4),         VAL1(0x13),                                                                                FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR3),         VAL1(0xF),                                                                                  // Large window for DYNAMIC DIFFAMP
  xxxxE1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00000001)                           , AP(SET,       D_F_T),                   5,   FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_DDR3),           VAL2(DYN_DQ_DIFFAMPCTL_BL02_7),                                                            FT(F_2400,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_8),                                                            FT(F_2133,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_9),                                                            FT(F_1600,T_LPDDR4),                                                                       VAL2(DYN_DQ_DIFFAMPCTL_BL02_10),                                                           FT(F_800|F_1066|F_1333|F_1600|F_1866|F_2133|F_2400|F_2666|F_3200|F_2933,T_LPDDR3),         VAL2(DYN_DQ_DIFFAMPCTL_BL02_11),                                                            // Turn on DIFFAMP early when DYNAMIC
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL4(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL4(0x7F7F7F7F),                                                                          T(T_LPDDR4),                                                                               VAL4(0x7F7F7F7F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(AFEMISC1_DQ_REG)                                                 ,  BB(DQ,         _00001111), MASK4(0x7777777F)        , AP(SET,       _____),                                                                                                                   VAL4(0x7777111F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00001100)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxNMx1xx, xxxxxxIx                              , _I(  0)      , VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS :
  xxNMx1xx, xxxxxxIx                              , _I(  1)      , VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0xA0),                                                                                 // static_DIGREGS :
  xxNMx1xx, xxxxxxIx                              , _I(  2)      , VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0xA0),                                                                                 // static_DIGREGS :
  xxNMx1xx, xxxxxxIx                              , _I(  3)      , VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                  // static_DIGREGS :
  xxNMx1xx, xxxxxCIx                              , CI(  2,   0), VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL1(0xA0),                                                                                 // static_DIGREGS :
  xxNMx1xx, xxxxxCIx                              , CI(  2,   1), VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL1(0x0),                                                                                  // static_DIGREGS :
  xxNMx1xx, xxxxxCIx                              , CI(  3,   0), VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL1(0xA0),                                                                                 // static_DIGREGS :
  xxNMx1xx, xxxxxCIx                              , CI(  3,   1), VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL1(0x0),                                                                                  // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0xF),                                                                                 T(T_LPDDR3),                                                                               VAL1(0xF),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000001), MASK1(0xFC)              , AP(SET,       _____),                                                                                                                   VAL1(0xFC),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(AFEMISC0_DQ_REG)                                                 ,  BB(DQ,         _00000001), MASK1(0x3)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x3),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x3),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(TXDLLREF2XCTL_DQ_REG)                                            ,  BB(DQ,         _00000111)                           , AP(SET,       __F__),                   5,   F(F_1333),                                                                                 VAL3(0x5E3F1F),                                                                            F(F_1600),                                                                                 VAL3(0x4E341A),                                                                            F(F_1866),                                                                                 VAL3(0x432D17),                                                                            F(F_2133),                                                                                 VAL3(0x3B2714),                                                                            F(F_2400),                                                                                 VAL3(0x2F1F0F),                                                                             // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXBL8PBDCTL1_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),                                                                                  // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXPBDBLCTL1_DQ_REG)                                              ,  BB(DQ,         _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xFFFFFFFF),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXBL8PBDCTL0_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),                                                                                  // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(RXPBDBLCTL0_DQ_REG)                                              ,  BB(DQ,         _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xFFFFFFFF),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDCTL1_DQ_REG)                                                ,  BB(DQ,         _00000101), MASK2(0xC00F)            , AP(SET,       _____),                                                                                                                   VAL2(0xF),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL5_DQ_REG)                                              ,  BB(DQ,         _00000111), MASK3(0x1F1F1F)          , AP(SET,       _____),                                                                                                                   VAL3(0x1F1F1F),                                                                             // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL4_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x1F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL3_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x1F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL2_DQ_REG)                                              ,  BB(DQ,         _00000111), MASK3(0x1F1F1F)          , AP(SET,       _____),                                                                                                                   VAL3(0x1F1F1F),                                                                             // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL1_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x1F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(TXPBDBLCTL0_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x1F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x1F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(OFFSETCNCLCTRL3_DQ_REG)                                          ,  BB(DQ,         _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : PO_SAFE, static_DIGREGS : PO_SAFE, static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(OFFSETCNCLCTRL2_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(OFFSETCNCLCTRL1_DQ_REG)                                          ,  BB(DQ,         _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : PO_SAFE, static_DIGREGS : PO_SAFE, static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(OFFSETCNCLCTRL0_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL4_DQ_REG)                                                 ,  BB(DQ,         _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL3_DQ_REG)                                                 ,  BB(DQ,         _00000110), MASK2(0xFFE)             , AP(SET,       _____),                                                                                                                   VAL2(0x430),                                                                                // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL3_DQ_REG)                                                 ,  BB(DQ,         _00000011), MASK2(0x180)             , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_DDR3),                                                                        VAL2(0x80),                                                                                T(T_LPDDR4),                                                                               VAL2(0x100),                                                                                // static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL3_DQ_REG)                                                 ,  BB(DQ,         _00000001), MASK1(0x7F)              , AP(SET,       _____),                                                                                                                   VAL1(0x50),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(CTLECTL2_DQ_REG)                                                 ,  BB(DQ,         _00001100)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(CTLECTL2_DQ_REG)                                                 ,  BB(DQ,         _00000011)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_DDR3),                                                                        VAL2(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL2(0xAAAA),                                                                               // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0xFC)              , AP(SET,       _____),                                                                                                                   VAL1(0x60),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(CTLECTL1_DQ_REG)                                                 ,  BB(DQ,         _00000010), MASK1(0x3)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_DDR3),                                                                        VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x2),                                                                                  // static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(CTLECTL1_DQ_REG)                                                 ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xD0),                                                                                 // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE2xx          , VAL2(BXT_P_A0)              ,                VAL2(CTLECTL0_DQ_REG)                                                 ,  BB(DQ,         _00001100)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxE2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(CTLECTL0_DQ_REG)                                                 ,  BB(DQ,         _00001100)                           , AP(SET,       ____T),                   2,   T(T_DDR3),                                                                                 VAL2(0xAAAA),                                                                              T(T_LPDDR3|T_LPDDR4),                                                                      VAL2(0x0),                                                                                  // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx2xx                                        ,                VAL2(CTLECTL0_DQ_REG)                                                 ,  BB(DQ,         _00000011)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_DDR3),                                                                        VAL2(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL2(0xAAAA),                                                                               // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(TCOCTL_DQCC_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x9F1F9F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x9F1F9F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(TCOCTL_DQ_DQ_REG)                                                ,  BB(DQ,         _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x3F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxMx2xx                                        ,                VAL2(TCOCTL_CC_DQ_REG)                                                ,  BB(DQ,         _00001111), MASK4(0x3F1F1F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x3F1F1F1F),                                                                           // static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00001000)                           , AP(SET,       D_F_T),                   6,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL2(DYN_DQDPLVUG_PTCTL0),                                                                 FT(F_1333,T_DDR3|T_LPDDR3),                                                                VAL2(DYN_DQDPLVUG_PTCTL0_1),                                                               FT(F_1600,T_DDR3|T_LPDDR3),                                                                VAL2(DYN_DQDPLVUG_PTCTL0_2),                                                               FT(F_1866,T_DDR3|T_LPDDR3),                                                                VAL2(DYN_DQDPLVUG_PTCTL0_3),                                                               FT(F_1066|F_1600|F_2133|F_2400|F_2666|F_2933,T_LPDDR4),                                    VAL2(DYN_DQDPLVUG_PTCTL0_4),                                                               FT(F_3200,T_LPDDR4),                                                                       VAL2(DYN_DQDPLVUG_PTCTL0_5),                                                                // static_PTCMNREGS :
  xxxMx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00000111), MASK3(0xFFFFC0)          , AP(SET,       _____),                                                                                                                   VAL3(0x40),                                                                                 // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxMx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00000001), MASK1(0x38)              , AP(SET,       __F_T),                   4,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL1(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL1(0x0),                                                                                 FT(F_1066|F_1600|F_2133|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x0),                                                                                 FT(F_2400|F_2666,T_LPDDR4),                                                                VAL1(0x0),                                                                                  // static_PTCMNREGS :
  xxxMx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL1_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       __F_T),                   7,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL4(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL4(0x0),                                                                                 FT(F_1066,T_LPDDR4),                                                                       VAL4(0x0),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL4(0x680D1A27),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x4E09131D),                                                                          FT(F_2400|F_2666|F_2933,T_LPDDR4),                                                         VAL4(0x3E070F17),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x34060D13),                                                                           // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL2_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       __F_T),                   7,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL4(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL4(0x0),                                                                                 FT(F_1066,T_LPDDR4),                                                                       VAL4(0x0),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL4(0x34414E5B),                                                                          FT(F_2133,T_LPDDR4),                                                                       VAL4(0x27303A44),                                                                          FT(F_2400|F_2666|F_2933,T_LPDDR4),                                                         VAL4(0x1F272E36),                                                                          FT(F_3200,T_LPDDR4),                                                                       VAL4(0x1A20272D),                                                                           // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL3_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00001000)                           , AP(SET,       __F_T),                   4,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL1(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL1(0x0),                                                                                 FT(F_1066,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                    VAL1(0xF5),                                                                                 // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxMx1xx                                        ,                VAL1(DBREGIONCTL3_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00000100), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_PTCMNREGS : , static_PTCMNREGS :
  xxxMx1xx                                        ,                VAL1(DBREGIONCTL3_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00000110), MASK2(0xFFF)             , AP(SET,       __F_T),                   4,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL2(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL2(0x0),                                                                                 FT(F_1066,T_LPDDR4),                                                                       VAL2(0x0),                                                                                 FT(F_1600|F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                    VAL2(0xA55),                                                                                // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL3_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS : , static_PTCMNREGS :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CTL0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x67BFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x3800800),                                                                            // static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CTL0_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111), MASK4(0x7BFFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x3800800),                                                                            // static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl : , static_lrcompctl :
  xxxMx2xx                                        ,                VAL2(DIGCTL1663_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_rpdext :
  xxNME2xx, xxxxxCxx, VAL2(SLICE_0_MASTER)        , C_(  0)      , VAL2(DIGCTL1663_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_rpdext :
  xxNME2xx, xxxxxCxx, VAL2(SLICE_1_MASTER)        , C_(  1)      , VAL2(DIGCTL1663_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_rpdext :
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP5CTL_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP4CTL_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP3CTL_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP2CTL_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP1CTL_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP0CTL_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP3CTL_CCC_REG)                                         ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP2CTL_CCC_REG)                                         ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP0CTL_CCC_REG)                                         ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP3CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP2CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP0CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLSIGGRP2CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLSIGGRP0CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp3p75_seq
  //
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000001), MASK1(0x10)              , AP(POLL,      _____),                                                                                                                   VAL1(0x10),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp4m_seq
  //
  xxxMx1xx                                        ,                VAL1(RXDLLCTL_DQBLDM_CCC_REG)                                         ,  BB(CCC,        _00001100), MASK2(0x1F35)            , AP(SET,       _____),                                                                                                                   VAL2(0x1435),                                                                               // static_RXEN_m : , static_RXEN_m : , static_RXEN_m : , static_RXEN_m : , static_RXEN_m :
  xxxMx1xx                                        ,                VAL1(RXDLLCTL_CCBLDM_CCC_REG)                                         ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_RXEN_m : , static_RXEN_m :
  xxxMx2xx                                        ,                VAL2(CH1_RXDLLCTL_DQBLDM_CCC_REG)                                     ,  BB(CCC,        _00000100), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // static_RXEN_m :
  xxxMx2xx                                        ,                VAL2(CH1_RXDLLCTL_CCBLDM_CCC_REG)                                     ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_RXEN_m :
  xxxMx1xx                                        ,                VAL1(RXDLLCTL_DQBLDM_DQ_REG)                                          ,  BB(DQ,         _00001100), MASK2(0x1F35)            , AP(SET,       _____),                                                                                                                   VAL2(0x1435),                                                                               // static_RXEN_m : , static_RXEN_m : , static_RXEN_m : , static_RXEN_m : , static_RXEN_m :
  xxxMx1xx                                        ,                VAL1(RXDLLCTL_CCBLDM_DQ_REG)                                          ,  BB(DQ,         _00000101), MASK2(0x501)             , AP(SET,       _____),                                                                                                                   VAL2(0x501),                                                                                // static_RXEN_m : , static_RXEN_m : , static_RXEN_m :
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL2_DPIC_REG)                                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  ASSIGNDONE,
  //
  // modmem_bxtp_ldo_offsetcomp_seq
  //
  xxxMx1xx                                        ,                VAL1(TXSAOFFSET_LDO_REG)                                              ,  BB(LDO,        _00001000), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp2p5_seq
  //
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx1xx                                        ,                VAL1(LDOCLKVAL_DPIC_REG)                                              ,  BB(DPIC,       _00000001), MASK1(0xF0)              , AP(SET,       __F__),                   5,   F(F_1333),                                                                                 VAL1(0x50),                                                                                F(F_1600),                                                                                 VAL1(0x60),                                                                                F(F_1866),                                                                                 VAL1(0x70),                                                                                F(F_2133),                                                                                 VAL1(0x80),                                                                                F(F_2400),                                                                                 VAL1(0xA0),                                                                                 // static_LDOCLKVAL :
  xxxMx1xx                                        ,                VAL1(LDOCLKVAL_DPIC_REG)                                              ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       __F__),                   8,   F(F_1066),                                                                                 VAL1(0x1),                                                                                 F(F_1333),                                                                                 VAL1(0x1),                                                                                 F(F_1600),                                                                                 VAL1(0x1),                                                                                 F(F_1866),                                                                                 VAL1(0x1),                                                                                 F(F_2133),                                                                                 VAL1(0x1),                                                                                 F(F_2400|F_2666),                                                                          VAL1(0x1),                                                                                 F(F_2933),                                                                                 VAL1(0x1),                                                                                 F(F_3200),                                                                                 VAL1(0x1),                                                                                  // static_LDOCLKVAL :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x0000000A),
  xxxMx1xx                                        ,                VAL1(LDOCTL1_DPIC_REG)                                                ,  BB(DPIC,       _00000011), MASK2(0x17F)             , AP(SET,       _____),                                                                                                                   VAL2(0x5F),                                                                                 // static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x0000000A),
  xxxMx1xx                                        ,                VAL1(LDOCTL1_DQDPIC_REG)                                              ,  BB(DQDPIC,     _00000001), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x1F),                                                                                 // static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG : , static_LDOREG :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000258),
  xxxxx1xx                                        ,                VAL1(LDORSTCTLX_DPIC_REG)                                             ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x1),
  ASSIGNDONE,
  //
  // modmem_bxtp_ldo_offsetcomp_poll_seq
  //
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000258),
  xxxMx1xx                                        ,                VAL1(TXSAOFFSET_LDO_REG)                                              ,  BB(LDO,        _00001000), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp4_seq
  //
  xxxMx1xx                                        ,                VAL1(LDOONCTL_DPIC_REG)                                               ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_LDOONREG :
  xxxxx1xx                                        ,                VAL1(VREFCTL2_CCC_REG)                                                ,  BB(CCC,        _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x8),                                                                                  // static_VREFIOBUFACT_m :
  xxxxx1xx                                        ,                VAL1(VREFCTL2_CCC_REG)                                                ,  BB(CCC,        _00000100)                           , AP(SET,       __F_T),                   2,   FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x25),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x1D),                                                                                 // static_VREFIOBUFACT_m :
  xxxxx1xx                                        ,                VAL1(VREFCTL2_CCC_REG)                                                ,  BB(CCC,        _00000010)                           , AP(SET,       _____),                                                                                                                   VAL1(0x8),                                                                                  // static_VREFIOBUFACT_m :
  xxxxx1xx                                        ,                VAL1(VREFCTL2_CCC_REG)                                                ,  BB(CCC,        _00000001)                           , AP(SET,       __F_T),                   2,   FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x25),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x1F),                                                                                 // static_VREFIOBUFACT_m :
  xxxxx1xx                                        ,                VAL1(VREFCTL0_CCC_REG)                                                ,  BB(CCC,        _00001000)                           , AP(SET,       _____),                                                                                                                   VAL1(0x1F),                                                                                 // static_VREFIOBUFACT_m :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(VREFCTL0_CCC_REG)                                                ,  BB(CCC,        _00000100), MASK1(0x80)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x80),                                                                                 // static_VREFIOBUFACT_m :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(VREFCTL0_CCC_REG)                                                ,  BB(CCC,        _00000100), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),                                                                                 // static_VREFIOBUFACT_m :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(VREFCTL0_CCC_REG)                                                ,  BB(CCC,        _00000100), MASK1(0x20)              , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x20),                                                                                 // static_VREFIOBUFACT_m :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(VREFCTL0_CCC_REG)                                                ,  BB(CCC,        _00000100), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // static_VREFIOBUFACT_m :
  xxxME1xx          , VAL2(BXT_P_POST_A0)         ,                VAL1(AFEBONUS_CCC_REG)                                                ,  BB(CCC,        _00000001), MASK1(0xF)               , AP(SET,       ____T),                   1,   T(T_LPDDR3),                                                                               VAL1(0x8),                                                                                  // static_VREFIOBUFACT_m :
  xxxME1xx          , VAL2(BXT_P_A0)              ,                VAL1(AFEBONUS_CCC_REG)                                                ,  BB(CCC,        _00000001), MASK1(0xF)               , AP(SET,       ____T),                   1,   T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                  // static_VREFIOBUFACT_m :
  xxxMx1xx                                        ,                VAL1(VREFCTL0_CCC_REG)                                                ,  BB(CCC,        _00000111), MASK3(0xDFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x80808),                                                                              // static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m :
  xxxMx1xx                                        ,                VAL1(VREFCTL0_DQ_REG)                                                 ,  BB(DQ,         _00001100), MASK2(0xFFF0)            , AP(SET,       _____),                                                                                                                   VAL2(0x1FA0),                                                                               // static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m :
  xxxMx1xx                                        ,                VAL1(VREFCTL0_DQ_REG)                                                 ,  BB(DQ,         _00000100), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_VREFIOBUFACT_m :
  xxxxx1xx                                        ,                VAL1(VREFCTL0_DQ_REG)                                                 ,  BB(DQ,         _00000011)                           , AP(SET,       __F_T),                   3,   FT(F_1333|F_1600|F_1866,T_DDR3|T_LPDDR3),                                                  VAL2(0x1F1F),                                                                              FT(F_1600,T_LPDDR4),                                                                       VAL2(0x1010),                                                                              FT(F_2133|F_2400,T_LPDDR4),                                                                VAL2(0xA0A),                                                                                // static_VREFIOBUFACT_m : , static_VREFIOBUFACT_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000FA),
  xxxMx1xx                                        ,                VAL1(VREFCTL1_CCC_REG)                                                ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x1),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_VREFEN_m :
  xxxMx1xx                                        ,                VAL1(VREFCTL1_DQ_REG)                                                 ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x1),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_VREFEN_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000003E8),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp4p5_seq
  //
  xxxMx1xx                                        ,                VAL1(TXDLLCTL_CCC_REG)                                                ,  BB(CCC,        _00000111), MASK3(0x18F04)           , AP(SET,       _____),                                                                                                                   VAL3(0x18F04),                                                                              // static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL :
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLCTL_CCC_REG)                                            ,  BB(CCC,        _00000011), MASK2(0xF04)             , AP(SET,       _____),                                                                                                                   VAL2(0xF04),                                                                                // static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL :
  xxxMx2xx                                        ,                VAL2(ECC_TXDLLCTL_CCC_REG)                                            ,  BB(CCC,        _00000111), MASK3(0x10704)           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL3(0x10704),                                                                             T(T_LPDDR3),                                                                               VAL3(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL3(0x0),                                                                                  // static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL :
  xxxMx1xx                                        ,                VAL1(TXDLLCTL_DQ_REG)                                                 ,  BB(DQ,         _00000111), MASK3(0x13F0E)           , AP(SET,       _____),                                                                                                                   VAL3(0x13F0E),                                                                              // static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL : , static_TXDLLCTL :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_COMPOVR : , static_COMPOVR : , static_COMPOVR : , static_COMPOVR :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_COMPOVR : , static_COMPOVR : , static_COMPOVR : , static_COMPOVR :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_COMPOVR : , static_COMPOVR : , static_COMPOVR : , static_COMPOVR :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111), MASK4(0x7F7F7F7F)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // static_COMPOVR : , static_COMPOVR : , static_COMPOVR : , static_COMPOVR :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5m_seq
  //
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CFG1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x5010A0E),                                                                            // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CFG2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x707075),                                                                             // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CFG3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010), MASK1(0xF)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x5),                                                                                 T(T_LPDDR3),                                                                               VAL1(0xF),                                                                                 T(T_LPDDR4),                                                                               VAL1(0xF),                                                                                  // static_3_m :
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CFG3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x3F),                                                                                 // static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x3FC0FF)          , AP(SET,       _____),                                                                                                                   VAL3(0x8000),                                                                               // static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CTL1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0xFC0),                                                                                // static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMPOVR_DPLVUG_REG)                                    ,  BB(DPLVUG,     _00001111), MASK4(0xFFF1FFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0xFF),                                                                                 // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CTL2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x7FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x1111),                                                                               // static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CFG2_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x707075),                                                                             // static_3_m : , static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR0_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000111), MASK3(0x3FC0FF)          , AP(SET,       _____),                                                                                                                   VAL3(0x8000),                                                                               // static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_CTL1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0xFC0),                                                                                // static_3_m : , static_3_m : , static_3_m :
  xxxMx2xx                                        ,                VAL2(DPIC_LRCOMP_CTL2_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000111), MASK3(0x7FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x1111),                                                                               // static_3_m : , static_3_m : , static_3_m : , static_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000), MASK1(0xC0)              , AP(SET,       ____T),                   2,   T(T_LPDDR4),                                                                               VAL1(0xC0),                                                                                T(T_LPDDR3|T_DDR3),                                                                        VAL1(0xC0),                                                                                 // static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000), MASK1(0x30)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001100), MASK2(0xF80)             , AP(SET,       __F_T),                   8,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x280),                                                                               FT(F_1866,T_LPDDR4),                                                                       VAL2(0x200),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0x380),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0x300),                                                                               FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x280),                                                                               FT(F_1866,T_DDR3),                                                                         VAL2(0x200),                                                                               FT(F_1333|F_1600,T_LPDDR3),                                                                VAL2(0x280),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0x200),                                                                                // static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x7FFFF0)          , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x8)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x8),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_0_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                                                   VAL1(0x4),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7C)              , AP(SET,       __F_T),                   8,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x14),                                                                                FT(F_1866,T_LPDDR4),                                                                       VAL1(0x10),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x1C),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x18),                                                                                FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x14),                                                                                FT(F_1866,T_DDR3),                                                                         VAL1(0x10),                                                                                FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x10),                                                                                 // static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x3FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7C)              , AP(SET,       __F_T),                   8,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x14),                                                                                FT(F_1866,T_LPDDR4),                                                                       VAL1(0x10),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x1C),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x18),                                                                                FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0xC),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0xC),                                                                                 FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x10),                                                                                 // static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x3FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7C)              , AP(SET,       __F_T),                   8,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x14),                                                                                FT(F_1866,T_LPDDR4),                                                                       VAL1(0x10),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x1C),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x18),                                                                                FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0xC),                                                                                 FT(F_1866,T_DDR3),                                                                         VAL1(0xC),                                                                                 FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0x10),                                                                                 // static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x3FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_4_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7C)              , AP(SET,       __F_T),                   8,   FT(F_1600,T_LPDDR4),                                                                       VAL1(0x14),                                                                                FT(F_1866,T_LPDDR4),                                                                       VAL1(0x10),                                                                                FT(F_2133,T_LPDDR4),                                                                       VAL1(0x1C),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x18),                                                                                FT(F_1333|F_1600,T_DDR3),                                                                  VAL1(0x10),                                                                                FT(F_1866,T_DDR3),                                                                         VAL1(0xC),                                                                                 FT(F_1333|F_1600,T_LPDDR3),                                                                VAL1(0x10),                                                                                FT(F_1866,T_LPDDR3),                                                                       VAL1(0xC),                                                                                  // static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_4_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000111), MASK3(0x3FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(CH1_DPIC_TXDLYCOMP_0_DPLVUG_REG)                                 ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(CH1_DPIC_TXDLYCOMP_1_DPLVUG_REG)                                 ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx1xx                                        ,                VAL1(CH1_DPIC_TXDLYCOMP_2_DPLVUG_REG)                                 ,  BB(DPLVUG,     _00000111), MASK3(0x1FFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),                                                                                  // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx2xx                                        ,                VAL2(DPIC_TXDLYCOMP_0_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111), MASK4(0x3FFFFFF6)        , AP(SET,       _____),                                                                                                                   VAL4(0x3000004),                                                                            // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  xxxMx2xx                                        ,                VAL2(DPIC_TXDLYCOMP_1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000111), MASK3(0x7FFFFF)          , AP(SET,       _____),                                                                                                                   VAL3(0x180000),                                                                             // static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m : , static_lcomp_3_m :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5_seq
  //
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_CFG1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0x7FFFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x5010A0E),                                                                            // static_4 : , static_4 : , static_4 : , static_4 : , static_4 :
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_CFG2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111), MASK4(0xFFFFFF3)         , AP(SET,       _____),                                                                                                                   VAL4(0xE0E0E1),                                                                             // static_4 : , static_4 : , static_4 : , static_4 :
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_CFG3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_GRCOMP_CFG3),                                                          // static_4 : , static_4 :
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00001111)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL4(0x25211C1C),                                                                          T(T_LPDDR3),                                                                               VAL4(0x1C211C1C),                                                                          T(T_LPDDR4),                                                                               VAL4(0x20212020),                                                                           // static_4 : , static_4 : , static_4 : , static_4 :
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000010)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x1C),                                                                                T(T_LPDDR3),                                                                               VAL1(0x1C),                                                                                T(T_LPDDR4),                                                                               VAL1(0x20),                                                                                 // static_4 :
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x18),                                                                                 // static_4 :
  xxxMx2xx                                        ,                VAL2(DPIC_GRCOMP_CTL_DPIC_REG)                                        ,  BB(DPIC,       _00001111), MASK4(0x7FFFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0xFA01),                                                                               // static_gcomp_4 : , static_gcomp_4 : , static_gcomp_4 :
  xxxMx2xx                                        ,                VAL2(DPIC_GRCOMP_CTL_DQDPIC_REG)                                      ,  BB(DQDPIC,     _00001100), MASK2(0x7E0)             , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_gcomp_4 :
  xxxMx2xx                                        ,                VAL2(DPIC_GRCOMP_CTL_DQDPIC_REG)                                      ,  BB(DQDPIC,     _00000111), MASK3(0x1FFFFE)          , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL3(0xFA00),                                                                              T(T_LPDDR3),                                                                               VAL3(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL3(0x0),                                                                                  // static_gcomp_4 :
  xxxMx2xx                                        ,                VAL2(DPIC_GRCOMP_CTL_DQDPIC_REG)                                      ,  BB(DQDPIC,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_gcomp_4 :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p25_seq
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL_DQ_REG)                                         ,  BB(DQ,         _00001100), MASK2(0x801F)            , AP(SET,       _____),                                                                                                                   VAL2(0x17),                                                                                 // static_5 : , static_5 :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL_DQ_REG)                                         ,  BB(DQ,         _00000011), MASK2(0x1F1F)            , AP(SET,       __F_T),                   6,   FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL2(0x120E),                                                                              FT(F_1600,T_LPDDR3|T_DDR3),                                                                VAL2(0xF0C),                                                                               FT(F_1600,T_LPDDR4),                                                                       VAL2(0xF0D),                                                                               FT(F_1866,T_LPDDR3|T_DDR3),                                                                VAL2(0xD0A),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0xB0A),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0xA09),                                                                                // static_5 : , static_5 :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p5m_seq
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_LPDDRTYPE_DQ_REG)                                        ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_LOCKCTL_DQ_REG)                                          ,  BB(DQ,         _00001001), MASK2(0xC00F)            , AP(SET,       _____),                                                                                                                   VAL2(0x3),                                                                                  // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00001111), MASK4(0xCF0F0F0F)        , AP(SET,       _____),                                                                                                                   VAL4(0x7070F02),                                                                            // static_5_m : , static_5_m : , static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_DQ_REG)                                         ,  BB(DQ,         _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x641EF414),                                                                           // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINEMUXSEL_DQ_REG)                                       ,  BB(DQ,         _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xE8),                                                                                 // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FINECTL_DQ_REG)                                          ,  BB(DQ,         _00001001), MASK2(0xE0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x203F),                                                                               // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FINECODEOVR_DQ_REG)                                      ,  BB(DQ,         _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FPTIMER_DQ_REG)                                          ,  BB(DQ,         _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x7F),                                                                                 // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_SAMPLEWAIT_DQ_REG)                                       ,  BB(DQ,         _00000010), MASK1(0x1F)              , AP(SET,       __F_T),                   5,   FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL1(0x7),                                                                                 FT(F_1600|F_1866,T_DDR3),                                                                  VAL1(0x6),                                                                                 FT(F_1600|F_1866,T_LPDDR3),                                                                VAL1(0x6),                                                                                 FT(F_1600|F_2133,T_LPDDR4),                                                                VAL1(0x6),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x5),                                                                                  // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_SAMPLEWAIT_DQ_REG)                                       ,  BB(DQ,         _00000001), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXCOARSEOVR_DQ_REG)                                      ,  BB(DQ,         _00001001), MASK2(0x800F)            , AP(SET,       _____),                                                                                                                   VAL2(0x2),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXFINEOVR_DQ_REG)                                        ,  BB(DQ,         _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_LPDDRTYPE_CCC_REG)                                       ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_LOCKCTL_CCC_REG)                                         ,  BB(CCC,        _00001001), MASK2(0xC00F)            , AP(SET,       _____),                                                                                                                   VAL2(0x3),                                                                                  // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL0_CH0_CCC_REG)                                   ,  BB(CCC,        _00001100), MASK2(0x801F)            , AP(SET,       _____),                                                                                                                   VAL2(0xF),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL0_CH1_CCC_REG)                                   ,  BB(CCC,        _00001100), MASK2(0x801F)            , AP(SET,       _____),                                                                                                                   VAL2(0xF),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL0_ECC_CCC_REG)                                   ,  BB(CCC,        _00001100), MASK2(0x801F)            , AP(SET,       _____),                                                                                                                   VAL2(0xF),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL1_CCC_REG)                                       ,  BB(CCC,        _00001100), MASK2(0x1F1F)            , AP(SET,       __F_T),                   6,   FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL2(0x120E),                                                                              FT(F_1600,T_LPDDR3|T_DDR3),                                                                VAL2(0xF0C),                                                                               FT(F_1600,T_LPDDR4),                                                                       VAL2(0xF0D),                                                                               FT(F_1866,T_LPDDR3|T_DDR3),                                                                VAL2(0xD0A),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0xB0A),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0xA09),                                                                                // static_5 : , static_5 :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH0_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0xCF0F)            , AP(SET,       _____),                                                                                                                   VAL2(0x202),                                                                                // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH1_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0xCF0F)            , AP(SET,       _____),                                                                                                                   VAL2(0x202),                                                                                // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_ECC_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0xCF0F)            , AP(SET,       _____),                                                                                                                   VAL2(0x202),                                                                                // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE1_CCC_REG)                                     ,  BB(CCC,        _00001001), MASK2(0xF0F)             , AP(SET,       _____),                                                                                                                   VAL2(0xF02),                                                                                // static_5_m : , static_5_m :
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_CCC_REG)                                        ,  BB(CCC,        _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x641EF414),                                                                           // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINEMUXSEL_CCC_REG)                                      ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xE8),                                                                                 // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FINECTL_CCC_REG)                                         ,  BB(CCC,        _00001001), MASK2(0xE0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x203F),                                                                               // static_5_m : , static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FINECODEOVR_CH0_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FINECODEOVR_CH1_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FINECODEOVR_ECC_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FPTIMER_CCC_REG)                                         ,  BB(CCC,        _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0xFFFF),                                                                               // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_SAMPLEWAIT_CCC_REG)                                      ,  BB(CCC,        _00000010), MASK1(0x1F)              , AP(SET,       __F_T),                   5,   FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL1(0x7),                                                                                 FT(F_1600|F_1866,T_DDR3),                                                                  VAL1(0x6),                                                                                 FT(F_1600|F_1866,T_LPDDR3),                                                                VAL1(0x6),                                                                                 FT(F_1600|F_2133,T_LPDDR4),                                                                VAL1(0x6),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x5),                                                                                  // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_SAMPLEWAIT_CCC_REG)                                      ,  BB(CCC,        _00000001), MASK1(0x1F)              , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXCOARSEOVR_CH0_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0x800F)            , AP(SET,       _____),                                                                                                                   VAL2(0x2),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXCOARSEOVR_CH1_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0x800F)            , AP(SET,       _____),                                                                                                                   VAL2(0x2),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXCOARSEOVR_ECC_CCC_REG)                                 ,  BB(CCC,        _00001001), MASK2(0x800F)            , AP(SET,       _____),                                                                                                                   VAL2(0x2),                                                                                  // static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXFINEOVR_CH0_CCC_REG)                                   ,  BB(CCC,        _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXFINEOVR_CH1_CCC_REG)                                   ,  BB(CCC,        _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RXFINEOVR_ECC_CCC_REG)                                   ,  BB(CCC,        _00001001), MASK2(0xC0FF)            , AP(SET,       _____),                                                                                                                   VAL2(0x13),                                                                                 // static_5_m : , static_5_m : , static_5_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_RSTCTL_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00001100), MASK2(0x7F80)            , AP(SET,       _____),                                                                                                                   VAL2(0x0),                                                                                  // static_GRCOMP_RSTCTL_m :
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_RSTCTL_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x2B),                                                                                T(T_LPDDR3),                                                                               VAL1(0x2B),                                                                                T(T_LPDDR4),                                                                               VAL1(0x16),                                                                                 // static_GRCOMP_RSTCTL_m :
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_RSTCTL_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x12C1),                                                                               // static_GRCOMP_RSTCTL_m : , static_GRCOMP_RSTCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_RSTCTL_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_LRCOMP_RSTCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_RSTCTL_DQDPLVUG_REG)                                 ,  BB(DQDPLVUG,   _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_LRCOMP_RSTCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_DQ_REG)                                            ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DLLCOMP_RSTCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DLLCOMP_RSTCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000064),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CONFIG2_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x1),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // static_2_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_DELAY0_DPIC_REG)                                         ,  BB(DPIC,       _00001111), MASK4(0x3FFFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x30010000),                                                                           // static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY1_DPIC_REG)                                         ,  BB(DPIC,       _00001000)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x2),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x2),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x4),                                                                                  // static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY1_DPIC_REG)                                         ,  BB(DPIC,       _00000100)                           , AP(SET,       _____),                                                                                                                   VAL1(0x4),                                                                                  // static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY1_DPIC_REG)                                         ,  BB(DPIC,       _00000011)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL2(0x51),                                                                                T(T_LPDDR3),                                                                               VAL2(0x51),                                                                                T(T_LPDDR4),                                                                               VAL2(0x6C),                                                                                 // static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY2_DPIC_REG)                                         ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xE20202),                                                                             // static_2_m : , static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY3_DPIC_REG)                                         ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x5000F),                                                                              // static_2_m : , static_2_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_DELAY4_DPIC_REG)                                         ,  BB(DPIC,       _00001111), MASK4(0xFFFFF0F)         , AP(SET,       _____),                                                                                                                   VAL4(0x50C200),                                                                             // static_2_m : , static_2_m : , static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY5_DPIC_REG)                                         ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x20202FF),                                                                            // static_2_m : , static_2_m : , static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY6_DPIC_REG)                                         ,  BB(DPIC,       _00000111)                           , AP(SET,       _____),                                                                                                                   VAL3(0x10000),                                                                              // static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY7_DPIC_REG)                                         ,  BB(DPIC,       _00000111)                           , AP(SET,       _____),                                                                                                                   VAL3(0xC8002),                                                                              // static_2_m : , static_2_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_DELAY8_DPIC_REG)                                         ,  BB(DPIC,       _00001111), MASK4(0x1FFFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x905222),                                                                             // static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY9_DPIC_REG)                                         ,  BB(DPIC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x1E1200C8),                                                                           // static_2_m : , static_2_m : , static_2_m : , static_2_m : , static_2_m :
  xxxxx2xx                                        ,                VAL2(DPIC_PM_DELAY10_DPIC_REG)                                        ,  BB(DPIC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x202),                                                                                // static_2_m : , static_2_m :
  ASSIGNDONE,
  //
  // PhyConfigComplete
  //
  xxxMx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  ASSIGNDONE,
  //
  // DunitResetComplete
  //
  xxxMx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00000100), MASK1(0x2)               , AP(POLL,      _____),                                                                                                                   VAL1(0x2),
  ASSIGNDONE,
  //
  // wake_dunit
  //
  xxxxx2xx                                        ,                VAL2(FAKE_WAKE_DUNIT_REG)                                             ,  BB(DUNIT,      _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x1),
  xxxxx2xx                                        ,                VAL2(FAKE_WAKE_DUNIT_REG)                                             ,  BB(DUNIT,      _00001111)                           , AP(POLL,      _____),                                                                                                                   VAL4(0x1),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp5p5_seq
  //
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_RSTB_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_PM_RSTB_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_RSTB_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_PM_RSTB_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CLKREQ_DPIC_REG)                                     ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_PMCLKREQ_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CLKREQ_DPIC_REG)                                     ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_PMCLKREQ_m :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp6_seq
  //
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_TXDLYCOMP_INIT_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_TXDLYCOMP_INIT_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_INIT_CH0_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DLLCOMP_INIT_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_INIT_CH1_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DLLCOMP_INIT_m :
  xxxME2xx          , VAL2(ECCEN)                 ,                VAL2(DLLCOMP_INIT_ECC_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DLLCOMP_INIT_m :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_INIT_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DLLCOMP_INIT_m :
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL2_DPIC_REG)                                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp6p5_seq
  //
  xxNME1xx, xxxxxCxx, VAL2(SLICE_0_MASTER)        , C_(  0)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxNME1xx, xxxxxCxx, VAL2(SLICE_1_MASTER)        , C_(  1)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7_seq
  //
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxME2xx          , VAL2(ECCEN)                 ,                VAL2(DLLCOMP_INIT_ECC_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CODE_STATUS_CH0_CCC_REG)                                 ,  BB(CCC,        _00000010), MASK1(0xF0)              , AP(GET,       D____),                                                                                                                   VAL2(TEMPVAR),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  xxxxx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00001100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPIC_PLLCTL),
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL2_DPIC_REG)                                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),// static_PLLDIVRST_m : 
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7p5_seq
  //
  xxNME1xx, xxxxxCxx, VAL2(SLICE_0_MASTER)        , C_(  0)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxNME1xx, xxxxxCxx, VAL2(SLICE_1_MASTER)        , C_(  1)      , VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7p75_seq
  //
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP0),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1),                                                        // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_DNGRP0),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_1),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_1),                                                      // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP1),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_2),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_2),                                                      // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_DNGRP1),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_3),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_3),                                                      // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP2),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_DNGRP2),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_1),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP3),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_2),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_1_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_DNGRP3),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_3),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP4),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_DNGRP4),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_1),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP5),                                                                   // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_2),                                                        // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_2_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_DNGRP5),                                                                   // Unused MP from KT
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001)                           , AP(SET_DELAY, D____), VAL4(0x00000001),                                                                                                 VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_3),                                                        // Unused MP from KT
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000010), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x3F),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000010), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x3F),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x3F),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x3F),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp7p75_lp4seq
  //
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000010), MASK1(0x7F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // Unused MP from KT
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR_UPGRP1),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp8m_seq
  //
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_DIGRSTCTL_m : , static_DIGRSTCTL_m :
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_DIGRSTCTL_m : , static_DIGRSTCTL_m :
  xxxMx1xx                                        ,                VAL1(FIFOPTREN_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_FIFOPTREN_m :
  xxxMx1xx                                        ,                VAL1(IOBUFACT_DIG_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_IOBUFACT_DIG_m : , static_IOBUFACT_DIG_m :
  xxxMx1xx                                        ,                VAL1(IOBUFACT_AFE_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_IOBUFACT_AFE_m : , static_IOBUFACT_AFE_m :
  xxxMx2xx                                        ,                VAL2(CH1_DIGRSTCTL_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_DIGRSTCTL_m : , static_DIGRSTCTL_m :
  xxxMx1xx                                        ,                VAL1(FIFOPTREN_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_FIFOPTREN_m :
  xxxMx2xx                                        ,                VAL2(CH1_FIFOPTREN_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_FIFOPTREN_m :
  xxxMx1xx                                        ,                VAL1(IOBUFACT_DIG_CCC_REG)                                            ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                                                   VAL1(0x7),                                                                                  // static_IOBUFACT_DIG_m : , static_IOBUFACT_DIG_m : , static_IOBUFACT_DIG_m :
  xxxMx1xx                                        ,                VAL1(IOBUFACT_AFE_CCC_REG)                                            ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                                                   VAL1(0x7),                                                                                  // static_IOBUFACT_AFE_m : , static_IOBUFACT_AFE_m : , static_IOBUFACT_AFE_m :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp0_seq
  //
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x1),                                                                                  // static_LP4RSTCTL : // cold boot only, static_LP4RSTCTL : // cold boot only, static_LP4RSTCTL : // cold boot only
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp10m_seq
  //
  xxxMx1xx                                        ,                VAL1(CH0_SPIDIC_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_SPIDIC_m :
  xxxMx2xx                                        ,                VAL2(CH1_SPIDIC_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_SPIDIC_m :
  xxxMx1xx                                        ,                VAL1(SPIDIC_DQ_REG)                                                   ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_SPIDIC_m :
  ASSIGNDONE,
  //
  // InitDunit
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRP0),
  xxxMx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00001000), MASK1(0xE)               , AP(SET,       ____T),                   3,   T(T_LPDDR3|T_DDR3),                                                                        VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x4),                                                                                 T(T_WIO2),                                                                                 VAL1(0x0),                                                                                  // LP3 is always BL8, LP4 is always BL32, and WIO2 is always BL8
  xxxMx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00001100), MASK2(0x1C0)             , AP(SET,       ____T),                   5,   T(T_LPDDR3),                                                                               VAL2(0x40),                                                                                T(T_LPDDR4),                                                                               VAL2(0x80),                                                                                T(T_WIO2),                                                                                 VAL2(0xC0),                                                                                T(T_DDR3),                                                                                 VAL2(0x0),                                                                                 T(T_DDR4),                                                                                 VAL2(0x100),
  xxxxx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRP0_1),
  xxxMx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL1(0x0),                                                                                 T(T_DDR3),                                                                                 VAL1(0x4),
  xxxxx1xx                                        ,                VAL1(D_CR_DTR0A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR0A),
  xxxxx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00000111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRP0_2),                                                                // DDR3/DDR4 width
  xxxxx1xx                                        ,                VAL1(D_CR_DTR1A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR1A),                                                                 // N/A for WIO2, N/A for LP4/WIO2, N/A for LP3/WIO2
  xxxxx1xx                                        ,                VAL1(D_CR_DTR2A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR2A),
  xxxxx1xx                                        ,                VAL1(D_CR_DTR3A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR3A),                                                                 // for HVM stretch mode only, Not Available for LP3
  xxxxx1xx                                        ,                VAL1(D_CR_DTR4A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR4A),
  xxxxx1xx                                        ,                VAL1(D_CR_DTR5A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR5A),                                                                 // 1.875ns/DRAM Freq
  xxxxx1xx                                        ,                VAL1(D_CR_DTR6A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR6A),                                                                 // not in JEDEC spec, Def Value should be ok, Previously :TCKSRE, tRP + tRCD + RL + tCCD   , RL + tDQSCK +MRR/MRW BL/2 + 1, Max(WL + 1 + BL/2 + tWTR, tXP + tMRRI)
  xxxxx1xx                                        ,                VAL1(D_CR_DTR7A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR7A),
  xxxxx1xx                                        ,                VAL1(D_CR_DTR8A_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR8A),                                                                 // PHY Spec, Depends on Technology, PHY Spec, Depends on Technology
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00001000), MASK1(0x38)              , AP(SET,       _____),                                                                                                                   VAL1(0x38),
  xxxMx1xx                                        ,                VAL1(D_CR_DSCH_DUNIT_REG)                                             ,  BB(DUNIT,      _00001101), MASK3(0x7E00F)           , AP(SET,       _____),                                                                                                                   VAL3(0x38000),
  xxxxx1xx                                        ,                VAL1(D_CR_SSKPD0_DUNIT_REG)                                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_SSKPD0),
  xxxxx1xx                                        ,                VAL1(D_CR_BONUS0_DUNIT_REG)                                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BONUS0),
  xxxxx1xx                                        ,                VAL1(D_CR_BONUS1_DUNIT_REG)                                           ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BONUS1),
  xxxxx2xx                                        ,                VAL2(D_CR_MR4_DESWIZZLE_DUNIT_REG)                                    ,  BB(DUNIT,      _00001111)                           , AP(SET,       D___T),                   1,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL2(DYN_DUNIT_D_CR_MR4_DESWIZZLE),                                                         // Check with Package Team, Check with Package Team, Check with Package Team, BXT-P is 3 bits, Check with Package Team, Check with Package Team, Check with Package Team, BXT-P is 3 bits
  xxxMx1xx                                        ,                VAL1(D_CR_DSCH_DUNIT_REG)                                             ,  BB(DUNIT,      _00001000), MASK1(0x78)              , AP(SET,       _PF_T),                   2,   PFT(P_SIM,F_2400,T_LPDDR4),                                                                VAL1(0x0),                                                                                 PFT(P_SIM,F_2133,T_LPDDR4),                                                                VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DOCRA_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0xF)               , AP(SET,       __F_T),                   3,   FT(F_1600,T_LPDDR3),                                                                       VAL1(0x6),                                                                                 FT(F_1866,T_LPDDR3),                                                                       VAL1(0x7),                                                                                 FT(F_1333,T_LPDDR3),                                                                       VAL1(0x5),                                                                                  // Temp value used in SIM, Need value from SI.
  xxxxx1xx                                        ,                VAL1(D_CR_DOCRA_DUNIT_REG)                                            ,  BB(DUNIT,      _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DOCRA),                                                                 // Temp value used in SIM, Need value from SI.
  xxxxx1xx                                        ,                VAL1(D_CR_DOCRA_DUNIT_REG)                                            ,  BB(DUNIT,      _00000110)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_DUNIT_D_CR_DOCRA_1),                                                               // Temp value used in SIM, Need value from SI.
  xxxxx1xx                                        ,                VAL1(D_CR_DOCRA_DUNIT_REG)                                            ,  BB(DUNIT,      _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DOCRA_2),                                                               // Temp value used in SIM, Need value from SI., Temp value used in SIM, Need value from SI.
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x000001F4),                                                                                                 VAL1(0x0),
  ASSIGNDONE,
  //
  // InitDunitWake
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000101)                           , AP(SET_DELAY, D____), VAL4(0x0000012C),                                                                                                 VAL2(DYN_DUNIT_D_CR_DRMC),
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x000000C8),                                                                                                 VAL1(0x0),
  ASSIGNDONE,
  //
  // PrepareForTraining
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),                                                                                 // Prepare for training by switching PMI to CPGC
  xxxMx1xx                                        ,                VAL1(D_CR_DSCH_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // change if it was changed for CPGC
  xxxxx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00001000)                           , AP(SET,       D___T),                   2,   T(T_LPDDR3|T_LPDDR4|T_DDR3),                                                               VAL2(DYN_DUNIT_D_CR_BGF_CTL),                                                              T(T_WIO2),                                                                                 VAL2(DYN_DUNIT_D_CR_BGF_CTL_1),
  xxxxx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BGF_CTL_2),
  xxxMx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x1D)              , AP(SET_DELAY, _____), VAL4(0x00000384),                                                                                                 VAL1(0xD),
  ASSIGNDONE,
  //
  // CPGC_ONE_TIME_INIT
  //
  xxxMx2xx                                        ,                VAL2(CPGC2_CHICKEN_REG_CPGC_REG)                                      ,  BB(CPGC,       _00000011), MASK2(0x7FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x350),
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                                                 VAL1(0x2),
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                                                 VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC0_DUNIT_REG)                                            ,  BB(DUNIT,      _00001111), MASK4(0x1F7FFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x420022),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000100), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_CONTROL_CPGC_REG)                                  ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_ADDRESS_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  xxxMx1xx                                        ,                VAL1(CPGC2_DATA_INSTRUCTION_0__CPGC_REG)                              ,  BB(CPGC,       _00000001), MASK1(0xF8)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  xxxxx1xx                                        ,                VAL1(CPGC2_DATA_CONTROL_CPGC_REG)                                     ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_1__CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x81),
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_CPGC_REG)                     ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_CPGC_REG)                     ,  BB(CPGC,       _00001011), MASK3(0xC3FFFF)          , AP(SET,       _____),                                                                                                                   VAL3(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_BASE_COL_REPEATS_CPGC_REG)                                 ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x81),
  xxxxx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)                           ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_BUF_CTL_CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0x7077F)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00001111), MASK4(0x1FFFE0DB)        , AP(SET,       _____),                                                                                                                   VAL4(0x2049),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_XTRA_LFSR_CFG_CPGC_REG)                                ,  BB(CPGC,       _00001111), MASK4(0x3F9C9C9C)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x11111111),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x11224488),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_2__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x77777777),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_INVDCCTL_CPGC_REG)                                     ,  BB(CPGC,       _00001011), MASK3(0xE00FFF)          , AP(SET,       _____),                                                                                                                   VAL3(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_INV_DC_MASK_LO_CPGC_REG)                               ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_INV_DC_MASK_HI_CPGC_REG)                               ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_DRAMDM_CPGC_REG)                                       ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xFFFFFFFF),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_XDRAMDM_CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xFFFFFFFF),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                                   ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00001111), MASK4(0x1FFFF1FF)        , AP(SET,       _____),                                                                                                                   VAL4(0xC5270C5),
  xxxMx1xx                                        ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)                             ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC_LB_SEQ_CFG_CPGC_REG)                                        ,  BB(CPGC,       _00001111), MASK4(0xFF1FFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC_LB_SEQ_CTL_CPGC_REG)                                        ,  BB(CPGC,       _00000011), MASK2(0x307F)            , AP(SET,       _____),                                                                                                                   VAL2(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000111), MASK3(0x207F40)          , AP(SET,       _____),                                                                                                                   VAL3(0x201000),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_B_CPGC_REG)                                         ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                                        ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00001100)                           , AP(SET,       _____),                                                                                                                   VAL2(0xFFFF),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_RANK_L2P_MAPPING_CPGC_REG)                              ,  BB(CPGC,       _00001111), MASK4(0x77777777)        , AP(SET,       _____),                                                                                                                   VAL4(0x76543210),                                                                           // RANK_1, RANK_0
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)                            ,  BB(CPGC,       _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // A0 bug, cannot close page on bank0
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_LNEN_HI_CPGC_REG)                                       ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL4(0xFFFFFFFF),                                                                          T(T_DDR3),                                                                                 VAL4(0x0),                                                                                  // For B0 and beyond
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_LNEN_LO_CPGC_REG)                                       ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq_sim
  //
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x2),                                                                                  // Set Reset High
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x0),                                                                                  // Latch Reset State
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       ____T),                   1,   T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x10),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000000C8),
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111), MASK4(0x70FFFFFF)        , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR3),                                                                               VAL4(0xFC3F0),
  xxxME2xx          , VAL2(RANK1_ENABLED)         ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111), MASK4(0x70FFFFFF)        , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR3),                                                                               VAL4(0x400FC3F0),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000007D0),
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4|T_DDR3),                                                                        VAL2(DYN_DUNIT_D_CR_DRMC_1),
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq
  //
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_DDR3|T_LPDDR4),                                                                        VAL1(0x2),                                                                                  // Set Reset High
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_DDR3|T_LPDDR4),                                                                        VAL1(0x0),                                                                                  // Latch Reset State
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       ____T),                   1,   T(T_DDR3|T_LPDDR4),                                                                        VAL1(0x10),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00030D40),
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_DDR3|T_LPDDR4),                                                                        VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111), MASK4(0x70FFFFFF)        , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR3),                                                                               VAL4(0xFC3F0),
  xxxME2xx          , VAL2(RANK1_ENABLED)         ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111), MASK4(0x70FFFFFF)        , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR3),                                                                               VAL4(0x400FC3F0),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x001E8480),
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D___T),                   1,   T(T_DDR3|T_LPDDR4),                                                                        VAL2(DYN_DUNIT_D_CR_DRMC_2),
  ASSIGNDONE,
  //
  // ProgramSelfRefresh
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), AP(SET,       D____),                                                                                                                           VAL2(DYN_DUNIT_D_CR_DRFC),
  xxxxx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000011)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4),                                                                               VAL2(DYN_DUNIT_D_CR_DRFC_1),
  ASSIGNDONE,
  //
  // ProgramFinalSettings
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRP0_3),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00001000), MASK1(0x30)              , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x0),                                                                                 C(C_PO),                                                                                   VAL1(0x30),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00001000), MASK1(0x4)               , AP(SET,       ___CT),                   3,   CT(C_POR,T_LPDDR3|T_LPDDR4),                                                               VAL1(0x4),                                                                                 CT(C_PO,T_LPDDR3|T_LPDDR4|T_DDR3),                                                         VAL1(0x0),                                                                                 CT(C_POR,T_DDR3),                                                                          VAL1(0x4),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00001000), MASK1(0x8)               , AP(SET,       ___C_),                   2,   C(C_PO),                                                                                   VAL1(0x8),                                                                                 C(C_POR),                                                                                  VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00001110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DPMC1),                                                                 // P0 POR=2, Page time out time, need to confirm
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1E)              , AP(SET,       ___CT),                   3,   CT(C_POR,T_LPDDR3|T_LPDDR4),                                                               VAL1(0x16),                                                                                CT(C_POR,T_DDR3),                                                                          VAL1(0x2),                                                                                 CT(C_PO,T_LPDDR4|T_LPDDR3|T_DDR3),                                                         VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x0),                                                                                 C(C_PO),                                                                                   VAL1(0x80),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // moved to after set and poll SD_init in MLMC
  xxxxx1xx                                        ,                VAL1(D_CR_DSCH_DUNIT_REG)                                             ,  BB(DUNIT,      _00001011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DSCH),                                                                  // change if it was changed for CPGC, move to final setting, move to final setting
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x21)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // ProgramCustomTsv, ProgramCustomTsv; assert BGF reset
  xxxxx1xx                                        ,                VAL1(D_CR_BGF_CUSTOM_TSV_CMD_PATTERN_DUNIT_REG)                       ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_PATTERN),                                            // ProgramCustomTsv, ProgramCustomTsv
  xxxxx1xx                                        ,                VAL1(D_CR_BGF_CUSTOM_TSV_CMD_INIT_DUNIT_REG)                          ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_INIT),                                               // ProgramCustomTsv, ProgramCustomTsv
  xxxxx1xx                                        ,                VAL1(D_CR_BGF_CUSTOM_TSV_DATA_PATTERN_DUNIT_REG)                      ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_PATTERN),                                           // ProgramCustomTsv, ProgramCustomTsv
  xxxxx1xx                                        ,                VAL1(D_CR_BGF_CUSTOM_TSV_DATA_INIT_DUNIT_REG)                         ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_INIT),                                              // ProgramCustomTsv, ProgramCustomTsv
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // ProgramCustomTsv; deassert BGF reset
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x60)              , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x0),                                                                                 C(C_PO),                                                                                   VAL1(0x20),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x2)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4|T_DDR3),                                                               VAL1(0x2),                                                                                 T(T_WIO2),                                                                                 VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x2)               , AP(SET,       ___CT),                   1,   CT(C_POR,T_LPDDR4),                                                                        VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000011), MASK2(0x3FFF)            , AP(SET,       _____),                                                                                                                   VAL2(0x1062),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4|T_DDR3),                                                               VAL1(0x0),                                                                                 T(T_WIO2),                                                                                 VAL1(0x1),                                                                                  // Enable ZQCal
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_TQCTL),                                                                 // 1ms, Kaleen Man
  xxxxx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_DUNIT_D_CR_TQCTL_1),                                                               // 1x refresh rate. Still Open. Different for WIO2/LP3 vs LP4?
  xxxMx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       ___CT),                   3,   CT(C_POR,T_LPDDR4|T_LPDDR3),                                                               VAL1(0x4),                                                                                 CT(C_POR,T_DDR3),                                                                          VAL1(0x0),                                                                                 CT(C_PO,T_LPDDR4|T_LPDDR3|T_DDR3),                                                         VAL1(0x0),                                                                                  // HSD1202170264 ; need to set 1 for E0 POR
  xxxMx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x3)               , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_LPDDR4),                                                                      VAL1(0x3),                                                                                 T(T_DDR3),                                                                                 VAL1(0x0),                                                                                  // Depands on the package and DRAM type, contact Kaleen Man, Depands on the package and DRAM type, contact Kaleen Man
  xxxxx1xx                                        ,                VAL1(D_CR_TQOFFSET_DUNIT_REG)                                         ,  BB(DUNIT,      _00001100)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4|T_DDR3),                                                                        VAL2(DYN_DUNIT_D_CR_TQOFFSET),                                                              // write the DRAM Mode Register that contains Temp Offset
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x2)               , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x0),                                                                                 C(C_PO),                                                                                   VAL1(0x2),
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x8)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x10)              , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x0),                                                                                 C(C_PO),                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),                                                                                 // P0=1
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x1)               , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x0),                                                                                 C(C_PO),                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                                        ,  BB(DUNIT,      _00001000), MASK1(0x30)              , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x30),                                                                                C(C_PO),                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00001000)                           , AP(SET,       DP__T),                   2,   PT(P_SIM,T_LPDDR3|T_LPDDR4|T_DDR3),                                                        VAL2(DYN_DUNIT_D_CR_BGF_CTL_3),                                                            PT(P_SIM,T_WIO2),                                                                          VAL2(DYN_DUNIT_D_CR_BGF_CTL_4),
  xxxxx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000110)                           , AP(SET,       DP___),                   1,   P(P_SIM),                                                                                  VAL2(DYN_DUNIT_D_CR_BGF_CTL_5),
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x1C)              , AP(SET_DELAY, _P___), VAL4(0x0000001E), 1,   P(P_SIM|P_EMU),                                                                            VAL1(0x8),
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0xC0)              , AP(SET_DELAY, _P___), VAL4(0x0000001E), 1,   P(P_SIM|P_EMU),                                                                            VAL1(0x40),
  xxxME2xx          , VAL2(BXT_A0_WA)             ,                VAL2(D_CR_ACCIP_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x38)              , AP(SET,       _____),                                                                                                                   VAL1(0x28),
  xxxMx2xx                                        ,                VAL2(D_CR_RD_PROM0_DUNIT_REG)                                         ,  BB(DUNIT,      _00000110), MASK2(0xF80)             , AP(SET,       _____),                                                                                                                   VAL2(0xF80),
  xxxMx2xx                                        ,                VAL2(D_CR_RD_PROM1_DUNIT_REG)                                         ,  BB(DUNIT,      _00001100), MASK2(0x3FF0)            , AP(SET,       _____),                                                                                                                   VAL2(0x3EA0),                                                                               // HSD 1207123062
  xxxMx2xx                                        ,                VAL2(D_CR_RD_PROM3_DUNIT_REG)                                         ,  BB(DUNIT,      _00000110), MASK2(0xF80)             , AP(SET,       _____),                                                                                                                   VAL2(0xF80),
  xxxMx2xx                                        ,                VAL2(D_CR_RD_PROM4_DUNIT_REG)                                         ,  BB(DUNIT,      _00000110), MASK2(0xF80)             , AP(SET,       _____),                                                                                                                   VAL2(0xF80),
  xxxMx2xx                                        ,                VAL2(D_CR_MMC_DUNIT_REG)                                              ,  BB(DUNIT,      _00001111), MASK4(0x383FFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x281A355),
  xxxME2xx          , VAL2(BXT_A0_WA)             ,                VAL2(D_CR_MM_BLK_DUNIT_REG)                                           ,  BB(DUNIT,      _00000010), MASK1(0x8)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(D_CR_MMRDWR_AB_DUNIT_REG)                                        ,  BB(DUNIT,      _00001111), MASK4(0x3F00FC0)         , AP(SET,       _____),                                                                                                                   VAL4(0x1000400),
  xxxMx2xx                                        ,                VAL2(D_CR_MMRDWR_CD_DUNIT_REG)                                        ,  BB(DUNIT,      _00001111), MASK4(0x3F00FC0)         , AP(SET,       _____),                                                                                                                   VAL4(0x1000300),
  xxxMx2xx                                        ,                VAL2(D_CR_DL_THRS_DUNIT_REG)                                          ,  BB(DUNIT,      _00000011), MASK2(0x7FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x2),
  xxxxx2xx                                        ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)                               ,  BB(DUNIT,      _00001111)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4),                                                                               VAL2(DYN_DUNIT_D_CR_DQS_RETRAINING_CTL),                                                    // LPDDR4 only, Chris Mozak, ame value as LPDDR4 MR23, 500ns? Chris Mozak. Should not larger than interval, LPDDR4 only, LPDDR4 only
  xxxxx1xx                                        ,                VAL1(RDVLDCTL_CCC_REG)                                                ,  BB(CCC,        _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_RDVLDCTL_8),                                                                   // static_DIGREGS_m :
  xxxxx1xx                                        ,                VAL1(RDVLDCTL_DQ_REG)                                                 ,  BB(DQ,         _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RDVLDCTL_8),                                                                    // static_DIGREGS_m :
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(D_CR_ERR_ECC_LOG_DUNIT_REG)                                      ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x80),
  xBxME2xx          , VAL2(ECCEN)                 ,                VAL2(B_CR_BCTRL2_BUNIT_REG)                                           , BB2(BUNIT,      _00001000), MASK1(0x2)               , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x2),
  xBxMx2xx                                        ,                VAL2(B_CR_BMCMODE_LOW_BUNIT_REG)                                      , BB2(BUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // TrainingDone
  //
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x21)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // assert BGF reset
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET_DELAY, _____), VAL4(0x0000000A),                                                                                                 VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // deassert BGF reset
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp11m_seq
  //
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_CLKGATE_DPLVUG_REG)                               ,  BB(DPLVUG,     _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_LRCOMP_CLKGATE_m, static_LRCOMP_CLKGATE_m
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_CLKGATE_DQDPLVUG_REG)                             ,  BB(DQDPLVUG,   _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_LRCOMP_CLKGATE_m, static_LRCOMP_CLKGATE_m
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_CLKGATE_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_DPIC_GRCOMP_CLKGATE_m
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_PERIODICCOMP_DPLVUG_REG)                             ,  BB(DPLVUG,     _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),                                                                                  // static_GRCOMP_PERIODICCOMP_m : , static_GRCOMP_PERIODICCOMP_m : PO_SAFE
  xxxMx1xx                                        ,                VAL1(CLKGATERDCTL_CCC_REG)                                            ,  BB(CCC,        _00000110), MASK2(0xF77)             , AP(SET,       _____),                                                                                                                   VAL2(0xF33),                                                                                // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATERDCTL_CCC_REG)                                            ,  BB(CCC,        _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL1(0x11),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x14),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x14),                                                                                FT(F_1066|F_1600,T_LPDDR4),                                                                VAL1(0x18),                                                                                FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x1D),                                                                                 // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_CCC_REG)                                            ,  BB(CCC,        _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),                                                                                  // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_CCC_REG)                                            ,  BB(CCC,        _00000010), MASK1(0x70)              , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x20),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x30),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x30),                                                                                FT(F_1600|F_2133,T_LPDDR4),                                                                VAL1(0x20),                                                                                FT(F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL1(0x30),                                                                                 // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_CCC_REG)                                            ,  BB(CCC,        _00000010), MASK1(0x7)               , AP(SET,       __F_T),                   6,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x2),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x3),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x3),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x3),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x5),                                                                                 FT(F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL1(0x6),                                                                                  // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_CCC_REG)                                            ,  BB(CCC,        _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   6,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL1(0xC),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0xE),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0xE),                                                                                 FT(F_1066|F_1600,T_LPDDR4),                                                                VAL1(0xB),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0xD),                                                                                 FT(F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL1(0xE),                                                                                  // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0x18)              , AP(SET,       _____),                                                                                                                   VAL1(0x8),                                                                                  // static_DQCLKGATE_m :, static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_CCC_REG)                                              ,  BB(CCC,        _00000100), MASK1(0x7)               , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x0),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x7),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x7),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x7),                                                                                  // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_CCC_REG)                                              ,  BB(CCC,        _00000011), MASK2(0x1C0)             , AP(SET,       _____),                                                                                                                   VAL2(0x100),                                                                                // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_CCC_REG)                                              ,  BB(CCC,        _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL1(0x11),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x14),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x14),                                                                                FT(F_1066|F_1600,T_LPDDR4),                                                                VAL1(0x18),                                                                                FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x1D),                                                                                 // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATERDCTL_DQ_REG)                                             ,  BB(DQ,         _00000110), MASK2(0xF77)             , AP(SET,       _____),                                                                                                                   VAL2(0xF33),                                                                                // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATERDCTL_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL1(0x11),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x14),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x14),                                                                                FT(F_1066|F_1600,T_LPDDR4),                                                                VAL1(0x18),                                                                                FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x1D),                                                                                 // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_DQ_REG)                                             ,  BB(DQ,         _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),                                                                                  // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_DQ_REG)                                             ,  BB(DQ,         _00000010), MASK1(0x70)              , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x20),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x30),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x30),                                                                                FT(F_1600|F_2133,T_LPDDR4),                                                                VAL1(0x20),                                                                                FT(F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL1(0x30),                                                                                 // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_DQ_REG)                                             ,  BB(DQ,         _00000010), MASK1(0x7)               , AP(SET,       __F_T),                   6,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x2),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x3),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x3),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x3),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x5),                                                                                 FT(F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL1(0x6),                                                                                  // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATEWRCTL_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   6,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL1(0xC),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0xE),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0xE),                                                                                 FT(F_1066|F_1600,T_LPDDR4),                                                                VAL1(0xB),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0xD),                                                                                 FT(F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                                  VAL1(0xE),                                                                                  // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_DQ_REG)                                               ,  BB(DQ,         _00000100), MASK1(0x8)               , AP(SET,       _____),                                                                                                                   VAL1(0x8),                                                                                  // static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_DQ_REG)                                               ,  BB(DQ,         _00000100), MASK1(0x7)               , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3|T_LPDDR4),                                                       VAL1(0x0),                                                                                 FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x7),                                                                                 FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x7),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),                                                                                 FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x7),                                                                                  // static_DQCLKGATE_m : , static_DQCLKGATE_m : , static_DQCLKGATE_m :
  xxxMx1xx                                        ,                VAL1(CLKGATECTL_DQ_REG)                                               ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   5,   FT(F_1066,T_DDR3|T_LPDDR3),                                                                VAL1(0x11),                                                                                FT(F_1333|F_1600|F_1866,T_DDR3),                                                           VAL1(0x14),                                                                                FT(F_1333|F_1600|F_1866,T_LPDDR3),                                                         VAL1(0x14),                                                                                FT(F_1066|F_1600,T_LPDDR4),                                                                VAL1(0x18),                                                                                FT(F_2133|F_2400|F_2666|F_2933|F_3200,T_LPDDR4),                                           VAL1(0x1D),                                                                                 // static_DQCLKGATE_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CLKGATE_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_PMCLKGATE_m :
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CLKGATE_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_PMCLKGATE_m :
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp12m_seq
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CLKUNGATE_CCC_REG)                                       ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DLLCOMP_CLKUG_m : //CRI/DLLCOMP Clock Gating:
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CLKUNGATE_ECC_CCC_REG)                                   ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DLLCOMP_CLKUG_m : //CRI/DLLCOMP Clock Gating
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CLKUNGATE_DQ_REG)                                        ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // static_DLLCOMP_CLKUG_m : //CRI/DLLCOMP Clock Gating
  xxxMx1xx                                        ,                VAL1(DPIC_CRI_CFG_DPIC_REG)                                           ,  BB(DPIC,       _00000100), MASK1(0x1)               , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x0),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_CRIPGCTL_m :
  xxxMx1xx                                        ,                VAL1(DPIC_CRI_CFG_DPIC_REG)                                           ,  BB(DPIC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x210),                                                                                // static_CRIPGCTL_m : , static_CRIPGCTL_m : , static_CRIPGCTL_m :
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000009C4),
  ASSIGNDONE,
  //
  // CPGCModeComplete
  //
  xxxxx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00000101)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_1),
  ASSIGNDONE,
  //
  // SetMrcDone
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000320),
  ASSIGNDONE,
  //
  // InitDunitWakeS0set
  //
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                                      ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // Wake the DRAMs (handle in punit)
  ASSIGNDONE,
  //
  // InitDunitWakeS0poll
  //
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                                      ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),                                                                                  // Wait until DRAMs are awake
  ASSIGNDONE,
  //
  // modmem_init_lpddrgrp10_seq
  //
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH0_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x27),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH1_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x27),
  ASSIGNDONE,
  //
  // modmem_lp4_freq_switch_seq1
  //
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // // Assert SPID RSTB
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(CH1_DIGRSTCTL_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL2_DPIC_REG)                                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(TXDLLCTL_DQ_REG)                                                 ,  BB(DQ,         _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // // Disable DLL and assert reset to Tx Dcomp and DLL Dcomp
  xxxMx1xx                                        ,                VAL1(TXDLLCTL_CCC_REG)                                                ,  BB(CCC,        _00000110), MASK2(0x180)             , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL2(0x0),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_DQ_REG)                                            ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // // Assert DLLCOMP RSTB
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_RSTCTL_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // // Assert TX DLL RSTB
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_RSTCTL_DQDPLVUG_REG)                                 ,  BB(DQDPLVUG,   _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // // Disable PLL
  ASSIGNDONE,
  //
  // modmem_lp4_freq_switch_seq2
  //
  xxxxx1xx                                        ,                VAL1(PLLDIVRATIOS_0_ADPLL_REG)                                        ,  BB(ADPLL,      _00001100)                           , AP(SET,       __F_T),                   6,   FT(F_1866,T_LPDDR3|T_DDR3),                                                                VAL2(0x1C07),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x1806),                                                                              FT(F_1600,T_LPDDR4),                                                                       VAL2(0x1803),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x2004),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x4809),                                                                              FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL2(0x2805),
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL_DPIC_REG)                                              ,  BB(DPIC,       _00000001), MASK1(0x1F)              , AP(SET,       __F_T),                   5,   FT(F_1066|F_1333|F_1600|F_1866,T_DDR3),                                                    VAL1(0x0),                                                                                 FT(F_1066|F_1333|F_1600|F_1866,T_LPDDR3),                                                  VAL1(0x0),                                                                                 FT(F_1066|F_1600|F_2133|F_2666|F_2933|F_3200,T_LPDDR4),                                    VAL1(0x0),                                                                                 FT(F_2400,T_LPDDR4),                                                                       VAL1(0x1),                                                                                 FT(F_1600,T_LPDDR4),                                                                       VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(SPIDCLKCTL0_DPIC_REG)                                            ,  BB(DPIC,       _00000001), MASK1(0x3F)              , AP(SET,       __F_T),                   5,   FT(F_1333,T_DDR3|T_LPDDR3),                                                                VAL1(0x14),                                                                                FT(F_1600,T_DDR3|T_LPDDR3),                                                                VAL1(0x18),                                                                                FT(F_1600,T_LPDDR4),                                                                       VAL1(0xC),                                                                                 FT(F_2133,T_LPDDR4),                                                                       VAL1(0x10),                                                                                FT(F_2400,T_LPDDR4),                                                                       VAL1(0x12),                                                                                 // // Configure PLL for POR frequency// modmem_fbdiv_prog_seq// USYNC counter setting for operating freq
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // // Enable PLL
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000003E8),
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00000001), MASK1(0x2)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x2),
  ASSIGNDONE,
  //
  // modmem_lp4_freq_switch_seq2a
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_DQ_REG)                                            ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // // Deassert DLLCOMP RSTB
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_RSTCTL_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // // Deassert TX DLL RSTB
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_RSTCTL_DQDPLVUG_REG)                                 ,  BB(DQDPLVUG,   _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(TXDLLCTL_DQ_REG)                                                 ,  BB(DQ,         _00000100), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // // Enable DLL
  xxxMx1xx                                        ,                VAL1(TXDLLCTL_CCC_REG)                                                ,  BB(CCC,        _00000110), MASK2(0x180)             , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL2(0x180),
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_TXDLYCOMP_INIT_m : // TX and DLL COMP init
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_TXDLYCOMP_INIT_m : // TX and DLL COMP init
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_TXDLYCOMP_INIT_m :
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_TXDLYCOMP_INIT_m :
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL2_DPIC_REG)                                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                        ,                VAL1(DPIC_TXDLYCOMP_INIT_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  ASSIGNDONE,
  //
  // modmem_lp4_freq_switch_seq3
  //
  xxxMx1xx                                        ,                VAL1(PLLDIVCTL2_DPIC_REG)                                             ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // static_PLLDIVRST_m :
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),                                                                                  // // Deassert SPID RSTB
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(CH1_DIGRSTCTL_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x3),
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_DQ_REG)                                                ,  BB(DQ,         _00000001), MASK1(0x2)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x2),
  xxxMx1xx                                        ,                VAL1(DIGRSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x2)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x2),
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq_lp4_a
  //
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x2),                                                                                  // Set Reset High
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // Latch Reset State
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq_lp4_b
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x13)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x10),
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq_lp4_c
  //
  xxxMx1xx                                        ,                VAL1(LP4RSTCTL_CCC_REG)                                               ,  BB(CCC,        _00000001), MASK1(0x7)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  ASSIGNDONE,
  //
  // modmem_init_dramreset_seq_lp4_d
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4),                                                                               VAL2(DYN_DUNIT_D_CR_DRMC_3),
  ASSIGNDONE,
  //
  // maxpi_dll_init
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_INIT_CH0_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_INIT_CH1_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxME2xx          , VAL2(ECCEN)                 ,                VAL2(DLLCOMP_INIT_ECC_CCC_REG)                                        ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_INIT_DQ_REG)                                             ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00003E80),
  ASSIGNDONE,
  //
  // maxpi_override_coarse_init
  //
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00001100), MASK2(0x1F0)             , AP(SET,       _____),                                                                                                                   VAL2(0xF0),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH0_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0x4F)              , AP(SET,       _____),                                                                                                                   VAL1(0x4F),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH1_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0x4F)              , AP(SET,       _____),                                                                                                                   VAL1(0x4F),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_ECC_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0x4F)              , AP(SET,       _____),                                                                                                                   VAL1(0x4F),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00001000), MASK1(0x4F)              , AP(SET,       _____),                                                                                                                   VAL1(0x4F),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL_DQ_REG)                                         ,  BB(DQ,         _00000011), MASK2(0x1F1F)            , AP(SET,       __F_T),                   6,   FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL2(0x120E),                                                                              FT(F_1600,T_LPDDR3|T_DDR3),                                                                VAL2(0xF0C),                                                                               FT(F_1600,T_LPDDR4),                                                                       VAL2(0xF0D),                                                                               FT(F_1866,T_LPDDR3|T_DDR3),                                                                VAL2(0xD0A),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0xB0A),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0xA09),                                                                                // static_5 : , static_5 :
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL1_CCC_REG)                                       ,  BB(CCC,        _00001100), MASK2(0x1F1F)            , AP(SET,       __F_T),                   6,   FT(F_1333,T_LPDDR3|T_DDR3),                                                                VAL2(0x120E),                                                                              FT(F_1600,T_LPDDR3|T_DDR3),                                                                VAL2(0xF0C),                                                                               FT(F_1600,T_LPDDR4),                                                                       VAL2(0xF0D),                                                                               FT(F_1866,T_LPDDR3|T_DDR3),                                                                VAL2(0xD0A),                                                                               FT(F_2133,T_LPDDR4),                                                                       VAL2(0xB0A),                                                                               FT(F_2400,T_LPDDR4),                                                                       VAL2(0xA09),                                                                                // static_5 : , static_5 :
  ASSIGNDONE,
  //
  // maxpi_set_codes
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_DQ_REG)                                            ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL_DQ_REG)                                         ,  BB(DQ,         _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DLLCOMP_FBMUXSEL),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL1_CCC_REG)                                       ,  BB(CCC,        _00001100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_FBMUXSEL1),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_DQ_REG)                                         ,  BB(DQ,         _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DLLCOMP_FINECODE),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_CCC_REG)                                        ,  BB(CCC,        _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_FINECODE),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DLLCOMP_COARSECODE),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_COARSECODE1_CCC_REG)                                     ,  BB(CCC,        _00001001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_DQ_REG)                                            ,  BB(DQ,         _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_RESET_CCC_REG)                                           ,  BB(CCC,        _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  ASSIGNDONE,
  //
  // maxpi_get_codes
  //
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL_DQ_REG)                                         ,  BB(DQ,         _00000010), MASK1(0x1F)              , AP(GET,       D____),                                                                                                                   VAL2(MUX_MAX),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_FBMUXSEL_DQ_REG)                                         ,  BB(DQ,         _00000001), MASK1(0x1F)              , AP(GET,       D____),                                                                                                                   VAL2(MUX_MIN),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                                                   VAL2(COARSE_MAX),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00000001), MASK1(0xF)               , AP(GET,       D____),                                                                                                                   VAL2(COARSE_MIN),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_DQ_REG)                                         ,  BB(DQ,         _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(FINE_SOFT_MAX),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_DQ_REG)                                         ,  BB(DQ,         _00000100)                           , AP(GET,       D____),                                                                                                                   VAL2(FINE_SOFT_MIN),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_DQ_REG)                                         ,  BB(DQ,         _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(FINE_MAX),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_FINECODE_DQ_REG)                                         ,  BB(DQ,         _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(FINE_MIN),
  ASSIGNDONE,
  //
  // maxpi_override_coarse_final
  //
  xxxMx1xx                                        ,                VAL1(PLLCTL_DPIC_REG)                                                 ,  BB(DPIC,       _00001100), MASK2(0x1F0)             , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CODE_STATUS_CH0_CCC_REG)                                 ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH0_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxxE2xx          , VAL2(BXT_P_A0)              ,                VAL2(DLLCOMP_COARSECODE0_CH0_CCC_REG)                                 ,  BB(CCC,        _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE0_CH0),
  xxxME2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(DLLCOMP_COARSECODE0_CH0_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH0_CCC_REG)                                 ,  BB(CCC,        _00001001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE0_CH0_1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CODE_STATUS_CH1_CCC_REG)                                 ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH1_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxxE2xx          , VAL2(BXT_P_A0)              ,                VAL2(DLLCOMP_COARSECODE0_CH1_CCC_REG)                                 ,  BB(CCC,        _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE0_CH1),
  xxxME2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(DLLCOMP_COARSECODE0_CH1_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_CH1_CCC_REG)                                 ,  BB(CCC,        _00001001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE0_CH1_1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CODE_STATUS_ECC_CCC_REG)                                 ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_ECC_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxxE2xx          , VAL2(BXT_P_A0)              ,                VAL2(DLLCOMP_COARSECODE0_ECC_CCC_REG)                                 ,  BB(CCC,        _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE0_ECC),
  xxxME2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(DLLCOMP_COARSECODE0_ECC_CCC_REG)                                 ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_COARSECODE0_ECC_CCC_REG)                                 ,  BB(CCC,        _00001001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_DLLCOMP_COARSECODE0_ECC_1),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_CODE_STATUS_DQ_REG)                                      ,  BB(DQ,         _00000010), MASK1(0xF)               , AP(GET,       D____),                                                                                                                   VAL2(SS_TEMP_VAR),
  xxxMx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00001000), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxxE2xx          , VAL2(BXT_P_A0)              ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DLLCOMP_COARSECODE_1),
  xxxME2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),
  xxxxx2xx                                        ,                VAL2(DLLCOMP_COARSECODE_DQ_REG)                                       ,  BB(DQ,         _00001100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DLLCOMP_COARSECODE_2),
  ASSIGNDONE,
  //
  // WEAK_ODT_SET
  //
  xxxxE1xx          , VAL2(WEAK_ODT_CONFIG)       ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000100)                           , AP(SET,       ____T),                   3,   T(T_DDR3),                                                                                 VAL1(0x7),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x2),                                                                                 T(T_LPDDR4),                                                                               VAL1(0x21),                                                                                 // static_4 :
  ASSIGNDONE,
  //
  // ECC_PHY_INIT
  //
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(CTLECTL1_CCC_REG)                                                ,  BB(CCC,        _00001110), MASK3(0x838070)          , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL3(0x818030),
  ASSIGNDONE,
  //
  // modmem_init_progcmdckctl_seq
  //
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3109),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3107),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // CmdCh0, CmdCh0, CmdCh0
  xxxME1xR          , VAL2(RANK1_ENABLED)         ,                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x215D),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x214B),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // CmdCh0, CmdCh0, CmdCh0
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3109),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3107),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // CmdCh1, CmdCh1, CmdCh1
  xxxME2xR          , VAL2(RANK1_ENABLED)         ,                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x215D),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x214B),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3109),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3207),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3209),                                                                               // CmdCh1, CmdCh1, CmdCh1
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP2CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3107),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3104),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3103),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3002),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3107),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3105),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3107),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3205),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3207),                                                                               // CtlCh0, CtlCh0, CtlCh0
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP2CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3107),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3104),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3103),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3002),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3107),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3105),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x3107),                                                                              FT(F_1866,T_LPDDR3),                                                                       VAL2(0x3205),                                                                              FT(F_1333,T_LPDDR3),                                                                       VAL2(0x3207),                                                                               // CtlCh1, CtlCh1, CtlCh1
  xxxMx1xx                                        ,                VAL1(TXDLLSIGGRP0CTL_CCC_REG)                                         ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3100),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3100),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x23F),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0x336),                                                                               FT(F_1333,T_LPDDR3),                                                                       VAL2(0x33F),                                                                                // ClkCh0, ClkCh0, ClkCh0
  xxxMx2xx                                        ,                VAL2(CH1_TXDLLSIGGRP0CTL_CCC_REG)                                     ,  BB(CCC,        _00000011), MASK2(0x3FFF)            , AP(SET,       __F_T),                   10,   FT(F_1600,T_LPDDR4),                                                                       VAL2(0x3109),                                                                              FT(F_2133,T_LPDDR4),                                                                       VAL2(0x3106),                                                                              FT(F_2400,T_LPDDR4),                                                                       VAL2(0x3105),                                                                              FT(F_2666,T_LPDDR4),                                                                       VAL2(0x3004),                                                                              FT(F_3200,T_LPDDR4),                                                                       VAL2(0x3003),                                                                              FT(F_1333|F_1600,T_DDR3),                                                                  VAL2(0x3100),                                                                              FT(F_1866,T_DDR3),                                                                         VAL2(0x3100),                                                                              FT(F_1600,T_LPDDR3),                                                                       VAL2(0x23F),                                                                               FT(F_1866,T_LPDDR3),                                                                       VAL2(0x336),                                                                               FT(F_1333,T_LPDDR3),                                                                       VAL2(0x33F),                                                                                // ClkCh1, ClkCh1, ClkCh1
  ASSIGNDONE,
  //
  // DunitFreqChangePart1
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x8)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x8),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC0_DUNIT_REG)                                            ,  BB(DUNIT,      _00001000), MASK1(0x1F)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET_DELAY, ____T), VAL4(0x000000C8), 1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                                      ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET_DELAY, ____T), VAL4(0x000007D0), 1,   T(T_LPDDR4),                                                                               VAL1(0x4),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                                      ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),                                                                                  // Poll for the bit to go to zero
  ASSIGNDONE,
  //
  // ChangePHYFreq
  //
  ASSIGNDONE,
  //
  // DunitFreqChangePart3
  //
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00000BB8),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                                      ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET_DELAY, ____T), VAL4(0x00000064), 1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_SR_CMD_DUNIT_REG)                                      ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(POLL,      ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(D_CR_BGF_CTL_DUNIT_REG)                                          ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET_DELAY, ____T), VAL4(0x000000C8), 1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x8)               , AP(SET_DELAY, ____T), VAL4(0x000000C8), 1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  ASSIGNDONE,
  //
  // SetICBitDone
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  ASSIGNDONE,
  //
  // ProgramECCEnable
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRP0_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRP0_4),
  ASSIGNDONE,
  //
  // ReadFuses
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DFUSESTAT_DUNIT_REG)                                        ,  BB(DUNIT,      _00000011)                           , AP(GET,       D____),                                                                                                                   VAL2(FUSESTAT),
  ASSIGNDONE,
  //
  // EnableScrambling
  //
  xxxxx1xx                                        ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                                        ,  BB(DUNIT,      _00001011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_SCRAMCTRL),                                                             // Random Number, Enable Bit
  ASSIGNDONE,
  //
  // SetMrcDoneRemove
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x4),
  ASSIGNDONE,
  //
  // ReadBarAddress
  //
  xxxMx1xx                                        ,                VAL1(MCHBAR_LO_0_0_0_PCI_CUNIT_REG)                                   ,  BB(CUNIT,      _00001110), MASK3(0xFFFF80)          , AP(GET,       D____),                                                                                                                   VAL2(MCHBAR),                                                                               // Read mchbar address
  xxxxx1xx                                        ,                VAL1(SBREG_BAR_P2SB_REG)                                              ,  BB(P2SB,       _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(P2SBBAR),                                                                              // Read PHY base adress
  xxxMx1xx                                        ,                VAL1(PCIEXBAR_LO_0_0_0_PCI_CUNIT_REG)                                 ,  BB(CUNIT,      _00001000), MASK1(0xF0)              , AP(GET,       D____),                                                                                                                   VAL2(ECBASE_LO),                                                                            // Read EC Base LO
  xxxMx1xx                                        ,                VAL1(PCIEXBAR_LO_0_0_0_PCI_CUNIT_REG)                                 ,  BB(CUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(ECBASE_EN),                                                                            // Read EC Base EN
  xxxMx1xx                                        ,                VAL1(PCIEXBAR_HI_0_0_0_PCI_CUNIT_REG)                                 ,  BB(CUNIT,      _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(ECBASE_HI),                                                                            // Read EC Base HI
  ASSIGNDONE,
  //
  // WriteMchBarAddress
  //
  xxxxx1xx                                        ,                VAL1(MCHBAR_LO_0_0_0_PCI_CUNIT_REG)                                   ,  BB(CUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CUNIT_MCHBAR_LO_0_0_0_PCI),                                                        // Write mchbar address, Enable MchBar
  ASSIGNDONE,
  //
  // WriteBarAddress
  //
  xxxxx1xx                                        ,                VAL1(SBREG_BAR_P2SB_REG)                                              ,  BB(P2SB,       _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_P2SB_SBREG_BAR),                                                                   // Write PHY base adress
  xxxxx1xx                                        ,                VAL1(SBREG_BARH_P2SB_REG)                                             ,  BB(P2SB,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxMx1xx                                        ,                VAL1(PCICMD_P2SB_REG)                                                 ,  BB(P2SB,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),
  ASSIGNDONE,
  //
  // SetSliceChannel
  //
  xBxMx2xx                                        ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG)                  , BB2(AUNIT,      _00001000), MASK1(0x80)              , AP(SET,       ____T),                   2,   T(T_DDR3),                                                                                 VAL1(0x80),                                                                                T(T_LPDDR4|T_LPDDR3),                                                                      VAL1(0x0),
  xBxxx2xx                                        ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG)                  , BB2(AUNIT,      _00010001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR),
  xBxxE2xx          , VAL2(BXT_P_POST_A0)         ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG)                  , BB2(AUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_1),
  xBxxx2xx                                        ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG)                  , BB2(AUNIT,      _01110111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_2),
  xxxxx2xx                                        ,                VAL2(A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR_AUNIT_REG)                    ,  BB(AUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR),
  xxxxx2xx                                        ,                VAL2(A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR_AUNIT_REG)                    ,  BB(AUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR),
  xxxxx2xx                                        ,                VAL2(A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR_AUNIT_REG)                ,  BB(AUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR),
  xBxMx2xx                                        ,                VAL2(B_CR_BCTRL2_BUNIT_REG)                                           , BB2(BUNIT,      _00000001), MASK1(0x20)              , AP(SET,       ____T),                   2,   T(T_LPDDR4|T_DDR3),                                                                        VAL1(0x20),                                                                                T(T_LPDDR3),                                                                               VAL1(0x0),
  xBxMx2xx                                        ,                VAL2(B_CR_BCTRL2_BUNIT_REG)                                           , BB2(BUNIT,      _00000001), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xBxxx2xx                                        ,                VAL2(B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR_BUNIT_REG)                    , BB2(BUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR),
  xBxxx2xx                                        ,                VAL2(B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR_BUNIT_REG)                    , BB2(BUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR),
  xBxxx2xx                                        ,                VAL2(B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR_BUNIT_REG)                , BB2(BUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR),
  ASSIGNDONE,
  //
  // LockAunitSliceChannel
  //
  xBxMx2xx                                        ,                VAL2(A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_REG)                  , BB2(AUNIT,      _10000000), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  ASSIGNDONE,
  //
  // DisableDynamicSr
  //
  xxxMx2xx                                        ,                VAL2(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR_PUNIT_REG)              ,  BB(PUNIT,      _00001000), MASK1(0x80)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(P_CR_BIOS_MAILBOX_DATA_0_0_0_MCHBAR_PUNIT_REG)                   ,  BB(PUNIT,      _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x80008000),
  xxxMx2xx                                        ,                VAL2(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR_PUNIT_REG)              ,  BB(PUNIT,      _00001111), MASK4(0x9FFFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x80000021),
  xxxMx2xx                                        ,                VAL2(P_CR_BIOS_MAILBOX_INTERFACE_0_0_0_MCHBAR_PUNIT_REG)              ,  BB(PUNIT,      _00001000), MASK1(0x80)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // ReadPunit
  //
  xxxMx2xx                                        ,                VAL2(P_CR_MEMSS_FREQUENCY_CAPABILITIES1_0_0_0_MCHBAR_PUNIT_REG)       ,  BB(PUNIT,      _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(DDR_CONFIG_LIMITATION),
  xxxxx2xx                                        ,                VAL2(P_CR_SYSTEM_AGENT_FREQUENCY_CAPABILITIES_0_0_0_MCHBAR_PUNIT_REG) ,  BB(PUNIT,      _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(SABY2CLK),
  ASSIGNDONE,
  //
  // SetPunitMemDone
  //
  xxxMx2xx                                        ,                VAL2(P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_REG)                         ,  BB(PUNIT,      _00000100), MASK1(0x8)               , AP(SET,       _____),                                                                                                                   VAL1(0x8),
  ASSIGNDONE,
  //
  // RESETDRAMS
  //
  xxNxx1xx, xxxxxxIx                              , _I(  0)      , VAL1(RXPBDBLCTL0_DQ_REG)                                              ,  BB(DQ,         _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXPBDBLCTL0),
  ASSIGNDONE,
  //
  // ECCClockGate
  //
  xxxMx1xx                                        ,                VAL1(D_CR_SCRAMCTRL_DUNIT_REG)                                        ,  BB(DUNIT,      _00001000), MASK1(0x30)              , AP(SET,       ___C_),                   2,   C(C_POR),                                                                                  VAL1(0x30),                                                                                C(C_PO),                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // HALF_CFG_PWR_GATE
  //
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CLKGATE_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CLKGATE_DPIC_REG)                                    ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH0_CLKREQ_DPIC_REG)                                     ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH0_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x80)              , AP(POLL,      _____),                                                                                                                   VAL1(0x80),
  xxxMx2xx                                        ,                VAL2(DPIC_PM_CH1_CLKREQ_DPIC_REG)                                     ,  BB(DPIC,       _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH1_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x80)              , AP(POLL,      _____),                                                                                                                   VAL1(0x80),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH0_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x1F)              , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                                                 VAL1(0x7),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH0_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH1_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x1F)              , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                                                 VAL1(0x7),
  xxxMx2xx                                        ,                VAL2(DPIC_PMSWMSG_CH1_DPIC_REG)                                       ,  BB(DPIC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  ASSIGNDONE,
  //
  // SwitchTo2N
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DTR3A_DUNIT_REG)                                            ,  BB(DUNIT,      _00000010), MASK1(0x18)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111), MASK4(0xF0FFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x80380000),                                                                           // LP3 is always BL8, LP4 is always BL32, and WIO2 is always BL8, Rank Bit, MRRCMD, Issue Dynamic Command
  xxxMx1xx                                        ,                VAL1(D_CR_DOCRA_DUNIT_REG)                                            ,  BB(DUNIT,      _00000011), MASK2(0x1EF)             , AP(SET,       _____),                                                                                                                   VAL2(0xE1),                                                                                 // Temp value used in SIM, Need value from SI., Temp value used in SIM, Need value from SI.
  xxxME1xx          , VAL2(CMD_RDPTROFFSET_ADJUST),                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_SIGGRPS :
  xxxME2xx          , VAL2(CMD_RDPTROFFSET_ADJUST),                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // static_SIGGRPS :
  ASSIGNDONE,
  //
  // SwitchTo1N
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DTR3A_DUNIT_REG)                                            ,  BB(DUNIT,      _00000010), MASK1(0x18)              , AP(SET,       _____),                                                                                                                   VAL1(0x8),
  xxxMx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111), MASK4(0xF0FFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x380000),                                                                             // LP3 is always BL8, LP4 is always BL32, and WIO2 is always BL8, Rank Bit, MRRCMD, Issue Dynamic Command
  xxxMx1xx                                        ,                VAL1(D_CR_DOCRA_DUNIT_REG)                                            ,  BB(DUNIT,      _00000011), MASK2(0x1EF)             , AP(SET,       _____),                                                                                                                   VAL2(0xC0),                                                                                 // Temp value used in SIM, Need value from SI., Temp value used in SIM, Need value from SI.
  xxxME1xx          , VAL2(CMD_RDPTROFFSET_ADJUST),                VAL1(TXDLLSIGGRP1CTL_CCC_REG)                                         ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_SIGGRPS :
  xxxME2xx          , VAL2(CMD_RDPTROFFSET_ADJUST),                VAL2(CH1_TXDLLSIGGRP1CTL_CCC_REG)                                     ,  BB(CCC,        _00000010), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),                                                                                  // static_SIGGRPS :
  ASSIGNDONE,
  //
  // WRLVLMODE
  //
  xxxxx1xx                                        ,                VAL1(WRLVL_DQ_REG)                                                    ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_WRLVL),
  xxxxx1xx                                        ,                VAL1(WRLVL_CCC_REG)                                                   ,  BB(CCC,        _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_WRLVL),
  ASSIGNDONE,
  //
  // DiffAmpOverride
  //
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                                                   VAL2(CC_DQS_OVR_VAL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                                                   VAL2(CC_DQS_OVR_SEL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                                                   VAL2(CC_DQDM_OVR_VAL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(CC_DQDM_OVR_SEL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                                                   VAL2(BL_DQS_OVR_VAL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                                                   VAL2(BL_DQS_OVR_SEL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                                                   VAL2(BL_DQDM_OVR_VAL),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(BL_DQDM_OVR_SEL),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x1)               , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DQDM_OVR_SEL_ECC),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x4)               , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DQS_OVR_SEL_ECC),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x2)               , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DQDM_OVR_ECC),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0x8)               , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DQS_OVR_ECC),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0xF),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xF)               , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0xF),
  ASSIGNDONE,
  //
  // DiffAmpRestore
  //
  xxxxx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DIFFAMPCTL_BL13_12),
  xxxxx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DIFFAMPCTL_BL02_12),
  xxxxE1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_CCC_DIFFAMPCTL_13),
  ASSIGNDONE,
  //
  // SEND_DRAM_CMD
  //
  xxxxx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRAM_CMD),                                                              // LP3 is always BL8, LP4 is always BL32, and WIO2 is always BL8, Rank Bit, MRRCMD, Issue Dynamic Command
  ASSIGNDONE,
  //
  // CPGC_RUN_KIRK
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000110), MASK2(0x6070)            , AP(SET,       _____),                                                                                                                   VAL2(0x6010),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000001),                                                                                                 VAL1(0x4),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                                                 VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                                        ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(ERROR_STATUS),
  ASSIGNDONE,
  //
  // xyz
  //
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00000011)                           , AP(SUBTASK,   _____),                                                                                                                   VAL2(CPGC_RUN_KIRK),
  ASSIGNDONE,
  //
  // FORCEODT_ON
  //
  ASSIGNDONE,
  //
  // FORCEODT_OFF
  //
  ASSIGNDONE,
  //
  // FORCEODT_REL
  //
  ASSIGNDONE,
  //
  // READTRAINING_EXIT
  //
  ASSIGNDONE,
  //
  // CPGC_DISABLE
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x4),
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // SetAunitSliceChannel
  //
  ASSIGNDONE,
  //
  // CPGC_RUN_TEST_L
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000002),                                                                                                 VAL1(0x4),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_ERR_CTL),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_LNEN_HI_CPGC_REG)                                       ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_ERR_LNEN_HI),                                                            // For B0 and beyond
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000002),                                                                                                 VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                                                 VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                                        ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(BYTEGRP_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)                            ,  BB(CPGC,       _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(CHUNK_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_STAT03_CPGC_REG)                                        ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(LANE_ERR_STAT_LO),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_STAT47_CPGC_REG)                                        ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(LANE_ERR_STAT_HI),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000010), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(ECC_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)                            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(ECC_LANE_ERR_STAT),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_0__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT0),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_1__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT1),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_2__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT2),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_3__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT3),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_4__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT4),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_5__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT5),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_6__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT6),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_7__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT7),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_8__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT8),
  ASSIGNDONE,
  //
  // CPGC_SETUP_ERT
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  ASSIGNDONE,
  //
  // CPGC_EXIT_ERT
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // CPGC_RUN_DIRECT
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x4),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                                                 VAL1(0x1),
  ASSIGNDONE,
  //
  // CPGC_CHECK_ERRORS
  //
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(REG_DATA),
  ASSIGNDONE,
  //
  // CPGC_SETUP_DPAT0
  //
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_0_),
  ASSIGNDONE,
  //
  // CPGC_RUN_TEST
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x4),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                                                 VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                                        ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(BYTEGRP_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)                            ,  BB(CPGC,       _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(CHUNK_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_STAT03_CPGC_REG)                                        ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(LANE_ERR_STAT_LO),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_STAT47_CPGC_REG)                                        ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(LANE_ERR_STAT_HI),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000010), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(ECC_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)                            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(ECC_LANE_ERR_STAT),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_0__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT0),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_1__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT1),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_2__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT2),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_3__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT3),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_4__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT4),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_5__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT5),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_6__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT6),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_7__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT7),
  xxxMx2xx                                        ,                VAL2(CPGC_ERR_CNTR_8__CPGC_REG)                                       ,  BB(CPGC,       _00000111), MASK3(0x7FFFFF)          , AP(GET,       D____),                                                                                                                   VAL2(ERR_COUNT8),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000001F4),
  ASSIGNDONE,
  //
  // CPGC_ENABLE
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCBR_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x4)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00001000), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DSCH_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // set DUNIT to in order mode
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  ASSIGNDONE,
  //
  // CPGC_RESETUP_WRITE_READ
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),                                                                                 // can be removed, for safety
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_1__CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                                                   VAL1(0x81),                                                                                 // can be removed, for safety
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),                                                                                 // can be removed, for safety
  xxxxx1xx                                        ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_BASE_REPEATS),
  xxxxx1xx                                        ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_BLOCK_REPEATS),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  ASSIGNDONE,
  //
  // DQ_DB_REGION_PROGRAM
  //
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL1_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x680C1926),
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL2_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x33404D5A),
  xxxxx1xx                                        ,                VAL1(DBREGIONCTL3_DQDPLVUG_REG)                                       ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xF50A5505),
  ASSIGNDONE,
  //
  // CPGC_SETUP_VA
  //
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAA55AFC0),                                                                           // 0xaa55afc0
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAF0FF00),                                                                           // 0xaaf0ff00
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00000001), MASK1(0xDB)              , AP(SET,       _____),                                                                                                                   VAL1(0x92),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_XTRA_LFSR_CFG_CPGC_REG)                                ,  BB(CPGC,       _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_XTRA_LFSR_CFG),                                                     // LANE_ROTATE_RATE
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0xAAAAAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_XTRA_LFSR_CFG_CPGC_REG)                                ,  BB(CPGC,       _00000111), MASK3(0x9C9C9C)          , AP(SET,       _____),                                                                                                                   VAL3(0x1C1C1C),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00001100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_CFG),                                                               // RELOAD_LFSR_SEED_RATE, SAVE_LFSR_SEED_RATE
  ASSIGNDONE,
  //
  // CPGC_LOOPS
  //
  xxxxx1xx                                        ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_BASE_REPEATS_1),                                                        // NUM_BURSTS
  xxxxx1xx                                        ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_BLOCK_REPEATS_1),                                                       // LOOP_COUNT
  ASSIGNDONE,
  //
  // DRIVE_CKE
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRMC_4),
  ASSIGNDONE,
  //
  // CPGC_STOP_TEST
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x2),
  ASSIGNDONE,
  //
  // DQCALRD
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DQCALRDATLO_DUNIT_REG)                                      ,  BB(DUNIT,      _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(REG_DATA),
  ASSIGNDONE,
  //
  // ENABLE_CKE_OVERRIDE
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRMC_5),
  ASSIGNDONE,
  //
  // PRECHARGEALL
  //
  xxxxx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRAM_CMD_1),
  xxxxx2xx                                        ,                VAL2(D_CR_DRAM_CMD_DUNIT_REG)                                         ,  BB(DUNIT,      _00000111)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL3(0x1B),                                                                                T(T_LPDDR4),                                                                               VAL3(0x30),                                                                                 // precharge all
  ASSIGNDONE,
  //
  // CPGC_TARGET_BANK
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xxxxx2xx                                        ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)                            ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A),
  ASSIGNDONE,
  //
  // CPGC_FIXVAR
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxxx2xx                                        ,                VAL2(CPGC_SEQ_RANK_L2P_MAPPING_CPGC_REG)                              ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_SEQ_RANK_L2P_MAPPING),
  ASSIGNDONE,
  //
  // CPGC_FIXVAR_REVERT
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00000010), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x70),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)                            ,  BB(CPGC,       _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00000100), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_RANK_L2P_MAPPING_CPGC_REG)                              ,  BB(CPGC,       _00000001), MASK1(0x7)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // CPGC_MRS
  //
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00001100), MASK2(0x333)             , AP(SET,       _____),                                                                                                                   VAL2(0x111),                                                                                // pattern buff mode, pattern buff mode, pattern buff mode
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ0_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0xAAAA),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ1_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0xCCCC),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ2_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0xF0F0),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),                                                                                 // MRS mode
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),                                                                                  // set to always on mode
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_MRSCFG_CPGC_REG)                                       ,  BB(CPGC,       _00001111), MASK4(0x30070710)        , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  //  depending on #N mode, not working in RTL, used to strech CA
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_0_),                                                           // 0xa4290
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                                      ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                                                   VAL2(0x4F03),                                                                               // Enable, set to 1, LP3: 0x2 = Rank0; 0x1 = Rank1
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_1_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                                      ,  BB(CPGC,       _00001001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_1_),                                                           // Enable, set to 1, LP3: 0x2 = Rank0; 0x1 = Rank1
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_2_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_3_),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                                      ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                                                   VAL2(0x4F03),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                                      ,  BB(CPGC,       _00001001), MASK2(0x4F03)            , AP(SET,       _____),                                                                                                                   VAL2(0x4F03),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x1),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x000001F4),
  ASSIGNDONE,
  //
  // CPGC_CADB1
  //
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // CADB_BUFA0_BANK, CADB_BUFA0_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x8008888),                                                                            // CADB_BUFA1_BANK, CADB_BUFA1_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x7007777),                                                                            // CADB_BUFA2_BANK, CADB_BUFA2_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0xF00FFFF),                                                                            // CADB_BUFA3_BANK, CADB_BUFA3_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x0),                                                                                  // CADB_BUFA4_BANK, CADB_BUFA4_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0x1001111),                                                                            // CADB_BUFA5_BANK, CADB_BUFA5_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0xE00EEEE),                                                                            // CADB_BUFA6_BANK, CADB_BUFA6_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xF0FFFFF)         , AP(SET,       _____),                                                                                                                   VAL4(0xF00FFFF),                                                                            // CADB_BUFA7_BANK, CADB_BUFA7_ROW_COL
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000000),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000800),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000700),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000F00),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_4__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000000),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_5__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000100),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_6__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000E00),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_7__CPGC_REG)                                      ,  BB(CPGC,       _00001111), MASK4(0xCF0F0F1F)        , AP(SET,       _____),                                                                                                                   VAL4(0x40000F00),                                                                           // 0x0, 0x0, 0x0, 0x0, CADB_BUFB0_CMD, 0x0, 0x0
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00001111), MASK4(0xAFFFFFFF)        , AP(SET,       _____),                                                                                                                   VAL4(0x1C00),                                                                               // 0, 0, 0, 0, 0, 0, 0, 7, 0, f, 1
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00001111), MASK4(0x3330333)         , AP(SET,       _____),                                                                                                                   VAL4(0x2220022),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ0_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x95D9),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ1_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x871E),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ2_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ2_LMN_CPGC_REG)                                  ,  BB(CPGC,       _00001111), MASK4(0x7070773)         , AP(SET,       _____),                                                                                                                   VAL4(0x7070110),
  xxxMx1xx                                        ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)                             ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                                                   VAL4(0x4C00000),
  xxxxx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_ADDRESS_SIZE),
  xxxxx1xx                                        ,                VAL1(CPGC2_ADDRESS_CONTROL_CPGC_REG)                                  ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_ADDRESS_CONTROL),
  ASSIGNDONE,
  //
  // CPGC_DESELECT_DIS
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // 1
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),                                                                                  // 1
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x3C0),                                                                                // 0, f, 1
  xxxxx1xx                                        ,                VAL1(CPGC2_ADDRESS_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x80),
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_CONTROL_CPGC_REG)                                  ,  BB(CPGC,       _00000001), MASK1(0x3F)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00001111), MASK4(0x1FFFF1FF)        , AP(SET,       _____),                                                                                                                   VAL4(0xC5270C5),
  xxxMx1xx                                        ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)                             ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  ASSIGNDONE,
  //
  // CPGC_DESELECT_EN
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_0__CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // 1
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_CTRL_1__CPGC_REG)                    ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),                                                                                 // 1
  xxxxx1xx                                        ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       _____),                                                                                                                   VAL4(0x7),                                                                                  // NUM_BURSTS
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x3D),                                                                                 // 0, f, 1
  xxxxx1xx                                        ,                VAL1(CPGC2_ADDRESS_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xC1),
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x20)              , AP(SET,       _____),                                                                                                                   VAL1(0x20),
  ASSIGNDONE,
  //
  // CPGC_CADB1_BUFA
  //
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_0__1),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_1__1),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_2__1),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_3__1),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_4_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_5_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_6_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFA_7_),
  ASSIGNDONE,
  //
  // CPGC_CADB1_BUFB
  //
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_0_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_1__1),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_2_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_3_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_4__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_4_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_5__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_5_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_6__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_6_),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_BUFB_7__CPGC_REG)                                      ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_BUFB_7_),
  ASSIGNDONE,
  //
  // CPGC_CWL_PATTERN
  //
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_0__1),                                                       // AGG_PATTERN
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_1_),                                                         // VIC_PATTERN
  ASSIGNDONE,
  //
  // CPGC_EXIT_MRS
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_A_CPGC_REG)                                         ,  BB(CPGC,       _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  ASSIGNDONE,
  //
  // CPGC_CADB_MODE
  //
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00001100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_CFG),
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ0_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_UNISEQ0_PBUF),                                                      // LDO_CADB_LFSR0
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ1_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_UNISEQ1_PBUF),                                                      // LDO_CADB_LFSR1
  xxxxx2xx                                        ,                VAL2(CPGC_CADB_UNISEQ2_PBUF_CPGC_REG)                                 ,  BB(CPGC,       _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_CADB_UNISEQ2_PBUF),                                                      // LDO_CADB_LFSR2
  ASSIGNDONE,
  //
  // CPGC_RESETUP_TRAFFIC
  //
  xxxxx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_REG)                         ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_),
  xxxMx1xx                                        ,                VAL1(CPGC2_ALGORITHM_INSTRUCTION_1__CPGC_REG)                         ,  BB(CPGC,       _00000001), MASK1(0x9F)              , AP(SET,       _____),                                                                                                                   VAL1(0x81),                                                                                 // can be removed, for safety
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_1__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x80),                                                                                 // can be removed, for safety
  ASSIGNDONE,
  //
  // CPGC_DPAT_MODE
  //
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_0__2),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_1__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_UNISEQ_1__1),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_DPAT_CFG_1),
  ASSIGNDONE,
  //
  // CPGC_LDO_CADB
  //
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x55555),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0xAAAAA),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0xFFFFF),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x55555),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0xAAAAA),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0xFFFFF),
  ASSIGNDONE,
  //
  // CPGC_LDO_DPAT
  //
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xCC),
  ASSIGNDONE,
  //
  // CPGC_LDO_CADB_LFSR
  //
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_0__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_1__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x19),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_2__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x2A),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_3__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x33),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_4__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x34),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_5__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x2D),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_6__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x1E),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFA_7__CPGC_REG)                                      ,  BB(CPGC,       _00000111), MASK3(0xFFFFF)           , AP(SET,       _____),                                                                                                                   VAL3(0x7),
  ASSIGNDONE,
  //
  // CPGC_LDO_DPAT_LFSR
  //
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_8__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_9__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_10__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_11__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_12__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_13__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_14__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_15__CPGC_REG)                                   ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xAA),
  ASSIGNDONE,
  //
  // EARLY_READ_TRAINING_ENTRY
  //
  ASSIGNDONE,
  //
  // EARLY_READ_TRAINING_EXIT
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x80)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // FINEWRITELEVEL_ENTRY
  //
  xxxxx1xx                                        ,                VAL1(U32_WRDQCTL_DQ_REG)                                              ,  BB(DQ,         _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_WRDQCTL),
  xxxxx1xx                                        ,                VAL1(U32_WRDQSCTL_CC_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_WRDQSCTL_CC),
  xxxxx1xx                                        ,                VAL1(U32_WRDQSCTL_BL_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_WRDQSCTL_BB),
  xxxxx1xx                                        ,                VAL1(U32_WRDQCTL_CCC_REG)                                             ,  BB(CCC,        _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_CC_WRDQCTL),
  xxxxx1xx                                        ,                VAL1(U32_WRDQSCTL_CCC_REG)                                            ,  BB(CCC,        _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_CC_WRDQSCTL),
  ASSIGNDONE,
  //
  // FINEWRITELEVEL_SHAPE
  //
  xxxxx1xx                                        ,                VAL1(WRDQCTL_DQ_REG)                                                  ,  BB(DQ,         _00000011)                           , AP(SET,       _____),                                                                                                                   VAL2(0xFFFF),
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_DDR3),                                                                        VAL1(0x44),                                                                                T(T_LPDDR4),                                                                               VAL1(0x11),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010)                           , AP(SET,       ____T),                   2,   T(T_LPDDR3|T_DDR3),                                                                        VAL1(0x44),                                                                                T(T_LPDDR4),                                                                               VAL1(0x11),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(WRDQCTL_CCC_REG)                                                 ,  BB(CCC,        _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0xFF),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CCC_REG)                                                ,  BB(CCC,        _00000110), MASK2(0x3FF)             , AP(SET,       _____),                                                                                                                   VAL2(0x44),
  ASSIGNDONE,
  //
  // FINEWRITELEVEL_EXIT
  //
  xxxxx1xx                                        ,                VAL1(U32_WRDQCTL_DQ_REG)                                              ,  BB(DQ,         _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_U32_WRDQCTL),
  xxxxx1xx                                        ,                VAL1(U32_WRDQSCTL_CC_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_U32_WRDQSCTL_CC),
  xxxxx1xx                                        ,                VAL1(U32_WRDQSCTL_BL_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_U32_WRDQSCTL_BL),
  xxxxx1xx                                        ,                VAL1(U32_WRDQCTL_CCC_REG)                                             ,  BB(CCC,        _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_U32_WRDQCTL),
  xxxxx1xx                                        ,                VAL1(U32_WRDQSCTL_CCC_REG)                                            ,  BB(CCC,        _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_U32_WRDQSCTL),
  ASSIGNDONE,
  //
  // ENTER_CA_TRAINING
  //
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000001), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(CCCCTL_CCC_REG)                                                  ,  BB(CCC,        _00001000), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC0)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC0)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x30)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x10),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x30)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x10),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x3)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x3)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_INVDCCTL_CPGC_REG)                                     ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_INV_DC_MASK_LO_CPGC_REG)                               ,  BB(CPGC,       _00001111)                           , AP(SET,       D___T),                   1,   T(T_LPDDR4),                                                                               VAL2(DYN_CPGC_CPGC_DPAT_INV_DC_MASK_LO),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_UNISEQ_0__CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_0__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_1__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_2__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_3__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_4__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_5__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_6__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_EXTBUF_7__CPGC_REG)                                    ,  BB(CPGC,       _00000001)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0xAA),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_0__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_1__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_2__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_3__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_4__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_5__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_6__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_BUFB_7__CPGC_REG)                                      ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(CPGC2_COMMAND_INSTRUCTION_0__CPGC_REG)                           ,  BB(CPGC,       _00000001), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x80),
  xxxxx1xx                                        ,                VAL1(CPGC2_BASE_REPEATS_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_BLOCK_REPEATS_CPGC_REG)                                    ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CFG_B_CPGC_REG)                                         ,  BB(CPGC,       _00000011), MASK2(0x3FF)             , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL2(0x20),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x0),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x2),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x3),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x3),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000011), MASK2(0xFF80)            , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL2(0x3E00),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x8)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x8),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x8)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x8),
  ASSIGNDONE,
  //
  // EXIT_CA_TRAINING
  //
  xxxMx1xx                                        ,                VAL1(DIGCTL_DQ_REG)                                                   ,  BB(DQ,         _00000001), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(CCCCTL_CCC_REG)                                                  ,  BB(CCC,        _00001000), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRMC_6),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC0)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC0)              , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x4),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0xC)               , AP(SET_DELAY, ____T), VAL4(0x00000001), 1,   T(T_LPDDR4),                                                                               VAL1(0x4),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x3),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x3),
  xxxMx2xx                                        ,                VAL2(CPGC_CADB_CTL_CPGC_REG)                                          ,  BB(CPGC,       _00000001), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x81)              , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_CC_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x8)               , AP(SET,       ____T),                   2,   T(T_LPDDR4),                                                                               VAL1(0x8),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(WRDQSCTL_BL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x8)               , AP(SET,       ____T),                   2,   T(T_LPDDR4),                                                                               VAL1(0x8),                                                                                 T(T_LPDDR3),                                                                               VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_DPAT_INV_DC_MASK_LO_CPGC_REG)                               ,  BB(CPGC,       _00001111)                           , AP(SET,       ____T),                   1,   T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxxx1xx                                        ,                VAL1(U32_WKPUPPDNCTL_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_U32_WKPUPPDNCTL),
  xxxxx1xx                                        ,                VAL1(U32_WKPUPPDNCTL_CCC_REG)                                         ,  BB(CCC,        _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_U32_WKPUPPDNCTL),
  ASSIGNDONE,
  //
  // ECT_ENTRY
  //
  xxxxx1xx                                        ,                VAL1(U32_WKPUPPDNCTL_DQ_REG)                                          ,  BB(DQ,         _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_DQ_WKCTL),
  xxxxx1xx                                        ,                VAL1(U32_WKPUPPDNCTL_CCC_REG)                                         ,  BB(CCC,        _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(ORIG_CC_WKCTL),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x3F3F3F3F)        , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL4(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x3F3F3F3F)        , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL4(0x0),                                                                                 T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001111), MASK4(0x40404040)        , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL4(0x40404040),                                                                          T(T_LPDDR4),                                                                               VAL4(0x0),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_CCC_REG)                                             ,  BB(CCC,        _00001111), MASK4(0x40404040)        , AP(SET,       ____T),                   2,   T(T_LPDDR3),                                                                               VAL4(0x40404040),                                                                          T(T_LPDDR4),                                                                               VAL4(0x0),
  ASSIGNDONE,
  //
  // RCVEN_ENTRY
  //
  xxxMx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                                                   VAL2(CC_DQSRXODTENOVRVAL),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                                                   VAL2(CC_DQSRXODTENOVRSEL),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                                                   VAL2(CC_RXODTENOVRVAL),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(CC_RXODTENOVRSEL),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xE0)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RXODTSEGOVRVAL_ecc),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0x10)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RXODTSEGOVRSEL_ecc),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                                                   VAL2(BL_DQSRXODTENOVRVAL),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                                                   VAL2(BL_DQSRXODTENOVRSEL),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                                                   VAL2(BL_RXODTENOVRVAL),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(BL_RXODTENOVRSEL),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x40)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_CC_WEAKPUPSTATIC),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_CC_WEAKPUP),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x40)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_CC_WEAKPDNSTATIC),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_CC_WEAKPDN),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_BL_WEAKPUPSTATIC),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_BL_WEAKPUP),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000001), MASK1(0x40)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_BL_WEAKPDNSTATIC),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(LVL_BL_WEAKPDN),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x5),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x10),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x5),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x3F)              , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0xA),                                                                                 T(T_LPDDR4),                                                                               VAL1(0xF),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000100), MASK1(0x3F)              , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0xA),                                                                                 T(T_LPDDR4),                                                                               VAL1(0xF),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000010), MASK1(0x3F)              , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0xA),                                                                                 T(T_LPDDR4),                                                                               VAL1(0xF),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000001), MASK1(0x40)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxMx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(SET,       ____T),                   2,   T(T_DDR3|T_LPDDR3),                                                                        VAL1(0xA),                                                                                 T(T_LPDDR4),                                                                               VAL1(0xF),
  ASSIGNDONE,
  //
  // RCVEN_EXIT
  //
  xxxxx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXODTCTL_BL13_7),
  xxxxE1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_CCC_RXODTSEGCTL_7),
  xxxxx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXODTCTL_DQ_7),
  xxxxx1xx                                        ,                VAL1(WKPUPPDNCTL_DQ_REG)                                              ,  BB(DQ,         _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_WKPUPPDNCTL),
  ASSIGNDONE,
  //
  // VOC_TRAINING_ENTRY
  //
  xxNMx1xx, xxxxxxIx                              , _I(  0)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP0_dq0),
  xxNMx1xx, xxxxxxIx                              , _I(  0)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP0_dq0),
  xxNMx1xx, xxxxxxIx                              , _I(  0)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP1_dq0),
  xxNMx1xx, xxxxxxIx                              , _I(  0)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP1_dq0),
  xxNMx1xx, xxxxxxIx                              , _I(  1)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP0_dq1),
  xxNMx1xx, xxxxxxIx                              , _I(  1)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP0_dq1),
  xxNMx1xx, xxxxxxIx                              , _I(  1)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP1_dq1),
  xxNMx1xx, xxxxxxIx                              , _I(  1)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP1_dq1),
  xxNMx1xx, xxxxxxIx                              , _I(  2)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001000), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Up_GRP0_dq2),
  xxNMx1xx, xxxxxxIx                              , _I(  2)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000100), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Dn_GRP0_dq2),
  xxNMx1xx, xxxxxxIx                              , _I(  2)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000010), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Up_GRP1_dq2),
  xxNMx1xx, xxxxxxIx                              , _I(  2)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000001), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Dn_GRP1_dq2),
  xxNMx1xx, xxxxxxIx                              , _I(  3)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001000), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Up_GRP0_dq3),
  xxNMx1xx, xxxxxxIx                              , _I(  3)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000100), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Dn_GRP0_dq3),
  xxNMx1xx, xxxxxxIx                              , _I(  3)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000010), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Up_GRP1_dq3),
  xxNMx1xx, xxxxxxIx                              , _I(  3)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000001), MASK1(0x7F)              , AP(GET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(RCOMP_Dn_GRP1_dq3),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP0),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP0),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP1),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP1),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP2),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP2),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP3),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP3),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001000), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP4),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000100), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP4),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000010), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Up_GRP5),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x7F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Dn_GRP5),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000010), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_OVR_Up_En),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_OVR_Dn_En),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_OVR_Up_En_dq),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000010), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_OVR_Dn_En_dq),
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00001000), MASK1(0xE0)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Seg_Ovr_Val_bl),
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00001000), MASK1(0x10)              , AP(GET,       D____),                                                                                                                   VAL2(RCOMP_Seg_Ovr_En_bl),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x8)               , AP(GET,       D____),                                                                                                                   VAL2(DIFF_Ovr_Val_bl),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0x4)               , AP(GET,       D____),                                                                                                                   VAL2(DIFF_Ovr_Val_sel_bl),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00001000)                           , AP(GET,       D____),                                                                                                                   VAL2(comp_vref_0),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000100)                           , AP(GET,       D____),                                                                                                                   VAL2(comp_vref_1),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(comp_vref_2),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(comp_vref_3),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(comp_vref_4),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(comp_vref_5),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(RX_ODTEN_OVR_SEL_bl),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x2)               , AP(GET,       D____),                                                                                                                   VAL2(RX_ODTEN_OVR_VAL_bl),
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0x10)              , AP(GET,       D____),                                                                                                                   VAL2(ECC_RX_ODTEN_OVR_SEL_bl),
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xE0)              , AP(GET,       D____),                                                                                                                   VAL2(ECC_RX_ODTEN_OVR_VAL_bl),
  xxxxx1xx                                        ,                VAL1(VREFCTL0_DQ_REG)                                                 ,  BB(DQ,         _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(RXBLVREFCTL),
  ASSIGNDONE,
  //
  // VOC_GET_LDO_ENABLE
  //
  xxxMx1xx                                        ,                VAL1(TXFB_LDO_REG)                                                    ,  BB(LDO,        _00000100), MASK1(0x4)               , AP(GET,       D____),                                                                                                                   VAL2(VOC_LDO_ENABLE),
  ASSIGNDONE,
  //
  // VOC_PHY_ENTRY
  //
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                                                   VAL2(0x0),
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00001000), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x70),                                                                                 // static_DIGREGS : , static_DIGREGS :
  xxxMx1xx                                        ,                VAL1(RXODTSEGCTL_BL13_DQ_REG)                                         ,  BB(DQ,         _00001000), MASK1(0xF0)              , AP(SET,       _____),                                                                                                                   VAL1(0x70),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000), MASK1(0xC)               , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0xC),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0xC)               , AP(SET,       _____),                                                                                                                   VAL1(0xC),
  xxxMx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000), MASK1(0xC)               , AP(SET,       _____),                                                                                                                   VAL1(0xC),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(OFFSETCNCLCTRL1_CCC_REG)                                         ,  BB(CCC,        _00000100), MASK1(0x80)              , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x80),
  xxxMx1xx                                        ,                VAL1(OFFSETCNCLCTRL1_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(OFFSETCNCLCTRL3_DQ_REG)                                          ,  BB(DQ,         _00000010), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTCTL_CCC_REG)                                                ,  BB(CCC,        _00001000), MASK1(0x3)               , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x1),
  xxxME1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000), MASK1(0xF0)              , AP(SET,       ____T),                   1,   T(T_DDR3),                                                                                 VAL1(0x70),                                                                                 // Needs to be a 3, to match the DQ modules. Without this fix, the ECC DQS was not going to a reasonable common mode (about middle of VDDQ, but was in fact being pulled low). This would make it where the whole VOC/RXVREF sweep during VOC training would be 'out of range' of the low common mode. So this is one reason VOC training didn't work.
  ASSIGNDONE,
  //
  // VOC_COMP_VREF_AND_INIT
  //
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000100)                           , AP(SET_DELAY, D____), VAL4(0x00002710),                                                                                                 VAL2(DYN_DPLVUG_DPIC_GRCOMP_VREF_0),
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                                                 VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(DPIC_GRCOMP_INIT_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000001), MASK1(0x1)               , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // VOC_GET_RCOMP_PUP_VALUE
  //
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(VOC_RCOMP_PUP),
  ASSIGNDONE,
  //
  // VOC_GET_RCOMP_PDN_VALUE
  //
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_CODES_0_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(VOC_RCOMP_PDN),
  ASSIGNDONE,
  //
  // VOC_SET_ODT_RCOMP_OVERRIDE
  //
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_4),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_4),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                                                   VAL2(0x3F3F),
  xxxMx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000011), MASK2(0x3F3F)            , AP(SET,       _____),                                                                                                                   VAL2(0x3F3F),
  ASSIGNDONE,
  //
  // VOC_ENABLE_WLMODE
  //
  xxxMx1xx                                        ,                VAL1(WRLVL_DQ_REG)                                                    ,  BB(DQ,         _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x3),
  xxxMx1xx                                        ,                VAL1(WRLVL_CCC_REG)                                                   ,  BB(CCC,        _00001000), MASK1(0xE)               , AP(SET,       _____),                                                                                                                   VAL1(0xE),
  ASSIGNDONE,
  //
  // VOC_DISABLE_WLMODE
  //
  xxxMx1xx                                        ,                VAL1(WRLVL_DQ_REG)                                                    ,  BB(DQ,         _00001000), MASK1(0x3)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(WRLVL_CCC_REG)                                                   ,  BB(CCC,        _00001000), MASK1(0xE)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // VOC_TRAINING_EXIT
  //
  xxNxx1xx, xxxxxxIx                              , _I(  0)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_5),
  xxNxx1xx, xxxxxxIx                              , _I(  1)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_6),
  xxNxx1xx, xxxxxxIx                              , _I(  2)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_7),
  xxNxx1xx, xxxxxxIx                              , _I(  3)      , VAL1(DPIC_LRCOMP_OVR1_DQDPLVUG_REG)                                   ,  BB(DQDPLVUG,   _00001111)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_8),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR1_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR1_5),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR2_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR2_4),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_OVR3_DPLVUG_REG)                                     ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_OVR3_4),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_PUPDOVR),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DQDPLVUG_REG)                                ,  BB(DQDPLVUG,   _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_DPIC_LRCOMP_PUPDOVR),
  xxxxx1xx                                        ,                VAL1(DPIC_LRCOMP_PUPDOVR_DPLVUG_REG)                                  ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_LRCOMP_PUPDOVR_1),
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_BL02_DQ_REG)                                         ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXODTSEGCTL_BL02_7),
  xxxxx1xx                                        ,                VAL1(DIFFAMPCTL_BL02_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DIFFAMPCTL_BL02_13),
  xxxxx1xx                                        ,                VAL1(RXODTSEGCTL_BL13_DQ_REG)                                         ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXODTSEGCTL_BL13_7),
  xxxxx1xx                                        ,                VAL1(DIFFAMPCTL_BL13_DQ_REG)                                          ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_DIFFAMPCTL_BL13_13),
  xxxxE1xx          , VAL2(ECCEN)                 ,                VAL1(DIFFAMPCTL_CCC_REG)                                              ,  BB(CCC,        _00001000)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_CCC_DIFFAMPCTL_14),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_0_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_GRCOMP_VREF_0_1),
  xxxxx1xx                                        ,                VAL1(DPIC_GRCOMP_VREF_1_DPLVUG_REG)                                   ,  BB(DPLVUG,     _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DPLVUG_DPIC_GRCOMP_VREF_1),
  xxxxx1xx                                        ,                VAL1(RXODTCTL_DQ_DQ_REG)                                              ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXODTCTL_DQ_8),
  xxxxE1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTSEGCTL_CCC_REG)                                             ,  BB(CCC,        _00001000)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_CCC_RXODTSEGCTL_8),
  xxxxE1xx          , VAL2(ECCEN)                 ,                VAL1(RXODTCTL_CCC_REG)                                                ,  BB(CCC,        _00001000)                           , AP(SET,       D___T),                   1,   T(T_DDR3),                                                                                 VAL2(DYN_CCC_RXODTCTL_7),
  xxxxx1xx                                        ,                VAL1(RXODTCTL_BL13_DQ_REG)                                            ,  BB(DQ,         _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_RXODTCTL_BL13_8),
  xxxxx1xx                                        ,                VAL1(VREFCTL0_DQ_REG)                                                 ,  BB(DQ,         _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_VREFCTL0),
  xxxxx1xx                                        ,                VAL1(VREFCTL2_CCC_REG)                                                ,  BB(CCC,        _00001000)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_VREFCTL2),
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_START
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRMC_7),
  xxxMx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(TQPOLLEN_SAVE),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x60)              , AP(GET,       D____),                                                                                                                   VAL2(SRXZQC_SAVE),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(ZQDIS_SAVE),
  xxxMx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(OREFDIS_SAVE),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC0_DUNIT_REG)                                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(DYNSREN_SAVE),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(DISPWRDN_SAVE),
  xxxMx2xx                                        ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)                               ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(GET,       D____),                                                                                                                   VAL2(DQS_RETAIN_EN_SAVE),
  xxxMx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100), MASK1(0x61)              , AP(SET,       _____),                                                                                                                   VAL1(0x61),
  xxxMx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC0_DUNIT_REG)                                            ,  BB(DUNIT,      _00000100), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x1),
  xxxxx2xx                                        ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)                               ,  BB(DUNIT,      _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_1),                                                  // ame value as LPDDR4 MR23, 500ns? Chris Mozak. Should not larger than interval
  xxxMx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x70)              , AP(SET,       _____),                                                                                                                   VAL1(0x30),
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx2xx                                        ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)                               ,  BB(DUNIT,      _00000001), MASK1(0x1)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_READ
  //
  xxxMx1xx                                        ,                VAL1(RDVLDCTL_DQ_REG)                                                 ,  BB(DQ,         _00000001), MASK1(0x3F)              , AP(GET,       D____),                                                                                                                   VAL2(RDCMD2RDVLD),
  xxxxx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00000011)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_PTCTL0_6),
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_MNT_DIS
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxxx1xx                                        ,                VAL1(0xFF)                                                            ,  BB(0xFF,       _00001111)                         , AP(DELAY,     _____), VAL4(0x00002710),
  xxxMx1xx                                        ,                VAL1(D_CR_DRMC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001), MASK1(0x10)              , AP(SET,       _____),                                                                                                                   VAL1(0x10),
  xxxxx1xx                                        ,                VAL1(D_CR_TQCTL_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_TQCTL_2),
  xxxxx1xx                                        ,                VAL1(D_CR_DCAL_DUNIT_REG)                                             ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DCAL),
  xxxxx1xx                                        ,                VAL1(D_CR_DRFC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DRFC_2),
  xxxxx1xx                                        ,                VAL1(D_CR_DPMC0_DUNIT_REG)                                            ,  BB(DUNIT,      _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DPMC0),
  xxxxx1xx                                        ,                VAL1(D_CR_DPMC1_DUNIT_REG)                                            ,  BB(DUNIT,      _00000001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DPMC1_1),
  xxxxx2xx                                        ,                VAL2(D_CR_DQS_RETRAINING_CTL_DUNIT_REG)                               ,  BB(DUNIT,      _00001101)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_2),
  ASSIGNDONE,
  //
  // PERIODIC_TRAINING_EN
  //
  xxxxx1xx                                        ,                VAL1(D_CR_DTR4A_DUNIT_REG)                                            ,  BB(DUNIT,      _00000110)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR4A_1),
  xxxxx1xx                                        ,                VAL1(D_CR_DTR6A_DUNIT_REG)                                            ,  BB(DUNIT,      _00000010)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DUNIT_D_CR_DTR6A_1),                                                               // RL + tDQSCK +MRR/MRW BL/2 + 1
  xxxxx1xx                                        ,                VAL1(PTCTL0_DQDPLVUG_REG)                                             ,  BB(DQDPLVUG,   _00001001)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQDPLVUG_PTCTL0_7),
  ASSIGNDONE,
  //
  // CPGC_GET_TEST_RESULT
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_STATUS_CPGC_REG)                                        ,  BB(CPGC,       _00001000), MASK1(0x40)              , AP(POLL,      _____),                                                                                                                   VAL1(0x0),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_BYTE_NTH_PAR_STAT_CPGC_REG)                             ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(BYTEGRP_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)                            ,  BB(CPGC,       _00000010)                           , AP(GET,       D____),                                                                                                                   VAL2(CHUNK_ERR_STAT),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_STAT03_CPGC_REG)                                        ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(LANE_ERR_STAT_LO),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_STAT47_CPGC_REG)                                        ,  BB(CPGC,       _00001111)                           , AP(GET,       D____),                                                                                                                   VAL2(LANE_ERR_STAT_HI),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_ECC_CHNK_RANK_STAT_CPGC_REG)                            ,  BB(CPGC,       _00000001)                           , AP(GET,       D____),                                                                                                                   VAL2(ECC_ERR_STAT),
  ASSIGNDONE,
  //
  // CPGC_SET_CHUNK_MASK
  //
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC_ERR_CTL_1),
  ASSIGNDONE,
  //
  // CPGC_STOP_CLEAR_ERR
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x2)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x2),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x4)               , AP(SET_DELAY, _____), VAL4(0x00000014),                                                                                                 VAL1(0x4),
  ASSIGNDONE,
  //
  // CPGC_START_TEST
  //
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_CTL_CPGC_REG)                                           ,  BB(CPGC,       _00000001), MASK1(0x1)               , AP(SET_DELAY, _____), VAL4(0x00000064),                                                                                                 VAL1(0x1),
  ASSIGNDONE,
  //
  // gen_rxpbden_set
  //
  xxxxx1xx                                        ,                VAL1(TXPBDCTL1_DQ_REG)                                                ,  BB(DQ,         _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_DQ_TXPBDCTL1),                                                                     // static_DIGREGS : , static_DIGREGS :
  xxxxx1xx                                        ,                VAL1(TXPBDCTL1_CCC_REG)                                               ,  BB(CCC,        _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_TXPBDCTL1),                                                                    // static_DIGREGS : , static_DIGREGS :
  xxxxx2xx                                        ,                VAL2(ECC_TXPBDCTL1_CCC_REG)                                           ,  BB(CCC,        _00000100)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CCC_ECC_TXPBDCTL1),                                                                // static_DIGREGS :
  ASSIGNDONE,
  //
  // CPGC_ECC_EN
  //
  xxxMx2xx                                        ,                VAL2(CPGC_DPAT_CFG_CPGC_REG)                                          ,  BB(CPGC,       _00000010), MASK1(0xE0)              , AP(SET,       _____),                                                                                                                   VAL1(0x40),
  xxxxx2xx                                        ,                VAL2(CPGC_ERR_XLNEN_CPGC_REG)                                         ,  BB(CPGC,       _00000001)                           , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  xxxMx1xx                                        ,                VAL1(D_CR_DTRC_DUNIT_REG)                                             ,  BB(DUNIT,      _00000010), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  ASSIGNDONE,
  //
  // MEM_INIT
  //
  xxxMx1xx                                        ,                VAL1(CPGC2_BASE_ADDRESS_CONTROL_CPGC_REG)                             ,  BB(CPGC,       _00001111), MASK4(0x7FFFBF0)         , AP(SET,       _____),                                                                                                                   VAL4(0x0),
  xxxxx1xx                                        ,                VAL1(CPGC2_ADDRESS_SIZE_CPGC_REG)                                     ,  BB(CPGC,       _00001111)                           , AP(SET,       D____),                                                                                                                   VAL2(DYN_CPGC_CPGC2_ADDRESS_SIZE_1),
  xxxMx2xx                                        ,                VAL2(CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_REG)                            ,  BB(CPGC,       _00000001), MASK1(0xF)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // MNTEN_SET
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x2),
  ASSIGNDONE,
  //
  // MNTEN_CLR
  //
  xxxMx1xx                                        ,                VAL1(D_CR_DCO_DUNIT_REG)                                              ,  BB(DUNIT,      _00000001), MASK1(0x2)               , AP(SET,       _____),                                                                                                                   VAL1(0x0),
  ASSIGNDONE,
  //
  // READTRAINING_ENTRY
  //
  ASSIGNDONE,
};

MMRC_STATUS
DynamicAssignmentGenerated (
  IN  OUT   UINT32        DynamicVars[MAX_CHANNELS][DYNVAR_MAX],
  IN        UINT8         Channel,
  IN        UINT16        Index,
  IN        UINTX        *Value
)
{
  P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_STRUCT *DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR;
  DIGCTL_CCC_STRUCT *DYNSTRUCT_CCC_DIGCTL;
  CH1_DIGCTL_CCC_STRUCT *DYNSTRUCT_CCC_CH1_DIGCTL;
  DIGCTL_DQ_STRUCT *DYNSTRUCT_DQ_DIGCTL;
  WRDQSCTL_CCC_STRUCT *DYNSTRUCT_CCC_WRDQSCTL;
  RDVLDCTL_CCC_STRUCT *DYNSTRUCT_CCC_RDVLDCTL;
  RK2RKCTL0_CCC_STRUCT *DYNSTRUCT_CCC_RK2RKCTL0;
  RXDLLRDCMDCTL0_CCC_STRUCT *DYNSTRUCT_CCC_RXDLLRDCMDCTL0;
  WRDQSCTL_CC_DQ_STRUCT *DYNSTRUCT_DQ_WRDQSCTL_CC;
  WRDQSCTL_BL_DQ_STRUCT *DYNSTRUCT_DQ_WRDQSCTL_BL;
  RDVLDCTL_DQ_STRUCT *DYNSTRUCT_DQ_RDVLDCTL;
  RK2RKCTL0_DQ_STRUCT *DYNSTRUCT_DQ_RK2RKCTL0;
  RXDLLRDCMDCTL0_DQ_STRUCT *DYNSTRUCT_DQ_RXDLLRDCMDCTL0;
  RXODTSEGCTL_CCC_STRUCT *DYNSTRUCT_CCC_RXODTSEGCTL;
  RXODTCTL_CCC_STRUCT *DYNSTRUCT_CCC_RXODTCTL;
  RCVENCTL_CCC_STRUCT *DYNSTRUCT_CCC_RCVENCTL;
  DIFFAMPCTL_CCC_STRUCT *DYNSTRUCT_CCC_DIFFAMPCTL;
  FIFOPTRCTL_DQ_STRUCT *DYNSTRUCT_DQ_FIFOPTRCTL;
  RXODTSEGCTL_BL13_DQ_STRUCT *DYNSTRUCT_DQ_RXODTSEGCTL_BL13;
  RXODTSEGCTL_BL02_DQ_STRUCT *DYNSTRUCT_DQ_RXODTSEGCTL_BL02;
  RXODTCTL_BL13_DQ_STRUCT *DYNSTRUCT_DQ_RXODTCTL_BL13;
  RXODTCTL_DQ_DQ_STRUCT *DYNSTRUCT_DQ_RXODTCTL_DQ;
  RCVENCTL_BL13_DQ_STRUCT *DYNSTRUCT_DQ_RCVENCTL_BL13;
  RCVENCTL_BL02_DQ_STRUCT *DYNSTRUCT_DQ_RCVENCTL_BL02;
  DIFFAMPCTL_BL13_DQ_STRUCT *DYNSTRUCT_DQ_DIFFAMPCTL_BL13;
  DIFFAMPCTL_BL02_DQ_STRUCT *DYNSTRUCT_DQ_DIFFAMPCTL_BL02;
  PTCTL0_DQDPLVUG_STRUCT *DYNSTRUCT_DQDPLVUG_PTCTL0;
  DPIC_GRCOMP_CFG3_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_GRCOMP_CFG3;
  PLLCTL_DPIC_STRUCT *DYNSTRUCT_DPIC_PLLCTL;
  DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1;
  DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1;
  DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2;
  DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3;
  D_CR_DRP0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRP0;
  D_CR_DTR0A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR0A;
  D_CR_DTR1A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR1A;
  D_CR_DTR2A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR2A;
  D_CR_DTR3A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR3A;
  D_CR_DTR4A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR4A;
  D_CR_DTR5A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR5A;
  D_CR_DTR6A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR6A;
  D_CR_DTR7A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR7A;
  D_CR_DTR8A_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DTR8A;
  D_CR_SSKPD0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_SSKPD0;
  D_CR_BONUS0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BONUS0;
  D_CR_BONUS1_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BONUS1;
  D_CR_MR4_DESWIZZLE_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE;
  D_CR_DOCRA_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DOCRA;
  D_CR_DRMC_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRMC;
  D_CR_BGF_CTL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BGF_CTL;
  D_CR_DRFC_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRFC;
  D_CR_DPMC1_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DPMC1;
  D_CR_DSCH_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DSCH;
  D_CR_BGF_CUSTOM_TSV_CMD_PATTERN_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_PATTERN;
  D_CR_BGF_CUSTOM_TSV_CMD_INIT_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_INIT;
  D_CR_BGF_CUSTOM_TSV_DATA_PATTERN_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_PATTERN;
  D_CR_BGF_CUSTOM_TSV_DATA_INIT_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_INIT;
  D_CR_TQCTL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_TQCTL;
  D_CR_TQOFFSET_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_TQOFFSET;
  D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL;
  DLLCOMP_FBMUXSEL_DQ_STRUCT *DYNSTRUCT_DQ_DLLCOMP_FBMUXSEL;
  DLLCOMP_FBMUXSEL1_CCC_STRUCT *DYNSTRUCT_CCC_DLLCOMP_FBMUXSEL1;
  DLLCOMP_FINECODE_DQ_STRUCT *DYNSTRUCT_DQ_DLLCOMP_FINECODE;
  DLLCOMP_FINECODE_CCC_STRUCT *DYNSTRUCT_CCC_DLLCOMP_FINECODE;
  DLLCOMP_COARSECODE_DQ_STRUCT *DYNSTRUCT_DQ_DLLCOMP_COARSECODE;
  DLLCOMP_COARSECODE1_CCC_STRUCT *DYNSTRUCT_CCC_DLLCOMP_COARSECODE1;
  DLLCOMP_COARSECODE0_CH0_CCC_STRUCT *DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH0;
  DLLCOMP_COARSECODE0_CH1_CCC_STRUCT *DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH1;
  DLLCOMP_COARSECODE0_ECC_CCC_STRUCT *DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_ECC;
  D_CR_SCRAMCTRL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL;
  MCHBAR_LO_0_0_0_PCI_CUNIT_STRUCT *DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI;
  SBREG_BAR_P2SB_STRUCT *DYNSTRUCT_P2SB_SBREG_BAR;
  A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_STRUCT *DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR;
  A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR_AUNIT_STRUCT *DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR;
  A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR_AUNIT_STRUCT *DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR;
  A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR_AUNIT_STRUCT *DYNSTRUCT_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR;
  B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR_BUNIT_STRUCT *DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR;
  B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR_BUNIT_STRUCT *DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR;
  B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR_BUNIT_STRUCT *DYNSTRUCT_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR;
  RXPBDBLCTL0_DQ_STRUCT *DYNSTRUCT_DQ_RXPBDBLCTL0;
  WRLVL_DQ_STRUCT *DYNSTRUCT_DQ_WRLVL;
  WRLVL_CCC_STRUCT *DYNSTRUCT_CCC_WRLVL;
  D_CR_DRAM_CMD_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DRAM_CMD;
  CPGC_ERR_CTL_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_ERR_CTL;
  CPGC_ERR_LNEN_HI_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_ERR_LNEN_HI;
  CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_;
  CPGC2_BASE_REPEATS_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS;
  CPGC2_BLOCK_REPEATS_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS;
  CPGC_DPAT_XTRA_LFSR_CFG_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_XTRA_LFSR_CFG;
  CPGC_DPAT_CFG_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_CFG;
  CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A;
  CPGC_SEQ_RANK_L2P_MAPPING_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_SEQ_RANK_L2P_MAPPING;
  CPGC_CADB_BUFA_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_;
  CPGC_CADB_BUFA_1__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_;
  CPGC_CADB_BUFB_1__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_;
  CPGC_CADB_BUFA_2__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_;
  CPGC_CADB_BUFA_3__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_;
  CPGC2_ADDRESS_SIZE_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE;
  CPGC2_ADDRESS_CONTROL_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_ADDRESS_CONTROL;
  CPGC_CADB_BUFA_4__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_;
  CPGC_CADB_BUFA_5__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_;
  CPGC_CADB_BUFA_6__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_;
  CPGC_CADB_BUFA_7__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_;
  CPGC_CADB_BUFB_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_;
  CPGC_CADB_BUFB_2__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_;
  CPGC_CADB_BUFB_3__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_;
  CPGC_CADB_BUFB_4__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_;
  CPGC_CADB_BUFB_5__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_;
  CPGC_CADB_BUFB_6__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_;
  CPGC_CADB_BUFB_7__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_;
  CPGC_DPAT_UNISEQ_1__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_;
  CPGC_CADB_CFG_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_CFG;
  CPGC_CADB_UNISEQ0_PBUF_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ0_PBUF;
  CPGC_CADB_UNISEQ1_PBUF_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ1_PBUF;
  CPGC_CADB_UNISEQ2_PBUF_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ2_PBUF;
  CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_;
  U32_WRDQCTL_DQ_STRUCT *DYNSTRUCT_DQ_U32_WRDQCTL;
  U32_WRDQSCTL_CC_DQ_STRUCT *DYNSTRUCT_DQ_U32_WRDQSCTL_CC;
  U32_WRDQSCTL_BL_DQ_STRUCT *DYNSTRUCT_DQ_U32_WRDQSCTL_BL;
  U32_WRDQCTL_CCC_STRUCT *DYNSTRUCT_CCC_U32_WRDQCTL;
  U32_WRDQSCTL_CCC_STRUCT *DYNSTRUCT_CCC_U32_WRDQSCTL;
  CPGC_DPAT_INV_DC_MASK_LO_CPGC_STRUCT *DYNSTRUCT_CPGC_CPGC_DPAT_INV_DC_MASK_LO;
  U32_WKPUPPDNCTL_DQ_STRUCT *DYNSTRUCT_DQ_U32_WKPUPPDNCTL;
  U32_WKPUPPDNCTL_CCC_STRUCT *DYNSTRUCT_CCC_U32_WKPUPPDNCTL;
  WKPUPPDNCTL_DQ_STRUCT *DYNSTRUCT_DQ_WKPUPPDNCTL;
  DPIC_GRCOMP_VREF_0_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0;
  DPIC_LRCOMP_PUPDOVR_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR;
  DPIC_LRCOMP_PUPDOVR_DQDPLVUG_STRUCT *DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_PUPDOVR;
  DPIC_GRCOMP_VREF_1_DPLVUG_STRUCT *DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1;
  VREFCTL0_DQ_STRUCT *DYNSTRUCT_DQ_VREFCTL0;
  VREFCTL2_CCC_STRUCT *DYNSTRUCT_CCC_VREFCTL2;
  D_CR_DCAL_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DCAL;
  D_CR_DPMC0_DUNIT_STRUCT *DYNSTRUCT_DUNIT_D_CR_DPMC0;
  TXPBDCTL1_DQ_STRUCT *DYNSTRUCT_DQ_TXPBDCTL1;
  TXPBDCTL1_CCC_STRUCT *DYNSTRUCT_CCC_TXPBDCTL1;
  ECC_TXPBDCTL1_CCC_STRUCT *DYNSTRUCT_CCC_ECC_TXPBDCTL1;

  switch (Index) {
  case DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR:
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR = (P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_STRUCT *) Value;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch3_active = DynamicVars[Channel][FM_CH3];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch2_active = DynamicVars[Channel][FM_CH2];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch1_active = DynamicVars[Channel][FM_CH1];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.fm_ch0_active = DynamicVars[Channel][FM_CH0];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.wio_only = 0x0;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_type_special = 0x0;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_type = DynamicVars[Channel][PUNIT_REQ_TYPE];
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_data = DynamicVars[Channel][PUNIT_REQ_DATA];
    break;
  case DYN_CCC_DIGCTL:
    DYNSTRUCT_CCC_DIGCTL = (DIGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIGCTL->Bits.stretchmode = DynamicVars[Channel][str_m];
    break;
  case DYN_CCC_CH1_DIGCTL:
    DYNSTRUCT_CCC_CH1_DIGCTL = (CH1_DIGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_CH1_DIGCTL->Bits.ch1_rdmcpsel = 0x1;
    DYNSTRUCT_CCC_CH1_DIGCTL->Bits.ch1_reserved = DynamicVars[Channel][RSVD];
    break;
  case DYN_DQ_DIGCTL:
    DYNSTRUCT_DQ_DIGCTL = (DIGCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIGCTL->Bits.stretchmode = DynamicVars[Channel][str_m];
    break;
  case DYN_CCC_WRDQSCTL:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.dqsdrvenbpream0 = 0x3;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.dmdrven = 0x1;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrpream0en = DynamicVars[Channel][WRPREAM0EN];
    DYNSTRUCT_CCC_WRDQSCTL->Bits.dqsdrvenbidle = 0x3;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.dqsdataph1 = 0x1;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.dqsdatapream1 = 0x1;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.dqsdatalastph = 0x1;
    break;
  case DYN_CCC_WRDQSCTL_1:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_CCC_WRDQSCTL_2:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = DynamicVars[Channel][WL]-4;
    break;
  case DYN_CCC_WRDQSCTL_3:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = DynamicVars[Channel][WL]-2;
    break;
  case DYN_CCC_WRDQSCTL_4:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_CCC_WRDQSCTL_5:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-3+3):(DynamicVars[Channel][WL]);
    break;
  case DYN_CCC_WRDQSCTL_6:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]+1):(DynamicVars[Channel][WL]);
    break;
  case DYN_CCC_WRDQSCTL_7:
    DYNSTRUCT_CCC_WRDQSCTL = (WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRDQSCTL->Bits.wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-3):(DynamicVars[Channel][WL]-4);
    break;
  case DYN_CCC_RDVLDCTL:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = (((DynamicVars[Channel][RL]+1)/2)-1)+2;
    break;
  case DYN_CCC_RDVLDCTL_1:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+8)/2-4);
    break;
  case DYN_CCC_RDVLDCTL_2:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+9)/2-4);
    break;
  case DYN_CCC_RDVLDCTL_3:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+10)/2-4)+2;
    break;
  case DYN_CCC_RDVLDCTL_4:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = (1+DynamicVars[Channel][RL]/2);
    break;
  case DYN_CCC_RDVLDCTL_5:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4)+2-1);
    break;
  case DYN_CCC_RDVLDCTL_6:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4)-1+2-1);
    break;
  case DYN_CCC_RDVLDCTL_7:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.rdcmd2rdvld = (((DynamicVars[Channel][RL]+1)/2)-1)+3;
    break;
  case DYN_CCC_RK2RKCTL0:
    DYNSTRUCT_CCC_RK2RKCTL0 = (RK2RKCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-7;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_RK2RKCTL0_1:
    DYNSTRUCT_CCC_RK2RKCTL0 = (RK2RKCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-7;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = (DynamicVars[Channel][RL]-4);
    break;
  case DYN_CCC_RK2RKCTL0_2:
    DYNSTRUCT_CCC_RK2RKCTL0 = (RK2RKCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-7;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_RK2RKCTL0_3:
    DYNSTRUCT_CCC_RK2RKCTL0 = (RK2RKCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-4+3):(DynamicVars[Channel][WL]-4-1+3);
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3+3;
    break;
  case DYN_CCC_RK2RKCTL0_4:
    DYNSTRUCT_CCC_RK2RKCTL0 = (RK2RKCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.wrcmd2rkchglatency = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-7+3-1-1):(DynamicVars[Channel][WL]-7-1+3-1-1);
    DYNSTRUCT_CCC_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-6+3-1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rxdllupdt = DynamicVars[Channel][RL]-1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0_1:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>9)?(DynamicVars[Channel][RL]-9):1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0_2:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>12)?(DynamicVars[Channel][RL]-12):1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0_3:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL] > 9) ? DynamicVars[Channel][RL]-9: 1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0_4:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>12)?(DynamicVars[Channel][RL]-12):1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0_5:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>10)?(DynamicVars[Channel][RL]-10):1;
    break;
  case DYN_CCC_RXDLLRDCMDCTL0_6:
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>13)?(DynamicVars[Channel][RL]-13):1;
    break;
  case DYN_DQ_WRDQSCTL_CC:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdrvenbph1 = 0x0;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdrvenbpream1 = 0x0;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdrvenblastph = 0x0;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdrvenbpream0 = DynamicVars[Channel][DQSDRVENPREAM0];
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dmdrven = 0x1;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrpream0en = DynamicVars[Channel][WRPREAM0EN];
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdrvenbidle = 0x3;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdataph1 = 0x1;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdatapream1 = 0x1;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_dqsdatalastph = 0x1;
    break;
  case DYN_DQ_WRDQSCTL_CC_1:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_DQ_WRDQSCTL_CC_2:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = DynamicVars[Channel][WL]-4;
    break;
  case DYN_DQ_WRDQSCTL_CC_3:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = DynamicVars[Channel][WL]-2;
    break;
  case DYN_DQ_WRDQSCTL_CC_4:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_DQ_WRDQSCTL_CC_5:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-3+3):(DynamicVars[Channel][WL]);
    break;
  case DYN_DQ_WRDQSCTL_CC_6:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]+1):(DynamicVars[Channel][WL]);
    break;
  case DYN_DQ_WRDQSCTL_CC_7:
    DYNSTRUCT_DQ_WRDQSCTL_CC = (WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_CC->Bits.cc_wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-3):(DynamicVars[Channel][WL]-4);
    break;
  case DYN_DQ_WRDQSCTL_BL:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdrvenbph1 = 0x0;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdrvenbpream1 = 0x0;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdrvenblastph = 0x0;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdrvenbpream0 = DynamicVars[Channel][DQSDRVENPREAM0];
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dmdrven = 0x1;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrpream0en = DynamicVars[Channel][WRPREAM0EN];
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdrvenbidle = 0x3;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdataph1 = 0x1;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdatapream1 = 0x1;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_dqsdatalastph = 0x1;
    break;
  case DYN_DQ_WRDQSCTL_BL_1:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_DQ_WRDQSCTL_BL_2:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = DynamicVars[Channel][WL]-4;
    break;
  case DYN_DQ_WRDQSCTL_BL_3:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = DynamicVars[Channel][WL]-2;
    break;
  case DYN_DQ_WRDQSCTL_BL_4:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = DynamicVars[Channel][WL]-3;
    break;
  case DYN_DQ_WRDQSCTL_BL_5:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-3+3):(DynamicVars[Channel][WL]);
    break;
  case DYN_DQ_WRDQSCTL_BL_6:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]+1):(DynamicVars[Channel][WL]);
    break;
  case DYN_DQ_WRDQSCTL_BL_7:
    DYNSTRUCT_DQ_WRDQSCTL_BL = (WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRDQSCTL_BL->Bits.bl_wrcmd2dqsstart = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-3):(DynamicVars[Channel][WL]-4);
    break;
  case DYN_DQ_RDVLDCTL:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = (((DynamicVars[Channel][RL]+1)/2)-1)+2;
    break;
  case DYN_DQ_RDVLDCTL_1:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+8)/2-4);
    break;
  case DYN_DQ_RDVLDCTL_2:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+9)/2-4);
    break;
  case DYN_DQ_RDVLDCTL_3:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]+10)/2-4)+2;
    break;
  case DYN_DQ_RDVLDCTL_4:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = (1+DynamicVars[Channel][RL]/2)+4;
    break;
  case DYN_DQ_RDVLDCTL_5:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4)+2-1);
    break;
  case DYN_DQ_RDVLDCTL_6:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = ((DynamicVars[Channel][RL]/4)-1+2-1);
    break;
  case DYN_DQ_RDVLDCTL_7:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.rdcmd2rdvld = (((DynamicVars[Channel][RL]+1)/2)-1)+3;
    break;
  case DYN_DQ_RK2RKCTL0:
    DYNSTRUCT_DQ_RK2RKCTL0 = (RK2RKCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-7;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RK2RKCTL0_1:
    DYNSTRUCT_DQ_RK2RKCTL0 = (RK2RKCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-7;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.rdcmd2rkchglatency = (DynamicVars[Channel][RL]-4);
    break;
  case DYN_DQ_RK2RKCTL0_2:
    DYNSTRUCT_DQ_RK2RKCTL0 = (RK2RKCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-7;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RK2RKCTL0_3:
    DYNSTRUCT_DQ_RK2RKCTL0 = (RK2RKCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.wrcmd2rkchglatency = DynamicVars[Channel][WL]-6;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RK2RKCTL0_4:
    DYNSTRUCT_DQ_RK2RKCTL0 = (RK2RKCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.wrcmd2rkchglatency = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-4+3-1):(DynamicVars[Channel][WL]-4-1+3-1);
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-3+3-1;
    break;
  case DYN_DQ_RK2RKCTL0_5:
    DYNSTRUCT_DQ_RK2RKCTL0 = (RK2RKCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.wrcmd2rkchglatency = (DynamicVars[Channel][pream]==1)?(DynamicVars[Channel][WL]-7+3-1-1):(DynamicVars[Channel][WL]-7-1+3-1-1);
    DYNSTRUCT_DQ_RK2RKCTL0->Bits.rdcmd2rkchglatency = DynamicVars[Channel][RL]-6+3-1;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rxdllupdt = DynamicVars[Channel][RL]-1;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rxdllupdtlen = 0x0;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0_1:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>9)?(DynamicVars[Channel][RL]-9):1;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0_2:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>12)?(DynamicVars[Channel][RL]-12):1;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0_3:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL] > 9) ? DynamicVars[Channel][RL]-9: 1;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0_4:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>12)?(DynamicVars[Channel][RL]-12):1;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0_5:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>10)?(DynamicVars[Channel][RL]-10):1;
    break;
  case DYN_DQ_RXDLLRDCMDCTL0_6:
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0 = (RXDLLRDCMDCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXDLLRDCMDCTL0->Bits.rdcmd2rdactive = (DynamicVars[Channel][RL]>13)?(DynamicVars[Channel][RL]-13):1;
    break;
  case DYN_CCC_RXODTSEGCTL:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x6;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-7;
    break;
  case DYN_CCC_RXODTSEGCTL_1:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x6;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-7;
    break;
  case DYN_CCC_RXODTSEGCTL_2:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x7;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x0;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x0;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_CCC_RXODTSEGCTL_3:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x7;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x0;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x0;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-5;
    break;
  case DYN_CCC_RXODTSEGCTL_4:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x7;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-2;
    break;
  case DYN_CCC_RXODTSEGCTL_5:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x7;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_CCC_RXODTSEGCTL_6:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtseglenbl4 = 0x7;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_CCC_RXODTCTL:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x8;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-6;
    break;
  case DYN_CCC_RXODTCTL_1:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x8;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-6;
    break;
  case DYN_CCC_RXODTCTL_2:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x5;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x0;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x0;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-5;
    break;
  case DYN_CCC_RXODTCTL_3:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x5;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x0;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x0;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-4;
    break;
  case DYN_CCC_RXODTCTL_4:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x8;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_RXODTCTL_5:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x5;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-5;
    break;
  case DYN_CCC_RXODTCTL_6:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenlenbl4 = 0x5;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst1 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre1 = 0x3;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpst0 = 0x1;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenpre0 = 0x2;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rdcmd2rxodten = DynamicVars[Channel][RL]-5;
    break;
  case DYN_CCC_RCVENCTL:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x2;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]-4;
    break;
  case DYN_CCC_RCVENCTL_1:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x2;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]-4;
    break;
  case DYN_CCC_RCVENCTL_2:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x2;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_RCVENCTL_3:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x2;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_RCVENCTL_4:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]+1;
    break;
  case DYN_CCC_RCVENCTL_5:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_RCVENCTL_6:
    DYNSTRUCT_CCC_RCVENCTL = (RCVENCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenlenbl4 = 0x1;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst1 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre1 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpst0 = 0x0;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rcvenpre0 = 0x3;
    DYNSTRUCT_CCC_RCVENCTL->Bits.rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_CCC_DIFFAMPCTL:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0x9;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_CCC_DIFFAMPCTL_1:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0xA;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-10;
    break;
  case DYN_CCC_DIFFAMPCTL_2:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0xA;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_CCC_DIFFAMPCTL_3:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0xB;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_CCC_DIFFAMPCTL_4:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0xA;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-5;
    break;
  case DYN_CCC_DIFFAMPCTL_5:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0xB;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-10;
    break;
  case DYN_CCC_DIFFAMPCTL_6:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenpre0 = 0x2;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.diffampenlenbl4 = 0xC;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-11;
    break;
  case DYN_CCC_DIFFAMPCTL_7:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = 1+0;
    break;
  case DYN_CCC_DIFFAMPCTL_8:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = 9+3;
    break;
  case DYN_CCC_DIFFAMPCTL_9:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = 9+0;
    break;
  case DYN_CCC_DIFFAMPCTL_10:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = 8+0;
    break;
  case DYN_CCC_DIFFAMPCTL_11:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_CCC_DIFFAMPCTL_12:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_FIFOPTRCTL:
    DYNSTRUCT_DQ_FIFOPTRCTL = (FIFOPTRCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.invph0to180 = DynamicVars[Channel][INVPH0TO180_DDR3_VAL];
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.compclkrdptrinit = 0x2;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.compclkrdptroffset = 0x2;
    break;
  case DYN_DQ_FIFOPTRCTL_1:
    DYNSTRUCT_DQ_FIFOPTRCTL = (FIFOPTRCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.invph0to180 = 0x0;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.compclkrdptrinit = 0x0;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.compclkrdptroffset = 0x0;
    break;
  case DYN_DQ_FIFOPTRCTL_2:
    DYNSTRUCT_DQ_FIFOPTRCTL = (FIFOPTRCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.invph0to180 = 0x0;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.compclkrdptrinit = 0x0;
    DYNSTRUCT_DQ_FIFOPTRCTL->Bits.compclkrdptroffset = 0x0;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x6;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-7;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_1:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x6;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-7;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_2:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_3:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_4:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-2;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_5:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_6:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x6;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-7;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_1:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x6;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-7;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_2:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_3:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-5;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_4:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-2;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_5:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_6:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtseglenbl4 = 0x7;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rdcmd2rxodtseg = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTCTL_BL13:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTCTL_BL13_1:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTCTL_BL13_2:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-5-1;
    break;
  case DYN_DQ_RXODTCTL_BL13_3:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RXODTCTL_BL13_4:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RXODTCTL_BL13_5:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-7;
    break;
  case DYN_DQ_RXODTCTL_BL13_6:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenlenbl4 = 0x9;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rdcmd2rxodten = DynamicVars[Channel][RL]-8;
    break;
  case DYN_DQ_RXODTCTL_DQ:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTCTL_DQ_1:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-6;
    break;
  case DYN_DQ_RXODTCTL_DQ_2:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-5-1;
    break;
  case DYN_DQ_RXODTCTL_DQ_3:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x5;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x0;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RXODTCTL_DQ_4:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RXODTCTL_DQ_5:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x8;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-7;
    break;
  case DYN_DQ_RXODTCTL_DQ_6:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenlenbl4 = 0x9;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst1 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre1 = 0x3;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpst0 = 0x1;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenpre0 = 0x2;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rdcmd2rxodten = DynamicVars[Channel][RL]-8;
    break;
  case DYN_DQ_RCVENCTL_BL13:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RCVENCTL_BL13_1:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RCVENCTL_BL13_2:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL13_3:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL13_4:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]+1;
    break;
  case DYN_DQ_RCVENCTL_BL13_5:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL13_6:
    DYNSTRUCT_DQ_RCVENCTL_BL13 = (RCVENCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rcvenpre0 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL13->Bits.cc_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL02:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RCVENCTL_BL02_1:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-4;
    break;
  case DYN_DQ_RCVENCTL_BL02_2:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL02_3:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x2;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL02_4:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]+1;
    break;
  case DYN_DQ_RCVENCTL_BL02_5:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_RCVENCTL_BL02_6:
    DYNSTRUCT_DQ_RCVENCTL_BL02 = (RCVENCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenlenbl4 = 0x1;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst1 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre1 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpst0 = 0x0;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rcvenpre0 = 0x3;
    DYNSTRUCT_DQ_RCVENCTL_BL02->Bits.bl_rdcmd2rcven = DynamicVars[Channel][RL]-3;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0x9;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_1:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-10;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_2:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_3:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0xB;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_4:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-5;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_5:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0xB;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-10;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_6:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_diffampenlenbl4 = 0xC;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = DynamicVars[Channel][RL]-11;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_7:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = 1+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_8:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = 9+3;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_9:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = 9+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_10:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = 8+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_11:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_rdcmd2diffampen = 4+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0x9;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_1:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-10;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_2:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_3:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0xB;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-9;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_4:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0xA;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-5;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_5:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0xB;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-10;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_6:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenpre0 = 0x2;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_diffampenlenbl4 = 0xC;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = DynamicVars[Channel][RL]-11;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_7:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = 1+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_8:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = 9+3;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_9:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = 9+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_10:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = 8+0;
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_11:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_rdcmd2diffampen = 4+0;
    break;
  case DYN_DQDPLVUG_PTCTL0:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL] + 8)/2 - 5;
    break;
  case DYN_DQDPLVUG_PTCTL0_1:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL] + 9)/2 - 5;
    break;
  case DYN_DQDPLVUG_PTCTL0_2:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL] + 10)/2 - 5;
    break;
  case DYN_DQDPLVUG_PTCTL0_3:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL]/2);
    break;
  case DYN_DQDPLVUG_PTCTL0_4:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL]/4) - 2;
    break;
  case DYN_DQDPLVUG_PTCTL0_5:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = (DynamicVars[Channel][RL]/4) - 1;
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_CFG3:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_CFG3 = (DPIC_GRCOMP_CFG3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_CFG3->Bits.gcomp_ch_en = DynamicVars[Channel][GCOMP_CH_EN];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_CFG3->Bits.rcomp_max_code_val = 0x3F;
    break;
  case DYN_DPIC_PLLCTL:
    DYNSTRUCT_DPIC_PLLCTL = (PLLCTL_DPIC_STRUCT *) Value;
    DYNSTRUCT_DPIC_PLLCTL->Bits.pll_cmn_fbclktrim = DynamicVars[Channel][TEMPVAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP0];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP0];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP0];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_1:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP0];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP1];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_2:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP1];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP1];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_3:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP1];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP2];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP2];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP3];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP3];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP4];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP4];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_2:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pu_override = DynamicVars[Channel][SS_TEMP_VAR_UPGRP5];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_3:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pd_override = DynamicVars[Channel][SS_TEMP_VAR_DNGRP5];
    break;
  case DYN_DUNIT_D_CR_DRP0:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.dramdevice_pr = DynamicVars[Channel][DRAMDEVICE_PR];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.addrdec = DynamicVars[Channel][ADDRDEC];
    break;
  case DYN_DUNIT_D_CR_DRP0_1:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.caswizzle = DynamicVars[Channel][CASWIZZLE];
    break;
  case DYN_DUNIT_D_CR_DTR0A:
    DYNSTRUCT_DUNIT_D_CR_DTR0A = (D_CR_DTR0A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.tckckeh = DynamicVars[Channel][TCKSRX];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.txsdll = DynamicVars[Channel][TXSDLL];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.txsr = DynamicVars[Channel][TXSR];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.trcd = DynamicVars[Channel][TRCD];
    DYNSTRUCT_DUNIT_D_CR_DTR0A->Bits.trppb = DynamicVars[Channel][TRPPB];
    break;
  case DYN_DUNIT_D_CR_DRP0_2:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.eccen = DynamicVars[Channel][ECCEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.bahen = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rsien = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.dden = DynamicVars[Channel][DDEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.dwid = DynamicVars[Channel][DWID];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rken1 = DynamicVars[Channel][RANK1_ENABLED];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rken0 = DynamicVars[Channel][RANK0_ENABLED];
    break;
  case DYN_DUNIT_D_CR_DTR1A:
    DYNSTRUCT_DUNIT_D_CR_DTR1A = (D_CR_DTR1A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.txp = DynamicVars[Channel][TXP];
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.tzqcl = DynamicVars[Channel][TZQCL];
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.tzqcs = DynamicVars[Channel][TZQCS];
    DYNSTRUCT_DUNIT_D_CR_DTR1A->Bits.tzqlat = DynamicVars[Channel][TZQLAT];
    break;
  case DYN_DUNIT_D_CR_DTR2A:
    DYNSTRUCT_DUNIT_D_CR_DTR2A = (D_CR_DTR2A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR2A->Bits.nrfcab = DynamicVars[Channel][NRFCAB];
    DYNSTRUCT_DUNIT_D_CR_DTR2A->Bits.tcke = DynamicVars[Channel][TCKE];
    DYNSTRUCT_DUNIT_D_CR_DTR2A->Bits.nrefi = DynamicVars[Channel][NREFI];
    break;
  case DYN_DUNIT_D_CR_DTR3A:
    DYNSTRUCT_DUNIT_D_CR_DTR3A = (D_CR_DTR3A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.trtp = DynamicVars[Channel][TRTP];
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.tccd_inc = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.twtp = DynamicVars[Channel][TWTP];
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.tcmd = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.tcwl = DynamicVars[Channel][TCWL];
    DYNSTRUCT_DUNIT_D_CR_DTR3A->Bits.twmwsb = DynamicVars[Channel][TCCDMW];
    break;
  case DYN_DUNIT_D_CR_DTR4A:
    DYNSTRUCT_DUNIT_D_CR_DTR4A = (D_CR_DTR4A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.tfaw = DynamicVars[Channel][TFAW];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.twrdr = DynamicVars[Channel][TWRDR];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.trwdr = DynamicVars[Channel][TRWDR];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.twwdr = DynamicVars[Channel][TWWDR];
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.trrdr = DynamicVars[Channel][TRRDR];
    break;
  case DYN_DUNIT_D_CR_DTR5A:
    DYNSTRUCT_DUNIT_D_CR_DTR5A = (D_CR_DTR5A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.trrd = DynamicVars[Channel][TRRD];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.tderate_inc = DynamicVars[Channel][TDERATE_INC];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.twwsr = DynamicVars[Channel][TWWSR];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.trrsr = DynamicVars[Channel][TRRSR];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.twrsr = DynamicVars[Channel][TWRSR];
    DYNSTRUCT_DUNIT_D_CR_DTR5A->Bits.trwsr = DynamicVars[Channel][TRWSR];
    break;
  case DYN_DUNIT_D_CR_DTR6A:
    DYNSTRUCT_DUNIT_D_CR_DTR6A = (D_CR_DTR6A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.orefdly = 0x40;
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tckckel = DynamicVars[Channel][TCKCKEL];
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.mntdly = DynamicVars[Channel][MNTDLY];
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tpstmrrblk = DynamicVars[Channel][TPSTMRRBLK];
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tpremrblk = DynamicVars[Channel][TPREMRBLK];
    break;
  case DYN_DUNIT_D_CR_DTR7A:
    DYNSTRUCT_DUNIT_D_CR_DTR7A = (D_CR_DTR7A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.trpab = DynamicVars[Channel][TRPAB];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.tpstmrwblk = DynamicVars[Channel][TPSTMRWBLK];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.twrpden = DynamicVars[Channel][TWRPDEN];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.trdpden = DynamicVars[Channel][TRDPDEN];
    DYNSTRUCT_DUNIT_D_CR_DTR7A->Bits.tras = DynamicVars[Channel][TRAS];
    break;
  case DYN_DUNIT_D_CR_DTR8A:
    DYNSTRUCT_DUNIT_D_CR_DTR8A = (D_CR_DTR8A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.tckesr = DynamicVars[Channel][TCKESR];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.lpmdres = DynamicVars[Channel][LPMDRES];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.lpmdtockedly = DynamicVars[Channel][TLPCKDLY];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.cketolpmddly = DynamicVars[Channel][TCKLPDLY];
    DYNSTRUCT_DUNIT_D_CR_DTR8A->Bits.pwddly = DynamicVars[Channel][PWDDLY];
    break;
  case DYN_DUNIT_D_CR_SSKPD0:
    DYNSTRUCT_DUNIT_D_CR_SSKPD0 = (D_CR_SSKPD0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_SSKPD0->Bits.val = DynamicVars[Channel][SSKPD0];
    DYNSTRUCT_DUNIT_D_CR_SSKPD0->Bits.val = DynamicVars[Channel][SSKPD1];
    break;
  case DYN_DUNIT_D_CR_BONUS0:
    DYNSTRUCT_DUNIT_D_CR_BONUS0 = (D_CR_BONUS0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BONUS0->Bits.bonus0 = DynamicVars[Channel][BONUS0];
    break;
  case DYN_DUNIT_D_CR_BONUS1:
    DYNSTRUCT_DUNIT_D_CR_BONUS1 = (D_CR_BONUS1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BONUS1->Bits.bonus1 = DynamicVars[Channel][BONUS1];
    break;
  case DYN_DUNIT_D_CR_MR4_DESWIZZLE:
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE = (D_CR_MR4_DESWIZZLE_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit2_sel = DynamicVars[Channel][MR4_BIT2_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit1_sel = DynamicVars[Channel][MR4_BIT1_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit0_sel = DynamicVars[Channel][MR4_BIT0_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_byte_sel = DynamicVars[Channel][MR4_BYTE_SEL];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit0_sel2 = DynamicVars[Channel][MR4_BIT0_SEL2];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit1_sel2 = DynamicVars[Channel][MR4_BIT1_SEL2];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_bit2_sel2 = DynamicVars[Channel][MR4_BIT2_SEL2];
    DYNSTRUCT_DUNIT_D_CR_MR4_DESWIZZLE->Bits.mr4_byte_sel2 = DynamicVars[Channel][MR4_BYTE_SEL2];
    break;
  case DYN_DUNIT_D_CR_DOCRA:
    DYNSTRUCT_DUNIT_D_CR_DOCRA = (D_CR_DOCRA_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.wrodtstop = DynamicVars[Channel][WRODTSTOP];
    break;
  case DYN_DUNIT_D_CR_DOCRA_1:
    DYNSTRUCT_DUNIT_D_CR_DOCRA = (D_CR_DOCRA_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.rdodtstart = DynamicVars[Channel][RDODTSTART];
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.rdodtstop = 0x6;
    break;
  case DYN_DUNIT_D_CR_DOCRA_2:
    DYNSTRUCT_DUNIT_D_CR_DOCRA = (D_CR_DOCRA_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.r0wrodtctl = DynamicVars[Channel][R0WRODTCTL];
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.r1wrodtctl = DynamicVars[Channel][R1WRODTCTL];
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.r0rdodtctl = DynamicVars[Channel][R0RDODTCTL];
    DYNSTRUCT_DUNIT_D_CR_DOCRA->Bits.r1rdodtctl = DynamicVars[Channel][R1RDODTCTL];
    break;
  case DYN_DUNIT_D_CR_DRMC:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.coldwake = 0x1;
    break;
  case DYN_DUNIT_D_CR_BGF_CTL:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_1:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDDATA_RATIO_WIO2];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_2:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spidcmdclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.saclkby2_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DUNIT_D_CR_DRMC_1:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    break;
  case DYN_DUNIT_D_CR_DRMC_2:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    break;
  case DYN_DUNIT_D_CR_DRFC:
    DYNSTRUCT_DUNIT_D_CR_DRFC = (D_CR_DRFC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.minrefrate = DynamicVars[Channel][MINREFRATE];
    break;
  case DYN_DUNIT_D_CR_DRFC_1:
    DYNSTRUCT_DUNIT_D_CR_DRFC = (D_CR_DRFC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.refwmpnc = DynamicVars[Channel][REFWMPNC];
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.refwmhi = DynamicVars[Channel][REFWMHI];
    break;
  case DYN_DUNIT_D_CR_DRP0_3:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.bahen = DynamicVars[Channel][BAHEN];
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.rsien = DynamicVars[Channel][RSIEN];
    break;
  case DYN_DUNIT_D_CR_DPMC1:
    DYNSTRUCT_DUNIT_D_CR_DPMC1 = (D_CR_DPMC1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.cmdtrist = DynamicVars[Channel][CMDTRIST];
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.pasr = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.pclsto = DynamicVars[Channel][PCLSTO];
    break;
  case DYN_DUNIT_D_CR_DSCH:
    DYNSTRUCT_DUNIT_D_CR_DSCH = (D_CR_DSCH_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.inordermode = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.blkrdbf_add_rddata_cr = DynamicVars[Channel][BLKRDBF_ADD_RDDATA];
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.blkrdbf = DynamicVars[Channel][BLKRDBF];
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.spid_early_rddata_valid = DynamicVars[Channel][SPID_EARLY_RDDATA_VALID];
    DYNSTRUCT_DUNIT_D_CR_DSCH->Bits.bgf_early_rddata_valid = DynamicVars[Channel][BGF_EARLY_RDDATA_VALID];
    break;
  case DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_PATTERN:
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_PATTERN = (D_CR_BGF_CUSTOM_TSV_CMD_PATTERN_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_PATTERN->Bits.cmdspid_to_saby2_tsvs = DynamicVars[Channel][PATTERN_CMDSPID_TO_SABY2_TSVS];
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_PATTERN->Bits.saby2_to_cmdspid_tsvs = DynamicVars[Channel][PATTERN_SABY2_TO_CMDSPID_TSVS];
    break;
  case DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_INIT:
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_INIT = (D_CR_BGF_CUSTOM_TSV_CMD_INIT_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_INIT->Bits.cmdspid_to_saby2_tsvs = DynamicVars[Channel][INIT_CMDSPID_TO_SABY2_TSVS];
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_CMD_INIT->Bits.saby2_to_cmdspid_tsvs = DynamicVars[Channel][INIT_SABY2_TO_CMDSPID_TSVS];
    break;
  case DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_PATTERN:
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_PATTERN = (D_CR_BGF_CUSTOM_TSV_DATA_PATTERN_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_PATTERN->Bits.dataspid_to_saby2_tsvs = DynamicVars[Channel][PATTERN_DATASPID_TO_SABY2_TSVS];
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_PATTERN->Bits.saby2_to_dataspid_tsvs = DynamicVars[Channel][PATTERN_SABY2_TO_DATASPID_TSVS];
    break;
  case DYN_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_INIT:
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_INIT = (D_CR_BGF_CUSTOM_TSV_DATA_INIT_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_INIT->Bits.dataspid_to_saby2_tsvs = DynamicVars[Channel][INIT_DATASPID_TO_SABY2_TSVS];
    DYNSTRUCT_DUNIT_D_CR_BGF_CUSTOM_TSV_DATA_INIT->Bits.saby2_to_dataspid_tsvs = DynamicVars[Channel][INIT_SABY2_TO_DATASPID_TSVS];
    break;
  case DYN_DUNIT_D_CR_TQCTL:
    DYNSTRUCT_DUNIT_D_CR_TQCTL = (D_CR_TQCTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQCTL->Bits.tqpollper = DynamicVars[Channel][TQPOLLPER];
    break;
  case DYN_DUNIT_D_CR_TQCTL_1:
    DYNSTRUCT_DUNIT_D_CR_TQCTL = (D_CR_TQCTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQCTL->Bits.srten = DynamicVars[Channel][SRTEN];
    break;
  case DYN_DUNIT_D_CR_TQOFFSET:
    DYNSTRUCT_DUNIT_D_CR_TQOFFSET = (D_CR_TQOFFSET_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQOFFSET->Bits.mr_value = DynamicVars[Channel][MR_VALUE];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_3:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_4:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spiddataclk_ratio = DynamicVars[Channel][SPIDDATA_RATIO_WIO2];
    break;
  case DYN_DUNIT_D_CR_BGF_CTL_5:
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL = (D_CR_BGF_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.spidcmdclk_ratio = DynamicVars[Channel][SPIDCMDCLK_RATIO];
    DYNSTRUCT_DUNIT_D_CR_BGF_CTL->Bits.saclkby2_ratio = DynamicVars[Channel][SACLKBY2_RATIO];
    break;
  case DYN_DUNIT_D_CR_DQS_RETRAINING_CTL:
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL = (D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_int = DynamicVars[Channel][DQS_RETRAIN_INT];
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_osc_rt = DynamicVars[Channel][DQS_OSC_RT];
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_srx_en = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_en = 0x1;
    break;
  case DYN_CCC_RDVLDCTL_8:
    DYNSTRUCT_CCC_RDVLDCTL = (RDVLDCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RDVLDCTL->Bits.earlyrdvld = DynamicVars[Channel][SPID_EARLY_RDDATA_VALID];
    break;
  case DYN_DQ_RDVLDCTL_8:
    DYNSTRUCT_DQ_RDVLDCTL = (RDVLDCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RDVLDCTL->Bits.earlyrdvld = DynamicVars[Channel][SPID_EARLY_RDDATA_VALID];
    break;
  case DYN_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_1:
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR = (P_CR_MC_BIOS_REQ_0_0_0_MCHBAR_PUNIT_STRUCT *) Value;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.cpgc_mode_complete = 0x1;
    DYNSTRUCT_PUNIT_P_CR_MC_BIOS_REQ_0_0_0_MCHBAR->Bits.req_data = DynamicVars[Channel][PUNIT_REQ_DATA];
    break;
  case DYN_DUNIT_D_CR_DRMC_3:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    break;
  case DYN_DQ_DLLCOMP_FBMUXSEL:
    DYNSTRUCT_DQ_DLLCOMP_FBMUXSEL = (DLLCOMP_FBMUXSEL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DLLCOMP_FBMUXSEL->Bits.muxcode_max = DynamicVars[Channel][MUX_MAX];
    DYNSTRUCT_DQ_DLLCOMP_FBMUXSEL->Bits.muxcode_min = DynamicVars[Channel][MUX_MIN];
    break;
  case DYN_CCC_DLLCOMP_FBMUXSEL1:
    DYNSTRUCT_CCC_DLLCOMP_FBMUXSEL1 = (DLLCOMP_FBMUXSEL1_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_FBMUXSEL1->Bits.muxcode_max = DynamicVars[Channel][MUX_MAX];
    DYNSTRUCT_CCC_DLLCOMP_FBMUXSEL1->Bits.muxcode_min = DynamicVars[Channel][MUX_MIN];
    break;
  case DYN_DQ_DLLCOMP_FINECODE:
    DYNSTRUCT_DQ_DLLCOMP_FINECODE = (DLLCOMP_FINECODE_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DLLCOMP_FINECODE->Bits.finecode_max = DynamicVars[Channel][FINE_MAX];
    DYNSTRUCT_DQ_DLLCOMP_FINECODE->Bits.finecode_min = DynamicVars[Channel][FINE_MIN];
    break;
  case DYN_CCC_DLLCOMP_FINECODE:
    DYNSTRUCT_CCC_DLLCOMP_FINECODE = (DLLCOMP_FINECODE_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_FINECODE->Bits.finecode_max = DynamicVars[Channel][FINE_MAX];
    DYNSTRUCT_CCC_DLLCOMP_FINECODE->Bits.finecode_min = DynamicVars[Channel][FINE_MIN];
    break;
  case DYN_DQ_DLLCOMP_COARSECODE:
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE = (DLLCOMP_COARSECODE_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE->Bits.coarsecode_max = DynamicVars[Channel][COARSE_MAX];
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE->Bits.coarsecode_min = DynamicVars[Channel][COARSE_MIN];
    break;
  case DYN_CCC_DLLCOMP_COARSECODE1:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE1 = (DLLCOMP_COARSECODE1_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE1->Bits.coarsecode_max = DynamicVars[Channel][COARSE_MAX];
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE1->Bits.coarsecode_min = DynamicVars[Channel][COARSE_MIN];
    break;
  case DYN_CCC_DLLCOMP_COARSECODE0_CH0:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH0 = (DLLCOMP_COARSECODE0_CH0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH0->Bits.ch0_coarseicode_ovr = DynamicVars[Channel][SS_TEMP_VAR]+3;
    break;
  case DYN_CCC_DLLCOMP_COARSECODE0_CH0_1:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH0 = (DLLCOMP_COARSECODE0_CH0_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH0->Bits.ch0_coarsecode_ovr_sel = 0x0;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH0->Bits.ch0_coarsecode_ovr = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_CCC_DLLCOMP_COARSECODE0_CH1:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH1 = (DLLCOMP_COARSECODE0_CH1_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH1->Bits.ch1_coarseicode_ovr = DynamicVars[Channel][SS_TEMP_VAR]+3;
    break;
  case DYN_CCC_DLLCOMP_COARSECODE0_CH1_1:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH1 = (DLLCOMP_COARSECODE0_CH1_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH1->Bits.ch1_coarsecode_ovr_sel = 0x0;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_CH1->Bits.ch1_coarsecode_ovr = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_CCC_DLLCOMP_COARSECODE0_ECC:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_ECC = (DLLCOMP_COARSECODE0_ECC_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_ECC->Bits.ecc_coarseicode_ovr = DynamicVars[Channel][SS_TEMP_VAR]+3;
    break;
  case DYN_CCC_DLLCOMP_COARSECODE0_ECC_1:
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_ECC = (DLLCOMP_COARSECODE0_ECC_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_ECC->Bits.ecc_coarsecode_ovr_sel = 0x0;
    DYNSTRUCT_CCC_DLLCOMP_COARSECODE0_ECC->Bits.ecc_coarsecode_ovr = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DQ_DLLCOMP_COARSECODE_1:
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE = (DLLCOMP_COARSECODE_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE->Bits.coarseicode_ovr = DynamicVars[Channel][SS_TEMP_VAR]+3;
    break;
  case DYN_DQ_DLLCOMP_COARSECODE_2:
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE = (DLLCOMP_COARSECODE_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE->Bits.coarsecode_ovr_sel = 0x0;
    DYNSTRUCT_DQ_DLLCOMP_COARSECODE->Bits.coarsecode_ovr = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DUNIT_D_CR_DRP0_4:
    DYNSTRUCT_DUNIT_D_CR_DRP0 = (D_CR_DRP0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRP0->Bits.eccen = DynamicVars[Channel][ECCEN];
    break;
  case DYN_DUNIT_D_CR_SCRAMCTRL:
    DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL = (D_CR_SCRAMCTRL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL->Bits.key = DynamicVars[Channel][SCRAMBLER_KEY];
    DYNSTRUCT_DUNIT_D_CR_SCRAMCTRL->Bits.scrm_en = 0x1;
    break;
  case DYN_CUNIT_MCHBAR_LO_0_0_0_PCI:
    DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI = (MCHBAR_LO_0_0_0_PCI_CUNIT_STRUCT *) Value;
    DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI->Bits.base_addr = DynamicVars[Channel][MCHBAR];
    DYNSTRUCT_CUNIT_MCHBAR_LO_0_0_0_PCI->Bits.mchbaren = 0x1;
    break;
  case DYN_P2SB_SBREG_BAR:
    DYNSTRUCT_P2SB_SBREG_BAR = (SBREG_BAR_P2SB_STRUCT *) Value;
    DYNSTRUCT_P2SB_SBREG_BAR->Bits.rba = DynamicVars[Channel][P2SBBAR];
    break;
  case DYN_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR:
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR = (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_STRUCT *) Value;
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.sym_slice1_channel_enabled = DynamicVars[Channel][SYM_SLICE1_CHANNEL_ENABLED];
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.sym_slice0_channel_enabled = DynamicVars[Channel][SYM_SLICE0_CHANNEL_ENABLED];
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.slice_1_disabled = DynamicVars[Channel][SLICE_1_DISABLED];
    break;
  case DYN_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_1:
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR = (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_STRUCT *) Value;
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.slice_0_mem_disabled = DynamicVars[Channel][SLICE_0_MEM_DISABLED];
    break;
  case DYN_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_2:
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR = (A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR_AUNIT_STRUCT *) Value;
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.ch_hash_mask = DynamicVars[Channel][CHANNEL_HASH_MASK];
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.interleave_mode = DynamicVars[Channel][AUNIT_INTERLEAVED_MODE];
    DYNSTRUCT_AUNIT_A_CR_SLICE_CHANNEL_HASH_0_0_0_MCHBAR->Bits.slice_hash_mask = DynamicVars[Channel][SLICE_HASH_MASK];
    break;
  case DYN_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR:
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR = (A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR_AUNIT_STRUCT *) Value;
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_enable = DynamicVars[Channel][SLICE0_ASYM_ENABLE];
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_channel_select = DynamicVars[Channel][SLICE0_ASYM_CHANNEL_SELECT];
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_limit = DynamicVars[Channel][SLICE0_ASYM_LIMIT];
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_base = DynamicVars[Channel][SLICE0_ASYM_BASE];
    break;
  case DYN_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR:
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR = (A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR_AUNIT_STRUCT *) Value;
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_enable = DynamicVars[Channel][SLICE1_ASYM_ENABLE];
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_channel_select = DynamicVars[Channel][SLICE1_ASYM_CHANNEL_SELECT];
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_limit = DynamicVars[Channel][SLICE1_ASYM_LIMIT];
    DYNSTRUCT_AUNIT_A_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_base = DynamicVars[Channel][SLICE1_ASYM_BASE];
    break;
  case DYN_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR:
    DYNSTRUCT_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR = (A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR_AUNIT_STRUCT *) Value;
    DYNSTRUCT_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_interleave_enable = DynamicVars[Channel][ASYM_2WAY_INTERLEAVE_ENABLE];
    DYNSTRUCT_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_limit = DynamicVars[Channel][ASYM_2WAY_LIMIT];
    DYNSTRUCT_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_base = DynamicVars[Channel][ASYM_2WAY_BASE];
    DYNSTRUCT_AUNIT_A_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_intlv_mode = DynamicVars[Channel][ASYM_2WAY_INTLV_MODE];
    break;
  case DYN_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR:
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR = (B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR_BUNIT_STRUCT *) Value;
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_enable = DynamicVars[Channel][SLICE0_ASYM_ENABLE];
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_channel_select = DynamicVars[Channel][SLICE0_ASYM_CHANNEL_SELECT];
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_limit = DynamicVars[Channel][SLICE0_ASYM_LIMIT];
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION0_0_0_0_MCHBAR->Bits.slice0_asym_base = DynamicVars[Channel][SLICE0_ASYM_BASE];
    break;
  case DYN_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR:
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR = (B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR_BUNIT_STRUCT *) Value;
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_enable = DynamicVars[Channel][SLICE1_ASYM_ENABLE];
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_channel_select = DynamicVars[Channel][SLICE1_ASYM_CHANNEL_SELECT];
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_limit = DynamicVars[Channel][SLICE1_ASYM_LIMIT];
    DYNSTRUCT_BUNIT_B_CR_ASYM_MEM_REGION1_0_0_0_MCHBAR->Bits.slice1_asym_base = DynamicVars[Channel][SLICE1_ASYM_BASE];
    break;
  case DYN_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR:
    DYNSTRUCT_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR = (B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR_BUNIT_STRUCT *) Value;
    DYNSTRUCT_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_interleave_enable = DynamicVars[Channel][ASYM_2WAY_INTERLEAVE_ENABLE];
    DYNSTRUCT_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_limit = DynamicVars[Channel][ASYM_2WAY_LIMIT];
    DYNSTRUCT_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_base = DynamicVars[Channel][ASYM_2WAY_BASE];
    DYNSTRUCT_BUNIT_B_CR_ASYM_2WAY_MEM_REGION_0_0_0_MCHBAR->Bits.asym_2way_intlv_mode = DynamicVars[Channel][ASYM_2WAY_INTLV_MODE];
    break;
  case DYN_DQ_RXPBDBLCTL0:
    DYNSTRUCT_DQ_RXPBDBLCTL0 = (RXPBDBLCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXPBDBLCTL0->Bits.rxdll_bl_dq0rxpbdcode = DynamicVars[Channel][S0_Fixes0];
    break;
  case DYN_DQ_WRLVL:
    DYNSTRUCT_DQ_WRLVL = (WRLVL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WRLVL->Bits.bl_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    DYNSTRUCT_DQ_WRLVL->Bits.cc_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    break;
  case DYN_CCC_WRLVL:
    DYNSTRUCT_CCC_WRLVL = (WRLVL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_WRLVL->Bits.cc0_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    DYNSTRUCT_CCC_WRLVL->Bits.cc1_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    DYNSTRUCT_CCC_WRLVL->Bits.bl_wrlvl = DynamicVars[Channel][WRLVLMODEVAR];
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_12:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_dqsdiffampenovrval = DynamicVars[Channel][CC_DQS_OVR_VAL];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_dqsdiffampenovrsel = DynamicVars[Channel][CC_DQS_OVR_SEL];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_dqdmdiffampenovrval = DynamicVars[Channel][CC_DQDM_OVR_VAL];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_dqdmdiffampenovrsel = DynamicVars[Channel][CC_DQDM_OVR_SEL];
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_12:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_dqsdiffampenovrval = DynamicVars[Channel][BL_DQS_OVR_VAL];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_dqsdiffampenovrsel = DynamicVars[Channel][BL_DQS_OVR_SEL];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_dqdmdiffampenovrval = DynamicVars[Channel][BL_DQDM_OVR_VAL];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_dqdmdiffampenovrsel = DynamicVars[Channel][BL_DQDM_OVR_SEL];
    break;
  case DYN_CCC_DIFFAMPCTL_13:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.dqdmdiffampenovrsel = DynamicVars[Channel][DQDM_OVR_SEL_ECC];
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.dqsdiffampenovrsel = DynamicVars[Channel][DQS_OVR_SEL_ECC];
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.dqdmdiffampenovrval = DynamicVars[Channel][DQDM_OVR_ECC];
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.dqsdiffampenovrval = DynamicVars[Channel][DQS_OVR_ECC];
    break;
  case DYN_DUNIT_D_CR_DRAM_CMD:
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD = (D_CR_DRAM_CMD_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.bl = DynamicVars[Channel][DRAM_CMD_BL];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.rank = DynamicVars[Channel][RANK];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.mrrcmd = DynamicVars[Channel][RDDCMD];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.data = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_CPGC_CPGC_ERR_CTL:
    DYNSTRUCT_CPGC_CPGC_ERR_CTL = (CPGC_ERR_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_ERR_CTL->Bits.errchk_mask_chunk = DynamicVars[Channel][CHUNK_ERR_MASK];
    break;
  case DYN_CPGC_CPGC_ERR_LNEN_HI:
    DYNSTRUCT_CPGC_CPGC_ERR_LNEN_HI = (CPGC_ERR_LNEN_HI_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_ERR_LNEN_HI->Bits.data_errchk_mask_hi = DynamicVars[Channel][CHUNK_ERR_MASK_LP];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_0_:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_ = (CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_->Bits.pattern_buffer = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_CPGC_CPGC2_BASE_REPEATS:
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS = (CPGC2_BASE_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS->Bits.base_repeats = DynamicVars[Channel][NUM_BURSTS_EXP];
    break;
  case DYN_CPGC_CPGC2_BLOCK_REPEATS:
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS = (CPGC2_BLOCK_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS->Bits.block_repeats = DynamicVars[Channel][NUM_LOOPS_EXP];
    break;
  case DYN_CPGC_CPGC_DPAT_XTRA_LFSR_CFG:
    DYNSTRUCT_CPGC_CPGC_DPAT_XTRA_LFSR_CFG = (CPGC_DPAT_XTRA_LFSR_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_XTRA_LFSR_CFG->Bits.lane_rotate_rate = DynamicVars[Channel][LANE_ROTATE_RATE];
    break;
  case DYN_CPGC_CPGC_DPAT_CFG:
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG = (CPGC_DPAT_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.reload_lfsr_seed_rate = DynamicVars[Channel][RELOAD_LFSR_SEED_RATE];
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.save_lfsr_seed_rate = DynamicVars[Channel][SAVE_LFSR_SEED_RATE];
    break;
  case DYN_CPGC_CPGC2_BASE_REPEATS_1:
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS = (CPGC2_BASE_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BASE_REPEATS->Bits.base_repeats = DynamicVars[Channel][NUM_BURSTS_EXP];
    break;
  case DYN_CPGC_CPGC2_BLOCK_REPEATS_1:
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS = (CPGC2_BLOCK_REPEATS_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_BLOCK_REPEATS->Bits.block_repeats = DynamicVars[Channel][NUM_LOOPS_EXP];
    break;
  case DYN_DUNIT_D_CR_DRMC_4:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][REG_DATA];
    break;
  case DYN_DUNIT_D_CR_DRMC_5:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    break;
  case DYN_DUNIT_D_CR_DRAM_CMD_1:
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD = (D_CR_DRAM_CMD_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.rank = DynamicVars[Channel][RANK_INDEX];
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.mrrcmd = 0x0;
    DYNSTRUCT_DUNIT_D_CR_DRAM_CMD->Bits.bl = 0x1;
    break;
  case DYN_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A:
    DYNSTRUCT_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A = (CPGC_SEQ_BANK_L2P_MAPPING_A_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_SEQ_BANK_L2P_MAPPING_A->Bits.l2p_bank0_mapping = DynamicVars[Channel][TARGET_BANK];
    break;
  case DYN_CPGC_CPGC_SEQ_RANK_L2P_MAPPING:
    DYNSTRUCT_CPGC_CPGC_SEQ_RANK_L2P_MAPPING = (CPGC_SEQ_RANK_L2P_MAPPING_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_SEQ_RANK_L2P_MAPPING->Bits.l2p_rank0_mapping = DynamicVars[Channel][TARGET_RANK];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_0_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_ = (CPGC_CADB_BUFA_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.bank_addr = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_1_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_ = (CPGC_CADB_BUFA_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_->Bits.bank_addr = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_1_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_ = (CPGC_CADB_BUFB_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cke = 0xF;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cs = (DynamicVars[Channel][RANK]==0)?2:1;
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_2_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_ = (CPGC_CADB_BUFA_2__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.bank_addr = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_3_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_ = (CPGC_CADB_BUFA_3__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.row_col_addr = DynamicVars[Channel][ROW_COL_ADDR];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.bank_addr = 0x0;
    break;
  case DYN_CPGC_CPGC2_ADDRESS_SIZE:
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE = (CPGC2_ADDRESS_SIZE_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_bits_col = DynamicVars[Channel][NUM_COLS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_bits_row = DynamicVars[Channel][NUM_ROWS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_num_banks = 0x7;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_num_ranks = 0x2;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.region_size_bits_col = DynamicVars[Channel][NUM_COLS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.region_size_bits_row = DynamicVars[Channel][NUM_ROWS];
    break;
  case DYN_CPGC_CPGC2_ADDRESS_CONTROL:
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_CONTROL = (CPGC2_ADDRESS_CONTROL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_CONTROL->Bits.address_decode_rotate_repeats = DynamicVars[Channel][ADD_ROTATE_RPT];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_0__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_ = (CPGC_CADB_BUFA_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA0_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_0_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA0_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_1__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_ = (CPGC_CADB_BUFA_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA1_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_1_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA1_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_2__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_ = (CPGC_CADB_BUFA_2__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA2_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_2_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA2_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_3__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_ = (CPGC_CADB_BUFA_3__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA3_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_3_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA3_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_4_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_ = (CPGC_CADB_BUFA_4__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA4_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_4_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA4_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_5_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_ = (CPGC_CADB_BUFA_5__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA5_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_5_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA5_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_6_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_ = (CPGC_CADB_BUFA_6__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA6_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_6_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA6_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFA_7_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_ = (CPGC_CADB_BUFA_7__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_->Bits.bank_addr = DynamicVars[Channel][CADB_BUFA7_BANK];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFA_7_->Bits.row_col_addr = DynamicVars[Channel][CADB_BUFA7_ROW_COL];
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_0_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_ = (CPGC_CADB_BUFB_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cmd = DynamicVars[Channel][CADB_BUFB0_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_0_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_1__1:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_ = (CPGC_CADB_BUFB_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cmd = DynamicVars[Channel][CADB_BUFB1_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_1_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_2_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_ = (CPGC_CADB_BUFB_2__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cmd = DynamicVars[Channel][CADB_BUFB2_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_2_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_3_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_ = (CPGC_CADB_BUFB_3__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cmd = DynamicVars[Channel][CADB_BUFB3_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_3_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_4_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_ = (CPGC_CADB_BUFB_4__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cmd = DynamicVars[Channel][CADB_BUFB4_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_4_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_5_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_ = (CPGC_CADB_BUFB_5__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cmd = DynamicVars[Channel][CADB_BUFB5_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_5_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_6_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_ = (CPGC_CADB_BUFB_6__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cmd = DynamicVars[Channel][CADB_BUFB6_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_6_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_CADB_BUFB_7_:
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_ = (CPGC_CADB_BUFB_7__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.par = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.val = 0x1;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cke = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.odt = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cmd = DynamicVars[Channel][CADB_BUFB7_CMD];
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cid = 0x0;
    DYNSTRUCT_CPGC_CPGC_CADB_BUFB_7_->Bits.cs = 0x0;
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_0__1:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_ = (CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_->Bits.pattern_buffer = DynamicVars[Channel][AGG_PATTERN];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_1_:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_ = (CPGC_DPAT_UNISEQ_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_->Bits.pattern_buffer = DynamicVars[Channel][VIC_PATTERN];
    break;
  case DYN_CPGC_CPGC_CADB_CFG:
    DYNSTRUCT_CPGC_CPGC_CADB_CFG = (CPGC_CADB_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_CFG->Bits.sel_uniseq0_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_CADB_CFG->Bits.sel_uniseq1_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_CADB_CFG->Bits.sel_uniseq2_mode = DynamicVars[Channel][UNIMODE];
    break;
  case DYN_CPGC_CPGC_CADB_UNISEQ0_PBUF:
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ0_PBUF = (CPGC_CADB_UNISEQ0_PBUF_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ0_PBUF->Bits.cmd = DynamicVars[Channel][PATTERN0];
    break;
  case DYN_CPGC_CPGC_CADB_UNISEQ1_PBUF:
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ1_PBUF = (CPGC_CADB_UNISEQ1_PBUF_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ1_PBUF->Bits.cmd = DynamicVars[Channel][PATTERN1];
    break;
  case DYN_CPGC_CPGC_CADB_UNISEQ2_PBUF:
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ2_PBUF = (CPGC_CADB_UNISEQ2_PBUF_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_CADB_UNISEQ2_PBUF->Bits.cmd = DynamicVars[Channel][PATTERN2];
    break;
  case DYN_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_:
    DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_ = (CPGC2_ALGORITHM_INSTRUCTION_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_->Bits.last = DynamicVars[Channel][INSTR_LAST];
    DYNSTRUCT_CPGC_CPGC2_ALGORITHM_INSTRUCTION_0_->Bits.command_start_pointer = DynamicVars[Channel][INSTR_POINTER];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_0__2:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_ = (CPGC_DPAT_UNISEQ_0__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_0_->Bits.pattern_buffer = DynamicVars[Channel][PATTERN0];
    break;
  case DYN_CPGC_CPGC_DPAT_UNISEQ_1__1:
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_ = (CPGC_DPAT_UNISEQ_1__CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_UNISEQ_1_->Bits.pattern_buffer = DynamicVars[Channel][PATTERN1];
    break;
  case DYN_CPGC_CPGC_DPAT_CFG_1:
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG = (CPGC_DPAT_CFG_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.uniseq2_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.uniseq1_mode = DynamicVars[Channel][UNIMODE];
    DYNSTRUCT_CPGC_CPGC_DPAT_CFG->Bits.uniseq0_mode = DynamicVars[Channel][UNIMODE];
    break;
  case DYN_DQ_U32_WRDQCTL:
    DYNSTRUCT_DQ_U32_WRDQCTL = (U32_WRDQCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_U32_WRDQCTL->Bits.data = DynamicVars[Channel][ORIG_WRDQCTL];
    break;
  case DYN_DQ_U32_WRDQSCTL_CC:
    DYNSTRUCT_DQ_U32_WRDQSCTL_CC = (U32_WRDQSCTL_CC_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_U32_WRDQSCTL_CC->Bits.data = DynamicVars[Channel][ORIG_WRDQSCTL_CC];
    break;
  case DYN_DQ_U32_WRDQSCTL_BL:
    DYNSTRUCT_DQ_U32_WRDQSCTL_BL = (U32_WRDQSCTL_BL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_U32_WRDQSCTL_BL->Bits.data = DynamicVars[Channel][ORIG_WRDQSCTL_BB];
    break;
  case DYN_CCC_U32_WRDQCTL:
    DYNSTRUCT_CCC_U32_WRDQCTL = (U32_WRDQCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_U32_WRDQCTL->Bits.data = DynamicVars[Channel][ORIG_CC_WRDQCTL];
    break;
  case DYN_CCC_U32_WRDQSCTL:
    DYNSTRUCT_CCC_U32_WRDQSCTL = (U32_WRDQSCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_U32_WRDQSCTL->Bits.data = DynamicVars[Channel][ORIG_CC_WRDQSCTL];
    break;
  case DYN_CPGC_CPGC_DPAT_INV_DC_MASK_LO:
    DYNSTRUCT_CPGC_CPGC_DPAT_INV_DC_MASK_LO = (CPGC_DPAT_INV_DC_MASK_LO_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_DPAT_INV_DC_MASK_LO->Bits.data_inv_dc_mask_lo = DynamicVars[Channel][CAVREF];
    break;
  case DYN_DUNIT_D_CR_DRMC_6:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    break;
  case DYN_DQ_U32_WKPUPPDNCTL:
    DYNSTRUCT_DQ_U32_WKPUPPDNCTL = (U32_WKPUPPDNCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_U32_WKPUPPDNCTL->Bits.data = DynamicVars[Channel][ORIG_DQ_WKCTL];
    break;
  case DYN_CCC_U32_WKPUPPDNCTL:
    DYNSTRUCT_CCC_U32_WKPUPPDNCTL = (U32_WKPUPPDNCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_U32_WKPUPPDNCTL->Bits.data = DynamicVars[Channel][ORIG_CC_WKCTL];
    break;
  case DYN_DQ_RXODTCTL_BL13_7:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_dqsrxodtenovrval = DynamicVars[Channel][CC_DQSRXODTENOVRVAL];
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_dqsrxodtenovrsel = DynamicVars[Channel][CC_DQSRXODTENOVRSEL];
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenovrval = DynamicVars[Channel][CC_RXODTENOVRVAL];
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenovrsel = DynamicVars[Channel][CC_RXODTENOVRSEL];
    break;
  case DYN_CCC_RXODTSEGCTL_7:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegovrval = DynamicVars[Channel][RXODTSEGOVRVAL_ecc];
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegovrsel = DynamicVars[Channel][RXODTSEGOVRSEL_ecc];
    break;
  case DYN_DQ_RXODTCTL_DQ_7:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_dqsrxodtenovrval = DynamicVars[Channel][BL_DQSRXODTENOVRVAL];
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_dqsrxodtenovrsel = DynamicVars[Channel][BL_DQSRXODTENOVRSEL];
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenovrval = DynamicVars[Channel][BL_RXODTENOVRVAL];
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenovrsel = DynamicVars[Channel][BL_RXODTENOVRSEL];
    break;
  case DYN_DQ_WKPUPPDNCTL:
    DYNSTRUCT_DQ_WKPUPPDNCTL = (WKPUPPDNCTL_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_cc_weakpupstatic = DynamicVars[Channel][LVL_CC_WEAKPUPSTATIC];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_cc_weakpup = DynamicVars[Channel][LVL_CC_WEAKPUP];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_cc_weakpdnstatic = DynamicVars[Channel][LVL_CC_WEAKPDNSTATIC];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_cc_weakpdn = DynamicVars[Channel][LVL_CC_WEAKPDN];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_bl_weakpupstatic = DynamicVars[Channel][LVL_BL_WEAKPUPSTATIC];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_bl_weakpup = DynamicVars[Channel][LVL_BL_WEAKPUP];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_bl_weakpdnstatic = DynamicVars[Channel][LVL_BL_WEAKPDNSTATIC];
    DYNSTRUCT_DQ_WKPUPPDNCTL->Bits.lvl_bl_weakpdn = DynamicVars[Channel][LVL_BL_WEAKPDN];
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_VREF_0:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0 = (DPIC_GRCOMP_VREF_0_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp1 = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_4:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][VOC_RCOMP_PUP];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][VOC_RCOMP_PDN];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_4:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][VOC_RCOMP_PUP];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][VOC_RCOMP_PDN];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_5:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][RCOMP_Up_GRP0_dq0];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP0_dq0];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][RCOMP_Up_GRP1_dq0];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP1_dq0];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_6:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][RCOMP_Up_GRP0_dq1];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP0_dq1];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][RCOMP_Up_GRP1_dq1];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP1_dq1];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_7:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][RCOMP_Up_GRP0_dq2];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP0_dq2];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][RCOMP_Up_GRP1_dq2];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP1_dq2];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_OVR1_8:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][RCOMP_Up_GRP0_dq3];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP0_dq3];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][RCOMP_Up_GRP1_dq3];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP1_dq3];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR1_5:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1 = (DPIC_LRCOMP_OVR1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pu_override = DynamicVars[Channel][RCOMP_Up_GRP0];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp0_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP0];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pu_override = DynamicVars[Channel][RCOMP_Up_GRP1];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR1->Bits.lrcomp_pdgrp1_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP1];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR2_4:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2 = (DPIC_LRCOMP_OVR2_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pu_override = DynamicVars[Channel][RCOMP_Up_GRP2];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp2_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP2];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pu_override = DynamicVars[Channel][RCOMP_Up_GRP3];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR2->Bits.lrcomp_pdgrp3_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP3];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_OVR3_4:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3 = (DPIC_LRCOMP_OVR3_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pu_override = DynamicVars[Channel][RCOMP_Up_GRP4];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp4_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP4];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pu_override = DynamicVars[Channel][RCOMP_Up_GRP5];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_OVR3->Bits.lrcomp_pdgrp5_pd_override = DynamicVars[Channel][RCOMP_Dn_GRP5];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_PUPDOVR:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR = (DPIC_LRCOMP_PUPDOVR_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppd_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Up_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppu_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Dn_En];
    break;
  case DYN_DQDPLVUG_DPIC_LRCOMP_PUPDOVR:
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_PUPDOVR = (DPIC_LRCOMP_PUPDOVR_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppu_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Up_En_dq];
    DYNSTRUCT_DQDPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppd_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Dn_En_dq];
    break;
  case DYN_DPLVUG_DPIC_LRCOMP_PUPDOVR_1:
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR = (DPIC_LRCOMP_PUPDOVR_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppd_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Up_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppu_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Dn_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppd_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Up_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppu_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Dn_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppd_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Up_En];
    DYNSTRUCT_DPLVUG_DPIC_LRCOMP_PUPDOVR->Bits.lrcomppu_grp_override_en = DynamicVars[Channel][RCOMP_OVR_Dn_En];
    break;
  case DYN_DQ_RXODTSEGCTL_BL02_7:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02 = (RXODTSEGCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegovrval = DynamicVars[Channel][RCOMP_Seg_Ovr_Val_bl];
    DYNSTRUCT_DQ_RXODTSEGCTL_BL02->Bits.bl_rxodtsegovrsel = DynamicVars[Channel][RCOMP_Seg_Ovr_En_bl];
    break;
  case DYN_DQ_DIFFAMPCTL_BL02_13:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02 = (DIFFAMPCTL_BL02_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_dqsdiffampenovrval = DynamicVars[Channel][DIFF_Ovr_Val_bl];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL02->Bits.bl_dqsdiffampenovrsel = DynamicVars[Channel][DIFF_Ovr_Val_sel_bl];
    break;
  case DYN_DQ_RXODTSEGCTL_BL13_7:
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13 = (RXODTSEGCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegovrval = DynamicVars[Channel][RCOMP_Seg_Ovr_Val_bl];
    DYNSTRUCT_DQ_RXODTSEGCTL_BL13->Bits.cc_rxodtsegovrsel = DynamicVars[Channel][RCOMP_Seg_Ovr_En_bl];
    break;
  case DYN_DQ_DIFFAMPCTL_BL13_13:
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13 = (DIFFAMPCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_dqsdiffampenovrval = DynamicVars[Channel][DIFF_Ovr_Val_bl];
    DYNSTRUCT_DQ_DIFFAMPCTL_BL13->Bits.cc_dqsdiffampenovrsel = DynamicVars[Channel][DIFF_Ovr_Val_sel_bl];
    break;
  case DYN_CCC_DIFFAMPCTL_14:
    DYNSTRUCT_CCC_DIFFAMPCTL = (DIFFAMPCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.dqsdiffampenovrval = DynamicVars[Channel][DIFF_Ovr_Val_bl];
    DYNSTRUCT_CCC_DIFFAMPCTL->Bits.dqsdiffampenovrsel = DynamicVars[Channel][DIFF_Ovr_Val_sel_bl];
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_VREF_0_1:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0 = (DPIC_GRCOMP_VREF_0_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp0 = DynamicVars[Channel][comp_vref_0];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp1 = DynamicVars[Channel][comp_vref_1];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp2 = DynamicVars[Channel][comp_vref_2];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_0->Bits.comp_vref_grp3 = DynamicVars[Channel][comp_vref_3];
    break;
  case DYN_DPLVUG_DPIC_GRCOMP_VREF_1:
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1 = (DPIC_GRCOMP_VREF_1_DPLVUG_STRUCT *) Value;
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1->Bits.comp_vref_grp4 = DynamicVars[Channel][comp_vref_4];
    DYNSTRUCT_DPLVUG_DPIC_GRCOMP_VREF_1->Bits.comp_vref_grp5 = DynamicVars[Channel][comp_vref_5];
    break;
  case DYN_DQ_RXODTCTL_DQ_8:
    DYNSTRUCT_DQ_RXODTCTL_DQ = (RXODTCTL_DQ_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenovrsel = DynamicVars[Channel][RX_ODTEN_OVR_SEL_bl];
    DYNSTRUCT_DQ_RXODTCTL_DQ->Bits.bl_rxodtenovrval = DynamicVars[Channel][RX_ODTEN_OVR_VAL_bl];
    break;
  case DYN_CCC_RXODTSEGCTL_8:
    DYNSTRUCT_CCC_RXODTSEGCTL = (RXODTSEGCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegovrsel = DynamicVars[Channel][ECC_RX_ODTEN_OVR_SEL_bl];
    DYNSTRUCT_CCC_RXODTSEGCTL->Bits.rxodtsegovrval = DynamicVars[Channel][ECC_RX_ODTEN_OVR_VAL_bl];
    break;
  case DYN_CCC_RXODTCTL_7:
    DYNSTRUCT_CCC_RXODTCTL = (RXODTCTL_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenovrsel = DynamicVars[Channel][RX_ODTEN_OVR_SEL_bl];
    DYNSTRUCT_CCC_RXODTCTL->Bits.rxodtenovrval = DynamicVars[Channel][RX_ODTEN_OVR_VAL_bl];
    break;
  case DYN_DQ_RXODTCTL_BL13_8:
    DYNSTRUCT_DQ_RXODTCTL_BL13 = (RXODTCTL_BL13_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenovrsel = DynamicVars[Channel][RX_ODTEN_OVR_SEL_bl];
    DYNSTRUCT_DQ_RXODTCTL_BL13->Bits.cc_rxodtenovrval = DynamicVars[Channel][RX_ODTEN_OVR_VAL_bl];
    break;
  case DYN_DQ_VREFCTL0:
    DYNSTRUCT_DQ_VREFCTL0 = (VREFCTL0_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_VREFCTL0->Bits.vref_rxblvrefctrl = DynamicVars[Channel][RXBLVREFCTL];
    DYNSTRUCT_DQ_VREFCTL0->Bits.vref_rxccvrefctrl = DynamicVars[Channel][RXBLVREFCTL];
    break;
  case DYN_CCC_VREFCTL2:
    DYNSTRUCT_CCC_VREFCTL2 = (VREFCTL2_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_VREFCTL2->Bits.vref_dq_rxblvrefctrl = DynamicVars[Channel][RXBLVREFCTL];
    break;
  case DYN_DUNIT_D_CR_DRMC_7:
    DYNSTRUCT_DUNIT_D_CR_DRMC = (D_CR_DRMC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckemode = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DRMC->Bits.ckeval = DynamicVars[Channel][CKEVAL_VAR];
    break;
  case DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_1:
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL = (D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_int = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_en = 0x1;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_osc_rt = DynamicVars[Channel][DQS_OSC_RT];
    break;
  case DYN_DQDPLVUG_PTCTL0_6:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptloadcode_dly = DynamicVars[Channel][PTLDCODE];
    break;
  case DYN_DUNIT_D_CR_TQCTL_2:
    DYNSTRUCT_DUNIT_D_CR_TQCTL = (D_CR_TQCTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_TQCTL->Bits.tqpollen = DynamicVars[Channel][TQPOLLEN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DCAL:
    DYNSTRUCT_DUNIT_D_CR_DCAL = (D_CR_DCAL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DCAL->Bits.srxzqc = DynamicVars[Channel][SRXZQC_SAVE];
    DYNSTRUCT_DUNIT_D_CR_DCAL->Bits.zqcdis = DynamicVars[Channel][ZQDIS_SAVE];
    break;
  case DYN_DUNIT_D_CR_DRFC_2:
    DYNSTRUCT_DUNIT_D_CR_DRFC = (D_CR_DRFC_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DRFC->Bits.orefdis = DynamicVars[Channel][OREFDIS_SAVE];
    break;
  case DYN_DUNIT_D_CR_DPMC0:
    DYNSTRUCT_DUNIT_D_CR_DPMC0 = (D_CR_DPMC0_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC0->Bits.dynsren = DynamicVars[Channel][DYNSREN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DPMC1_1:
    DYNSTRUCT_DUNIT_D_CR_DPMC1 = (D_CR_DPMC1_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DPMC1->Bits.dispwrdn = DynamicVars[Channel][DISPWRDN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DQS_RETRAINING_CTL_2:
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL = (D_CR_DQS_RETRAINING_CTL_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_int = DynamicVars[Channel][DQS_RETRAIN_INT];
    DYNSTRUCT_DUNIT_D_CR_DQS_RETRAINING_CTL->Bits.dqs_retrain_en = DynamicVars[Channel][DQS_RETAIN_EN_SAVE];
    break;
  case DYN_DUNIT_D_CR_DTR4A_1:
    DYNSTRUCT_DUNIT_D_CR_DTR4A = (D_CR_DTR4A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR4A->Bits.trwdr = DynamicVars[Channel][TRWDR];
    break;
  case DYN_DUNIT_D_CR_DTR6A_1:
    DYNSTRUCT_DUNIT_D_CR_DTR6A = (D_CR_DTR6A_DUNIT_STRUCT *) Value;
    DYNSTRUCT_DUNIT_D_CR_DTR6A->Bits.tpstmrrblk = DynamicVars[Channel][TPSTMRRBLK];
    break;
  case DYN_DQDPLVUG_PTCTL0_7:
    DYNSTRUCT_DQDPLVUG_PTCTL0 = (PTCTL0_DQDPLVUG_STRUCT *) Value;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.ptrdtype2rdvld = DynamicVars[Channel][RDCMD2RDVLD]-1;
    DYNSTRUCT_DQDPLVUG_PTCTL0->Bits.pten = 0x1;
    break;
  case DYN_CPGC_CPGC_ERR_CTL_1:
    DYNSTRUCT_CPGC_CPGC_ERR_CTL = (CPGC_ERR_CTL_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC_ERR_CTL->Bits.errchk_mask_chunk = DynamicVars[Channel][CHUNK_ERR_MASK];
    break;
  case DYN_DQ_TXPBDCTL1:
    DYNSTRUCT_DQ_TXPBDCTL1 = (TXPBDCTL1_DQ_STRUCT *) Value;
    DYNSTRUCT_DQ_TXPBDCTL1->Bits.rxdll_cc_rxpbden = DynamicVars[Channel][SS_TEMP_VAR];
    DYNSTRUCT_DQ_TXPBDCTL1->Bits.rxdll_bl_rxpbden = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_CCC_TXPBDCTL1:
    DYNSTRUCT_CCC_TXPBDCTL1 = (TXPBDCTL1_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_TXPBDCTL1->Bits.rxdll_bl0_rxpbden = DynamicVars[Channel][SS_TEMP_VAR];
    DYNSTRUCT_CCC_TXPBDCTL1->Bits.rxdll_bl1_rxpbden = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_CCC_ECC_TXPBDCTL1:
    DYNSTRUCT_CCC_ECC_TXPBDCTL1 = (ECC_TXPBDCTL1_CCC_STRUCT *) Value;
    DYNSTRUCT_CCC_ECC_TXPBDCTL1->Bits.ecc_rxdll_rxpbden = DynamicVars[Channel][SS_TEMP_VAR];
    break;
  case DYN_CPGC_CPGC2_ADDRESS_SIZE_1:
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE = (CPGC2_ADDRESS_SIZE_CPGC_STRUCT *) Value;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_bits_col = DynamicVars[Channel][NUM_COLS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_bits_row = DynamicVars[Channel][NUM_ROWS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_num_banks = 0x8;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.block_size_num_ranks = 0x2;
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.region_size_bits_col = DynamicVars[Channel][NUM_COLS];
    DYNSTRUCT_CPGC_CPGC2_ADDRESS_SIZE->Bits.region_size_bits_row = DynamicVars[Channel][NUM_ROWS];
    break;
  default:
    *Value = 0xFFFFFFFF;
    break;
  }

  return MMRC_SUCCESS;
}

//
// Array of all MRS commands for a given channel.
//
#ifdef MR0_0
UINT16 MrsCommandIndex[MAX_RANKS][MR_COUNT] = {
{MR0_0, MR1_0, MR2_0},
{MR0_1, MR1_1, MR2_1},
};
#endif

//
// Table to convert a PFCT and IoLevel to a blueprint to access the correct IO GetSet tab.
//
CONST PFCT_AND_IO_LEVEL_TO_BLUEPRINT PfctAndIoLevelToBlueprint[MAX_IO_LEVELS] = {
//     Plat     Freq   Config               Tech      IoLevel          Blueprint
  {   P_ALL,   F_ALL,   C_ALL,            T_DDR3,    DdrLevel,    BLUEPRINT_DDR3},
  {   P_ALL,   F_ALL,   C_ALL,          T_LPDDR3,    DdrLevel, BLUEPRINT_LPDDR34},
  {   P_ALL,   F_ALL,   C_ALL,          T_LPDDR4,    DdrLevel, BLUEPRINT_LPDDR34},
};

INSTANCE_PORT_MAP InstancePortMapGenerated[MAX_BLUEPRINTS][MAX_BOXES] = {
  //TotalInst    Inst/Channel  StartIndex     R-Op     W-Op  Access Method  Access BAR   SimSupported     StrIndex
  { // BLUEPRINT_LPDDR34
    {     4,            1,         0,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000000}, // DUNIT
    {     4,            1,         4,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000046}, // CPGC
    {     8,            2,         8,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000015A}, // DQ
    {     2,            1,        16,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000001CC}, // CCC
    {     2,            1,        18,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000266}, // SAI
    {     2,            1,        20,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000273}, // ADPLL
    {     2,            1,        22,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000282}, // LDO
    {     2,            1,        24,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000028D}, // DPLVUG
    {     2,            1,        26,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002B6}, // DPIC
    {     8,            2,        28,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002EA}, // DQDPIC
    {     8,            2,        36,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000303}, // DQDPLVUG
    {     1,            0,        44,         0xFF,    0xFF,    ePCI,          MMRC_NA,       TRUE,      0x0000033C}, // CUNIT
    {     1,            0,        45,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000371}, // PUNIT
    {     1,            0,        46,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x000003AC}, // MLMC
    {     1,            0,        47,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x000003BE}, // AUNIT
    {     1,            0,        48,         0xFF,    0xFF,    ePCI,          MMRC_NA,       TRUE,      0x000003FC}, // P2SB
    {     1,            0,        49,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x0000042B}, // BUNIT
  },
  { // BLUEPRINT_DDR3
    {     2,            1,         0,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000000}, // DUNIT
    {     2,            1,         4,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000046}, // CPGC
    {     8,            4,         8,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000015A}, // DQ
    {     2,            1,        16,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000001CC}, // CCC
    {     2,            1,        18,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000266}, // SAI
    {     2,            1,        20,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000273}, // ADPLL
    {     2,            1,        22,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000282}, // LDO
    {     2,            1,        24,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x0000028D}, // DPLVUG
    {     2,            1,        26,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002B6}, // DPIC
    {     8,            4,        28,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x000002EA}, // DQDPIC
    {     8,            4,        36,         0xFF,    0xFF,    eBAR,          P2SBBAR,       TRUE,      0x00000303}, // DQDPLVUG
    {     1,            0,        44,         0xFF,    0xFF,    ePCI,          MMRC_NA,       TRUE,      0x0000033C}, // CUNIT
    {     1,            0,        45,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x00000371}, // PUNIT
    {     1,            0,        46,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x000003AC}, // MLMC
    {     1,            0,        47,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x000003BE}, // AUNIT
    {     1,            0,        48,         0xFF,    0xFF,    ePCI,          MMRC_NA,       TRUE,      0x000003FC}, // P2SB
    {     1,            0,        49,         0xFF,    0xFF,    eBAR,           MCHBAR,       TRUE,      0x0000042B}, // BUNIT
  },
};

INSTANCE_PORT_OFFSET InstancePortOffsetGenerated[MAX_BLUEPRINTS][MAX_INSTANCE_PORTS] = {
  { // BLUEPRINT_LPDDR34
  {0x0000, 0x1400}, // DUNIT0
  {0x0000, 0x1000}, // DUNIT1
  {0x0000, 0x1200}, // DUNIT2
  {0x0000, 0x1600}, // DUNIT3
  {0x0000, 0x4400}, // CPGC0
  {0x0000, 0x3C00}, // CPGC1
  {0x0000, 0x4000}, // CPGC2
  {0x0000, 0x4800}, // CPGC3
  {0x001C, 0x1000}, // DQ0
  {0x001C, 0x1800}, // DQ1
  {0x001C, 0x0000}, // DQ2
  {0x001C, 0x0800}, // DQ3
  {0x001D, 0x1000}, // DQ4
  {0x001D, 0x1800}, // DQ5
  {0x001D, 0x0000}, // DQ6
  {0x001D, 0x0800}, // DQ7
  {0x001C, 0x6000}, // CCC0
  {0x001D, 0x6000}, // CCC1
  {0x001C, 0x0000}, // SAI0
  {0x001D, 0x0000}, // SAI1
  {0x001C, 0xA800}, // ADPLL0
  {0x001D, 0xA800}, // ADPLL1
  {0x001C, 0xB000}, // LDO0
  {0x001D, 0xB000}, // LDO1
  {0x001C, 0x6800}, // DPLVUG0
  {0x001D, 0x6800}, // DPLVUG1
  {0x001C, 0x7000}, // DPIC0
  {0x001D, 0x7000}, // DPIC1
  {0x001C, 0x5000}, // DQDPIC0
  {0x001C, 0x5800}, // DQDPIC1
  {0x001C, 0x4000}, // DQDPIC2
  {0x001C, 0x4800}, // DQDPIC3
  {0x001D, 0x5000}, // DQDPIC4
  {0x001D, 0x5800}, // DQDPIC5
  {0x001D, 0x4000}, // DQDPIC6
  {0x001D, 0x4800}, // DQDPIC7
  {0x001C, 0x3000}, // DQDPLVUG0
  {0x001C, 0x3800}, // DQDPLVUG1
  {0x001C, 0x2000}, // DQDPLVUG2
  {0x001C, 0x2800}, // DQDPLVUG3
  {0x001D, 0x3000}, // DQDPLVUG4
  {0x001D, 0x3800}, // DQDPLVUG5
  {0x001D, 0x2000}, // DQDPLVUG6
  {0x001D, 0x2800}, // DQDPLVUG7
  {0x0000, 0x0000}, // CUNIT0
  {0x0000, 0x0000}, // PUNIT0
  {0x0000, 0x0000}, // MLMC0
  {0x0000, 0x0000}, // AUNIT0
  {0x0068, 0x0000}, // P2SB0
  {0x0000, 0x0000}, // BUNIT0
  },
  { // BLUEPRINT_DDR3
  {0x0000, 0x1400}, // DUNIT0
  {0x0000, 0x1200}, // DUNIT1
  {0xFFFF, 0xFFFF}, // Invalid Instance
  {0xFFFF, 0xFFFF}, // Invalid Instance
  {0x0000, 0x4400}, // CPGC0
  {0x0000, 0x4000}, // CPGC1
  {0xFFFF, 0xFFFF}, // Invalid Instance
  {0xFFFF, 0xFFFF}, // Invalid Instance
  {0x001C, 0x0000}, // DQ0
  {0x001C, 0x0800}, // DQ1
  {0x001C, 0x1000}, // DQ2
  {0x001C, 0x1800}, // DQ3
  {0x001D, 0x0000}, // DQ4
  {0x001D, 0x0800}, // DQ5
  {0x001D, 0x1000}, // DQ6
  {0x001D, 0x1800}, // DQ7
  {0x001C, 0x6000}, // CCC0
  {0x001D, 0x6000}, // CCC1
  {0x001C, 0x0000}, // SAI0
  {0x001D, 0x0000}, // SAI1
  {0x001C, 0xA800}, // ADPLL0
  {0x001D, 0xA800}, // ADPLL1
  {0x001C, 0xB000}, // LDO0
  {0x001D, 0xB000}, // LDO1
  {0x001C, 0x6800}, // DPLVUG0
  {0x001D, 0x6800}, // DPLVUG1
  {0x001C, 0x7000}, // DPIC0
  {0x001D, 0x7000}, // DPIC1
  {0x001C, 0x4000}, // DQDPIC0
  {0x001C, 0x4800}, // DQDPIC1
  {0x001C, 0x5000}, // DQDPIC2
  {0x001C, 0x5800}, // DQDPIC3
  {0x001D, 0x4000}, // DQDPIC4
  {0x001D, 0x4800}, // DQDPIC5
  {0x001D, 0x5000}, // DQDPIC6
  {0x001D, 0x5800}, // DQDPIC7
  {0x001C, 0x2000}, // DQDPLVUG0
  {0x001C, 0x2800}, // DQDPLVUG1
  {0x001C, 0x3000}, // DQDPLVUG2
  {0x001C, 0x3800}, // DQDPLVUG3
  {0x001D, 0x2000}, // DQDPLVUG4
  {0x001D, 0x2800}, // DQDPLVUG5
  {0x001D, 0x3000}, // DQDPLVUG6
  {0x001D, 0x3800}, // DQDPLVUG7
  {0x0000, 0x0000}, // CUNIT0
  {0x0000, 0x0000}, // PUNIT0
  {0x0000, 0x0000}, // MLMC0
  {0x0000, 0x0000}, // AUNIT0
  {0x0068, 0x0000}, // P2SB0
  {0x0000, 0x0000}, // BUNIT0
  },
};

UINT8 ChannelToInstanceMapGenerated[MAX_BLUEPRINTS][MAX_BOXES][MAX_CHANNELS] = {
//CH00  CH01  CH02  CH03
  { // BLUEPRINT_LPDDR34
  {0x00, 0x01, 0x02, 0x03}, // DUNIT
  {0x00, 0x01, 0x02, 0x03}, // CPGC
  {0x00, 0x02, 0x04, 0x06}, // DQ
  {0x00, 0xFF, 0x01, 0xFF}, // CCC
  {0x00, 0xFF, 0x01, 0xFF}, // SAI
  {0x00, 0xFF, 0x01, 0xFF}, // ADPLL
  {0x00, 0x00, 0x01, 0x01}, // LDO
  {0x00, 0x00, 0x01, 0x01}, // DPLVUG
  {0x00, 0xFF, 0x01, 0xFF}, // DPIC
  {0x00, 0x02, 0x04, 0x06}, // DQDPIC
  {0x00, 0x02, 0x04, 0x06}, // DQDPLVUG
  {0x00, 0x00, 0x00, 0x00}, // CUNIT
  {0x00, 0x00, 0x00, 0x00}, // PUNIT
  {0x00, 0x00, 0x00, 0x00}, // MLMC
  {0x00, 0x00, 0x00, 0x00}, // AUNIT
  {0x00, 0x00, 0x00, 0x00}, // P2SB
  {0x00, 0x00, 0x00, 0x00}, // BUNIT
  },
  { // BLUEPRINT_DDR3
  {0x00, 0x01, 0xFF, 0xFF}, // DUNIT
  {0x00, 0x01, 0xFF, 0xFF}, // CPGC
  {0x00, 0x04, 0xFF, 0xFF}, // DQ
  {0x00, 0x01, 0xFF, 0xFF}, // CCC
  {0x00, 0x01, 0xFF, 0xFF}, // SAI
  {0x00, 0x01, 0xFF, 0xFF}, // ADPLL
  {0x00, 0x01, 0xFF, 0xFF}, // LDO
  {0x00, 0x01, 0xFF, 0xFF}, // DPLVUG
  {0x00, 0x01, 0xFF, 0xFF}, // DPIC
  {0x00, 0x04, 0xFF, 0xFF}, // DQDPIC
  {0x00, 0x04, 0xFF, 0xFF}, // DQDPLVUG
  {0x00, 0x00, 0x00, 0x00}, // CUNIT
  {0x00, 0x00, 0x00, 0x00}, // PUNIT
  {0x00, 0x00, 0x00, 0x00}, // MLMC
  {0x00, 0x00, 0x00, 0x00}, // AUNIT
  {0x00, 0x00, 0x00, 0x00}, // P2SB
  {0x00, 0x00, 0x00, 0x00}, // BUNIT
  },
};

#if CAPSULESTRINGS
CONST UINT8 UnitStringsGenerated[MAX_BLUEPRINTS][MAX_BOXES][MAX_BOXNAME_LENGTH] = {
  { // BLUEPRINT_LPDDR34
  {"DUNIT   "}, // 000
  {"CPGC    "}, // 001
  {"DQ      "}, // 002
  {"CCC     "}, // 003
  {"SAI     "}, // 004
  {"ADPLL   "}, // 005
  {"LDO     "}, // 006
  {"DPLVUG  "}, // 007
  {"DPIC    "}, // 008
  {"DQDPIC  "}, // 009
  {"DQDPLVUG"}, // 00A
  {"CUNIT   "}, // 00B
  {"PUNIT   "}, // 00C
  {"MLMC    "}, // 00D
  {"AUNIT   "}, // 00E
  {"P2SB    "}, // 00F
  {"BUNIT   "}, // 010
  },
  { // BLUEPRINT_DDR3
  {"DUNIT   "}, // 000
  {"CPGC    "}, // 001
  {"DQ      "}, // 002
  {"CCC     "}, // 003
  {"SAI     "}, // 004
  {"ADPLL   "}, // 005
  {"LDO     "}, // 006
  {"DPLVUG  "}, // 007
  {"DPIC    "}, // 008
  {"DQDPIC  "}, // 009
  {"DQDPLVUG"}, // 00A
  {"CUNIT   "}, // 00B
  {"PUNIT   "}, // 00C
  {"MLMC    "}, // 00D
  {"AUNIT   "}, // 00E
  {"P2SB    "}, // 00F
  {"BUNIT   "}, // 010
  },
};
#endif // CAPSULESTRINGS

//
// Floorplan layout to map logical channel and strobe to a physical channel and strobe.
//
CONST FLOORPLAN FloorPlanGenerated[MAX_BLUEPRINTS][MAX_CHANNELS][MAX_STROBES] = {
//     S0       S1       S2       S3       S4       S5       S6       S7       S8
  { // BLUEPRINT_LPDDR34
  {  {0,0},   {0,1},   {0,2},   {0,3},   {0,4},   {0,5},   {0,6},   {0,7},   {0,8}}, // CH0
  {  {1,0},   {1,1},   {1,2},   {1,3},   {1,4},   {1,5},   {1,6},   {1,7},   {1,8}}, // CH1
  {  {2,0},   {2,1},   {2,2},   {2,3},   {2,4},   {2,5},   {2,6},   {2,7},   {2,8}}, // CH2
  {  {3,0},   {3,1},   {3,2},   {3,3},   {3,4},   {3,5},   {3,6},   {3,7},   {3,8}}, // CH3
  },
  { // BLUEPRINT_DDR3
  {  {0,4},   {0,5},   {0,6},   {0,7},   {0,0},   {0,1},   {0,2},   {0,3},   {0,8}}, // CH0
  {  {1,4},   {1,5},   {1,6},   {1,7},   {1,0},   {1,1},   {1,2},   {1,3},   {1,8}}, // CH1
  {  {2,0},   {2,1},   {2,2},   {2,3},   {2,4},   {2,5},   {2,6},   {2,7},   {2,8}}, // CH2
  {  {3,0},   {3,1},   {3,2},   {3,3},   {3,4},   {3,5},   {3,6},   {3,7},   {3,8}}, // CH3
  },
};
//
// Given a base register (i.e. Strobe0/Rank0's copy of the register, these tables index to the correct register location for a given strobe/rank.
//
CONST INT16 StrobeToRegisterGenerated[MAX_BLUEPRINTS][MAX_STROBES][2] = {
//  Sub-box Offset  Register Offset
  { // BLUEPRINT_LPDDR34
  {0,              0},             // S0
  {0,              0},             // S1
  {0,              0},             // S2
  {0,              0},             // S3
  {0,              0},             // S4
  {0,              0},             // S5
  {0,              0},             // S6
  {0,              0},             // S7
  {0,              0},             // S8
  },
  { // BLUEPRINT_DDR3
  {0,              0},             // S0
  {0,              0},             // S1
  {0,              0},             // S2
  {0,              0},             // S3
  {0,              0},             // S4
  {0,              0},             // S5
  {0,              0},             // S6
  {0,              0},             // S7
  {0,              0},             // S8
  },
};

CONST INT16 RankToRegisterGenerated[MAX_BLUEPRINTS][MAX_RANKS][2] = {
//  Sub-box Offset  Register Offset
  { // BLUEPRINT_LPDDR34
   {0,              0},             // R0
   {0,              0},             // R1
  },
  { // BLUEPRINT_DDR3
   {0,              0},             // R0
   {0,              0},             // R1
  },
};
//
// Mapping of GSM_GT enumerated types to internal MMRC define.
//
UINT16 GsmGtToMmrcDefine[] = {
  MmrcRecEnDelay,
  MmrcRxDqsDelay,
  MMRC_NA,
  MmrcRxDqsPDelay,
  MmrcRxDqsNDelay,
  MmrcRxVref,
  MMRC_NA,
  MmrcRxDqBitDelay,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MmrcTxDqsDelay,
  MmrcTxDqDelay,
  MmrcTxVref,
  MMRC_NA,
  MmrcTxDqBitDelay,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MmrcCmdAll,
  MmrcCmdGrp0,
  MMRC_NA,
  MMRC_NA,
  MmrcCtlAll,
  MmrcCtlGrp0,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MmrcCkGrp0,
  MMRC_NA,
  MmrcTxCaVref,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
};
//
// Mapping of GSM_CSN enumerated types to internal MMRC define.
//
UINT16 GsmCsnToMmrcDefine[] = {
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
  MMRC_NA,
};
//
// External functions that need to be called for GetSet elements which require and external function to read/write the element.
//
EXTERNAL_GETSET_FUNCTION ExternalFunctions [] = {
{ GetSetCkeAll }, // CkeAll
{ GetSetCkGrp0 }, // CkGrp0
{ GetSetCmdAll }, // CmdAll
{ GetSetCmdGrp0 }, // CmdGrp0
{ GetSetCtlAll }, // CtlAll
{ GetSetCtlGrp0 }, // CtlGrp0
{ GetSetRecEnDelay }, // RecEnDelay
{ GetSetRecEnSmp }, // RecEnSmp
{ GetSetRxDqsDelay }, // RxDqsDelay
{ GetSetRxDqsNDelay }, // RxDqsNDelay
{ GetSetRxDqsPDelay }, // RxDqsPDelay
{ GetSetRxVocValAll }, // RxVocValAll
{ GetSetRxVrefDelay }, // RxVref
{ GetSetTxCaVref }, // TxCaVref
{ GetSetTxDqBitDelay }, // TxDqBitDelay
{ GetSetTxDqDelay }, // TxDqDelay
{ GetSetTxDqsDelay }, // TxDqsDelay
{ GetSetTxVref }, // TxVref
{ GetSetWrLvlSmp }, // WrLvlSmp
{ GetSetTimingMode }, // TimingMode
};
//
// DLL indexes into the HalfClk array for analog and digital DLLs.
//
UINT8 ADdllGenerated[MAX_BLUEPRINTS][2] = {
  // BLUEPRINT_LPDDR34
  {MMRC_NA, 0  },

  // BLUEPRINT_DDR3
  {MMRC_NA, 0  },

};
//
// The number of ticks in the 2X clock for analog and digital DLL. These can change depending on frequency.
//
UINT16 HalfClkGenerated[MAX_BLUEPRINTS][MAX_DLL_COUNT][NUM_FREQ] = {
  { // BLUEPRINT_LPDDR34
  { 248,  184,  152,  104,   88,   72,   64,   72,   68,   64  }, //  Digital DLL
  },
  { // BLUEPRINT_DDR3
  { 248,  184,  152,  104,   88,   72,   64,   72,   68,   64  }, //  Digital DLL
  },
};
//
// This array has all delays listed for analog DLL and digital DLL (depending on which are present), per frequency. Typically the first two delays on each line are the 1X clock and 2X clock.
//
UINT16 GranularityGenerated[MAX_BLUEPRINTS][MAX_DLL_COUNT][NUM_FREQ][MAX_NUM_DELAY_ELEMENTS] = {
  { // BLUEPRINT_LPDDR34
  // Digital DLL
  {
    {  496,  248,    1}, //  800
    {  368,  184,    1}, //  1066
    {  304,  152,    1}, //  1333
    {  208,  104,    1}, //  1600
    {  176,   88,    1}, //  1866
    {  144,   72,    1}, //  2133
    {  128,   64,    1}, //  2400
    {  144,   72,    1}, //  2667
    {  136,   68,    1}, //  2933
    {  128,   64,    1}, //  3200
  },
  },
  { // BLUEPRINT_DDR3
  // Digital DLL
  {
    {  496,  248,    1}, //  800
    {  368,  184,    1}, //  1066
    {  304,  152,    1}, //  1333
    {  208,  104,    1}, //  1600
    {  176,   88,    1}, //  1866
    {  144,   72,    1}, //  2133
    {  128,   64,    1}, //  2400
    {  144,   72,    1}, //  2667
    {  136,   68,    1}, //  2933
    {  128,   64,    1}, //  3200
  },
  },
};
//
// Clock crossings or deadbands. If the the delay value is between Min and Max, then InVal is used for the clock crossing.
// If Absolute is TRUE, InVal is programmed directly into the register. If FALSE, it is added to the current value of the register.
//
CLOCK_CROSSINGS ClockCrossingsGenerated[MAX_BLUEPRINTS][MAX_NUM_CC_RANGES]  = {
  // CcNum Min%  Max%  InVal Absolute
  { // BLUEPRINT_LPDDR34
  {    0,    0,   25,    3,    TRUE}, // CC0
  {    0,   25,   50,    1,    TRUE}, // CC0
  {    0,   50,   75,    0,    TRUE}, // CC0
  {    0,   75,  100,    2,    TRUE}, // CC0
  {    1,    0,   25,    1,    TRUE}, // CC1
  {    1,   25,   50,    1,    TRUE}, // CC1
  {    1,   50,   75,    0,    TRUE}, // CC1
  {    1,   75,  100,    1,    TRUE}, // CC1
  {    2,    0,   25,   -1,   FALSE}, // CC2
  {    2,   25,   50,   -1,   FALSE}, // CC2
  {    2,   50,   75,    0,   FALSE}, // CC2
  {    2,   75,  100,    0,   FALSE}, // CC2
  },
  { // BLUEPRINT_DDR3
  {    0,    0,   25,    3,    TRUE}, // CC0
  {    0,   25,   50,    0,    TRUE}, // CC0
  {    0,   50,   75,    0,    TRUE}, // CC0
  {    0,   75,  100,    3,    TRUE}, // CC0
  {    1,    0,   25,    1,    TRUE}, // CC1
  {    1,   25,   50,    1,    TRUE}, // CC1
  {    1,   50,   75,    0,    TRUE}, // CC1
  {    1,   75,  100,    1,    TRUE}, // CC1
  {    2,    0,   25,   -1,   FALSE}, // CC2
  {    2,   25,   50,    0,   FALSE}, // CC2
  {    2,   50,   75,    0,   FALSE}, // CC2
  {    2,   75,  100,    0,   FALSE}, // CC2
  },
};
//
// Digital DLL ranges. These are used to specify the min and max of the Digital DLL range per frequency. Also describes any holes in the range like ValleyView had.
//
const DIGITAL_DLL_LIST DigitalDllRangesGenerated[MAX_BLUEPRINTS][NUM_FREQ] = {
  { // BLUEPRINT_LPDDR34
  // PI     Min0     Max0     Min1     Max1
  { 248,       0,     247, MMRC_NA, MMRC_NA}, // 800
  { 184,       0,     183, MMRC_NA, MMRC_NA}, // 1066
  { 152,       0,     151, MMRC_NA, MMRC_NA}, // 1333
  { 104,       0,     103, MMRC_NA, MMRC_NA}, // 1600
  {  88,       0,      87, MMRC_NA, MMRC_NA}, // 1866
  {  72,       0,      71, MMRC_NA, MMRC_NA}, // 2133
  {  64,       0,      63, MMRC_NA, MMRC_NA}, // 2400
  {  72,       0,      71, MMRC_NA, MMRC_NA}, // 2667
  {  68,       0,      67, MMRC_NA, MMRC_NA}, // 2933
  {  64,       0,      63, MMRC_NA, MMRC_NA}, // 3200
  },
  { // BLUEPRINT_DDR3
  // PI     Min0     Max0     Min1     Max1
  { 248,       0,     247, MMRC_NA, MMRC_NA}, // 800
  { 184,       0,     183, MMRC_NA, MMRC_NA}, // 1066
  { 152,       0,     151, MMRC_NA, MMRC_NA}, // 1333
  { 104,       0,     103, MMRC_NA, MMRC_NA}, // 1600
  {  88,       0,      87, MMRC_NA, MMRC_NA}, // 1866
  {  72,       0,      71, MMRC_NA, MMRC_NA}, // 2133
  {  64,       0,      63, MMRC_NA, MMRC_NA}, // 2400
  {  72,       0,      71, MMRC_NA, MMRC_NA}, // 2667
  {  68,       0,      67, MMRC_NA, MMRC_NA}, // 2933
  {  64,       0,      63, MMRC_NA, MMRC_NA}, // 3200
  },
};
//
// List out the number of signal groups and the strings for each signal group.
//
SIGNAL_INFO SignalInfoGenerated[MAX_BLUEPRINTS][MAX_SIGNAL_INFO_ELEMENTS] = {
  { // BLUEPRINT_LPDDR34
// SigGrp NextFreq FreqIndex        VREF      Minus1                SigName
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "ClkCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "ClkCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CmdCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CmdCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CtlCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CtlCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxDqsNDelay_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxDqsPDelay_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,     "TxDqDelay_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "TxDqDrive"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxDqsDelay_dq"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,        "RecEnDelay_dq"},
  {     2,       1,        0,    MMRC_NA,    MMRC_NA,       "RecEnPiCode_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "CaVref_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkeAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkeCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkeCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkGrp0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CmdAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,              "CmdGrp0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CtlAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,              "CtlGrp0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "CURRENT_INDEX"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "DQS_CNT_RESET"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "FifoReset"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "INITIAL_INDEX"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "MuxcodeMax"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "MuxcodeMin"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "OdtEnOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "OdtSegEnOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "R2RRcvnEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "R2RRxDqsEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "R2RTxDqEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "R2RTxDqsEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA, "RDCMD2RDVLD_PLUS1SEL"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "RDCMD2RDVLD_REG"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RdRk2RkLatency"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RecEnDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "RecEnSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RecEnSmp_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxDqsDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RxDqsNDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RxDqsPDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocEnDq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxVocEnDqs"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "RxVocSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RxVocValAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "RxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVref_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "TrrdrGetSet"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "TxCaVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "TxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "TxDqDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "TxDqsDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "TxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxVref_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "WrLvlSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "WrLvlSmp_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,              "WrPtrEn"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal0"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal1"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal2"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal3"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal4"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal5"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal6"},
  {     8,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal7"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  {     0,       0,        0,    MMRC_NA,    MMRC_NA,        "INVALID ENTRY"},
  },
  { // BLUEPRINT_DDR3
// SigGrp NextFreq FreqIndex        VREF      Minus1                SigName
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "ClkCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "ClkCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CmdCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CmdCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CtlCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CtlCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxDqsNDelay_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "RxDqsNDelay_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxDqsPDelay_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "RxDqsPDelay_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,     "TxDqDelay_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA, "TxDqDelay_Actual_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "TxDqDrive"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxDqDrive_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxDqsDelay_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "TxDqsDelay_Ecc"},
  {     4,       1,        0,    MMRC_NA,    MMRC_NA,        "RecEnDelay_dq"},
  {     4,       1,        0,    MMRC_NA,    MMRC_NA,       "RecEnDelay_Ecc"},
  {     4,       1,        0,    MMRC_NA,    MMRC_NA,       "RecEnPiCode_dq"},
  {     4,       1,        0,    MMRC_NA,    MMRC_NA,      "RecEnPiCode_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "CaVref_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkeAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkeCh0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkeCh1"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CkGrp0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CmdAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,              "CmdGrp0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "CtlAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,              "CtlGrp0"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "CURRENT_INDEX"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "DQS_CNT_RESET"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,    "DQS_CNT_RESET_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "FifoReset"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "FifoReset_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "INITIAL_INDEX"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "MuxcodeMax"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "MuxcodeMax_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "MuxcodeMin"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "MuxcodeMin_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "OdtEnOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "OdtEnOff_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "OdtSegEnOff"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "OdtSegEnOff_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "R2RRcvnEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "R2RRcvnEn_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "R2RRxDqsEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "R2RRxDqsEn_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "R2RTxDqEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "R2RTxDqEn_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "R2RTxDqsEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "R2RTxDqsEn_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA, "RDCMD2RDVLD_PLUS1SEL"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,      "RDCMD2RDVLD_REG"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RdRk2RkLatency"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,   "RdRk2RkLatency_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RecEnDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "RecEnSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RecEnSmp_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RecEnSmp_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxDqsDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RxDqsNDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RxDqsPDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocEnDq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocEnDq_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxVocEnDqs"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,       "RxVocEnDqs_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "RxVocSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "RxVocSmp_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "RxVocValAll"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "RxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVref_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "RxVref_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "TimingMode"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "TrrdrGetSet"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "TxCaVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "TxDqBitDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,            "TxDqDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,           "TxDqsDelay"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,               "TxVref"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,        "TxVref_Actual"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,             "WrLvlSmp"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "WrLvlSmp_dq"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,         "WrLvlSmp_Ecc"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,              "WrPtrEn"},
  {     1,       1,        0,    MMRC_NA,    MMRC_NA,          "WrPtrEn_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal0"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal0_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal1"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal1_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal2"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal2_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal3"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal3_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal4"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal4_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal5"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal5_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal6"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal6_Ecc"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,            "RxVocVal7"},
  {    16,       1,        0,    MMRC_NA,    MMRC_NA,        "RxVocVal7_Ecc"},
  },
};
//
// Layer to get the right number of Algos
//
CONST UINT8 NumberAlgosGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_ALGOS_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_ALGOS_BLUEPRINT_DDR3,
};
//
// Layer to get the right number of CC Dependent Elements
//
CONST UINT8 NumberOfDependantElementsGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_CC_DEPENDENT_ELEMENTS_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_CC_DEPENDENT_ELEMENTS_BLUEPRINT_DDR3,
};
//
// Layer to get the right number of Delay Elements per Algo
//
CONST UINT8 NumberOfDelayElementsPerAlgoGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_DELAY_ELEMENTS_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_DELAY_ELEMENTS_BLUEPRINT_DDR3,
};
//
// Layer to get the right number of CC Elements
//
CONST UINT8 NumberOfCCElementsGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_CC_ELEMENTS_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_CC_ELEMENTS_BLUEPRINT_DDR3,
};
//
// Layer to get the right number of CC Ranges
//
CONST UINT8 NumberOfCCRangesGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_CC_RANGES_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_CC_RANGES_BLUEPRINT_DDR3,
};
//
// Layer to get the right number of elementes (delay + CC) per Algo
//
CONST UINT8 NumberOfElementsPerAlgoGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_ELEMENTS_PER_ALGO_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_ELEMENTS_PER_ALGO_BLUEPRINT_DDR3,
};
//
// Layer to get the right number of DVFS frequencies supported
//
CONST UINT8 NumberOfFrequenciesGenerated[MAX_BLUEPRINTS] = {
  // BLUEPRINT_LPDDR34
  NUM_DVFS_BLUEPRINT_LPDDR34,
  // BLUEPRINT_DDR3
  NUM_DVFS_BLUEPRINT_DDR3,
};
//
// Layer to get the right offset of a Delay
//
CONST INDEX_TO_OFFSET_LAYER DelayIndexToOffsetLayerGenerated[MAX_BLUEPRINTS][MAX_NUM_ALGOS] = {
  { // BLUEPRINT_LPDDR34
  {ClkCh0_BLUEPRINT_LPDDR34},
  {ClkCh1_BLUEPRINT_LPDDR34},
  {CmdCh0_BLUEPRINT_LPDDR34},
  {CmdCh1_BLUEPRINT_LPDDR34},
  {CtlCh0_BLUEPRINT_LPDDR34},
  {CtlCh1_BLUEPRINT_LPDDR34},
  {RxDqsNDelay_dq_BLUEPRINT_LPDDR34},
  {RxDqsPDelay_dq_BLUEPRINT_LPDDR34},
  {TxDqDelay_Actual_BLUEPRINT_LPDDR34},
  {TxDqDrive_BLUEPRINT_LPDDR34},
  {TxDqsDelay_dq_BLUEPRINT_LPDDR34},
  {RecEnDelay_dq_BLUEPRINT_LPDDR34},
  {RecEnPiCode_dq_BLUEPRINT_LPDDR34},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  },
  { // BLUEPRINT_DDR3
  {ClkCh0_BLUEPRINT_DDR3},
  {ClkCh1_BLUEPRINT_DDR3},
  {CmdCh0_BLUEPRINT_DDR3},
  {CmdCh1_BLUEPRINT_DDR3},
  {CtlCh0_BLUEPRINT_DDR3},
  {CtlCh1_BLUEPRINT_DDR3},
  {RxDqsNDelay_dq_BLUEPRINT_DDR3},
  {RxDqsPDelay_dq_BLUEPRINT_DDR3},
  {TxDqDelay_Actual_BLUEPRINT_DDR3},
  {TxDqDrive_BLUEPRINT_DDR3},
  {TxDqsDelay_dq_BLUEPRINT_DDR3},
  {RecEnDelay_dq_BLUEPRINT_DDR3},
  {RecEnPiCode_dq_BLUEPRINT_DDR3},
  {RxDqsNDelay_Ecc_BLUEPRINT_DDR3},
  {RxDqsPDelay_Ecc_BLUEPRINT_DDR3},
  {TxDqDelay_Actual_Ecc_BLUEPRINT_DDR3},
  {TxDqDrive_Ecc_BLUEPRINT_DDR3},
  {TxDqsDelay_Ecc_BLUEPRINT_DDR3},
  {RecEnDelay_Ecc_BLUEPRINT_DDR3},
  {RecEnPiCode_Ecc_BLUEPRINT_DDR3},
  },
};
//
// Layer to get the right offset of a Group
//
CONST INDEX_TO_OFFSET_LAYER GroupIndexToOffsetLayerGenerated[MAX_BLUEPRINTS][MAX_NUM_GROUP] = {
  { // BLUEPRINT_LPDDR34
  {R_BLUEPRINT_LPDDR34},
  },
  { // BLUEPRINT_DDR3
  {R_BLUEPRINT_DDR3},
  },
};
//
// Layer to get the right offset of a Unique
//
CONST INDEX_TO_OFFSET_LAYER UniqueIndexToOffsetLayerGenerated[MAX_BLUEPRINTS][MAX_NUM_UNIQUE] = {
  { // BLUEPRINT_LPDDR34
  {CaVref_Actual_BLUEPRINT_LPDDR34},
  {CkeAll_BLUEPRINT_LPDDR34},
  {CkeCh0_BLUEPRINT_LPDDR34},
  {CkeCh1_BLUEPRINT_LPDDR34},
  {CkGrp0_BLUEPRINT_LPDDR34},
  {CmdAll_BLUEPRINT_LPDDR34},
  {CmdGrp0_BLUEPRINT_LPDDR34},
  {CtlAll_BLUEPRINT_LPDDR34},
  {CtlGrp0_BLUEPRINT_LPDDR34},
  {CURRENT_INDEX_BLUEPRINT_LPDDR34},
  {DQS_CNT_RESET_BLUEPRINT_LPDDR34},
  {FifoReset_BLUEPRINT_LPDDR34},
  {INITIAL_INDEX_BLUEPRINT_LPDDR34},
  {MuxcodeMax_BLUEPRINT_LPDDR34},
  {MuxcodeMin_BLUEPRINT_LPDDR34},
  {OdtEnOff_BLUEPRINT_LPDDR34},
  {OdtSegEnOff_BLUEPRINT_LPDDR34},
  {R2RRcvnEn_BLUEPRINT_LPDDR34},
  {R2RRxDqsEn_BLUEPRINT_LPDDR34},
  {R2RTxDqEn_BLUEPRINT_LPDDR34},
  {R2RTxDqsEn_BLUEPRINT_LPDDR34},
  {RDCMD2RDVLD_PLUS1SEL_BLUEPRINT_LPDDR34},
  {RDCMD2RDVLD_REG_BLUEPRINT_LPDDR34},
  {RdRk2RkLatency_BLUEPRINT_LPDDR34},
  {RecEnDelay_BLUEPRINT_LPDDR34},
  {RecEnSmp_BLUEPRINT_LPDDR34},
  {RecEnSmp_dq_BLUEPRINT_LPDDR34},
  {RxDqBitDelay_BLUEPRINT_LPDDR34},
  {RxDqsDelay_BLUEPRINT_LPDDR34},
  {RxDqsNDelay_BLUEPRINT_LPDDR34},
  {RxDqsPDelay_BLUEPRINT_LPDDR34},
  {RxVocEnDq_BLUEPRINT_LPDDR34},
  {RxVocEnDqs_BLUEPRINT_LPDDR34},
  {RxVocSmp_BLUEPRINT_LPDDR34},
  {RxVocValAll_BLUEPRINT_LPDDR34},
  {RxVref_BLUEPRINT_LPDDR34},
  {RxVref_dq_BLUEPRINT_LPDDR34},
  {TrrdrGetSet_BLUEPRINT_LPDDR34},
  {TxCaVref_BLUEPRINT_LPDDR34},
  {TxDqBitDelay_BLUEPRINT_LPDDR34},
  {TxDqDelay_BLUEPRINT_LPDDR34},
  {TxDqsDelay_BLUEPRINT_LPDDR34},
  {TxVref_BLUEPRINT_LPDDR34},
  {TxVref_Actual_BLUEPRINT_LPDDR34},
  {WrLvlSmp_BLUEPRINT_LPDDR34},
  {WrLvlSmp_dq_BLUEPRINT_LPDDR34},
  {WrPtrEn_BLUEPRINT_LPDDR34},
  {RxVocVal0_BLUEPRINT_LPDDR34},
  {RxVocVal1_BLUEPRINT_LPDDR34},
  {RxVocVal2_BLUEPRINT_LPDDR34},
  {RxVocVal3_BLUEPRINT_LPDDR34},
  {RxVocVal4_BLUEPRINT_LPDDR34},
  {RxVocVal5_BLUEPRINT_LPDDR34},
  {RxVocVal6_BLUEPRINT_LPDDR34},
  {RxVocVal7_BLUEPRINT_LPDDR34},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  {REG_UNDEFINED},
  },
  { // BLUEPRINT_DDR3
  {CaVref_Actual_BLUEPRINT_DDR3},
  {CkeAll_BLUEPRINT_DDR3},
  {CkeCh0_BLUEPRINT_DDR3},
  {CkeCh1_BLUEPRINT_DDR3},
  {CkGrp0_BLUEPRINT_DDR3},
  {CmdAll_BLUEPRINT_DDR3},
  {CmdGrp0_BLUEPRINT_DDR3},
  {CtlAll_BLUEPRINT_DDR3},
  {CtlGrp0_BLUEPRINT_DDR3},
  {CURRENT_INDEX_BLUEPRINT_DDR3},
  {DQS_CNT_RESET_BLUEPRINT_DDR3},
  {FifoReset_BLUEPRINT_DDR3},
  {INITIAL_INDEX_BLUEPRINT_DDR3},
  {MuxcodeMax_BLUEPRINT_DDR3},
  {MuxcodeMin_BLUEPRINT_DDR3},
  {OdtEnOff_BLUEPRINT_DDR3},
  {OdtSegEnOff_BLUEPRINT_DDR3},
  {R2RRcvnEn_BLUEPRINT_DDR3},
  {R2RRxDqsEn_BLUEPRINT_DDR3},
  {R2RTxDqEn_BLUEPRINT_DDR3},
  {R2RTxDqsEn_BLUEPRINT_DDR3},
  {RDCMD2RDVLD_PLUS1SEL_BLUEPRINT_DDR3},
  {RDCMD2RDVLD_REG_BLUEPRINT_DDR3},
  {RdRk2RkLatency_BLUEPRINT_DDR3},
  {RecEnDelay_BLUEPRINT_DDR3},
  {RecEnSmp_BLUEPRINT_DDR3},
  {RecEnSmp_dq_BLUEPRINT_DDR3},
  {RxDqBitDelay_BLUEPRINT_DDR3},
  {RxDqsDelay_BLUEPRINT_DDR3},
  {RxDqsNDelay_BLUEPRINT_DDR3},
  {RxDqsPDelay_BLUEPRINT_DDR3},
  {RxVocEnDq_BLUEPRINT_DDR3},
  {RxVocEnDqs_BLUEPRINT_DDR3},
  {RxVocSmp_BLUEPRINT_DDR3},
  {RxVocValAll_BLUEPRINT_DDR3},
  {RxVref_BLUEPRINT_DDR3},
  {RxVref_dq_BLUEPRINT_DDR3},
  {TrrdrGetSet_BLUEPRINT_DDR3},
  {TxCaVref_BLUEPRINT_DDR3},
  {TxDqBitDelay_BLUEPRINT_DDR3},
  {TxDqDelay_BLUEPRINT_DDR3},
  {TxDqsDelay_BLUEPRINT_DDR3},
  {TxVref_BLUEPRINT_DDR3},
  {TxVref_Actual_BLUEPRINT_DDR3},
  {WrLvlSmp_BLUEPRINT_DDR3},
  {WrLvlSmp_dq_BLUEPRINT_DDR3},
  {WrPtrEn_BLUEPRINT_DDR3},
  {RxVocVal0_BLUEPRINT_DDR3},
  {RxVocVal1_BLUEPRINT_DDR3},
  {RxVocVal2_BLUEPRINT_DDR3},
  {RxVocVal3_BLUEPRINT_DDR3},
  {RxVocVal4_BLUEPRINT_DDR3},
  {RxVocVal5_BLUEPRINT_DDR3},
  {RxVocVal6_BLUEPRINT_DDR3},
  {RxVocVal7_BLUEPRINT_DDR3},
  {DQS_CNT_RESET_Ecc_BLUEPRINT_DDR3},
  {FifoReset_Ecc_BLUEPRINT_DDR3},
  {MuxcodeMax_Ecc_BLUEPRINT_DDR3},
  {MuxcodeMin_Ecc_BLUEPRINT_DDR3},
  {OdtEnOff_Ecc_BLUEPRINT_DDR3},
  {OdtSegEnOff_Ecc_BLUEPRINT_DDR3},
  {R2RRcvnEn_Ecc_BLUEPRINT_DDR3},
  {R2RRxDqsEn_Ecc_BLUEPRINT_DDR3},
  {R2RTxDqEn_Ecc_BLUEPRINT_DDR3},
  {R2RTxDqsEn_Ecc_BLUEPRINT_DDR3},
  {RdRk2RkLatency_Ecc_BLUEPRINT_DDR3},
  {RecEnSmp_Ecc_BLUEPRINT_DDR3},
  {RxVocEnDq_Ecc_BLUEPRINT_DDR3},
  {RxVocEnDqs_Ecc_BLUEPRINT_DDR3},
  {RxVocSmp_Ecc_BLUEPRINT_DDR3},
  {RxVref_Ecc_BLUEPRINT_DDR3},
  {TimingMode_BLUEPRINT_DDR3},
  {WrLvlSmp_Ecc_BLUEPRINT_DDR3},
  {WrPtrEn_Ecc_BLUEPRINT_DDR3},
  {RxVocVal0_Ecc_BLUEPRINT_DDR3},
  {RxVocVal1_Ecc_BLUEPRINT_DDR3},
  {RxVocVal2_Ecc_BLUEPRINT_DDR3},
  {RxVocVal3_Ecc_BLUEPRINT_DDR3},
  {RxVocVal4_Ecc_BLUEPRINT_DDR3},
  {RxVocVal5_Ecc_BLUEPRINT_DDR3},
  {RxVocVal6_Ecc_BLUEPRINT_DDR3},
  {RxVocVal7_Ecc_BLUEPRINT_DDR3},
  },
};
//
// This array has all delays, VREFs, clock crossings, and other DDRIO elements that MRC needs to access on a per-strobe or per-bit level.
//
CONST GET_SET_ELEMENTS ElementsGenerated[MAX_BLUEPRINTS][MAX_NUM_ELEMENTS] = {
  // BoxType,    Location                                                                      CacheIndex  Attribs       SB   Sb       NB   Nb       BB   Bb    MaxValue       Delay
  //             RANK 0                                 RANK 1
  { // BLUEPRINT_LPDDR34
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0000, ClkCh0
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0001, ClkCh0 Granularity HC
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    ,  0,  7}, {TXDLLSIGGRP0CTL_CCC_REG    ,  0,  7}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0002, ClkCh0 Granularity 1
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    , 12, 13}, {TXDLLSIGGRP0CTL_CCC_REG    , 12, 13}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0003, ClkCh0 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0004, ClkCh0 CC1
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}},       0x0A,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0005, ClkCh0 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0006, ClkCh1
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0007, ClkCh1 Granularity HC
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG,  0,  7}, {CH1_TXDLLSIGGRP0CTL_CCC_REG,  0,  7}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0008, ClkCh1 Granularity 1
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG, 12, 13}, {CH1_TXDLLSIGGRP0CTL_CCC_REG, 12, 13}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0009, ClkCh1 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x000A, ClkCh1 CC1
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}},       0x0B,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000B, ClkCh1 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x000C, CmdCh0
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}},       0x06,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000D, CmdCh0 Granularity HC
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    ,  0,  7}, {TXDLLSIGGRP1CTL_CCC_REG    ,  0,  7}},       0x06,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x000E, CmdCh0 Granularity 1
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    , 12, 13}, {TXDLLSIGGRP1CTL_CCC_REG    , 12, 13}},       0x06,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x000F, CmdCh0 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0010, CmdCh0 CC1
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}},       0x06,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0011, CmdCh0 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0012, CmdCh1
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}},       0x07,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0013, CmdCh1 Granularity HC
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG,  0,  7}, {CH1_TXDLLSIGGRP1CTL_CCC_REG,  0,  7}},       0x07,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0014, CmdCh1 Granularity 1
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG, 12, 13}, {CH1_TXDLLSIGGRP1CTL_CCC_REG, 12, 13}},       0x07,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0015, CmdCh1 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0016, CmdCh1 CC1
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}},       0x07,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0017, CmdCh1 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0018, CtlCh0
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}},       0x08,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0019, CtlCh0 Granularity HC
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    ,  0,  7}, {TXDLLSIGGRP2CTL_CCC_REG    ,  0,  7}},       0x08,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x001A, CtlCh0 Granularity 1
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    , 12, 13}, {TXDLLSIGGRP2CTL_CCC_REG    , 12, 13}},       0x08,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x001B, CtlCh0 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x001C, CtlCh0 CC1
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}},       0x08,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001D, CtlCh0 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x001E, CtlCh1
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}},       0x09,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001F, CtlCh1 Granularity HC
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG,  0,  7}, {CH1_TXDLLSIGGRP2CTL_CCC_REG,  0,  7}},       0x09,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0020, CtlCh1 Granularity 1
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG, 12, 13}, {CH1_TXDLLSIGGRP2CTL_CCC_REG, 12, 13}},       0x09,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0021, CtlCh1 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0022, CtlCh1 CC1
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}},       0x09,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0023, CtlCh1 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0024, RxDqsNDelay_dq
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0025, RxDqsNDelay_dq
  {DQ        , {{RXDLLDQSRK0CTL_DQ_REG      , 16, 23}, {RXDLLDQSRK1CTL_DQ_REG      , 16, 23}},       0x14,   {0x00},       0, -16,       0,   0,       0,   0, 0x000000ff,          0,     R2RRxDqsEn}, // Type 0x0026, RxDqsNDelay_dq Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0027, RxDqsNDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0028, RxDqsNDelay_dq CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0029, RxDqsNDelay_dq CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002A, RxDqsPDelay_dq
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002B, RxDqsPDelay_dq
  {DQ        , {{RXDLLDQSRK0CTL_DQ_REG      , 24, 31}, {RXDLLDQSRK1CTL_DQ_REG      , 24, 31}},       0x14,   {0x00},       0, -16,       0,   0,       0,   0, 0x000000ff,          0,     R2RRxDqsEn}, // Type 0x002C, RxDqsPDelay_dq Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002D, RxDqsPDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002E, RxDqsPDelay_dq CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002F, RxDqsPDelay_dq CC2
  {DQ        , {{WRDQSCTL_BL_DQ_REG         ,  0,  5}, {WRDQSCTL_BL_DQ_REG         ,  0,  5}},       0x03,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0030, TxDqDelay_Actual Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP0CTL_DQ_REG     , 24, 27}},       0x0C,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0031, TxDqDelay_Actual Granularity HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP0CTL_DQ_REG     , 16, 23}},       0x0C,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RTxDqEn}, // Type 0x0032, TxDqDelay_Actual Granularity 1
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     , 12, 13}, {TXDLLSIGGRP0CTL_DQ_REG     , 28, 29}},       0x0C,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RTxDqEn}, // Type 0x0033, TxDqDelay_Actual CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0034, TxDqDelay_Actual CC1
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP0CTL_DQ_REG     , 24, 27}},       0x0C,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0035, TxDqDelay_Actual CC2
  {DQ        , {{WRDQSCTL_BL_DQ_REG         ,  0,  5}, {WRDQSCTL_BL_DQ_REG         ,  0,  5}},       0x80,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0036, TxDqDrive Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG     ,  0,  3}, {TXDLLSIGGRP6CTL_DQ_REG     ,  6,  9}},       0x81,   {0x00},       4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0037, TxDqDrive Granularity HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP0CTL_DQ_REG     , 16, 23}},       0x82,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RTxDqEn}, // Type 0x0038, TxDqDrive Granularity 1
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG     ,  4,  5}, {TXDLLSIGGRP6CTL_DQ_REG     , 10, 11}},       0x81,   {0x00},       4,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RTxDqEn}, // Type 0x0039, TxDqDrive CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003A, TxDqDrive CC1
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG     ,  0,  3}, {TXDLLSIGGRP6CTL_DQ_REG     ,  6,  9}},       0x81,   {0x21},       4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x003B, TxDqDrive CC2
  {DQ        , {{WRDQSCTL_BL_DQ_REG         ,  0,  5}, {WRDQSCTL_BL_DQ_REG         ,  0,  5}},       0x03,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2RTxDqsEn}, // Type 0x003C, TxDqsDelay_dq Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP1CTL_DQ_REG     , 24, 27}},       0x04,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2RTxDqsEn}, // Type 0x003D, TxDqsDelay_dq Granularity HC
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP1CTL_DQ_REG     , 16, 23}},       0x04,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2RTxDqsEn}, // Type 0x003E, TxDqsDelay_dq Granularity 1
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     , 12, 13}, {TXDLLSIGGRP1CTL_DQ_REG     , 28, 29}},       0x04,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,     R2RTxDqsEn}, // Type 0x003F, TxDqsDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0040, TxDqsDelay_dq CC1
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP1CTL_DQ_REG     , 24, 27}},       0x04,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2RTxDqsEn}, // Type 0x0041, TxDqsDelay_dq CC2
  {DQ        , {{RCVENCTL_BL02_DQ_REG       ,  0,  5}, {RCVENCTL_BL02_DQ_REG       ,  0,  5}},       0x00,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000003f,          0,      R2RRcvnEn}, // Type 0x0042, RecEnDelay_dq Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP2CTL_DQ_REG     , 24, 27}},       0x01,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RRcvnEn}, // Type 0x0043, RecEnDelay_dq Granularity HC
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP2CTL_DQ_REG     , 16, 23}},       0x01,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RRcvnEn}, // Type 0x0044, RecEnDelay_dq Granularity 1
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     , 12, 13}, {TXDLLSIGGRP2CTL_DQ_REG     , 28, 29}},       0x01,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RRcvnEn}, // Type 0x0045, RecEnDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0046, RecEnDelay_dq CC1
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP2CTL_DQ_REG     , 24, 27}},       0x01,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RRcvnEn}, // Type 0x0047, RecEnDelay_dq CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0048, RecEnPiCode_dq
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0049, RecEnPiCode_dq
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP2CTL_DQ_REG     , 16, 23}},       0x8B,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RRcvnEn}, // Type 0x004A, RecEnPiCode_dq Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x004B, RecEnPiCode_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x004C, RecEnPiCode_dq CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x004D, RecEnPiCode_dq CC2
  {CCC       , {{VREFCTL2_CCC_REG           ,  0,  7}, {VREFCTL2_CCC_REG           ,  0,  7}},       0x1C,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x004E, CaVref_Actual
  {EXTERNAL  , {{CkeAll_FUNC                ,  0,  0}, {CkeAll_FUNC                ,  0,  0}},       0x1F,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x004F, CkeAll
  {CCC       , {{TXDLLSIGGRP6CTL_CCC_REG    , 14, 17}, {TXDLLSIGGRP6CTL_CCC_REG    , 14, 17}},       0x1E,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0050, CkeCh0
  {CCC       , {{TXDLLSIGGRP6CTL_CCC_REG    , 18, 21}, {TXDLLSIGGRP6CTL_CCC_REG    , 18, 21}},       0x1E,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0051, CkeCh1
  {EXTERNAL  , {{CkGrp0_FUNC                ,  0,  0}, {CkGrp0_FUNC                ,  0,  0}},       0x0D,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0052, CkGrp0
  {EXTERNAL  , {{CmdAll_FUNC                ,  0,  0}, {CmdAll_FUNC                ,  0,  0}},       0x10,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0053, CmdAll
  {EXTERNAL  , {{CmdGrp0_FUNC               ,  0,  0}, {CmdGrp0_FUNC               ,  0,  0}},       0x0E,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0054, CmdGrp0
  {EXTERNAL  , {{CtlAll_FUNC                ,  0,  0}, {CtlAll_FUNC                ,  0,  0}},       0x11,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0055, CtlAll
  {EXTERNAL  , {{CtlGrp0_FUNC               ,  0,  0}, {CtlGrp0_FUNC               ,  0,  0}},       0x0F,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0056, CtlGrp0
  {DQDPLVUG  , {{PTCTL1_DQDPLVUG_REG        ,  1,  7}, {PTCTL1_DQDPLVUG_REG        ,  9, 15}},       0x8A,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000007f,          0,     R2R_ENABLE}, // Type 0x0057, CURRENT_INDEX
  {DQ        , {{RCVENCTL_BL02_DQ_REG       , 27, 27}, {RCVENCTL_BL02_DQ_REG       , 27, 27}},       0x85,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0058, DQS_CNT_RESET
  {DQ        , {{DIGRSTCTL_DQ_REG           ,  1,  1}, {DIGRSTCTL_DQ_REG           ,  1,  1}},       0x87,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0059, FifoReset
  {DQDPLVUG  , {{PTCTL0_DQDPLVUG_REG        , 10, 16}, {PTCTL0_DQDPLVUG_REG        , 17, 23}},       0x24,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000007f,          0,     R2R_ENABLE}, // Type 0x005A, INITIAL_INDEX
  {DQ        , {{DLLCOMP_FBMUXSEL_DQ_REG    ,  8, 12}, {DLLCOMP_FBMUXSEL_DQ_REG    ,  8, 12}},       0x21,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x005B, MuxcodeMax
  {DQ        , {{DLLCOMP_FBMUXSEL_DQ_REG    ,  0,  4}, {DLLCOMP_FBMUXSEL_DQ_REG    ,  0,  4}},       0x21,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x005C, MuxcodeMin
  {DQ        , {{RXODTCTL_DQ_DQ_REG         , 28, 31}, {RXODTCTL_DQ_DQ_REG         , 28, 31}},       0x1A,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x005D, OdtEnOff
  {DQ        , {{RXODTSEGCTL_BL02_DQ_REG    , 24, 27}, {RXODTSEGCTL_BL02_DQ_REG    , 24, 27}},       0x1B,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x005E, OdtSegEnOff
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  0,  0}, {RK2RKCTL1_DQ_REG           ,  0,  0}},       0x20,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x005F, R2RRcvnEn
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  1,  1}, {RK2RKCTL1_DQ_REG           ,  1,  1}},       0x89,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0060, R2RRxDqsEn
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  4,  4}, {RK2RKCTL1_DQ_REG           ,  4,  4}},       0x89,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0061, R2RTxDqEn
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  5,  5}, {RK2RKCTL1_DQ_REG           ,  5,  5}},       0x89,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0062, R2RTxDqsEn
  {DQ        , {{RDVLDCTL_DQ_REG            , 12, 14}, {RDVLDCTL_DQ_REG            , 12, 14}},       0x25,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0063, RDCMD2RDVLD_PLUS1SEL
  {DQ        , {{RDVLDCTL_DQ_REG            ,  0,  5}, {RDVLDCTL_DQ_REG            ,  0,  5}},       0x25,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0064, RDCMD2RDVLD_REG
  {DQ        , {{RK2RKCTL0_DQ_REG           ,  8, 13}, {RK2RKCTL0_DQ_REG           ,  8, 13}},       0x26,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,    R2R_DISABLE}, // Type 0x0065, RdRk2RkLatency
  {EXTERNAL  , {{RecEnDelay_FUNC            ,  0,  0}, {RecEnDelay_FUNC            ,  0,  0}},       0x02,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0066, RecEnDelay
  {EXTERNAL  , {{RecEnSmp_FUNC              ,  0,  0}, {RecEnSmp_FUNC              ,  0,  0}},       0x86,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0067, RecEnSmp
  {DQ        , {{RCVENCTL_BL02_DQ_REG       , 31, 31}, {RCVENCTL_BL02_DQ_REG       , 31, 31}},       0x85,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0068, RecEnSmp_dq
  {DQ        , {{RXPBDBLCTL0_DQ_REG         ,  0,  3}, {RXPBDBLCTL0_DQ_REG         ,  0,  3}},       0x41,   {0x10},      -8,   0,       0,   0,       0,   4, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x0069, RxDqBitDelay
  {EXTERNAL  , {{RxDqsDelay_FUNC            ,  0,  0}, {RxDqsDelay_FUNC            ,  0,  0}},       0x17,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x006A, RxDqsDelay
  {EXTERNAL  , {{RxDqsNDelay_FUNC           ,  0,  0}, {RxDqsNDelay_FUNC           ,  0,  0}},       0x16,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x006B, RxDqsNDelay
  {EXTERNAL  , {{RxDqsPDelay_FUNC           ,  0,  0}, {RxDqsPDelay_FUNC           ,  0,  0}},       0x15,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x006C, RxDqsPDelay
  {DQ        , {{OFFSETCNCLCTRL1_DQ_REG     ,  8,  8}, {OFFSETCNCLCTRL1_DQ_REG     ,  8,  8}},       0x22,   {0x00},      -8,   0,       0,   0,       0,   0, 0x00000001,          0,    R2R_DISABLE}, // Type 0x006D, RxVocEnDq
  {DQ        , {{OFFSETCNCLCTRL1_DQ_REG     ,  9,  9}, {OFFSETCNCLCTRL1_DQ_REG     ,  9,  9}},       0x22,   {0x00},      -8,   0,       0,   0,       0,   0, 0x00000001,          0,    R2R_DISABLE}, // Type 0x006E, RxVocEnDqs
  {DQ        , {{WRLVL_DQ_REG               ,  8, 15}, {WRLVL_DQ_REG               ,  8, 15}},       0x83,   {0x00},       0,   8,       0,   0,       0,   0, 0x000000ff,          0,    R2R_DISABLE}, // Type 0x006F, RxVocSmp
  {EXTERNAL  , {{RxVocValAll_FUNC           ,  0,  0}, {RxVocValAll_FUNC           ,  0,  0}},       0x40,   {0x10},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0070, RxVocValAll
  {EXTERNAL  , {{RxVref_FUNC                ,  0,  0}, {RxVref_FUNC                ,  0,  0}},       0x19,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0071, RxVref
  {DQ        , {{VREFCTL0_DQ_REG            ,  8, 15}, {VREFCTL0_DQ_REG            ,  8, 15}},       0x18,   {0x00},       0,  -8,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0072, RxVref_dq
  {DUNIT     , {{D_CR_DTR4A_DUNIT_REG       ,  0,  5}, {D_CR_DTR4A_DUNIT_REG       ,  0,  5}},       0x27,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x0073, TrrdrGetSet
  {EXTERNAL  , {{TxCaVref_FUNC              ,  0,  0}, {TxCaVref_FUNC              ,  0,  0}},       0x13,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0074, TxCaVref
  {EXTERNAL  , {{TxDqBitDelay_FUNC          ,  0,  0}, {TxDqBitDelay_FUNC          ,  0,  0}},       0x42,   {0x10},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0075, TxDqBitDelay
  {EXTERNAL  , {{TxDqDelay_FUNC             ,  0,  0}, {TxDqDelay_FUNC             ,  0,  0}},       0x12,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0076, TxDqDelay
  {EXTERNAL  , {{TxDqsDelay_FUNC            ,  0,  0}, {TxDqsDelay_FUNC            ,  0,  0}},       0x05,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0077, TxDqsDelay
  {EXTERNAL  , {{TxVref_FUNC                ,  0,  0}, {TxVref_FUNC                ,  0,  0}},       0x1D,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0078, TxVref
  {CCC       , {{VREFCTL2_CCC_REG           , 16, 23}, {VREFCTL2_CCC_REG           , 16, 23}},       0x1C,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0079, TxVref_Actual
  {EXTERNAL  , {{WrLvlSmp_FUNC              ,  0,  0}, {WrLvlSmp_FUNC              ,  0,  0}},       0x84,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x007A, WrLvlSmp
  {DQ        , {{WRLVL_DQ_REG               ,  0,  0}, {WRLVL_DQ_REG               ,  0,  0}},       0x83,   {0x00},       0,   1,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x007B, WrLvlSmp_dq
  {DQ        , {{FIFOPTREN_DQ_REG           ,  0,  0}, {FIFOPTREN_DQ_REG           ,  0,  0}},       0x88,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x007C, WrPtrEn
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 28, 31}, {OFFSETCNCLCTRL0_DQ_REG     , 28, 31}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x007D, RxVocVal0
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 24, 27}, {OFFSETCNCLCTRL0_DQ_REG     , 24, 27}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x007E, RxVocVal1
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 20, 23}, {OFFSETCNCLCTRL0_DQ_REG     , 20, 23}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x007F, RxVocVal2
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 16, 19}, {OFFSETCNCLCTRL0_DQ_REG     , 16, 19}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x0080, RxVocVal3
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 12, 15}, {OFFSETCNCLCTRL0_DQ_REG     , 12, 15}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x0081, RxVocVal4
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     ,  8, 11}, {OFFSETCNCLCTRL0_DQ_REG     ,  8, 11}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x0082, RxVocVal5
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     ,  4,  7}, {OFFSETCNCLCTRL0_DQ_REG     ,  4,  7}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x0083, RxVocVal6
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     ,  0,  3}, {OFFSETCNCLCTRL0_DQ_REG     ,  0,  3}},       0x23,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x0084, RxVocVal7
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // INVALID ENTRY
  },
  { // BLUEPRINT_DDR3
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0000, ClkCh0
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}},       0x80,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0001, ClkCh0 Granularity HC
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    ,  0,  7}, {TXDLLSIGGRP0CTL_CCC_REG    ,  0,  7}},       0x80,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0002, ClkCh0 Granularity 1
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    , 12, 13}, {TXDLLSIGGRP0CTL_CCC_REG    , 12, 13}},       0x80,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0003, ClkCh0 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0004, ClkCh0 CC1
  {CCC       , {{TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP0CTL_CCC_REG    ,  8, 11}},       0x80,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0005, ClkCh0 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0006, ClkCh1
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}},       0x81,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0007, ClkCh1 Granularity HC
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG,  0,  7}, {CH1_TXDLLSIGGRP0CTL_CCC_REG,  0,  7}},       0x81,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0008, ClkCh1 Granularity 1
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG, 12, 13}, {CH1_TXDLLSIGGRP0CTL_CCC_REG, 12, 13}},       0x81,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0009, ClkCh1 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x000A, ClkCh1 CC1
  {CCC       , {{CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}},       0x81,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000B, ClkCh1 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x000C, CmdCh0
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x000D, CmdCh0 Granularity HC
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    ,  0,  7}, {TXDLLSIGGRP1CTL_CCC_REG    ,  0,  7}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x000E, CmdCh0 Granularity 1
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    , 12, 13}, {TXDLLSIGGRP1CTL_CCC_REG    , 12, 13}},       0x0A,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x000F, CmdCh0 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0010, CmdCh0 CC1
  {CCC       , {{TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP1CTL_CCC_REG    ,  8, 11}},       0x0A,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0011, CmdCh0 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0012, CmdCh1
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0013, CmdCh1 Granularity HC
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG,  0,  7}, {CH1_TXDLLSIGGRP1CTL_CCC_REG,  0,  7}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0014, CmdCh1 Granularity 1
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG, 12, 13}, {CH1_TXDLLSIGGRP1CTL_CCC_REG, 12, 13}},       0x0B,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0015, CmdCh1 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0016, CmdCh1 CC1
  {CCC       , {{CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}},       0x0B,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0017, CmdCh1 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0018, CtlCh0
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}},       0x0C,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0019, CtlCh0 Granularity HC
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    ,  0,  7}, {TXDLLSIGGRP2CTL_CCC_REG    ,  0,  7}},       0x0C,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x001A, CtlCh0 Granularity 1
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    , 12, 13}, {TXDLLSIGGRP2CTL_CCC_REG    , 12, 13}},       0x0C,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x001B, CtlCh0 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x001C, CtlCh0 CC1
  {CCC       , {{TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}, {TXDLLSIGGRP2CTL_CCC_REG    ,  8, 11}},       0x0C,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001D, CtlCh0 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x001E, CtlCh1
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}},       0x0D,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x001F, CtlCh1 Granularity HC
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG,  0,  7}, {CH1_TXDLLSIGGRP2CTL_CCC_REG,  0,  7}},       0x0D,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0020, CtlCh1 Granularity 1
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG, 12, 13}, {CH1_TXDLLSIGGRP2CTL_CCC_REG, 12, 13}},       0x0D,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,     R2R_ENABLE}, // Type 0x0021, CtlCh1 CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0022, CtlCh1 CC1
  {CCC       , {{CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}, {CH1_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}},       0x0D,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0023, CtlCh1 CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0024, RxDqsNDelay_dq
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0025, RxDqsNDelay_dq
  {DQ        , {{RXDLLDQSRK0CTL_DQ_REG      , 16, 23}, {RXDLLDQSRK1CTL_DQ_REG      , 16, 23}},       0x15,   {0x00},       0, -16,       0,   0,       0,   0, 0x000000ff,          0,     R2RRxDqsEn}, // Type 0x0026, RxDqsNDelay_dq Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0027, RxDqsNDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0028, RxDqsNDelay_dq CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0029, RxDqsNDelay_dq CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002A, RxDqsNDelay_Ecc
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002B, RxDqsNDelay_Ecc
  {CCC       , {{RXDLLDQSRK0CTL_CCC_REG     ,  0,  7}, {RXDLLDQSRK1CTL_CCC_REG     , 16, 23}},       0x16,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2RRxDqsEn}, // Type 0x002C, RxDqsNDelay_Ecc Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002D, RxDqsNDelay_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002E, RxDqsNDelay_Ecc CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x002F, RxDqsNDelay_Ecc CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0030, RxDqsPDelay_dq
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0031, RxDqsPDelay_dq
  {DQ        , {{RXDLLDQSRK0CTL_DQ_REG      , 24, 31}, {RXDLLDQSRK1CTL_DQ_REG      , 24, 31}},       0x15,   {0x00},       0, -16,       0,   0,       0,   0, 0x000000ff,          0,     R2RRxDqsEn}, // Type 0x0032, RxDqsPDelay_dq Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0033, RxDqsPDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0034, RxDqsPDelay_dq CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0035, RxDqsPDelay_dq CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0036, RxDqsPDelay_Ecc
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0037, RxDqsPDelay_Ecc
  {CCC       , {{RXDLLDQSRK0CTL_CCC_REG     ,  8, 15}, {RXDLLDQSRK1CTL_CCC_REG     , 24, 31}},       0x16,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2RRxDqsEn}, // Type 0x0038, RxDqsPDelay_Ecc Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0039, RxDqsPDelay_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003A, RxDqsPDelay_Ecc CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x003B, RxDqsPDelay_Ecc CC2
  {DQ        , {{WRDQSCTL_BL_DQ_REG         ,  0,  5}, {WRDQSCTL_BL_DQ_REG         ,  0,  5}},       0x05,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x003C, TxDqDelay_Actual Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP0CTL_DQ_REG     , 24, 27}},       0x0E,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x003D, TxDqDelay_Actual Granularity HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP0CTL_DQ_REG     , 16, 23}},       0x0E,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RTxDqEn}, // Type 0x003E, TxDqDelay_Actual Granularity 1
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     , 12, 13}, {TXDLLSIGGRP0CTL_DQ_REG     , 28, 29}},       0x0E,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RTxDqEn}, // Type 0x003F, TxDqDelay_Actual CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0040, TxDqDelay_Actual CC1
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP0CTL_DQ_REG     , 24, 27}},       0x0E,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0041, TxDqDelay_Actual CC2
  {CCC       , {{WRDQSCTL_CCC_REG           ,  0,  5}, {WRDQSCTL_CCC_REG           ,  0,  5}},       0x07,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0042, TxDqDelay_Actual_Ecc Granularity 2*HC
  {CCC       , {{ECC_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}, {ECC_TXDLLSIGGRP0CTL_CCC_REG, 24, 27}},       0x0F,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0043, TxDqDelay_Actual_Ecc Granularity HC
  {CCC       , {{ECC_TXDLLSIGGRP0CTL_CCC_REG,  0,  7}, {ECC_TXDLLSIGGRP0CTL_CCC_REG, 16, 23}},       0x0F,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RTxDqEn}, // Type 0x0044, TxDqDelay_Actual_Ecc Granularity 1
  {CCC       , {{ECC_TXDLLSIGGRP0CTL_CCC_REG, 12, 13}, {ECC_TXDLLSIGGRP0CTL_CCC_REG, 28, 29}},       0x0F,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RTxDqEn}, // Type 0x0045, TxDqDelay_Actual_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0046, TxDqDelay_Actual_Ecc CC1
  {CCC       , {{ECC_TXDLLSIGGRP0CTL_CCC_REG,  8, 11}, {ECC_TXDLLSIGGRP0CTL_CCC_REG, 24, 27}},       0x0F,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0047, TxDqDelay_Actual_Ecc CC2
  {DQ        , {{WRDQSCTL_BL_DQ_REG         ,  0,  5}, {WRDQSCTL_BL_DQ_REG         ,  0,  5}},       0x82,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0048, TxDqDrive Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG     ,  0,  3}, {TXDLLSIGGRP6CTL_DQ_REG     ,  6,  9}},       0x83,   {0x00},       4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0049, TxDqDrive Granularity HC
  {DQ        , {{TXDLLSIGGRP0CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP0CTL_DQ_REG     , 16, 23}},       0x84,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RTxDqEn}, // Type 0x004A, TxDqDrive Granularity 1
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG     ,  4,  5}, {TXDLLSIGGRP6CTL_DQ_REG     , 10, 11}},       0x83,   {0x00},       4,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RTxDqEn}, // Type 0x004B, TxDqDrive CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x004C, TxDqDrive CC1
  {DQ        , {{TXDLLSIGGRP6CTL_DQ_REG     ,  0,  3}, {TXDLLSIGGRP6CTL_DQ_REG     ,  6,  9}},       0x83,   {0x21},       4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x004D, TxDqDrive CC2
  {CCC       , {{WRDQSCTL_CCC_REG           ,  0,  5}, {WRDQSCTL_CCC_REG           ,  0,  5}},       0x85,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x004E, TxDqDrive_Ecc Granularity 2*HC
  {CCC       , {{TXDLLSIGGRP6CTL_CCC_REG    ,  0,  3}, {TXDLLSIGGRP6CTL_CCC_REG    ,  7, 10}},       0x86,   {0x00},       4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x004F, TxDqDrive_Ecc Granularity HC
  {CCC       , {{ECC_TXDLLSIGGRP0CTL_CCC_REG,  0,  7}, {ECC_TXDLLSIGGRP0CTL_CCC_REG, 16, 23}},       0x87,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RTxDqEn}, // Type 0x0050, TxDqDrive_Ecc Granularity 1
  {CCC       , {{ECC_TXDLLSIGGRP0CTL_CCC_REG, 12, 13}, {ECC_TXDLLSIGGRP0CTL_CCC_REG, 28, 29}},       0x87,   {0x00},       4,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RTxDqEn}, // Type 0x0051, TxDqDrive_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0052, TxDqDrive_Ecc CC1
  {CCC       , {{TXDLLSIGGRP6CTL_CCC_REG    ,  0,  3}, {TXDLLSIGGRP6CTL_CCC_REG    ,  7, 10}},       0x86,   {0x21},       4,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RTxDqEn}, // Type 0x0053, TxDqDrive_Ecc CC2
  {DQ        , {{WRDQSCTL_BL_DQ_REG         ,  0,  5}, {WRDQSCTL_BL_DQ_REG         ,  0,  5}},       0x05,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2RTxDqsEn}, // Type 0x0054, TxDqsDelay_dq Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP1CTL_DQ_REG     , 24, 27}},       0x06,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2RTxDqsEn}, // Type 0x0055, TxDqsDelay_dq Granularity HC
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP1CTL_DQ_REG     , 16, 23}},       0x06,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2RTxDqsEn}, // Type 0x0056, TxDqsDelay_dq Granularity 1
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     , 12, 13}, {TXDLLSIGGRP1CTL_DQ_REG     , 28, 29}},       0x06,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,     R2RTxDqsEn}, // Type 0x0057, TxDqsDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0058, TxDqsDelay_dq CC1
  {DQ        , {{TXDLLSIGGRP1CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP1CTL_DQ_REG     , 24, 27}},       0x06,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2RTxDqsEn}, // Type 0x0059, TxDqsDelay_dq CC2
  {CCC       , {{WRDQSCTL_CCC_REG           ,  0,  5}, {WRDQSCTL_CCC_REG           ,  0,  5}},       0x07,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2RTxDqsEn}, // Type 0x005A, TxDqsDelay_Ecc Granularity 2*HC
  {CCC       , {{ECC_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}, {ECC_TXDLLSIGGRP1CTL_CCC_REG, 24, 27}},       0x08,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2RTxDqsEn}, // Type 0x005B, TxDqsDelay_Ecc Granularity HC
  {CCC       , {{ECC_TXDLLSIGGRP1CTL_CCC_REG,  0,  7}, {ECC_TXDLLSIGGRP1CTL_CCC_REG, 16, 23}},       0x08,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2RTxDqsEn}, // Type 0x005C, TxDqsDelay_Ecc Granularity 1
  {CCC       , {{ECC_TXDLLSIGGRP1CTL_CCC_REG, 12, 13}, {ECC_TXDLLSIGGRP1CTL_CCC_REG, 28, 29}},       0x08,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,     R2RTxDqsEn}, // Type 0x005D, TxDqsDelay_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x005E, TxDqsDelay_Ecc CC1
  {CCC       , {{ECC_TXDLLSIGGRP1CTL_CCC_REG,  8, 11}, {ECC_TXDLLSIGGRP1CTL_CCC_REG, 24, 27}},       0x08,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2RTxDqsEn}, // Type 0x005F, TxDqsDelay_Ecc CC2
  {DQ        , {{RCVENCTL_BL02_DQ_REG       ,  0,  5}, {RCVENCTL_BL02_DQ_REG       ,  0,  5}},       0x00,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000003f,          0,      R2RRcvnEn}, // Type 0x0060, RecEnDelay_dq Granularity 2*HC
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP2CTL_DQ_REG     , 24, 27}},       0x01,   {0x00},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RRcvnEn}, // Type 0x0061, RecEnDelay_dq Granularity HC
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP2CTL_DQ_REG     , 16, 23}},       0x01,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RRcvnEn}, // Type 0x0062, RecEnDelay_dq Granularity 1
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     , 12, 13}, {TXDLLSIGGRP2CTL_DQ_REG     , 28, 29}},       0x01,   {0x00},     -12,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RRcvnEn}, // Type 0x0063, RecEnDelay_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0064, RecEnDelay_dq CC1
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  8, 11}, {TXDLLSIGGRP2CTL_DQ_REG     , 24, 27}},       0x01,   {0x21},     -12,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RRcvnEn}, // Type 0x0065, RecEnDelay_dq CC2
  {CCC       , {{RCVENCTL_CCC_REG           ,  0,  5}, {RCVENCTL_CCC_REG           ,  0,  5}},       0x02,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,      R2RRcvnEn}, // Type 0x0066, RecEnDelay_Ecc Granularity 2*HC
  {CCC       , {{ECC_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}, {ECC_TXDLLSIGGRP2CTL_CCC_REG, 24, 27}},       0x03,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RRcvnEn}, // Type 0x0067, RecEnDelay_Ecc Granularity HC
  {CCC       , {{ECC_TXDLLSIGGRP2CTL_CCC_REG,  0,  7}, {ECC_TXDLLSIGGRP2CTL_CCC_REG, 16, 23}},       0x03,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RRcvnEn}, // Type 0x0068, RecEnDelay_Ecc Granularity 1
  {CCC       , {{ECC_TXDLLSIGGRP2CTL_CCC_REG, 12, 13}, {ECC_TXDLLSIGGRP2CTL_CCC_REG, 28, 29}},       0x03,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000003,          0,      R2RRcvnEn}, // Type 0x0069, RecEnDelay_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x006A, RecEnDelay_Ecc CC1
  {CCC       , {{ECC_TXDLLSIGGRP2CTL_CCC_REG,  8, 11}, {ECC_TXDLLSIGGRP2CTL_CCC_REG, 24, 27}},       0x03,   {0x21},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,      R2RRcvnEn}, // Type 0x006B, RecEnDelay_Ecc CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x006C, RecEnPiCode_dq
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x006D, RecEnPiCode_dq
  {DQ        , {{TXDLLSIGGRP2CTL_DQ_REG     ,  0,  7}, {TXDLLSIGGRP2CTL_DQ_REG     , 16, 23}},       0x95,   {0x00},     -12,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RRcvnEn}, // Type 0x006E, RecEnPiCode_dq Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x006F, RecEnPiCode_dq CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0070, RecEnPiCode_dq CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0071, RecEnPiCode_dq CC2
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0072, RecEnPiCode_Ecc
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0073, RecEnPiCode_Ecc
  {CCC       , {{ECC_TXDLLSIGGRP2CTL_CCC_REG,  0,  7}, {ECC_TXDLLSIGGRP2CTL_CCC_REG, 16, 23}},       0x96,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,      R2RRcvnEn}, // Type 0x0074, RecEnPiCode_Ecc Granularity 1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0075, RecEnPiCode_Ecc CC0
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0076, RecEnPiCode_Ecc CC1
  {0xFF      , {{0xFF                       ,  0,  0}, {0xFF                       ,  0,  0}},       0xFF,   {0x00},  0xFFFF,   0,  0xFFFF,   0,  0xFFFF,   0, 0xFFFFFFFF,          0,         0xFFFF}, // Type 0x0077, RecEnPiCode_Ecc CC2
  {CCC       , {{VREFCTL2_CCC_REG           ,  0,  7}, {VREFCTL2_CCC_REG           ,  0,  7}},       0x1B,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x0078, CaVref_Actual
  {EXTERNAL  , {{CkeAll_FUNC                ,  0,  0}, {CkeAll_FUNC                ,  0,  0}},       0x24,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0079, CkeAll
  {CCC       , {{TXDLLSIGGRP6CTL_CCC_REG    , 14, 17}, {TXDLLSIGGRP6CTL_CCC_REG    , 14, 17}},       0x23,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x007A, CkeCh0
  {CCC       , {{TXDLLSIGGRP6CTL_CCC_REG    , 18, 21}, {TXDLLSIGGRP6CTL_CCC_REG    , 18, 21}},       0x23,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x007B, CkeCh1
  {EXTERNAL  , {{CkGrp0_FUNC                ,  0,  0}, {CkGrp0_FUNC                ,  0,  0}},       0x88,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x007C, CkGrp0
  {EXTERNAL  , {{CmdAll_FUNC                ,  0,  0}, {CmdAll_FUNC                ,  0,  0}},       0x12,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x007D, CmdAll
  {EXTERNAL  , {{CmdGrp0_FUNC               ,  0,  0}, {CmdGrp0_FUNC               ,  0,  0}},       0x10,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x007E, CmdGrp0
  {EXTERNAL  , {{CtlAll_FUNC                ,  0,  0}, {CtlAll_FUNC                ,  0,  0}},       0x13,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x007F, CtlAll
  {EXTERNAL  , {{CtlGrp0_FUNC               ,  0,  0}, {CtlGrp0_FUNC               ,  0,  0}},       0x11,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x0080, CtlGrp0
  {DQDPLVUG  , {{PTCTL1_DQDPLVUG_REG        ,  1,  7}, {PTCTL1_DQDPLVUG_REG        ,  9, 15}},       0x2B,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000007f,          0,    R2R_DISABLE}, // Type 0x0081, CURRENT_INDEX
  {DQ        , {{RCVENCTL_BL02_DQ_REG       , 27, 27}, {RCVENCTL_BL02_DQ_REG       , 27, 27}},       0x8C,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0082, DQS_CNT_RESET
  {CCC       , {{RCVENCTL_CCC_REG           , 26, 26}, {CH1_RCVENCTL_CCC_REG       , 27, 27}},       0x8D,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0083, DQS_CNT_RESET_Ecc
  {DQ        , {{DIGRSTCTL_DQ_REG           ,  1,  1}, {DIGRSTCTL_DQ_REG           ,  1,  1}},       0x8F,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0084, FifoReset
  {CCC       , {{DIGRSTCTL_CCC_REG          ,  1,  1}, {CH1_DIGRSTCTL_CCC_REG      ,  1,  1}},       0x90,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0085, FifoReset_Ecc
  {DQDPLVUG  , {{PTCTL0_DQDPLVUG_REG        , 10, 16}, {PTCTL0_DQDPLVUG_REG        , 17, 23}},       0x00,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000007f,          0,    R2R_DISABLE}, // Type 0x0086, INITIAL_INDEX
  {DQ        , {{DLLCOMP_FBMUXSEL_DQ_REG    ,  8, 12}, {DLLCOMP_FBMUXSEL_DQ_REG    ,  8, 12}},       0x25,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x0087, MuxcodeMax
  {CCC       , {{DLLCOMP_FBMUXSEL1_CCC_REG  , 24, 28}, {DLLCOMP_FBMUXSEL1_CCC_REG  , 24, 28}},       0x26,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x0088, MuxcodeMax_Ecc
  {DQ        , {{DLLCOMP_FBMUXSEL_DQ_REG    ,  0,  4}, {DLLCOMP_FBMUXSEL_DQ_REG    ,  0,  4}},       0x25,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x0089, MuxcodeMin
  {CCC       , {{DLLCOMP_FBMUXSEL1_CCC_REG  , 16, 20}, {DLLCOMP_FBMUXSEL1_CCC_REG  , 16, 20}},       0x26,   {0x00},    2048,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x008A, MuxcodeMin_Ecc
  {DQ        , {{RXODTCTL_DQ_DQ_REG         , 28, 31}, {RXODTCTL_DQ_DQ_REG         , 28, 31}},       0x1D,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x008B, OdtEnOff
  {CCC       , {{RXODTCTL_CCC_REG           , 28, 31}, {RXODTCTL_CCC_REG           , 28, 31}},       0x1F,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x008C, OdtEnOff_Ecc
  {DQ        , {{RXODTSEGCTL_BL02_DQ_REG    , 24, 27}, {RXODTSEGCTL_BL02_DQ_REG    , 24, 27}},       0x1E,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x008D, OdtSegEnOff
  {CCC       , {{RXODTSEGCTL_CCC_REG        , 24, 27}, {RXODTSEGCTL_CCC_REG        , 24, 27}},       0x20,   {0x00},      -4,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x008E, OdtSegEnOff_Ecc
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  0,  0}, {RK2RKCTL1_DQ_REG           ,  0,  0}},       0x93,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x008F, R2RRcvnEn
  {CCC       , {{RK2RKCTL1_CCC_REG          ,  0,  0}, {RK2RKCTL1_CCC_REG          ,  0,  0}},       0x94,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0090, R2RRcvnEn_Ecc
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  1,  1}, {RK2RKCTL1_DQ_REG           ,  1,  1}},       0x93,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0091, R2RRxDqsEn
  {CCC       , {{RK2RKCTL1_CCC_REG          ,  1,  1}, {RK2RKCTL1_CCC_REG          ,  1,  1}},       0x94,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0092, R2RRxDqsEn_Ecc
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  4,  4}, {RK2RKCTL1_DQ_REG           ,  4,  4}},       0x93,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0093, R2RTxDqEn
  {CCC       , {{RK2RKCTL1_CCC_REG          ,  6,  6}, {RK2RKCTL1_CCC_REG          ,  6,  6}},       0x94,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0094, R2RTxDqEn_Ecc
  {DQ        , {{RK2RKCTL1_DQ_REG           ,  5,  5}, {RK2RKCTL1_DQ_REG           ,  5,  5}},       0x93,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0095, R2RTxDqsEn
  {CCC       , {{RK2RKCTL1_CCC_REG          ,  7,  7}, {RK2RKCTL1_CCC_REG          ,  7,  7}},       0x94,   {0x00},       0,   2,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x0096, R2RTxDqsEn_Ecc
  {DQ        , {{RDVLDCTL_DQ_REG            , 12, 14}, {RDVLDCTL_DQ_REG            , 12, 14}},       0x2D,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000000f,          0,     R2R_ENABLE}, // Type 0x0097, RDCMD2RDVLD_PLUS1SEL
  {DQ        , {{RDVLDCTL_DQ_REG            ,  0,  5}, {RDVLDCTL_DQ_REG            ,  0,  5}},       0x2D,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,     R2R_ENABLE}, // Type 0x0098, RDCMD2RDVLD_REG
  {DQ        , {{RK2RKCTL0_DQ_REG           ,  8, 13}, {RK2RKCTL0_DQ_REG           ,  8, 13}},       0x2E,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,    R2R_DISABLE}, // Type 0x0099, RdRk2RkLatency
  {CCC       , {{RK2RKCTL0_CCC_REG          ,  8, 13}, {RK2RKCTL0_CCC_REG          ,  8, 13}},       0x2F,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000003f,          0,    R2R_DISABLE}, // Type 0x009A, RdRk2RkLatency_Ecc
  {EXTERNAL  , {{RecEnDelay_FUNC            ,  0,  0}, {RecEnDelay_FUNC            ,  0,  0}},       0x04,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x009B, RecEnDelay
  {EXTERNAL  , {{RecEnSmp_FUNC              ,  0,  0}, {RecEnSmp_FUNC              ,  0,  0}},       0x8E,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x009C, RecEnSmp
  {DQ        , {{RCVENCTL_BL02_DQ_REG       , 31, 31}, {RCVENCTL_BL02_DQ_REG       , 31, 31}},       0x8C,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,      R2RRcvnEn}, // Type 0x009D, RecEnSmp_dq
  {CCC       , {{RCVENCTL_CCC_REG           , 29, 29}, {RCVENCTL_CCC_REG           , 29, 29}},       0x8D,   {0x00},      -4,   0,       0,   0,       0,   0, 0x00000001,          0,      R2RRcvnEn}, // Type 0x009E, RecEnSmp_Ecc
  {DQ        , {{RXPBDBLCTL0_DQ_REG         ,  0,  3}, {RXPBDBLCTL0_DQ_REG         ,  0,  3}},       0x41,   {0x10},       0,   4,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x009F, RxDqBitDelay
  {EXTERNAL  , {{RxDqsDelay_FUNC            ,  0,  0}, {RxDqsDelay_FUNC            ,  0,  0}},       0x19,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x00A0, RxDqsDelay
  {EXTERNAL  , {{RxDqsNDelay_FUNC           ,  0,  0}, {RxDqsNDelay_FUNC           ,  0,  0}},       0x18,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x00A1, RxDqsNDelay
  {EXTERNAL  , {{RxDqsPDelay_FUNC           ,  0,  0}, {RxDqsPDelay_FUNC           ,  0,  0}},       0x17,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x00A2, RxDqsPDelay
  {DQ        , {{OFFSETCNCLCTRL1_DQ_REG     ,  8,  8}, {OFFSETCNCLCTRL1_DQ_REG     ,  8,  8}},       0x27,   {0x00},      -8,   0,       0,   0,       0,   0, 0x00000001,          0,    R2R_DISABLE}, // Type 0x00A3, RxVocEnDq
  {CCC       , {{OFFSETCNCLCTRL1_CCC_REG    , 23, 23}, {OFFSETCNCLCTRL1_CCC_REG    , 23, 23}},       0x28,   {0x00},      -8,   0,       0,   0,       0,   0, 0x00000001,          0,    R2R_DISABLE}, // Type 0x00A4, RxVocEnDq_Ecc
  {DQ        , {{OFFSETCNCLCTRL1_DQ_REG     ,  9,  9}, {OFFSETCNCLCTRL1_DQ_REG     ,  9,  9}},       0x27,   {0x00},      -8,   0,       0,   0,       0,   0, 0x00000001,          0,    R2R_DISABLE}, // Type 0x00A5, RxVocEnDqs
  {CCC       , {{OFFSETCNCLCTRL1_CCC_REG    , 21, 21}, {OFFSETCNCLCTRL1_CCC_REG    , 21, 21}},       0x28,   {0x00},      -8,   0,       0,   0,       0,   0, 0x00000001,          0,    R2R_DISABLE}, // Type 0x00A6, RxVocEnDqs_Ecc
  {DQ        , {{WRLVL_DQ_REG               ,  8, 15}, {WRLVL_DQ_REG               ,  8, 15}},       0x89,   {0x00},       0,   8,       0,   0,       0,   0, 0x000000ff,          0,    R2R_DISABLE}, // Type 0x00A7, RxVocSmp
  {CCC       , {{WRLVL_CCC_REG              ,  8, 15}, {WRLVL_CCC_REG              ,  8, 15}},       0x8A,   {0x00},       0,   8,       0,   0,       0,   0, 0x000000ff,          0,    R2R_DISABLE}, // Type 0x00A8, RxVocSmp_Ecc
  {EXTERNAL  , {{RxVocValAll_FUNC           ,  0,  0}, {RxVocValAll_FUNC           ,  0,  0}},       0x40,   {0x10},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00A9, RxVocValAll
  {EXTERNAL  , {{RxVref_FUNC                ,  0,  0}, {RxVref_FUNC                ,  0,  0}},       0x1C,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00AA, RxVref
  {DQ        , {{VREFCTL0_DQ_REG            ,  8, 15}, {VREFCTL0_DQ_REG            ,  8, 15}},       0x1A,   {0x00},       0,  -8,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x00AB, RxVref_dq
  {CCC       , {{VREFCTL2_CCC_REG           , 24, 31}, {VREFCTL2_CCC_REG           , 24, 31}},       0x1B,   {0x00},       0,  -8,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x00AC, RxVref_Ecc
  {EXTERNAL  , {{TimingMode_FUNC            ,  0,  0}, {TimingMode_FUNC            ,  0,  0}},       0x30,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00AD, TimingMode
  {DUNIT     , {{D_CR_DTR4A_DUNIT_REG       ,  0,  5}, {D_CR_DTR4A_DUNIT_REG       ,  0,  5}},       0x31,   {0x00},       0,   0,       0,   0,       0,   0, 0x0000001f,          0,    R2R_DISABLE}, // Type 0x00AE, TrrdrGetSet
  {EXTERNAL  , {{TxCaVref_FUNC              ,  0,  0}, {TxCaVref_FUNC              ,  0,  0}},       0x22,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00AF, TxCaVref
  {EXTERNAL  , {{TxDqBitDelay_FUNC          ,  0,  0}, {TxDqBitDelay_FUNC          ,  0,  0}},       0x42,   {0x10},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00B0, TxDqBitDelay
  {EXTERNAL  , {{TxDqDelay_FUNC             ,  0,  0}, {TxDqDelay_FUNC             ,  0,  0}},       0x14,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00B1, TxDqDelay
  {EXTERNAL  , {{TxDqsDelay_FUNC            ,  0,  0}, {TxDqsDelay_FUNC            ,  0,  0}},       0x09,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00B2, TxDqsDelay
  {EXTERNAL  , {{TxVref_FUNC                ,  0,  0}, {TxVref_FUNC                ,  0,  0}},       0x21,   {0x00},       0,   0,       0,   0,       0,   0, 0x00001000,          0,     R2R_ENABLE}, // Type 0x00B3, TxVref
  {CCC       , {{VREFCTL2_CCC_REG           , 16, 23}, {VREFCTL2_CCC_REG           , 16, 23}},       0x1B,   {0x00},       0,   0,       0,   0,       0,   0, 0x000000ff,          0,     R2R_ENABLE}, // Type 0x00B4, TxVref_Actual
  {EXTERNAL  , {{WrLvlSmp_FUNC              ,  0,  0}, {WrLvlSmp_FUNC              ,  0,  0}},       0x8B,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x00B5, WrLvlSmp
  {DQ        , {{WRLVL_DQ_REG               ,  0,  0}, {WRLVL_DQ_REG               ,  0,  0}},       0x89,   {0x00},       0,   1,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x00B6, WrLvlSmp_dq
  {CCC       , {{WRLVL_CCC_REG              ,  0,  0}, {WRLVL_CCC_REG              ,  0,  0}},       0x8A,   {0x00},       0,   1,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x00B7, WrLvlSmp_Ecc
  {DQ        , {{FIFOPTREN_DQ_REG           ,  0,  0}, {FIFOPTREN_DQ_REG           ,  0,  0}},       0x91,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x00B8, WrPtrEn
  {CCC       , {{FIFOPTREN_CCC_REG          ,  0,  0}, {CH1_FIFOPTREN_CCC_REG      ,  0,  0}},       0x92,   {0x00},       0,   0,       0,   0,       0,   0, 0x00000001,          0,     R2R_ENABLE}, // Type 0x00B9, WrPtrEn_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 28, 31}, {OFFSETCNCLCTRL0_DQ_REG     , 28, 31}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00BA, RxVocVal0
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    , 28, 31}, {OFFSETCNCLCTRL0_CCC_REG    , 28, 31}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00BB, RxVocVal0_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 24, 27}, {OFFSETCNCLCTRL0_DQ_REG     , 24, 27}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00BC, RxVocVal1
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    , 24, 27}, {OFFSETCNCLCTRL0_CCC_REG    , 24, 27}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00BD, RxVocVal1_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 20, 23}, {OFFSETCNCLCTRL0_DQ_REG     , 20, 23}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00BE, RxVocVal2
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    , 20, 23}, {OFFSETCNCLCTRL0_CCC_REG    , 20, 23}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00BF, RxVocVal2_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 16, 19}, {OFFSETCNCLCTRL0_DQ_REG     , 16, 19}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C0, RxVocVal3
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    , 16, 19}, {OFFSETCNCLCTRL0_CCC_REG    , 16, 19}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C1, RxVocVal3_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     , 12, 15}, {OFFSETCNCLCTRL0_DQ_REG     , 12, 15}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C2, RxVocVal4
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    , 12, 15}, {OFFSETCNCLCTRL0_CCC_REG    , 12, 15}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C3, RxVocVal4_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     ,  8, 11}, {OFFSETCNCLCTRL0_DQ_REG     ,  8, 11}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C4, RxVocVal5
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    ,  8, 11}, {OFFSETCNCLCTRL0_CCC_REG    ,  8, 11}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C5, RxVocVal5_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     ,  4,  7}, {OFFSETCNCLCTRL0_DQ_REG     ,  4,  7}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C6, RxVocVal6
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    ,  4,  7}, {OFFSETCNCLCTRL0_CCC_REG    ,  4,  7}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C7, RxVocVal6_Ecc
  {DQ        , {{OFFSETCNCLCTRL0_DQ_REG     ,  0,  3}, {OFFSETCNCLCTRL0_DQ_REG     ,  0,  3}},       0x29,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C8, RxVocVal7
  {CCC       , {{OFFSETCNCLCTRL0_CCC_REG    ,  0,  3}, {OFFSETCNCLCTRL0_CCC_REG    ,  0,  3}},       0x2A,   {0x00},      -8,   0,       0,   0,       0,   0, 0x0000000f,          0,    R2R_DISABLE}, // Type 0x00C9, RxVocVal7_Ecc
  },
};

//
// Blueprint project defines
//
UINT32 test_GENERATED[MAX_BLUEPRINTS] = {test_BLUEPRINT_LPDDR34        , test_BLUEPRINT_DDR3           };
