/** @file
  Initializes Miscellaneous SC configurations

 @copyright
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  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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  be modified by the user, subject to additional terms of the license agreement.

@par Specification Reference:
**/

#include "ScInitPei.h"
#include <Ppi/ReadOnlyVariable2.h>
#include <Library/PeiServicesLib.h>

/**
  Internal function performing miscellaneous init needed in early PEI phase

  @param[in] ScPolicyPpi  The SC Platform Policy PPI instance

  @retval EFI_SUCCESS             Succeeds.
  @retval EFI_DEVICE_ERROR        Device error, aborts abnormally.
**/
EFI_STATUS
ScMiscInit (
  IN  SC_POLICY_PPI      *ScPolicyPpi
  )
{


  UINTN           P2sbBase;
  UINT16          RegData16;
  EFI_STATUS      Status;
  SC_HPET_CONFIG  *HpetConfig;

  DEBUG ((DEBUG_INFO, "ScMiscInit() - Start\n"));
  Status = GetConfigBlock ((VOID *) ScPolicyPpi, &gHpetConfigGuid, (VOID *) &HpetConfig);
  ASSERT_EFI_ERROR (Status);

  P2sbBase = MmPciBase (
       DEFAULT_PCI_BUS_NUMBER_SC,
       PCI_DEVICE_NUMBER_P2SB,
       PCI_FUNCTION_NUMBER_P2SB
     );
  RegData16 = (
    (DEFAULT_PCI_BUS_NUMBER_SC << 8) +
    (PCI_DEVICE_NUMBER_P2SB << 3) +
    PCI_FUNCTION_NUMBER_P2SB
    );
  //
  // P2SB PCI CFG Offset 0x50 = VBDF (VLW Bus:Device:Function)
  //
  MmioWrite16((UINTN)(P2sbBase + R_SC_PCH_P2SB_CFG_VBDF), RegData16);
  //
  // P2SB PCI CFG Offset 0xA0 = DISPBDF (Display Bus:Device:Function)
  // Must be set to P2SB BDF - used by CSE for PAVP flows
  //
  MmioWrite16((UINTN)(P2sbBase + R_SC_PCH_P2SB_CFG_DISPBDF), RegData16);

  ///
  /// Initial and enable HPET High Precision Timer memory address for basic usage
  ///
  if (HpetConfig->Enable == TRUE) {
    ///
    /// Set HPET Timer enable to start counter spinning
    ///
	  MmioOr32(HpetConfig->Base + R_SC_HPET_MEM_GCFG, B_SC_HPET_MEM_GCFG_EN);
    //
    // Read back Posted Writes Register
    //
	  MmioRead32(HpetConfig->Base + R_SC_HPET_MEM_GCFG);

    ///
    /// P2SB PCI CFG Offset 0x70 = HBDF (HPET Bus:Device:Function)
    ///
    if (HpetConfig->BdfValid) {
		RegData16 = ((UINT16)(HpetConfig->BusNumber) << 8) & B_SC_PCH_P2SB_CFG_HBDF_BUF;
		RegData16 |= ((UINT16)(HpetConfig->DeviceNumber) << 3) & B_SC_PCH_P2SB_CFG_HBDF_DEV;
		RegData16 |= (UINT16)(HpetConfig->FunctionNumber) & B_SC_PCH_P2SB_CFG_HBDF_FUNC;
		MmioWrite16((UINTN)(P2sbBase + R_SC_PCH_P2SB_CFG_HBDF), RegData16);
    }
  }


  DEBUG ((DEBUG_INFO, "ScMiscInit() - End\n"));

  return EFI_SUCCESS;
}

