/** @file
  This file include defination for ICH register.

 @copyright
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  and is protected by worldwide copyright and trade secret laws and treaty
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  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
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  be modified by the user, subject to additional terms of the license agreement.

@par Specification Reference:
**/


#ifndef _ICHREGS_H_
#define _ICHREGS_H_

///
/// Definitions beginning with "R_" are registers
/// Definitions beginning with "B_" are bits within registers
/// Definitions beginning with "V_" are meaningful values of bits within the
///   registers
///

//
// P2SB device (D13:F0)
//
#define P2SB_BUS 0
#define P2SB_DEV 13
#define P2SB_FUN 0

#define ICH_HPET_BASE_ADDRESS                   0xFED00000          ///< Program by McEnableHpet and restore by McDisableHPET
#define R_PCH_PCH_HPET_GCFG                     0x10
#define B_PCH_PCH_HPET_GCFG_LRE                 BIT1
#define B_PCH_PCH_HPET_GCFG_EN                  BIT0

#define PCI_BUS_NUMBER_ICH                      0x00

//
// PMC device (D13:F1)
//
#define PCI_DEVICE_NUMBER_PMC                   13
#define PCI_FUNCTION_NUMBER_PMC                 1
#define PMC_BAR_BASE_ADDRESS                    0x10
#define PMC_GCR_GEN_PMCON1                      0x20
#define PMC_GCR_GEN_PMCON1_DRAM_INIT_BIT_STS    BIT23
#define PMC_GCR_GEN_PMCON1_MEM_SR_BIT_STS       BIT21
#define PMC_GCR_GEN_PMCON1_GLOBAL_RESET_STS     BIT24
#define PMC_GCR_GEN_PMCON1_WARM_RESET_STS       BIT25
#define PMC_GCR_GEN_PMCON1_COLD_RESET_STS       BIT26
#define PMC_GCR_GEN_PMCON1_COLD_BOOT_STS        BIT27
#define PMC_GCR_BASE_ADDRESS                    0x1000

#define R_SC_PMC_MEM_PM_CFG                          0x08  ///< Power Management Configuration
#define B_PMC_PM_CFG_NO_REBOOT                BIT4  ///< No Reboot Strap


#define SC_ADDR_BASE                            0xFF040000
//#define GCR_BASE_ADDRESS                      (SC_ADDR_BASE+0x00003000) //(SC_ADDR_BASE+0x00027000)
#define IPC1_BASE_ADDRESS                       0xFE042000
//#define GCR_BASE_ADDRESS                      (IPC1_BASE_ADDRESS + 0x1000) 
#define ACPI_BASE_ADDRESS                       0x0400
#define PMC_BASEADDRESS                         (IPC1_BASE_ADDRESS + 0x1000) //GCR_BASE_ADDRESS // PMC Memory Base Address
// restore this later once the merge gets un-screwed-up
//#define ACPI_BASE_ADDRESS                       0x0400
//#define SC_ADDR_BASE                            0xFF040000
//#define GCR_BASE_ADDRESS                        PcdGet32(PcdPmcGcrBaseAddress) 
//#define PMC_BASEADDRESS                         PcdGet32(PcdPmcGcrBaseAddress)

//
// LPC Bridge Registers(D31:F0)
//
#define PCI_DEVICE_NUMBER_ICH_LPC               31
#define PCI_FUNCTION_NUMBER_ICH_LPC             0

#define R_ICH_LPC_GEN_PMCON_2                   0xA2
#define B_ICH_LPC_GEN_PMCON_MIN_SLP_S4          0x04
#define B_ICH_LPC_GEN_PMCON_DRAM_INIT           0x80
#define R_ICH_LPC_GEN_PMCON_3                   0xA4
#define R_ICH_LPC_ETR3                          0xAC
#define B_ICH_LPC_ETR3_CF9GR                    (BIT20)
#define R_ICH_LPC_RCBA                          0xF0

#define ICH_RCRB_HPTC                           0x3404            ///< High Performance Timer Configuration
#define ICH_RCRB_HPTC_AS                        (BIT1+BIT0)       ///< Address selection
#define ICH_RCRB_HPTC_AE                        (BIT7)            ///< Address enable

//
// SMBUS Bridge Registers(D31:F1)
//
#define PCI_DEVICE_NUMBER_ICH_SMBUS               31
#define PCI_FUNCTION_NUMBER_ICH_SMBUS             1
#define R_SC_SMBUS_CFG_BASE                              0x20




#endif
