/** @file
  File name:    DQDPIC.h
  Input File:   BXTP_SOC.xlsx

  THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.

  If edits are needed in this file, they must be done via the MMRC tool.

  If there is additional project-specific data required by the MMRC, it
  can be placed in DQDPIC.h, which is used for non-tool-generated
  data

  Includes register defines specific to a project.

  @copyright
  Copyright (c) 2005-2016 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as 'Intel Reference Module' and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

  @par Specification
**/
#ifndef _DQDPIC_H_
#define _DQDPIC_H_

#include "DataTypes.h"

#if USE_64_BIT_VARIABLES
#define UINTX UINT64
#else
#define UINTX UINT32
#endif

#define DPIC_CRI_CFG_DQDPIC_REG                            0x00000000
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[0:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved0 : 1;
#else
    UINTX reserved : 1;
#endif // MEM_SV_HOOKS
    //
    // Reserved
    //
    // Bits[31:1], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_1 : 31;
#else
    UINTX reserved_1 : 31;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} DPIC_CRI_CFG_DQDPIC_STRUCT;
#endif // ASM_INC

#define PLLDIVCTL_DQDPIC_REG                               0x00000004
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved bits
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} PLLDIVCTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define PLLCTL_DQDPIC_REG                                  0x00000008
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} PLLCTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define CRIPG_DELAY1_DQDPIC_REG                            0x0000000C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} CRIPG_DELAY1_DQDPIC_STRUCT;
#endif // ASM_INC

#define CRIPG_DELAY0_DQDPIC_REG                            0x00000010
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} CRIPG_DELAY0_DQDPIC_STRUCT;
#endif // ASM_INC

#define CRIPGCTL_DQDPIC_REG                                0x00000014
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} CRIPGCTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define CRIPGEN_CTL_DQDPIC_REG                             0x00000018
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} CRIPGEN_CTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define OBSCTL0_DQDPIC_REG                                 0x0000001C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Digital Observation Control 0
    //
    // Bits[3:0], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX func_mon_bl1_digobs0sel : 4;
#else
    UINTX reserved : 4;
#endif // MEM_SV_HOOKS
    //
    // Digital Observation Control 1
    //
    // Bits[7:4], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX func_mon_bl1_digobs1sel : 4;
#else
    UINTX reserved_1 : 4;
#endif // MEM_SV_HOOKS
    //
    // Analog Observation Control
    //
    // Bits[9:8], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX func_mon_bl1_anaobssel : 2;
#else
    UINTX reserved_2 : 2;
#endif // MEM_SV_HOOKS
    //
    // Digital Observation Control 0
    //
    // Bits[13:10], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX func_mon_bl0_digobs0sel : 4;
#else
    UINTX reserved_3 : 4;
#endif // MEM_SV_HOOKS
    //
    // Digital Observation Control 1
    //
    // Bits[17:14], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX func_mon_bl0_digobs1sel : 4;
#else
    UINTX reserved_4 : 4;
#endif // MEM_SV_HOOKS
    //
    // Analog Observation Control
    //
    // Bits[19:18], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX func_mon_bl0_anaobssel : 2;
#else
    UINTX reserved_5 : 2;
#endif // MEM_SV_HOOKS
    //
    // Reserved
    //
    // Bits[31:20], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_6 : 12;
#else
    UINTX reserved_6 : 12;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} OBSCTL0_DQDPIC_STRUCT;
#endif // ASM_INC

#define OBSCTL1_DQDPIC_REG                                 0x00000020
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} OBSCTL1_DQDPIC_STRUCT;
#endif // ASM_INC

#define SPIDCLKCTL0_DQDPIC_REG                             0x00000024
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} SPIDCLKCTL0_DQDPIC_STRUCT;
#endif // ASM_INC

#define LDOCTL1_DQDPIC_REG                                 0x00000028
#ifndef ASM_INC
typedef union {
  struct {
    //
    // LDO Clock Enable
    //
    // Bits[0:0], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX pll_cmn_ldoclken : 1;
#else
    UINTX reserved : 1;
#endif // MEM_SV_HOOKS
    //
    // LDO FF Clock Enable - BL
    //
    // Bits[1:1], RW, default = 0x1
    //
#ifdef MEM_SV_HOOKS
    UINTX ldoffdig_bl_ldoffclkenable : 1;
#else
    UINTX reserved_1 : 1;
#endif // MEM_SV_HOOKS
    //
    // LDO FF Clock Enable - CC
    //
    // Bits[2:2], RW, default = 0x1
    //
#ifdef MEM_SV_HOOKS
    UINTX ldoffdig_cc_ldoffclkenable : 1;
#else
    UINTX reserved_2 : 1;
#endif // MEM_SV_HOOKS
    //
    // LDO IO Bufact - BL
    //
    // Bits[3:3], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX ldoffdig_bl_ldoiobufact : 1;
#else
    UINTX reserved_3 : 1;
#endif // MEM_SV_HOOKS
    //
    // LDO IO Bufact - CC
    //
    // Bits[4:4], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX ldoffdig_cc_ldoiobufact : 1;
#else
    UINTX reserved_4 : 1;
#endif // MEM_SV_HOOKS
    //
    // Reseved
    //
    // Bits[15:5], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved0 : 11;
#else
    UINTX reserved_5 : 11;
#endif // MEM_SV_HOOKS
    //
    // Reseved
    //
    // Bits[31:16], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_6 : 16;
#else
    UINTX reserved_6 : 16;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LDOCTL1_DQDPIC_STRUCT;
#endif // ASM_INC

#define LDOONCTL_DQDPIC_REG                                0x0000002C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LDOONCTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define LDORSTCTL_DQDPIC_REG                               0x00000030
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LDORSTCTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define LVUGSUPPLYCTL0_DQDPIC_REG                          0x00000034
#ifndef ASM_INC
typedef union {
  struct {
    //
    // vccaddrug_lv to vccsocvnn_lv isolation control (1- isolation enabled; 0 - disabled)
    //
    // Bits[0:0], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX lvug_isolen : 1;
#else
    UINTX reserved : 1;
#endif // MEM_SV_HOOKS
    //
    // Reseved
    //
    // Bits[31:1], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_1 : 31;
#else
    UINTX reserved_1 : 31;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LVUGSUPPLYCTL0_DQDPIC_STRUCT;
#endif // ASM_INC

#define DPIC_GRCOMP_OVR_DQDPIC_REG                         0x00000100
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved bits
    //
    // Bits[9:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved1 : 10;
#else
    UINTX reserved : 10;
#endif // MEM_SV_HOOKS
    //
    // Reserved bits
    //
    // Bits[17:10], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved0 : 8;
#else
    UINTX reserved_1 : 8;
#endif // MEM_SV_HOOKS
    //
    // debug observation signal to AFE
    //
    // Bits[18:18], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX gcomp_cmn_obsen : 1;
#else
    UINTX reserved_2 : 1;
#endif // MEM_SV_HOOKS
    //
    // debug observation signal to AFE
    //
    // Bits[20:19], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX gcomp_cmn_digobs1_sel : 2;
#else
    UINTX reserved_3 : 2;
#endif // MEM_SV_HOOKS
    //
    // debug observation signal to AFE
    //
    // Bits[22:21], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX gcomp_cmn_digobs0_sel : 2;
#else
    UINTX reserved_4 : 2;
#endif // MEM_SV_HOOKS
    //
    // override enable for override for pull up live rcomp code going to AFE
    //
    // Bits[23:23], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX comp_rcomp_pu_live_override_en : 1;
#else
    UINTX reserved_5 : 1;
#endif // MEM_SV_HOOKS
    //
    // override for pull up live rcomp code going to AFE
    //
    // Bits[29:24], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX comp_rcomp_pu_live_override : 6;
#else
    UINTX reserved_6 : 6;
#endif // MEM_SV_HOOKS
    //
    // Reserved bits
    //
    // Bits[31:30], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_7 : 2;
#else
    UINTX reserved_7 : 2;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} DPIC_GRCOMP_OVR_DQDPIC_STRUCT;
#endif // ASM_INC

#define DPIC_GRCOMP_CTL_DQDPIC_REG                         0x00000104
#ifndef ASM_INC
typedef union {
  struct {
    //
    // static leg signal for the AFE
    //
    // Bits[0:0], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX rcomp_pu_staticlive : 1;
#else
    UINTX reserved : 1;
#endif // MEM_SV_HOOKS
    //
    // this tells a timer to start the periodic c73p1ddrlp34l64x1top_comp cycle when
    // this number of cycles are completed. Usually this is programmed to 'h7d00 for
    // a 4us delay between two periodic c73p1ddrlp34l64x1top_comp cycles.
    //
    // Bits[20:1], RW, default = 0x7D00
    //
#ifdef MEM_SV_HOOKS
    UINTX rcomp_wakeup_period : 20;
#else
    UINTX reserved_1 : 20;
#endif // MEM_SV_HOOKS
    //
    // Not used.
    //
    // Bits[26:21], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX rcomp_general_timer : 6;
#else
    UINTX reserved_2 : 6;
#endif // MEM_SV_HOOKS
    //
    // Reserved bits
    //
    // Bits[31:27], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_3 : 5;
#else
    UINTX reserved_3 : 5;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} DPIC_GRCOMP_CTL_DQDPIC_STRUCT;
#endif // ASM_INC

#define DPIC_LRCOMP_DEBUG_DQDPIC_REG                       0x00000300
#ifndef ASM_INC
typedef union {
  struct {
    //
    // debug signal to AFE
    //
    // Bits[3:0], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX lrcomp_cmn_ibonus : 4;
#else
    UINTX reserved : 4;
#endif // MEM_SV_HOOKS
    //
    // debug ctrl bits.
    //
    // Bits[4:4], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX lrcomp_cmn_obsen : 1;
#else
    UINTX reserved_1 : 1;
#endif // MEM_SV_HOOKS
    //
    // debug ctrl bits.
    //
    // Bits[6:5], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX lrcomp_cmn_digobs1sel : 2;
#else
    UINTX reserved_2 : 2;
#endif // MEM_SV_HOOKS
    //
    // debug ctrl bits.
    //
    // Bits[8:7], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX lrcomp_cmn_digobs0sel : 2;
#else
    UINTX reserved_3 : 2;
#endif // MEM_SV_HOOKS
    //
    // spare bits
    //
    // Bits[24:9], RW, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX lrcomp_spare : 16;
#else
    UINTX reserved_4 : 16;
#endif // MEM_SV_HOOKS
    //
    // Reserved bits
    //
    // Bits[31:25], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_5 : 7;
#else
    UINTX reserved_5 : 7;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} DPIC_LRCOMP_DEBUG_DQDPIC_STRUCT;
#endif // ASM_INC

#define LOWER_DFXVISAULM0_DQDPIC_REG                       0x00000500
#ifndef ASM_INC
typedef union {
  struct {
    //
    // VISA Lower Level Bypass ULM0
    //
    // Bits[0:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved0 : 1;
#else
    UINTX reserved : 1;
#endif // MEM_SV_HOOKS
    //
    // Reserved
    //
    // Bits[31:1], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved_1 : 31;
#else
    UINTX reserved_1 : 31;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LOWER_DFXVISAULM0_DQDPIC_STRUCT;
#endif // ASM_INC

#define LOWER_DFXVISAULM1_DQDPIC_REG                       0x00000504
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LOWER_DFXVISAULM1_DQDPIC_STRUCT;
#endif // ASM_INC

#define LOWER_DFXVISAPATTGEN_DQDPIC_REG                    0x00000508
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LOWER_DFXVISAPATTGEN_DQDPIC_STRUCT;
#endif // ASM_INC

#define TOP_DFXVISAULM0_DQDPIC_REG                         0x0000050C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} TOP_DFXVISAULM0_DQDPIC_STRUCT;
#endif // ASM_INC

#define TOP_DFXVISAULM1_DQDPIC_REG                         0x00000510
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} TOP_DFXVISAULM1_DQDPIC_STRUCT;
#endif // ASM_INC

#define TOP_DFXVISAPATTGEN_DQDPIC_REG                      0x00000514
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
#ifdef MEM_SV_HOOKS
    UINTX reserved : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} TOP_DFXVISAPATTGEN_DQDPIC_STRUCT;
#endif // ASM_INC

#define LDOCTL1X_DQDPIC_REG                                0x00000028
#ifndef ASM_INC
typedef union {
  struct {
    //
    // LDO FF Clock Enable - CC
    //
    // Bits[31:0], RW, default = 0x1
    //
#ifdef MEM_SV_HOOKS
    UINTX rsvd : 32;
#else
    UINTX reserved : 32;
#endif // MEM_SV_HOOKS
  } Bits;
  UINTX Data;
} LDOCTL1X_DQDPIC_STRUCT;
#endif // ASM_INC


#endif // _DQDPIC_H_
