/** @file
  LPSS policy

 @copyright
  INTEL CONFIDENTIAL
  Copyright 2016 - 2018 Intel Corporation.

  The source code contained or described herein and all documents related to the
  source code ("Material") are owned by Intel Corporation or its suppliers or
  licensors. Title to the Material remains with Intel Corporation or its suppliers
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  confidential information of Intel Corporation and its suppliers and licensors,
  and is protected by worldwide copyright and trade secret laws and treaty
  provisions. No part of the Material may be used, copied, reproduced, modified,
  published, uploaded, posted, transmitted, distributed, or disclosed in any way
  without Intel's prior express written permission.

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  Unless otherwise agreed by Intel in writing, you may not remove or alter
  this notice or any other notice embedded in Materials by Intel or
  Intel's suppliers or licensors in any way.

  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
  "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
  the terms of your license agreement with Intel or your vendor. This file may
  be modified by the user, subject to additional terms of the license agreement.

@par Specification Reference:
**/
#ifndef _LPSS_CONFIG_H_
#define _LPSS_CONFIG_H_

#define LPSS_CONFIG_REVISION 4
extern EFI_GUID gLpssConfigGuid;

#pragma pack (push,1)

#define  LPSS_I2C_DEVICE_NUM     8
#define  LPSS_HSUART_DEVICE_NUM  4
#define  LPSS_SPI_DEVICE_NUM     3

/**
  The SC_LPSS_CONFIG block describes Low Power Sub System (LPSS) settings for SC.
  @note: the order defined below is per the PCI BDF sequence, and MUST not change.
  Items defined will be accessed by its index in ScInit module
**/
typedef struct {
  /**
    Revision 1: Init version
    Revision 2: Deprecated ExiEnable
    Revision 3: Add/Adjust Reserved Bit(s)/Byte(s) for DWORD alignment due to ConfigBlock V4 update
    Revision 4: HostUartHide
  **/
  CONFIG_BLOCK_HEADER Header;           ///< Config Block Header
  /**
    Determine if I2C_n is enabled.
    0: Disabled; <b>1: PCI Mode</b>; 2: ACPI Mode;
  **/
  SC_DEV_MODE         I2c0Enable;
  SC_DEV_MODE         I2c1Enable;
  SC_DEV_MODE         I2c2Enable;
  SC_DEV_MODE         I2c3Enable;
  SC_DEV_MODE         I2c4Enable;
  SC_DEV_MODE         I2c5Enable;
  SC_DEV_MODE         I2c6Enable;
  SC_DEV_MODE         I2c7Enable;
  /**
    Determine if UART_n is enabled.
    0: Disabled; <b>1: PCI Mode</b>; 2: ACPI Mode;
  **/
  SC_DEV_MODE         Hsuart0Enable;
  SC_DEV_MODE         Hsuart1Enable;
  SC_DEV_MODE         Hsuart2Enable;
  SC_DEV_MODE         Hsuart3Enable;
  /**
    Determine if SPI_n is enabled.
    0: Disabled; <b>1: PCI Mode</b>; 2: ACPI Mode;
  **/
  SC_DEV_MODE         Spi0Enable;
  SC_DEV_MODE         Spi1Enable;
  SC_DEV_MODE         Spi2Enable;
  UINT32              Uart2KernelDebugBaseAddress;
  UINT8               I2cClkGateCfg[LPSS_I2C_DEVICE_NUM];
  UINT8               HsuartClkGateCfg[LPSS_HSUART_DEVICE_NUM];
  UINT8               SpiClkGateCfg[LPSS_SPI_DEVICE_NUM];
  UINT8               Rsvd0;            ///< Add padding for dword alignment due to configblock v4 update.
  UINT32              S0ixEnable  : 1;  ///< <b>0: Disabled</b>; 1: Enabled
  UINT32              OsDbgEnable : 1;  ///< <b>0: Disabled</b>; 1: Enabled
  UINT32              ExiEnable   : 1;  ///< @deprecated, please use DciEn from SC_DCI_CONFIG
  UINT32              HostUartHide:	1;	///< auto-config indicates Host UART hidden its BAR is fixed used in ACPI DBG table
  UINT32              SkipSpiPCP:	1;	///<b>0: Initialize(Default)</b>; 1: Skip LPSS SPI Private Clock Parameter Programming
  UINT32              RsvdBits    : 27;
} SC_LPSS_CONFIG;

#pragma pack (pop)

#endif // _LPSS_CONFIG_H_
