/** @file
  File name:    DDRSAI.h
  Input File:   BXTM_SOC.xlsx

  THIS FILE IS AUTO-GENERATED BY THE MMRC TOOL. DO NOT CHANGE THIS CODE.

  If edits are needed in this file, they must be done via the MMRC tool.

  If there is additional project-specific data required by the MMRC, it
  can be placed in DDRSAI.h, which is used for non-tool-generated
  data

  Includes register defines specific to a project.

  @copyright
  Copyright (c) 2005-2016 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as 'Intel Reference Module' and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

  @par Specification
**/
#ifndef _DDRSAI_H_
#define _DDRSAI_H_

#include "DataTypes.h"

#if USE_64_BIT_VARIABLES
#define UINTX UINT64
#else
#define UINTX UINT32
#endif

#define SAI_CTRL_REG0_DDRSAI_REG                           0x00000040
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Control Policy for Group 1 (LSB)
    //
    // Bits[31:0], RW, default = 0x61010202
    //
    UINTX sai_ctrl_policy : 32;
  } Bits;
  UINTX Data;
} SAI_CTRL_REG0_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_CTRL_REG0_1_DDRSAI_REG                         0x00000044
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Control Policy for Group 1 (MSB)
    //
    // Bits[31:0], RW, default = 0xC00
    //
    UINTX sai_ctrl_policy_1 : 32;
  } Bits;
  UINTX Data;
} SAI_CTRL_REG0_1_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG0_DDRSAI_REG                             0x00000048
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Read/Write Policy for Group 1: policy0
    //
    // Bits[31:0], RW, default = 0x1000212
    //
    UINTX sai_rw_policy0 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG0_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG0_1_DDRSAI_REG                           0x0000004C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // SAI Read/Write Policy for Group 2: policy0
    //
    // Bits[31:0], RW, default = 0xC00
    //
    UINTX sai_rw_policy0_1 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG0_1_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG1_DDRSAI_REG                             0x00000050
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX sai_rw_policy1 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG1_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG1_1_DDRSAI_REG                           0x00000054
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX sai_rw_policy1_1 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG1_1_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG2_DDRSAI_REG                             0x00000058
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX sai_rw_policy2 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG2_DDRSAI_STRUCT;
#endif // ASM_INC

#define SAI_RW_REG2_1_DDRSAI_REG                           0x0000005C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX sai_rw_policy2_1 : 32;
  } Bits;
  UINTX Data;
} SAI_RW_REG2_1_DDRSAI_STRUCT;
#endif // ASM_INC

#define REG_POLICY0_DDRSAI_REG                             0x00000060
#ifndef ASM_INC
typedef union {
  struct {
    //
    // CR Region Policy0: [br] 1'b1 (applicable for all indexes): The corresponding configuration
    // register region is locked and only accessible by trusted agents associated with
    // policy0 [br]1'b0 (applicable for all indexes): The corresponding configuration
    // register region is unlocked - all agents (trusted or untrusted) are allowed to
    // access this region.
    //
    // Bits[31:0], RW, default = 0x3
    //
    UINTX region_policy0 : 32;
  } Bits;
  UINTX Data;
} REG_POLICY0_DDRSAI_STRUCT;
#endif // ASM_INC

#define REG_POLICY1_DDRSAI_REG                             0x00000064
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX region_policy1 : 32;
  } Bits;
  UINTX Data;
} REG_POLICY1_DDRSAI_STRUCT;
#endif // ASM_INC

#define REG_POLICY2_DDRSAI_REG                             0x00000068
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX region_policy2 : 32;
  } Bits;
  UINTX Data;
} REG_POLICY2_DDRSAI_STRUCT;
#endif // ASM_INC

#define REG_RSVD_DDRSAI_REG                                0x0000006C
#ifndef ASM_INC
typedef union {
  struct {
    //
    // Reserved
    //
    // Bits[31:0], RO, default = 0x0
    //
    UINTX reg_rsvd : 32;
  } Bits;
  UINTX Data;
} REG_RSVD_DDRSAI_STRUCT;
#endif // ASM_INC


#endif // _DDRSAI_H_
